最新美国发明专利第2016-02-16期 - 专利汇|PatentHub专利检索|专利查询网|发明专利查询分析

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US09263716B2	Monolithic battery holder having resilient retention strap for use in battery-powered sensor A battery holder for use with a battery-powered sensor may be configured such that removing the battery involves at least two distinct motions. The battery holder may include a cradle and a resilient retention strap configured to be deflectable between relaxed and deflected positions. With the retention strap in the relaxed position, the cradle and the retention strap may cooperate to retain the battery in the inserted position within the battery holder. The battery may be removed by first manipulating the retention strap from the relaxed position to the deflected position, and then using a distinct second motion to remove the battery from the holder. The battery holder may be configured to substantially prevent movement of the battery relative to the cradle when the battery is in the inserted position. The battery holder may be configured to facilitate insertion of the battery into the holder in a desired orientation.
US09263710B2	Method for preparing semiconductor nanocrystals A method for preparing semiconductor nanocrystals including a core and an overcoating layer is disclosed. According to one aspect of the invention, the method comprises preparing more than one batch of cores comprising a first semiconductor material and having a maximum emission peak within a predetermined spectral region, wherein each batch of cores is characterized by a first excitonic absorption peak at an absorption wavelength and a maximum emission peak at an emission wavelength; selecting a batch of cores from the batches prepared wherein the selected batch is characterized by a difference between the absorption wavelength and the emission wavelength that is less than or equal to 13; and overcoating the cores of the selected batch with a layer comprising a second semiconductor material.
US09263709B2	Flexible display apparatus and manufacturing method thereof A method of manufacturing a flexible display apparatus includes sequentially forming a flexible substrate, a thin film transistor (TFT), an organic light-emitting diode (OLED) including a first electrode, an intermediate layer, and a second electrode, and a first attachment layer on a carrier substrate, sequentially forming a deposition layer and a second attachment layer on a sealing film, attaching the carrier substrate and the sealing film to each other such that the sealing film covers flexible substrate on the carrier substrate, sealing the first and second attachment layers, laminating the carrier substrate and the sealing film, and separating the sealing film and the flexible substrate from the carrier substrate.
US09263708B2	Method of removing particles from a display panel and apparatus for performing the same A method of removing particles from a display panel is disclosed. In one aspect, the method includes charging the particles and applying an electric field to the charged particles to capture the charged particles. Organic particles and inorganic particles may be forcibly charged to capture the organic and inorganic particles using a metal bar so that the organic and inorganic particles may be substantially removed.
US09263700B2	Opto-electric device and method of manufacturing an opto-electric device An opto-electric device is presented that comprises an opto-electric element enclosed by a barrier structure for inhibiting a transmission of moisture from an environment towards the opto-electric element. The barrier structure includes a stack of layers comprising at least an inorganic layer and a moisture getter material in a layer arranged between the inorganic layer and the opto-electric element. The stack includes a lateral diffusion layer, wherein the getter material is present in a separate getter layer arranged between the opto-electric element and the lateral diffusion layer and/or the getter material is present in the lateral diffusion layer.
US09263698B2	Flexible display apparatus and method of manufacturing the same A flexible display apparatus includes a flexible substrate, a display layer disposed on one surface of the flexible substrate and including a plurality of pixels, graphene disposed on a surface opposing the one surface of the flexible substrate, and an encapsulation layer covering the display layer.
US09263695B2	Light-emitting element, light-emitting device, display device, electronic device, and lighting device An object is to provide a light-emitting element which uses a plurality of kinds of light-emitting dopants and has high emission efficiency. In one embodiment of the present invention, a light-emitting device, a light-emitting module, a light-emitting display device, an electronic device, and a lighting device each having reduced power consumption by using the above light-emitting element are provided. Attention is paid to Förster mechanism, which is one of mechanisms of intermolecular energy transfer. Efficient energy transfer by Förster mechanism is achieved by making an emission wavelength of a molecule which donates energy overlap with the longest-wavelength-side local maximum peak of a graph obtained by multiplying an absorption spectrum of a molecule which receives energy by a wavelength raised to the fourth power.
US09263691B2	Light emitting device containing iridium complex A triplet light emitting device which has high efficiency and improved stability and which can be fabricated by a simpler process is provided by simplifying the device structure and avoiding use of an unstable material. In a multilayer device structure using no hole blocking layer conventionally used in a triplet light emitting device, that is, a device structure in which on a substrate, there are formed an anode, a hole transporting layer constituted by a hole transporting material, an electron transporting and light emitting layer constituted by an electron transporting material and a dopant capable of triplet light emission, and a cathode, which are laminated in the stated order, the combination of the hole transporting material and the electron transporting material and the combination of the electron transporting material and the dopant material are optimized.
US09263690B2	Organic el device and manufacturing method thereof An organic EL device with which occurrence of leakage current between electrodes can be prevented includes: a substrate; a first electrode layer separating groove that separates a first electrode layer into small pieces; a function layer separating groove that separates a function layer into small light emitting regions; and a unit light emitting element separating groove extending from a second electrode layer to the function layer and separating the second electrode layer into small pieces. One of the small pieces of the first electrode layer, one of the small light emitting regions, and one of the small pieces of the second electrode layer structure a unit organic EL element, electrically connected in series. The average width of the unit light emitting element separating groove at the second electrode layer is wider than the average width of the unit light emitting element separating groove at the light emitting portion separating layer.
US09263688B2	Photoelectric conversion material, method for producing the same, and organic photovoltaic cell containing the same In a BHJ solar cell, a photoelectric conversion layer contains a condensed carbocyclic ring polymer (photoelectric conversion material). The condensed carbocyclic ring polymer is obtained by polymerizing monomers represented by the following general formulae (1) and (2) to prepare a polyphenylene and then reacting the polyphenylene. R1 to R6 in the general formula (1) independently represent a hydrogen atom or a solubilizing group, and the monomer represented by the general formula (1) exhibits a higher solubility in an organic solvent with the solubilizing group than without the solubilizing group. Ar in the general formula (2) represents an unsubstituted or substituted aromatic group, and R7 and R8 in the general formula (2) independently represent a hydrogen atom, an unsubstituted or substituted aromatic group, a methyl group, or a silyl group.
US09263684B2	Organic electroluminescent element, display device and lighting device Disclosed is an organic electroluminescent device having high external quantum efficiency and long life. Also disclosed are an illuminating device and a display device. The organic electroluminescent device is characterized by containing at least one compound having a partial structure represented by the following general Formula (1). [chemical formula 1] (1) In the formula, R1 represents a group (preferably an aromatic hydrocarbon group, an aromatic heterocyclic group, an alkyl group or an alkoxy group) having 4-20 carbon atoms in total and a substituent having a formula weight or 70-350 (preferably an alkyl group or an alkoxy group): R2-R4 independently represent a substituent; n2 represents a number of 0-4; n3 represents a number of 0-2; n4 represents a number of 0-8; and Q represents an atomic group necessary for forming an aromatic hydrocarbon ring or an aromatic heterocyclic ring.
US09263680B2	Crosslinkable arylamine compounds Arylamine compounds comprising an arylamine core and at least one addition-polymerizable group X selected from the group consisting of formula (A); said addition polymerizable group attached to one ring of the arylamine core through a spacer of general formula (1): C(R1R2)—(C(R3R4))m; wherein, R1 and R2, independent of one another, each represent a C1-C8 alkyl group or an aryl group of from 5 to 30 carbon atoms, R3 and R4, independent of one another, are hydrogen, a C1 to C8 alkyl group or an aryl group of from 5 to 30 carbon atoms and m is an integer of from 0 to 6, or through a fluorene subunit of general formulae (2) or (3); wherein R5 represents hydrogen, C1 to C8-alkyl, or C5 to C30 aryl, and R6 and R7, independently of one another represent C1 alkylene or a C5 to C30 arylene group, provided that R6 and R7 both carry an addition-polymerizable group X and R5 is not hydrogen if R6 is methylene.
US09263679B2	Organic light emitting display and manufacturing method thereof An organic light emitting display includes a base substrate, an active layer on the base substrate, a gate insulating layer on the active layer, a gate electrode on the gate insulating layer, a first inter-insulating layer on the gate electrode, a second inter-insulating layer covering the first inter-insulating layer, source and drain electrodes on the second inter-insulating layer and connected to the active layer, a first electrode connected to the drain electrode, an organic light emitting layer on the first electrode, a second electrode facing the first electrode while the organic light emitting layer is between the first and second electrodes, and first and second capacitor electrodes facing each other while the gate insulating layer is between the first and second capacitor electrodes. The second inter-insulating layer makes contact with an upper surface of the second capacitor electrode through an opening formed on the first inter-insulating layer.
US09263676B2	Organic light-emitting display system and method of manufacturing the same An organic light-emitting display system and a method of manufacturing the same are disclosed. In one aspect, the organic light-emitting display system includes a substrate, a display unit that defines an active area on the substrate and includes a plurality of thin film transistor (TFTs), and an encapsulation layer that seals the display unit and has a stacked structure in which at least a first inorganic film, a first organic film, and a second inorganic film are sequentially stacked. The TFTs includes an active layer, a gate electrode, a source electrode, a drain electrode, and an interlayer insulating film that is disposed between the gate electrode and the source electrode and between the gate electrode and the drain electrode, wherein the second inorganic film directly contacts the interlayer insulating film outside the active area. Accordingly, in various embodiments, since an inorganic layer of a thin film encapsulation layer is prevented from being cracked, penetration of external moisture or oxygen into the active area of the display can be reduced or prevents.
US09263674B2	ETCH bias homogenization Methods and memory devices formed using etch bias homogenization are provided. One example method of forming a memory device using etch bias homogenization includes forming conductive material at respective levels over a substrate. Each respective level of conductive material is electrically coupled to corresponding circuitry on the substrate during patterning of the respective level of conductive material so that each respective level of conductive material has a homogenized etch bias during patterning thereof. Each respective level of conductive material electrically coupled to corresponding circuitry on the substrate is patterned.
US09263673B2	Resistive memory device having asymmetric diode structure A resistive memory device includes a switching device disposed on a lower interconnection, a resistor element disposed on the switching device, and an upper interconnection disposed on the resistor element. The switching device includes a diode electrode, a high-concentration lower anode disposed on the diode electrode, a middle-concentration lower anode disposed on the lower high-concentration anode electrode, a common cathode disposed on the middle-concentration lower anode, a low-concentration upper anode disposed on the common cathode, and an high-concentration upper anode disposed on the low-concentration upper anode. The peak dopant concentration of the middle-concentration lower anode is at least 10 times greater than the peak dopant concentration of the low-concentration upper anode.
US09263669B2	Magnetic trap for cylindrical diamagnetic materials A system for self-aligning diamagnetic materials includes first and second magnets contacting each other along a contact line and having a diametric magnetization perpendicular to the contact line and a diamagnetic rod positioned to levitate above the contact line of the first and second magnets.
US09263668B2	Method for manufacturing a magnetic tunnel junction device The present invention relates to a magnetic tunnel junction device and a manufacturing method thereof. The magnetic tunnel junction device includes: i) a first magnetic layer including a compound having a chemical formula of (A100-xBx)100-yCy; ii) an insulating layer deposited on the first magnetic layer; and iii) a second magnetic layer deposited on the insulating layer and including a compound having a chemical formula of (A100-xBx)100-yCy. The first and second magnetic layers have perpendicular magnetic anisotropy, A and B are respectively metal elements, and C is at least one amorphizing element selected from a group consisting of boron (B), carbon (C), tantalum (Ta), and hafnium (Hf).
US09263667B1	Method for manufacturing MTJ memory device A method for manufacturing MTJ pillars for a MTJ memory device. The method includes depositing multiple MTJ layers on a substrate, depositing a hard mask on the substrate and coating a photoresist on the hard mask. Further, alternating steps of reactive ion etching and ion beam etching are performed to isolate MTJ pillars and expose side surfaces of the MTJ layers. An insulating layer is the applied to protect the side surfaces of the MTJ layers. A second insulating layer is deposited before the device is planarized using chemical mechanical polishing.
US09263663B2	Method of making thick film transducer arrays This disclosure provides methods of fabricating a transducer array. The methods can include creating a lens shaped depression in a backing material, printing an electrode, printing a thick layer of lead zirconate titanate material, printing a ground electrode, and placing a plurality of equally spaced cuts into the depression.
US09263656B2	Semiconductor light-emitting device having double encapsulating structure A semiconductor light-emitting device having favorable optical characteristics can include a first conductor pattern having a die-bonding pad and a second conductor pattern having a wire bonding pad, which are formed on a circuit board. The semiconductor light-emitting device can also include a semiconductor light-emitting chip mounted on the die-bonding pad, a first encapsulating material, which can include a wavelength converting material to wavelength-convert light emitted from the chip and can cover the chip in a substantially fair dome shape on the circuit board, and a second encapsulating resin to cover the first encapsulating material, which can transmit light emitted from the first encapsulating material. Thus, a semiconductor light-emitting device is provided, which can emit a mixture light having various color tones and favorable optical characteristics and which can be used to illuminate goods laid out in a narrow show window, a vending machine, and the like.
US09263652B2	Semiconductor light-emitting device A semiconductor light-emitting device includes a semiconductor region having a light-emitting structure, an electrode layer formed on the semiconductor region, and a reflective protection structure extending exposing the upper surface of the electrode layer and covering the semiconductor region adjacent to the electrode layer.
US09263648B2	Method of manufacturing an integrated piece comprising a convex cured product and a substrate The present invention relates to a method of manufacturing an integrated piece comprising a convex cured product and a substrate, the method comprising a step of: depositing dropwise or dispensing a curable silicone composition onto the pre-heated substrate, the composition reaching a torque value of 1 dN·m within 60 seconds from immediately after beginning measurement as measured using a curelastometer according to JIS K 6300-2, at the temperature to which the substrate is heated, and having a viscosity at said temperature of at least 0.05 Pa·s. The method allows for the efficient manufacture of a hemispherical, hemicylindrical, dome-shaped, or similar convex cured product upon a substrate using a curable silicone composition.
US09263647B2	Light emitting diode package structure and manufacturing method thereof Various examples of a light emitting diode (LED) package structure and a manufacturing method thereof are described. In one aspect, a LED package structure includes a carrier, a LED chip, a first annular barricade, a second annular barricade and a fluorescent encapsulant. The LED chip is electrically connected to the carrier. The first annular barricade and the second annular barricade are disposed around the LED chip, with the second annular barricade disposed between the LED chip and the first annular barricade. The fluorescent encapsulant is disposed on the carrier and at least covers the LED chip and the second annular barricade. The fluorescent encapsulant includes at least a type of phosphor and at least a type of gel with the phosphor distributed over a surface of the LED chip.
US09263644B2	Semiconductor light-emitting device and method of forming electrode A semiconductor light-emitting device having an electrode that can be manufactured by a simple method and is unlikely to deteriorate, and a method for forming the electrode are provided. The semiconductor light-emitting device according to the present invention has a semiconductor layered structure having a light-emitting layer that emits light by supplying electric power and an electrode formed on the semiconductor layered structure. The electrode has a reflection layer that reflects light exiting from the light-emitting layer, a barrier layer formed on the upper side and side surface of the reflection layer, and a pad layer formed only on the top surface of the barrier layer.
US09263638B2	Preparation of stable, bright luminescent nanoparticles having compositionally engineered properties A method is provided for preparing luminescent semiconductor nanoparticles composed of a first component X, a second component A, and a third component B, wherein X, A, and B are different, by combining B with X and A in an amount such that the molar ratio B:(A+B) is in the range of approximately 0.001 to 0.20 and the molar ratio X:(A+B) is in the range of approximately 0.5:1.0 to 2:1. The characteristics of the thus-prepared nanoparticles can be substantially similar to those of nanoparticles containing only X and B while maintaining many useful properties characteristic of nanoparticles containing only X and A. The nanoparticles so prepared can additionally exhibit emergent properties such as a peak emission energy less than that characteristic of a particle composed of XA or XB alone; this method is particularly applicable to the preparation of stable, bright nanoparticles that emit in the red to infrared regions of the electromagnetic spectrum. Luminescent semiconductor nanoparticles having exemplary properties are also provided.
US09263628B2	Method for making light emitting diodes A method for making a LED comprises following steps. A substrate having a surface is provided. A first semiconductor layer, an active layer and a second semiconductor pre-layer is formed on the surface of the substrate. A patterned mask layer is applied on a surface of the second semiconductor pre-layer. A number of three-dimensional nano-structures is formed on the second semiconductor pre-layer and the patterned mask layer is removed. The substrate is removed and a first electrode is formed on a surface of the first semiconductor layer away from the active layer. A second electrode is formed to electrically connect with the second semiconductor pre-layer.
US09263620B1	Vacuum reflow voiding rework system A solar cell module comprises a solar cell soldered to a mounting element, such as a ceramic substrate. The solder bond can comprise a void. A method of reducing a solder void comprises reflowing the solder using a vacuum source and a heat source in a sealed chamber. The chamber is formed, at least in part, by a cowling into which the solar cell module is mounted. A system for reducing voids in a solder bond comprises a heat source and a vacuum source coupled to the sealed chamber into which a solar cell module is placed. The system can optionally include a control system that automates the execution of methods of reducing solder voids. The system can further include a pressure source to aid in reducing the solder void and reflowing the solder after the void is reduced.
US09263618B2	Proximity sensor module with light reflector A proximity sensor may be mounted below a display cover layer in an electronic device. The proximity sensor may have a light source that emits light and a detector configured to detect reflections of the emitted light from nearby external objects. The light emitted from the light source may pass through a lens along an axis towards external objects. The light source and the detector may be mounted in a proximity sensor housing having openings that are aligned with the light source and the detector. A reflector may be mounted to the proximity sensor in a configuration that bridges the opening over the light source. The reflector may be formed from a strip of metal or a strip of prism structures. Some of the light from the light source reflects from the reflector at a non-zero angle with respect to the axis and enhances proximity sensor performance.
US09263616B2	Selective emitter photovoltaic device A method for fabricating a photovoltaic device includes forming a patterned layer on a doped emitter portion of the photovoltaic device, the patterned layer including openings that expose areas of the doped emitter portion and growing an epitaxial layer over the patterned layer such that a crystalline phase grows in contact with the doped emitter portion and a non-crystalline phase grows in contact with the patterned layer. The non-crystalline phase is removed from the patterned layer. Conductive contacts are formed on the epitaxial layer in the openings to form a contact area for the photovoltaic device.
US09263613B2	Nanowire photo-detector grown on a back-side illuminated image sensor An embodiment relates to a device comprising a substrate having a front side and a back-side, a nanowire disposed on the back-side and an image sensing circuit disposed on the front side, wherein the nanowire is configured to be both a channel to transmit wavelengths up to a selective wavelength and an active element to detect the wavelengths up to the selective wavelength transmitted through the nanowire.
US09263608B2	Photovoltaic devices including doped semiconductor films A photovoltaic cell can include a dopant in contact with a semiconductor layer.
US09263606B2	Photoelectric conversion element and photoelectric conversion element array A photoelectric conversion element which converts incident light to an electrical signal and detects the signal, the element including: a lower electrode; an insulating layer, provided on the lower electrode; a light-receiving section, which is provided on the insulating layer and receives incident light on the surface; and a groove-like slit, provided such that the insulating layer is exposed from a surface of the light-receiving section, wherein the incident light is converted by the slit to surface plasmons which are wave-guided along the insulating layer, and the surface plasmon is detected as an electrical signal between the light-receiving section and the lower electrode.
US09263604B2	Wafer scale image sensor package and optical mechanism including the same There is provided an optical mechanism including a substrate, an image sensor chip, a light source, a blocking member and a securing member. The image sensor chip is attached to the substrate and has an active area. The light source is attached to the substrate. The blocking member covers the image sensor chip and has an opening to expose at least the active area of the image sensor chip. The securing member fits on the blocking member to secure the blocking member to the substrate.
US09263603B2	Solar cell with connecting sheet, solar cell module, and fabrication method of solar cell with connecting sheet A method of fabricating a solar cell with a connecting sheet includes a fixing step of bonding at least a portion of a peripheral region of a back electrode type solar cell (8) to a connecting sheet (10). A method of fabricating a solar cell module includes the step of sealing the solar cell with a connecting sheet obtained by the method on a transparent substrate (17) by a sealing material (18). A solar cell with a connecting sheet has a first adhesive arranged between a back electrode type solar cell (8) and a connecting sheet (10), and a second adhesive arranged at at least a portion of a peripheral region of the back electrode type solar cell (8) to bond a back electrode type solar cell (8) with a connecting sheet (10). A solar cell module has the solar cell with a connecting sheet sealed on a transparent substrate (17) by a sealing material (18).
US09263602B2	Laser processing of solar cells with anti-reflective coating Contact holes of solar cells are formed by laser ablation to accommodate various solar cell designs. Use of a laser to form the contact holes is facilitated by replacing films formed on the diffusion regions with a film that has substantially uniform thickness. Contact holes may be formed to deep diffusion regions to increase the laser ablation process margins. The laser configuration may be tailored to form contact holes through dielectric films of varying thicknesses.
US09263601B2	Enhanced adhesion of seed layer for solar cell conductive contact Enhanced adhesion of seed layers for solar cell conductive contacts and methods of forming solar cell conductive contacts are described. For example, a method of fabricating a solar cell includes forming an adhesion layer above an emitter region of a substrate. A metal seed paste layer is formed on the adhesion layer. The metal seed paste layer and the adhesion layer are annealed to form a conductive layer in contact with the emitter region of the substrate. A conductive contact for the solar cell is formed from the conductive layer.
US09263600B2	Silicon nanoparticle photovoltaic devices A photovoltaic device for converting light into electrical power includes a film (16, 26, 36) of silicon nanoparticles. The silicon nanoparticle film, which can be a multilayer film, has a photoluminescence response and couples light and or electricity into semiconductor layers. A particular example photovoltaic device of the invention include a solar cell that accepts and converts light of a predetermined wavelength range into electrical power. A film containing luminescent silicon nanoparticles is optically coupled to the solar cell. The film has a predetermined thickness. The film responds to incident radiation and produces light or electron response in the predetermined wavelength range that is optically coupled into the solar cell. In preferred embodiments, the film is additionally or alternatively electrically coupled to the solar cell, which produces charge response that is electrically coupled into the solar cell.
US09263597B2	Semiconductor arrangement having a Schottky diode A semiconductor assemblage of a super-trench Schottky barrier diode (STSBD) made up of an n+ substrate, an n-epilayer, trenches etched into the n-epilayer that have a width and a distance from the n+ substrate, mesa regions between the adjacent trenches having a width, a metal layer on the front side of the chip that is a Schottky contact and serves as an anode electrode, and a metal layer on the back side of the chip that is an ohmic contact and serves as a cathode electrode, wherein multiple Schottky contacts having a width or distance and a distance between the Schottky contacts, and between the Schottky contact as anode electrode and the first Schottky contact, are located on the trench wall.
US09263596B2	Semiconductor device and method of manufacturing the same A semiconductor device includes a channel layer including a sidewall having protrusions and depressions alternating with each other in a direction in which the channel layer extends, a tunnel insulating layer surrounding the channel layer, first charge storage patterns surrounding the tunnel insulating layer formed in the depressions, blocking insulation patterns surrounding the first charge patterns formed in the depressions, wherein the blocking insulating patterns include connecting portions coupled to the tunnel insulating layer, and second charge storage patterns surrounding the tunnel insulating layer formed in the protrusions.
US09263593B2	Semiconductor device A semiconductor device according to an embodiment, includes a first dielectric film arranged above a gate electrode, an oxide semiconductor film arranged above the first dielectric film, a second dielectric film arranged above the oxide semiconductor film, a drain electrode having a drain contact portion that is arranged in the second dielectric film and connects one end side of the oxide semiconductor film to a wire of an upper layer, and a source electrode having a source contact portion that is arranged in the second dielectric film and connects another end side of the oxide semiconductor film to a wire of an upper layer. A wiring portion arranged above the second dielectric film and forming the wire of the upper layer is formed to overhang toward a center direction of the oxide semiconductor film on a source electrode side more than on a drain electrode side.
US09263592B2	Oxide transistor with nano-layered structure A transistor includes source/drain electrodes provided on a substrate; a semiconductor oxide layer provided between the source/drain electrodes; a gate electrode facing the semiconductor oxide layer; and a gate insulating layer interposed between the semiconductor oxide layer and the gate electrode, wherein the semiconductor oxide layer has a nano-layered structure including at least one first nano layer comprised of a first material and at least one second nano layer comprised of a second material that are alternatingly stacked one on another to provide at least one interface, and wherein the first material and the second material are different materials that are effective to form an electron transfer channel layer at the interface.
US09263590B2	Thin film transistor and manufacturing method thereof A thin film transistor (TFT) includes a semiconductor active layer, a gate electrode, a source electrode, and a drain electrode. The semiconductor active layer includes a first doped region as a source region, a second doped region as a drain region, an undoped region between the first and second doped regions. A third doped region is disposed between the second doped region and the undoped region. The gate electrode is insulated from the semiconductor active layer and overlaps the third doped region and the undoped region. The source electrode and the drain electrode are connected to the first and second doped regions.
US09263588B2	Semiconductor device and method of fabricating the same A semiconductor device includes an isolation layer defining an active region formed in a semiconductor substrate. A first recessing process is performed on the isolation layer to expose edge portions of the active region. A first rounding process is performed to round the edge portions of the active region. A second recessing process is performed on the isolation layer. A second rounding process is performed to round the edge portions of the active region.
US09263587B1	Fin device with blocking layer in channel region A method includes forming an ion implant layer in a fin defined on a semiconductor substrate. The semiconductor substrate is annealed to convert the ion implant layer to a dielectric layer. A gate electrode structure is formed above the fin in a channel region after forming the ion implant layer. The fin is recessed in a source/drain region. A semiconductor material is epitaxially grown in the source/drain region.
US09263583B2	Integrated finFET-BJT replacement metal gate A method of forming a semiconductor structure that includes forming a first recess and a second recess between a first pair of sidewall spacers and a second pair of sidewall spacers respectively, the first and second pair of sidewall spacers surrounding a fin on top of a buried dielectric layer, the fin is formed from a top most semiconductor layer of a semiconductor-on-insulator substrate. A high-k dielectric layer is deposited within the first and second recesses and a dummy titanium nitride layer is deposited on the high-k dielectric layer. The high-k dielectric layer and the dummy titanium nitride layer are removed from the second recess and a silicon cap layer is deposited within the first and second recesses. Next, dopants are implanted into the silicon cap layer in the second recess without implanting dopants into the silicon cap layer in the first recess to form a BJT device.
US09263582B2	Strain engineering in semiconductor devices by using a piezoelectric material An efficient strain-inducing mechanism may be provided on the basis of a piezoelectric material so that performance of different transistor types may be enhanced by applying a single concept. For example, a piezoelectric material may be provided below the active region of different transistor types and may be appropriately connected to a voltage source so as to obtain a desired type of strain.
US09263581B2	Semiconductor structure and method for manufacturing the same A method for manufacturing a semiconductor structure comprises the following steps: providing an SOI substrate and forming a gate structure on the SOI substrate; implanting ions to induce stress in the semiconductor structure by using the gate structure as mask to form a stress-inducing region, which is located under the BOX layer on the SOI substrate on both sides of the gate structure. A semiconductor structure manufactured according to the above method is also disclosed. The semiconductor structure and the method for manufacturing the same disclosed in the present application form on the ground layer a stress-inducing region, which provides favorable stress to the semiconductor device channel and contributes to the improvement of the semiconductor device performance.
US09263578B2	Semiconductor substructure having elevated strain material-sidewall interface and method of making the same A semiconductor substructure with improved performance and a method of forming the same is described. In one embodiment, the semiconductor substructure includes a substrate, having an upper surface; a gate structure formed over the substrate; a spacer formed along a sidewall of the gate structure; and a source/drain structure disposed adjacent the gate structure. The source/drain structures is formed of a strain material and is disposed in an recess that extends below the upper surface of the substrate. An interface between the spacer and the source-drain structure can be at least 2 nm above the upper surface of the substrate.
US09263577B2	Ferroelectric field effect transistors, pluralities of ferroelectric field effect transistors arrayed in row lines and column lines, and methods of forming a plurality of ferroelectric field effect transistors A ferroelectric field effect transistor comprises a semiconductive channel comprising opposing sidewalls and an elevationally outermost top. A source/drain region is at opposite ends of the channel. A gate construction of the transistor comprises inner dielectric extending along the channel top and laterally along the channel sidewalls. Inner conductive material is elevationally and laterally outward of the inner dielectric and extends along the channel top and laterally along the channel sidewalls. Outer ferroelectric material is elevationally outward of the inner conductive material and extends along the channel top. Outer conductive material is elevationally outward of the outer ferroelectric material and extends along the channel. Other constructions and methods are disclosed.
US09263576B2	Semiconductor device having interconnection line Provided is a semiconductor device. The semiconductor device includes an insulating layer extending in a first direction. A first vertical channel pillar is disposed separately from the insulating layer. A first interconnection line extends in a second direction perpendicular to the first direction, and is electrically connected to the first vertical channel pillar. A first bit line extends in the second direction, and crosses over the first interconnection line and the first vertical channel pillar. A first bit contact overlaps the first interconnection line, and electrically connects the first interconnection line to the first bit line. A length of the first bit contact in the second direction is greater than a length of the first bit contact in the first direction.
US09263573B2	Power semiconductor devices, structures, and related methods Power semiconductor devices, and related methods, where majority carrier flow is divided into paralleled flows through two drift regions of opposite conductivity types.
US09263567B2	Nitride high electron mobility transistor having a channel forming stack A normally off nitride-based transistor may include a source electrode and a drain electrode, a channel layer serving as a charge transfer path between the source electrode and the drain electrode, and a gate electrode that controls charge transfer of the channel layer. The channel layer may have a junction structure of a first conductive nitride semiconductor layer and an intrinsic nitride semiconductor layer such that a fixed turn-off blocking electric field is generated in the channel layer between the source electrode and the drain electrode in a turn-off state. The intrinsic nitride semiconductor layer may include an intrinsic GaN semiconductor layer, and the first conductive nitride semiconductor layer may include a p type GaN semiconductor layer stacked over the intrinsic GaN semiconductor layer.
US09263566B2	Semiconductor device and manufacturing method thereof The present invention relates to a semiconductor device and its manufacturing method. The semiconductor device comprises: a gate structure located on a substrate, Ge-containing semiconductor layers located on the opposite sides of the gate structure, a doped semiconductor layer epitaxially grown between the Ge-containing semiconductor layers, the bottom surfaces of the Ge-containing semiconductor layers located on the same horizontal plane as that of the epitaxial semiconductor layer. The epitaxial semiconductor layer is used as a channel region, and the Ge-containing semiconductor layers are used as source/drain extension regions.
US09263562B2	Electrostatic discharge protection structure capable of preventing latch-up issue caused by unexpected noise An electrostatic discharge protection structure includes a first well, a second well disposed in the first well, a first and a second doped region disposed in the first well, a third and a fourth doped region disposed in the second well, a first electrode electrically connected to the first doped region and the second doped region, and a second electrode electrically connected to the fourth doped region.
US09263560B2	Power semiconductor device having reduced gate-collector capacitance A power semiconductor device may include a first conductivity type first semiconductor region; a second conductivity type second semiconductor region formed on an upper portion of the first semiconductor region; a first conductivity type third semiconductor region formed in an upper inner side of the second semiconductor region; a trench gate formed to penetrate through a portion of the first semiconductor region from the third semiconductor region; and a first conductivity type fourth semiconductor region formed below the second semiconductor region while being spaced apart from the trench gate.
US09263559B2	Semiconductor device and radio communication device A radio communication device includes a power amplifier having a semiconductor device formed with a plurality of unit transistors. Base electrodes of the unit transistors are connected with each other by a base line, and an input capacitor is connected to the base line such that the input capacitor is commonly and electrically connected to the base electrodes of a plurality of the unit transistors.
US09263558B2	Hybrid plasma-semiconductor transistors, logic devices and arrays A hybrid plasma semiconductor device has a thin and flexible semiconductor base layer. An emitter region is diffused into the base layer forming a pn-junction. An insulator layer is upon one side the base layer and emitter region. Base and emitter electrodes are isolated from each other by the insulator layer and electrically contact the base layer and emitter region through the insulator layer. A thin and flexible collector layer is upon an opposite side of the base layer. A microcavity is formed in the collector layer and is aligned with the emitter region. Collector electrodes are arranged to sustain a microplasma within the microcavity with application of voltage to the collector electrodes. A depth of the emitter region and a thickness of the base layer are set to define a predetermined thin portion of the base layer as a base region between the emitter region and the microcavity. Microplasma generated in the microcavity serves as a collector. Logic devices are provided in multiple sub collector and sub emitter microplasma devices formed in thin and flexible or not flexible semiconductor materials.
US09263545B2	Method of manufacturing a high breakdown voltage III-nitride device A method of manufacturing a semiconductor device includes forming a semiconductor body including a compound semiconductor material on a substrate, the compound semiconductor material having a channel region, forming a source region extending to the compound semiconductor material, forming a drain region extending to the compound semiconductor material and spaced apart from the source region by the channel region, and forming an insulating region buried in the semiconductor body below the channel region between the compound semiconductor material and the substrate in an active region of the semiconductor device such that the channel region is uninterrupted by the insulating region. The active region includes the source, the drain and the channel region. The insulating region is discontinuous over a length of the channel region between the source region and the drain region.
US09263540B1	Metal gate structure The metal gate structure includes at least a substrate, a dielectric layer, first and second trenches, first metal layer and second metal layers, and two cap layers. In particular, the dielectric layer is disposed on the substrate, and the first and second trenches are disposed in the dielectric layer. The width of the first trench is less than the width of the second trench. The first and second metal layers are respectively disposed in the first trench and the second trench, and the height of the first metal layer is less than or equal to the height of the second metal layer. The cap layers are respectively disposed in a top surface of the first metal layer and a top surface of the second metal layer.
US09263532B2	Semiconductor device, semiconductor substrate, method for manufacturing semiconductor device, and method for manufacturing semiconductor substrate A second epitaxial layer is grown epitaxially over a first epitaxial layer. The first epitaxial layer includes an epitaxially grown layer and a defect layer. The defect layer is disposed over the epitaxially grown layer and serves as a surface layer of the first epitaxial layer. The defect density of the defect layer is 5×1017 cm−2 or more. Defects penetrating through the defect layer form loops in the second epitaxial layer.
US09263531B2	Oxide semiconductor film, film formation method thereof, and semiconductor device An oxide semiconductor film with high crystallinity is formed. An oxide semiconductor film having a single crystal region, which is formed by a sputtering method using a sputtering target including a polycrystalline oxide containing a plurality of crystal grains, is provided. The plurality of crystal grains contained in the sputtering target has a plane that is cleaved or is likely to be cleaved because of a weak crystal bond; therefore, the cleavage planes in the plurality of crystal grains are cleaved when an ion collides with the sputtering target, whereby flat plate-like sputtered particles can be obtained. The obtained flat plate-like sputtered particles are deposited on a deposition surface; accordingly, an oxide semiconductor film is formed. The flat plate-like sputtered particle is formed by separation of part of the crystal grain and therefore the oxide semiconductor film can have high crystallinity.
US09263529B2	Semiconductor device with vertically inhomogeneous heavy metal doping profile Method of producing a vertically inhomogeneous platinum or gold distribution in a semiconductor substrate with a first and a second surface opposite the first surface, with diffusing platinum or gold into the semiconductor substrate from one of the first and second surfaces of the semiconductor substrate, removing platinum- or gold-comprising residues remaining on the one of the first and second surfaces after diffusing the platinum or gold, forming a phosphorus- or boron-doped surface barrier layer on the first or second surface, and heating the semiconductor substrate for local gettering of the platinum or gold by the phosphorus- or boron-doped surface barrier layer.
US09263527B2	Silicon carbide semiconductor device and method of manufacturing same A first impurity region is formed by ion implantation of a first impurity into a first main surface of a silicon carbide substrate. A metal layer is formed in contact with the first impurity region. By annealing the silicon carbide substrate and the metal layer, an electrode is formed. The metal layer is formed such that a concentration of a first impurity at a boundary portion between the metal layer and the first impurity region becomes less than a maximum value of a concentration of the first impurity in the first impurity region. The electrode is formed such that a concentration of the first impurity at a boundary portion between the electrode and the first impurity region becomes not less than 80% of a maximum value of a concentration of the first impurity in the first impurity region in a normal direction.
US09263524B2	Semiconductor materials, apparatuses and methods Various methods and apparatuses involving salt-based compounds and related doping are provided. In accordance with one or more embodiments, a salt-based material is introduced to a semiconductor material, and is heated to generate a neutral compound that dopes the semiconductor material. Other embodiments are directed to semiconductor materials with such a neutral compound as an impurity that affects electrical characteristics therein.
US09263522B2	Transistor with a diffusion barrier An apparatus comprises a substrate. The apparatus also comprises a diffusion barrier formed on a surface of a first region of the substrate. The diffusion barrier is formed using a first material having a first band gap energy. The apparatus further comprises a channel region formed on a surface of the diffusion barrier. The channel region is formed using a second material having a second band gap energy that is lower than the first band gap energy. The apparatus further comprises a back gate contact coupled to the first region of the substrate.
US09263521B2	Integrated circuit devices including finFETs and methods of forming the same Integrated circuit devices including Fin field effect transistors (finFETs) and methods of forming those devices are provided. The methods may include forming a fin on a substrate and forming a gate line on the fin. The method may also include forming a first recess in the fin having a first width and a first depth and forming a second recess in the first recess having a second width that is less than the first width and having a second depth that is greater than the first depth. The method may further include forming a source/drain region in the first and second recesses.
US09263518B2	Component, for example NMOS transistor, with active region with relaxed compression stresses, and fabrication method An integrated circuit includes a substrate and at least one NMOS transistor having, in the substrate, an active region surrounded by an insulating region. The insulating region is formed to includes at least one area in which the insulating region has two insulating extents that are mutually separated from each other by a separation region formed by a part of the substrate.
US09263514B2	Semiconductor device Provided is a semiconductor device having a structure with which a decrease in electrical characteristics that becomes more significant with miniaturization can be suppressed. The semiconductor device includes a first oxide semiconductor film, a gate electrode overlapping with the first oxide semiconductor film, a first gate insulating film between the first oxide semiconductor film and the gate electrode, and a second gate insulating film between the first gate insulating film and the gate electrode. In the first gate insulating film, a peak appears at a diffraction angle 2θ of around 28° by X-ray diffraction. A band gap of the first oxide semiconductor film is smaller than a band gap of the first gate insulating film, and the band gap of the first gate insulating film is smaller than a band gap of the second gate insulating film.
US09263507B2	Organic light-emitting diode (OLED) display and method for manufacturing the same An organic light-emitting diode (OLED) display having thin film transistors (TFTs) is disclosed. In one aspect, TFTs of the OLED display include a substrate and a first semiconductor layer formed over the substrate and including first channel, source, and drain regions and a lightly doped region between the first channel region and the first source and drain regions. The OLED display also includes a second semiconductor layer formed over the substrate and including second channel, source, and drain regions. The OLED display further includes first and second gate electrodes formed over the first semiconductor layer and a third gate electrode formed over the second semiconductor layer. The width of the second gate electrode is less than that of the first gate electrode and the lightly doped region overlaps a portion of the first gate electrode and does not overlap the second gate electrode.
US09263502B2	Organic light emitting element, organic light emitting display device, and method of manufacturing the organic light emitting display device A white organic light emitting element, a white organic light emitting display device, and a method of manufacturing the white organic light emitting element are provided. The organic light emitting element includes a multi-layered emission layer structure. The multi-layered emission layer structure includes a first electroluminescent layer and a second electroluminescent layer that are arranged to overlap at first area of the white organic light emitting element. The lights from the first and second electroluminescent layers collectively form white light. Among the first and second electroluminescent layers, one of the EL layers is extended out to the second area of the white organic light emitting element. A plurality of color filter elements are used to filter the white light to generate colored lights at the corresponding sub pixel regions.
US09263498B2	Method of manufacturing semiconductor device An improvement is achieved in the performance of a semiconductor device. In a method of manufacturing the semiconductor device, in an n-type semiconductor substrate, a p-type well as a p-type semiconductor region forming a part of a photodiode is formed and a gate electrode of a transfer transistor is formed. Then, after an n-type well as an n-type semiconductor region forming the other part of the photodiode is formed, a microwave is applied to the semiconductor substrate to heat the semiconductor substrate. Thereafter, a drain region of the transfer transistor is formed.
US09263497B2	Manufacturing method of back illumination CMOS image sensor device using wafer bonding Disclosed is a manufacturing method of a semiconductor device including a step of attaching semiconductor wafers together, in which it is prevented that the bonding strength between the attached semiconductor wafers may be decreased due to a void caused between the two semiconductor wafers. Moisture, etc., adsorbed to the surfaces of the semiconductor wafers is desorbed by performing a heat treatment on the semiconductor wafers after cleaning the surfaces thereof with pure water. Subsequently, after a plasma treatment is performed on the semiconductor wafers, the two semiconductor wafers are attached together. The wafers are firmly bonded together by subjecting to a high-temperature heat treatment.
US09263495B2	Image sensor and fabricating method thereof A method of fabricating an image sensor is provided. The method may include preparing a substrate with first to third pixel regions, coating a first color filter layer on the substrate, sequentially forming a first sacrificial layer and a first protection layer to cover the first color filter layer, forming a first photoresist pattern on the first protection layer to be overlapped with the first pixel region, performing a first dry etching process using the first photoresist pattern as an etch mask to the first sacrificial layer and the first protection layer to form a first color filter, a first sacrificial pattern, and a first protection pattern sequentially stacked on the first pixel region, and selectively removing the first sacrificial pattern to separate the first protection pattern from the first color filter.
US09263490B2	Methods of forming integrated circuits A solid-state imaging device includes a substrate in which a plurality of pixels including photoelectric converters are formed, a wiring layer that includes wirings in a plurality of layers formed via an interlayer insulating film in a front surface side of the substrate, a base electrode pad portion that includes a portion of the wirings formed in the wiring layer, an opening that penetrates the substrate from a rear surface side of the substrate and reaches the base electrode pad portion, and an embedded electrode pad layer that is formed so as to be embedded in the opening by electroless plating.
US09263487B2	Photoelectric conversion apparatus A photoelectric conversion apparatus includes a semiconductor substrate having a photoelectric conversion portion. An insulator is provided on the semiconductor substrate. The insulator has a hole corresponding to the photoelectric conversion portion. A waveguide member is provided in the hole. An in-layer lens is provided on a side of the waveguide member farther from the semiconductor substrate. A first intermediate member is provided between the waveguide member and the in-layer lens. The first intermediate member has a lower refractive index than the in-layer lens.
US09263482B2	Solid-state image pickup device A solid-state imaging apparatus having a plurality of pixels, comprising: a substrate; a wiring layer formed on the substrate and including an insulating film and a plurality of wires; a plurality of lower electrodes formed on the wiring layer in one-to-one correspondence with the plurality of pixels; a photoelectric conversion film formed covering the plurality of lower electrodes; a light-transmissive upper electrode formed on the photoelectric conversion film; and a shield electrode extending through a gap between each pair of adjacent lower electrodes among the plurality of lower electrodes, the shield electrode having a fixed potential and being electrically insulated from the plurality of lower electrodes.
US09263480B2	Method for fabricating array substrate of display using multiple photoresists A fabricating method of an array substrate, an array substrate and a display device are provided. The array substrate includes a substrate; a plate electrode, a gate electrode, a gate line, a gate insulating film, semiconductor silicon islands, a source electrode, a drain electrode, a data line, a slit electrode formed on the substrate, and the substrate is also provided with a gate line through hole and a data line through hole. The gate electrode and the gate line include the first transparent conductive material and gate metal material stacked sequentially; the slit electrode is directly connected to the drain electrode; a second transparent conductive material is connected to the gate line through the gate line through hole; and connected to the data line through the data line through hole.
US09263479B2	Display device and method of manufacturing the same A display device includes a display unit including a plurality of pixels respectively including thin film transistors; and a terminal unit including an array of a plurality of terminals. The display device includes a first insulating film provided on a substrate; the thin film transistors provided on the first insulating film; a second insulating film that is provided in the display unit and in the terminal unit and has openings located between the plurality of terminals; a plurality of signal lines that are provided on the second insulating film and are respectively connected to the thin film transistors, and a plurality of terminal lines that are provided on the second insulating film in the terminal unit; and a third insulating film that is located on the plurality of signal lines and the plurality of terminal lines and is formed of an organic insulating film.
US09263477B1	Tri-gate display panel A tri-gate display panel is provided, comprising: a plurality of pixel units each including three sub-pixel units for displaying different colors, wherein each sub-pixel unit is provided with a thin film transistor which has its source connected to a charge electrode of the sub-pixel unit via a capacitor of the sub-pixel unit per se; a plurality of gate lines which are successively arranged along a first direction of the display panel, so as to connect to gates of the thin film transistors of corresponding sub-pixel units; a plurality of data lines, which are successively arranged along a second direction of the display panel, so as to connect to drains of the thin film transistors of corresponding sub-pixel units; and a fanout area including a plurality of fanout lines, wherein output terminals of the plurality of fanout lines are arranged in accordance with the plurality of gate lines and are in pair-wise cross connections to the plurality of gate lines. According to the present disclosure, charging differences between different colors of sub-pixels can be reduced. Hence, color shifting of a blending picture at two sides of the panel can be avoided and display effects can be improved.
US09263476B2	Display device and method for fabricating the same An inexpensive display device, as well as an electrical apparatus employing the same, can be provided. In the display device in which a pixel section and a driver circuit are included on one and the same insulating surface, the driver circuit includes a decoder 100 and a buffer section 101. The decoder 100 includes a plurality of NAND circuits each including p-channel TFTs 104 to 106 connected to each other in parallel and other p-channel TFTs 107 to 109 connected to each other in series. The buffer section 101 includes a plurality of buffers each including three p-channel TFTs 114 to 116.
US09263471B2	Semiconductor device and semiconductor memory device An object is at least one of a longer data retention period of a memory circuit, a reduction in power consumption, a smaller circuit area, and an increase in the number of times written data can be read to one data writing operation. The memory circuit has a first field-effect transistor, a second field-effect transistor, and a rectifier element including a pair of current terminals. A data signal is input to one of a source and a drain of the first field-effect transistor. A gate of the second field-effect transistor is electrically connected to the other of the source and the drain of the first field-effect transistor. One of the pair of current terminals of the rectifier element is electrically connected to a source or a drain of the second field-effect transistor.
US09263467B2	Thin film transistor array panel and manufacturing method thereof A thin film transistor array panel according to an exemplary embodiment of the present disclosure includes: an insulating substrate; a gate electrode disposed on the insulating substrate; a gate insulating layer disposed on the gate electrode; a semiconductor disposed on the gate insulating layer; a source electrode and a drain electrode disposed on the semiconductor; an ohmic contact layer disposed at an interface between at least one of the source and drain electrodes and the semiconductor. Surface heights of the source and drain electrodes different, while surface heights of the semiconductor and the ohmic contact layer are the same. The ohmic contact layer is made of a silicide of a metal used for the source and drain electrodes.
US09263466B2	CMOS with dual raised source and drain for NMOS and PMOS An apparatus and a method for creating a CMOS with a dual raised source and drain for NMOS and PMOS. The spacers on both stack gates are of equal thickness. In this method, a first insulating layer is formed on the surface. The first region is then masked while the other region has the first layer etched away and has an epitaxial source and drain grown on the region. A second layer is formed to all exposed surfaces. The second region is then masked while the first region is etched away. The epitaxial source and drain is formed on the first region. The second region can also be masked by adding a thin layer of undoped silicon and then oxidize it. Another way to mask the second region is to use a hard mask. Another way to form the second source and drain is to use amorphous material.
US09263465B2	CMOS with dual raised source and drain for NMOS and PMOS An apparatus and a method for creating a CMOS with a dual raised source and drain for NMOS and PMOS. The spacers on both stack gates are of equal thickness. In this method, a first insulating layer is formed on the surface. The first region is then masked while the other region has the first layer etched away and has an epitaxial source and drain grown on the region. A second layer is formed to all exposed surfaces. The second region is then masked while the first region is etched away. The epitaxial source and drain is formed on the first region. The second region can also be masked by adding a thin layer of undoped silicon and then oxidize it. Another way to mask the second region is to use a hard mask. Another way to form the second source and drain is to use amorphous material.
US09263460B2	Methods and apparatuses including a select transistor having a body region including monocrystalline semiconductor material and/or at least a portion of its gate located in a substrate Some embodiments include apparatuses and methods having a memory cell string including memory cells located in different levels of the apparatuses and a select transistor coupled to the memory cell string. In at least one of such apparatuses, the select transistor can include a body region including a monocrystalline semiconductor material. Other embodiments including additional apparatuses and methods are described.
US09263459B1	Capping poly channel pillars in stacked circuits A three dimensional or stacked circuit device includes a conductive channel cap on a conductor channel. The channel cap can be created via selective deposition or other process to prevent polishing down the conductive material to isolate the contacts. The conductor channel extends through a deck of multiple tiers of circuit elements that are activated via a gate. The gate is activated by electrical potential in the conductor channel. The conductive cap on the conductor channel can electrically connect the conductor channel to a bitline or other signal line, and/or to another deck of multiple circuit elements.
US09263458B2	Non-volatile memory having charge storage layer and control gate According to one embodiment, a non-volatile memory includes a first non-volatile memory cell and a first selected transistor. A first cell block is formed by connecting a plurality of first non-volatile memory cells in series. An area S1 of the first insulating film at which the first floating gate is in contact with the first silicon channel is larger than an area S2 of the second insulating film at which the first floating gate is in contact with the first gate electrode.
US09263453B1	Secondary use of aspect ratio trapping holes as eDRAM structure A semiconductor structure is provided according to a method in which an aspect ratio trapping process is employed. The structure includes a semiconductor substrate comprising a first semiconductor material having a first lattice constant. A first layer of second semiconductor material formed on the substrate, the first layer having a second lattice constant that is greater than the first lattice constant. A second layer of a semi-insulating, third semiconductor material is formed atop a top surface of the first layer. A transistor device is formed on top of the second layer. An eDRAM structure is connected electronically with a channel region of the transistor device, the eDRAM structure extending from the channel region of the transistor device to a sub-surface below a top surface of the semiconductor substrate.
US09263450B2	OTP memory cell and fabricating method thereof A one-time programmable (OTP) memory cell is provided, which includes: a well of a first conductivity type; a gate insulating layer formed on the well and including first and second fuse regions; a gate electrode of a second conductivity type formed on the gate insulating layer, the second conductivity type being opposite in electric charge to the first conductivity type; a junction region of the second conductivity type formed in the well and arranged to surround the first and second fuse regions; and an isolation layer formed in the well between the first fuse region and the second fuse region.
US09263447B2	Semiconductor device A semiconductor device, including: a P-type substrate; an N-type region, contacting with the P-type substrate; a N+-type doped region, disposed in the N-type region; a first P+-type doped region, disposed in the N-type region; a second P+-type doped region, disposed in the N-type region; a P-type buried layer, disposed in the P-type substrate under the N-type region and contacting with the N-type region; and a N-type doped region, disposed in the P-type substrate under a contact surface between the P-type buried layer and the N-type region.
US09263445B2	Method of fabricating dual high-k metal gates for MOS devices The present disclosure provides a method of fabricating a semiconductor device. The method includes providing a semiconductor substrate having a first region and a second region, forming a high-k dielectric layer over the semiconductor substrate, forming a capping layer over the high-k dielectric layer in the first region, forming a first metal layer over capping layer in the first region and over the high-k dielectric in the second region, thereafter, forming a first gate stack in the first region and a second gate stack in the second region, protecting the first metal layer in the first gate stack while performing a treatment process on the first metal layer in the second gate stack, and forming a second metal layer over the first metal layer in the first gate stack and over the treated first metal layer in the second gate stack.
US09263443B2	Semiconductor device including a normally-off transistor and transistor cells of a normally-on GaN HEMT A semiconductor device includes a first semiconductor die including a normally-off transistor and a second semiconductor die including a plurality of transistor cells of a normally-on GaN HEMT. One of a source terminal and a drain terminal of the normally-off transistor is electrically coupled to a gate terminal of the normally-on GaN HEMT, and the other one of the source terminal and the drain terminal of the normally-off transistor is electrically coupled to one of a source terminal and a drain terminal of the normally-on GaN HEMT. The second semiconductor die further includes a gate resistor electrically coupled between the gate terminal of the normally-off transistor and respective gates of the plurality of transistor cells, and a voltage clamping element electrically coupled between the gate terminal and one of the source terminal and the drain terminal of the normally-on GaN HEMT.
US09263439B2	III-nitride switching device with an emulated diode Some exemplary embodiments of a III-nitride switching device with an emulated diode have been disclosed. One exemplary embodiment comprises a GaN switching device fabricated on a substrate comprising a high threshold GaN transistor coupled across a low threshold GaN transistor, wherein a gate and a source of the low threshold GaN transistor are shorted with an interconnect metal to function as a parallel diode in a reverse mode. The high threshold GaN transistor is configured to provide noise immunity for the GaN switching device when in a forward mode. The high threshold GaN transistor and the low threshold GaN transistor are typically fabricated on the same substrate, and with significantly different thresholds. As a result, the superior switching characteristics of III-nitride devices may be leveraged while retaining the functionality and the monolithic structure of the inherent body diode in traditional silicon FETs.
US09263438B2	Apparatus related to a diode device including a JFET portion In one general aspect, an apparatus can include an anode terminal, and a cathode terminal. The apparatus can include a junction field-effect transistor (JFET) portion having a channel disposed within a semiconductor substrate and defining a first portion of an electrical path between the anode terminal and the cathode terminal. The apparatus can also include a diode portion formed within the semiconductor substrate and defining a second portion of the electrical path between the anode terminal and the cathode terminal. The diode portion can be serially coupled to the channel of the JFET device.
US09263437B2	Mechanisms for forming metal-insulator-metal (MIM) capacitor structure Embodiments of mechanisms for forming a metal-insulator-metal (MIM) capacitor structure are provided. The metal-insulator-metal capacitor structure includes a substrate. The MIM capacitor structure also includes a CBM layer formed on the substrate, and the CBM layer includes a bottom barrier layer, a main metal layer and a top barrier layer. The MIM capacitor structure further includes a first high-k dielectric layer formed on the CBM layer, an insulating layer formed on the first high-k dielectric layer and a second high-k dielectric layer formed on the insulating layer. The MIM capacitor structure also includes a CTM layer formed on the second high-k dielectric layer, and the CBM layer includes a bottom barrier layer, a main metal layer and a top barrier layer.
US09263436B2	Semiconductor device and method for fabricating the same A semiconductor device includes: a semiconductor layer; a first doped well region disposed in a portion of the semiconductor layer; a first doped region disposed in the first doped well region; a second doped well region of an asymmetrical cross-sectional profile disposed in another portion of the semiconductor layer; second, third, and fourth doped regions formed in the second doped well region; a first gate structure disposed over a portion of the semiconductor layer, practically covering the second doped well region; and a second gate structure embedded in a portion of the semiconductor layer, penetrating a portion of the second doped well region.
US09263435B2	Switching element with a series-connected junction FET (JFET) and MOSFET achieving both improved withstand voltage and reduced on-resistance Technology capable of improving reliability of a semiconductor device is provided. In the present invention, a gate pad GPj formed on a front surface of a semiconductor chip CHP1 is disposed so as to be closer to a source lead SL than to other leads (a drain lead DL and a gate lead GL). As a result, according to the present invention, a distance between the gate pad GPj and the source lead SL can be shortened, and thus a length of the wire Wgj for connecting the gate pad GPj and the source lead SL together can be shortened. Thus, according to the present invention, a parasitic inductance that is present in the wire Wgj can be sufficiently reduced.
US09263434B2	Array substrate, display apparatus having the same and method of manufacturing the same An array substrate includes a substrate, a dummy pad and a driving signal output line. The substrate includes a display area displaying an image, and a peripheral area surrounding the display area. The dummy pad extends along a first direction in the peripheral area of the substrate, and includes a first protrusion portion protruding from an end portion of the dummy pad along the first direction. The driving signal output line extends along a second direction crossing with the first direction, is disposed adjacent to the dummy pad, and provides an external signal. Accordingly static electricity provided to the driving signal output line flows into the dummy pad having the first protrusion portion, so that static electricity may be prevented from flowing into the display area.
US09263428B2	Diode biased ESD protection device and method An ESD protection device includes an MOS transistor with a source region, drain region and gate region. A node designated for ESD protection is electrically coupled to the drain. A diode is coupled between the gate and source, wherein the diode would be reverse biased if the MOS transistor were in the active operating region.
US09263426B2	PoP structure with electrically insulating material between packages A PoP (package-on-package) package includes a bottom package coupled to a top package. Terminals on the top of the bottom package are coupled to terminals on the bottom of the top package with an electrically insulating material located between the upper surface of the bottom package and the lower surface of the top package. The bottom package and the top package are coupled during a process that applies force to bring the packages together while heating the packages.
US09263425B2	Semiconductor device including multiple semiconductor chips and a laminate A semiconductor device includes a laminate, a first semiconductor chip at least partly embedded in the laminate, a second semiconductor chip mounted on a first main surface of the laminate, and a first electrical contact arranged on the first main surface of the laminate. The second semiconductor chip is electrically coupled to the first electrical contact.
US09263421B2	Semiconductor device having multiple chips mounted to a carrier A semiconductor device includes a chip carrier having a first surface and a second surface opposite to the first surface. The device further includes a first semiconductor chip mounted on the first surface of the chip carrier. A second semiconductor chip is mounted on the second surface of the chip carrier, wherein a portion of a first surface of the second semiconductor chip which faces the chip carrier projects over an edge of the chip carrier. A first electrical conductor is coupled to an electrode formed on the portion of the first surface of the second semiconductor chip that projects over the edge of the chip carrier.
US09263420B2	Devices and stacked microelectronic packages with package surface conductors and methods of their fabrication Embodiments of methods for forming a device include performing an oxidation inhibiting treatment to exposed ends of first and second device-to-edge conductors, and forming a package surface conductor to electrically couple the exposed ends of the first and second device-to-edge conductors. Performing the oxidation inhibiting treatment may include applying an organic solderability protectant coating to the exposed ends, or plating the exposed ends with a conductive plating material. The method may further include applying a conformal protective coating over the package surface conductor. An embodiment of a device formed using such a method includes a package body, the first and second device-to-edge conductors, the package surface conductor on a surface of the package body and extending between the first and second device-to-edge conductors, and the conformal protective coating over the package surface conductor.
US09263419B2	Lead frame strips with electrical isolation of die paddles A lead frame strip includes connected unit lead frames each having a die paddle, a tie bar directly connecting the die paddle to a periphery of the unit lead frame, leads directly connected to the periphery of the unit lead frame and projecting toward the die paddle, and an opening in the periphery adjacent the tie bar. The openings in the periphery of the unit lead frames are spanned with an electrically insulating material that connects the tie bar of each unit lead frame to the periphery of the unit lead frame. The direct connections between the tie bars and the periphery of the unit lead frames are severed prior to subsequent processing, so that the tie bars remain connected to the periphery of the unit lead frames by the electrically insulating material and the die paddles are electrically disconnected from the periphery of the unit lead frames.
US09263418B2	Semiconductor device and manufacturing method thereof According to one embodiment, a semiconductor device includes a first loop and a second loop. A folded-back portion is a portion formed by stretching out the first loop from a first bond in a first direction and then folding it back in a second direction. The folded-back portion is in a shape in which it is squashed against the first bond. The second loop is bonded to the folded-back portion. An end of the second loop is located at a second position. The second position is offset in a direction in which the first loop extends, from a first position. The first position is the center of the first bond of the first loop.
US09263417B2	Semiconductor packages including a multi-layered dielectric layer and methods of manufacturing the same The embedded package includes a semiconductor chip having contact portions disposed on a top surface thereof, a first dielectric layer substantially surrounding sidewalls of the semiconductor chip and including first fillers dispersed therein, a second dielectric layer substantially covering the top surface of the semiconductor chip and including second fillers dispersed therein, and first external interconnection portions disposed on the second dielectric layer and electrically connected to the contact portions, wherein an average size of the first fillers is different from that of the second fillers.
US09263416B2	Methods and materials useful for chip stacking, chip and wafer bonding Materials, and methods that use such materials, that are useful for forming chip stacks, chip and wafer bonding and wafer thinning are disclosed. Such methods and materials provide strong bonds while also being readily removed with little or no residues.
US09263410B2	Chip detecting system and detecting method A chip detecting system is disclosed. The system includes a ball grid array (BGA) chip and a circuit board, the BGA chip includes at least two functional pins being located at a corner of the BGA chip, the at least two functional pins are electrically connected to each other, the circuit board is provided with at least two solder pads and at least two testing pads, the at least two functional pins are electrically connected to the at least two solder pads by using solder balls separately, the solder pads are electrically connected to the testing pads separately, and the at least two testing pads are configured to electrically connect to a detector, so as to detect whether a crack exists between the at least two functional pins and the circuit board.
US09263406B2	Semiconductor device and method for manufacturing semiconductor device A semiconductor device according to the present invention includes a semiconductor chip having a front surface and a rear surface, a sealing resin layer stacked on the front surface of the semiconductor chip, a post passing through the sealing resin layer in the thickness direction and having a side surface flush with a side surface of the sealing resin layer and a forward end surface flush with a front surface of the sealing resin layer, and an external connecting terminal provided on the forward end surface of the post.
US09263405B2	Semiconductor device A semiconductor device having a semiconductor substrate is provided. The semiconductor substrate includes an integrated circuit, which includes multi-layer structured metallization and inter-metal dielectric. The integrated circuit is below a passivation, which is over a metal structure. The metal structure includes a metal pad and an under bumper metallurgy, which is over and aligned with the metal pad. The metal pad is electrically connected to the integrated circuit, and the under bumper metallurgy is configured to electrically connect to a conductive component of another semiconductor device. The integrated circuit further includes a conductive trace, which is below and aligned with the metal structure. The conductive trace is connected to a power source such that an electromagnetic field is generated at the conductive trace when an electric current from the power source passes through the conductive trace.
US09263403B2	Semiconductor device having high frequency wiring and dummy metal layer at multilayer wiring structure A semiconductor device includes a semiconductor substrate, a first wiring layer including a plurality of first dummy metals provided inside an inductor wiring, a plurality of second dummy metals provided outside the inductor wiring, and a plurality of third dummy metals provided to overlap the inductor wiring in a plan view, and a second wiring layer provided between the semiconductor substrate and the first wiring layer. The second wiring layer includes the inductor wiring formed in the second wiring layer, a first region surrounding the inductor wiring which includes a plurality of fourth dummy metals, and a second region surrounding the first region which includes a plurality of fifth dummy metals. A density of the fourth dummy metals is lower than a density of the fifth dummy metals.
US09263399B2	Semiconductor device with electro-static discharge protection device above semiconductor device area A semiconductor device includes a semiconductor substrate on which a semiconductor device is formed; first and second pads; a first insulating film which is formed above the semiconductor substrate; a plurality of wiring lines which are embedded in ditches provided in the first insulating film; a second insulating film provided to cover the first insulating film and the plurality of wiring lines; a semiconductor layer formed on the second insulating film; a source electrode connected with the semiconductor layer; and a drain electrode connected with the semiconductor layer. The plurality of wiring lines includes a gate electrode provided in a position which is opposite to the semiconductor layer. The semiconductor layer, the source electrode, the drain electrode and the gate electrode configure an ESD protection device to discharge a current by ESD surge from the first pad to the second pad.
US09263397B2	Wafer mapping process control with indicator line A method for providing alignment in a die picking process may include aligning a semiconductor wafer based on a reference die, forming an indicator line relative to the reference die by picking a number of dice along a line extending across the wafer, and using the reference line to monitor a position of the picking machine relative to the wafer. A die attach machine may include a control system for automatically implementing such method.
US09263388B2	Overlay-tolerant via mask and reactive ion etch (RIE) technique A method is provided that includes first etching a substrate according to a first mask. The first etching forms a first etch feature in the substrate to a first depth. The first etching also forms a sliver opening in the substrate. The sliver opening may then be filled with a fill material. A second mask may be formed by removing a portion of the first mask. The substrate exposed by the second mask may be etched with a second etch, in which the second etching is selective to the fill material. The second etching extends the first etch feature to a second depth that is greater than the first depth, and the second etch forms a second etch feature. The first etch feature and the second etch feature may then be filled with a conductive metal.
US09263383B2	Anti-fuse array of semiconductor device and method for operating the same An anti-fuse array includes: a plurality of first transistors having a matrix structure over a semiconductor substrate; a plurality of second transistors respectively disposed adjacent to first ends of the plurality of first transistors along a first direction of the matrix structure; and a plurality of third transistors respectively disposed at second ends of the plurality of first transistors along a second direction.
US09263375B2	System, method and apparatus for leadless surface mounted semiconductor package A packaged semiconductor device may include a termination surface having terminations configured as leadless interconnects to be surface mounted to a printed circuit board. A first flange has a first surface and a second surface. The first surface provides a first one of the terminations, and the second surface is opposite to the first surface. A second flange also has a first surface and a second surface, with the first surface providing a second one of the terminations, and the second surface is opposite to the first surface. A die is mounted to the second surface of the first flange with a material having a melting point in excess of 240° C. An electrical interconnect extends between the die and the second surface of the second flange opposite the termination surface, such that the electrical interconnect, first flange and second flange are substantially housed within a body.
US09263373B2	Thin film RDL for nanochip package A high density film adapted for nanochip package comprises three redistribution layers. A bottom redistribution circuit has a plurality of first bottom pads adapted for a nanochip to mount; and has a plurality of first top pads. The density of the first bottom pads is higher than the density of the first top pads. A middle redistribution circuit has a plurality of second bottom pads electrically coupled to the first top pads; and has a plurality of second top pads. The density of the second bottom pads is higher than the density of the second top pads. A top redistribution circuit has a plurality of third bottom pads electrically coupled to the second top pads; and has a plurality of third top pads. The density of the third bottom pads is higher than the density of the third top pads.
US09263370B2	Semiconductor device with via bar A semiconductor device comprising a second surface of a logic die and a second surface of a via bar coupled to a first surface of a substrate, a second surface of a memory die coupled to a first surface of the via bar, a portion of the second surface of the memory die extending over the first surface of the logic die, such that the logic die and the memory die are vertically staggered, and the memory die electrically coupled to the logic die through the via bar. The via bar can be formed from glass, and include through-glass vias (TGVs) and embedded passives such as resistors, capacitors, and inductors. The semiconductor device can be formed as a single package or a package-on-package structure with the via bar and the memory die encapsulated in a package and the substrate and logic die in another package.
US09263366B2	Liquid cooling of semiconductor chips utilizing small scale structures A semiconductor assembly for use with forced liquid and gas cooling. A relatively rigid nano-structure (for example, array of elongated nanowires) extends from an interior surface of a cap toward a top surface of a semiconductor chip, but, because of the rigidness and structural integrity of the nano-structure built into the cap, and of the cap itself, the nano-structure is reliably spaced apart from the top surface of the chip, which helps allow for appropriate cooling fluid flows. The cap piece and nano-structures built into the cap may be made of silicon or silicon compounds.
US09263364B2	Thermal interface material with support structure Various semiconductor chip thermal interface material methods and apparatus are disclosed. In one aspect, a method of establishing thermal contact between a first semiconductor chip and a heat spreader is provided. The method includes placing a thermal interface material layer containing a support structure on the first semiconductor chip. The heat spreader is positioned proximate the thermal interface material layer. The thermal interface material layer is reflowed to establish thermal contact with both the first semiconductor chip and the heat spreader.
US09263363B2	Self orienting micro plates of thermally conducting material as component in thermal paste or adhesive The present invention relates generally to thermally-conductive pastes for use with integrated circuits, and particularly, but not by way of limitation, to self-orienting microplates of graphite.
US09263354B2	Pillar structure having cavities An apparatus comprises a pillar formed on a top surface of a semiconductor substrate, wherein the pillar comprises a first pillar region, a second pillar region and a first cavity formed between the first pillar region and the second pillar region, and wherein the first cavity is configured to accommodate a probe pin.
US09263350B2	Multi-station plasma reactor with RF balancing Methods and apparatus for multi-station semiconductor deposition operations with RF power frequency tuning are disclosed. The RF power frequency may be tuned according to a measured impedance of a plasma during the semiconductor deposition operation. In certain implementations of the methods and apparatus, a RF power parameter may be adjusted during or prior to the deposition operation. Certain other implementations of the semiconductor deposition operations may include multiple different deposition processes with corresponding different recipes. The recipes may include different RF power parameters for each respective recipe. The respective recipes may adjust the RF power parameter prior to each deposition process. RF power frequency tuning may be utilized during each deposition process.
US09263348B2	Film thickness metrology Methods for determining a target thickness of a conformal film with reduced uncertainty, and an integrated circuit (IC) chip having a conformal film of the target thickness are provided. In an embodiment, a first critical dimension of a structure disposed on a wafer is measured. Said structure has at least one vertical surface. A first conformal film is deposited over the structure covering each of a horizontal and the vertical surface of the structure. A second critical dimension of the covered structure is then measured. The target thickness of the conformal film is determined based on difference between the first CD measured on the structure and the second CD measured on the covered structure.
US09263346B2	Semiconductor device with silicon layer containing carbon A semiconductor device having an n channel MISFET formed on an SOI substrate including a support substrate, an insulating layer formed on the support substrate and a silicon layer formed on the insulating layer has the following structure. An impurity region for threshold adjustment is provided in the support substrate of a gate electrode so that the silicon layer contains carbon. The threshold value can be adjusted by the semiconductor region for threshold adjustment in this manner. Further, by providing the silicon layer containing carbon, even when the impurity of the semiconductor region for threshold adjustment is diffused to the silicon layer across the insulating layer, the impurity is inactivated by the carbon implanted into the silicon layer. As a result, the fluctuation of the transistor characteristics, for example, the fluctuation of the threshold voltage of the MISFET can be reduced.
US09263344B2	Low threshold voltage CMOS device A replacement metal gate process in which a high-k dielectric is applied. The high-k dielectric may be doped with lanthanum in an NMOS region or aluminum in a PMOS region. Alternatively, after a dummy gate is removed in the NMOS and PMOS regions to leave openings in the NMOS and PMOS regions, lanthanum oxide may be deposited in the NMOS opening or aluminum oxide deposited in the PMOS opening. Thereafter, first work function metals are deposited in the NMOS opening and second work function metals are applied in the PMOS openings. A suitable gate electrode material may then fill the remainder of the NMOS and PMOS openings.
US09263343B2	Dual EPI CMOS integration for planar substrates Silicon germanium regions are formed adjacent gates electrodes over both n-type and p-type regions in an integrated circuit. A hard mask patterned by lithography then protects structures over the p-type region while the silicon germanium is selectively removed from over the n-type region, even under remnants of the hard mask on sidewall spacers on the gate electrode. Silicon germanium carbon is epitaxially grown adjacent the gate electrode in place of the removed silicon germanium, and source/drain extension implants are performed prior to removal of the remaining hard mask over the p-type region structures.
US09263341B2	Methods of forming transistors Some embodiments include methods of forming transistors. Recesses are formed to extend into semiconductor material. The recesses have upper regions lined with liner material and have segments of semiconductor material exposed along lower regions. Semiconductor material is isotropically etched through the exposed segments which transforms the recesses into openings having wide lower regions beneath narrow upper regions. Gate dielectric material is formed along sidewalls of the openings. Gate material is formed within the openings and over regions of the semiconductor material between the openings. Insulative material is formed down the center of each opening and entirely through the gate material. A segment of gate material extends from one of the openings to the other, and wraps around a pillar of the semiconductor material between the openings. The segment is a gate of a transistor. Source/drain regions are formed on opposing sides of the gate.
US09263338B2	Semiconductor device including vertically spaced semiconductor channel structures and related methods A method for making a semiconductor device may include forming, on a substrate, at least one stack of alternating first and second semiconductor layers. The first semiconductor layer may comprise a first semiconductor material and the second semiconductor layer may comprise a second semiconductor material. The first semiconductor material may be selectively etchable with respect to the second semiconductor material. The method may further include removing portions of the at least one stack and substrate to define exposed sidewalls thereof, forming respective spacers on the exposed sidewalls, etching recesses through the at least one stack and substrate to define a plurality of spaced apart pillars, selectively etching the first semiconductor material from the plurality of pillars leaving second semiconductor material structures supported at opposing ends by respective spacers, and forming at least one gate adjacent the second semiconductor material structures.
US09263333B2	Wafer processing laminate, wafer processing member, temporary adhering material for processing wafer, and manufacturing method of thin wafer A wafer processing laminate, a wafer processing member, a temporary adhering material for processing a wafer, and a method for manufacturing a thin wafer, which facilitates to establish a temporary adhering the wafer and the support, enables to form a layer of uniform thickness on a heavily stepped substrate, and is compatible with the TSV formation and wafer back surface interconnect forming steps, and the wafer processing laminate includes a support, a temporary adhesive material layer formed thereon and a wafer laminated on the temporary adhesive material layer, where the wafer has a circuit-forming front surface and a back surface to be processed, wherein the temporary adhesive material layer includes a three-layered structure composite temporary adhesive material layer.
US09263331B2	Method for forming self-aligned contacts/vias with high corner selectivity A method of etching self-aligned contact/via features in a low-k dielectric layer disposed below a hardmask, which is disposed below a planarization layer. At least one cycle is provided, where each cycle comprises thinning the planarization layer, forming a deposition layer on the hardmask and planarization layer; and etching the low-k dielectric layer masked by the deposition layer.
US09263329B2	Methods of connecting a first electronic package to a second electronic package A method of fabricating an electronic package. The method includes filling a mold with an electric conductor to form a number of electrical interconnects within the mold. The mold includes openings that are filled with several electric conductors to form a number of electrical interconnects. The method of fabricating an electronic package further includes attaching the mold to a substrate such that the electrical interconnects engage electrical contacts on the substrate. The method of fabricating an electronic package may further include forming conductive pads on the electrical insulator that engage the electrical interconnects and attaching a die to the substrate such that the die is electrically connected to at least some of the electrical interconnects.
US09263327B2	Minimizing void formation in semiconductor vias and trenches Circuit structure fabrication methods are provided which include: patterning at least one opening within a dielectric layer disposed over a substrate structure; providing a liner material within the at least one opening of the dielectric layer; disposing a surfactant over at least a portion of the liner material; and depositing, using an electroless process, a conductive material over the liner material to form a conductive structure, and the disposed surfactant inhibits formation of a void within the conductive structure.
US09263320B2	Method of manufacturing semiconductor device An object of the invention is to provide a semiconductor device having improved performance. A method of manufacturing a semiconductor device includes: forming a trench and then forming a first insulating film made of a silicon oxide film through CVD using a gas containing an O3 gas and a TEOS gas to cover the side surface of the trench with the insulating film; forming a second insulating film made of a silicon oxide film through PECVD to cover the side surface of the trench with the second insulating film via the first insulating film; and forming a third insulating film made of a silicon oxide film through CVD using a gas containing an O3 gas and a TEOS gas to close the trench with the third insulating film while leaving a space in the trench.
US09263319B2	Semiconductor memory device and method for manufacturing the same According to one embodiment, a semiconductor memory device includes a plurality of stacked bodies and a spacer film provided on a side surface of the stacked bodies. Each of the plurality of stacked bodies includes a silicon electrode and a metal electrode stacked on the metal electrode. The plurality of stacked bodies are separated from each other by an air gap. The spacer film includes silicon oxide. A portion of the spacer film disposed on a side surface of the metal electrode is thicker than a portion of the spacer film disposed on a side surface of the silicon electrode.
US09263313B2	Plasma processing apparatus and plasma processing method A plasma processing apparatus is provided which includes a processing chamber disposed in a vacuum container, in a decompressed inside of which plasma is formed, a sample stage disposed in a lower part of the processing chamber, on a top surface of which a sample is mounted, a dielectric film made of a dielectric that forms a mounting surface on which the sample is mounted, and electrodes arranged inside the dielectric film and supplied with power for chucking and holding the sample onto the dielectric film, and when the sample is mounted on the sample stage, the sample is kept mounted on the sample stage until a sample temperature becomes a predetermined temperature or until a predetermined time elapses, and power is then supplied to the electrodes to chuck the sample to the sample stage and then start processing on the sample using the plasma.
US09263310B2	Substrate treating apparatus and substrate treating method A substrate treating apparatus is provided. The substrate treating apparatus includes a loading/unloading unit, a process unit in which a substrate treating process is performed, a loadlock unit disposed between the loading/unloading unit and the process unit, and a carrying member transferring a substrate between the process unit and the loadlock unit. Herein, the carrying member is provided in the process unit and the loadlock unit, and the loading/unloading unit, the loadlock unit, and the process unit are sequentially disposed.
US09263306B2	Protective layer for charged particle beam processing A protective layer is applied to a work piece to protect the surface during charged particle beam processing by directing a fluid toward the surface. The surface is preferably not touched by the applicator. Ink jet print-type print heads are suitable applicators. Ink jet-type print heads allow a wide variety of fluids to be used to form the protective layer. Useful fluids that form protective layers include colloidal silica having small silver particles and hydrocarbon-based inks.
US09263304B2	Manufacturing method of semiconductor device Suppressed is damage of a semiconductor wafer due to charging of a cleaning liquid used in a single wafer type wafer cleaning step.A chemical solution discharged from a tip of a cleaning nozzle is brought into contact with protrusions of wafer chucks to thereby let static electricity of the chemical solution go to the wafer chucks, and subsequently, the cleaning nozzle is moved above the wafer to supply the chemical solution onto a top surface of the wafer, thereby suppressing abnormal discharge (damage) of the wafer due to charging of the chemical solution.
US09263303B2	Methodologies for rinsing tool surfaces in tools used to process microelectronic workpieces Rinsing methodologies and components to accomplish rinsing of tool surfaces in tools that are used to process one or more microelectronic workpieces. The invention can be used to rinse structures that overlie a workpiece being treated in such a manner to function in part as a lid over the process chamber while also defining a tapering flow channel over the workpiece. Rather than spray rinsing liquid onto the surface in a manner that generates undue splashing, droplet, or mist generation, a swirling flow of rinse liquid is generated on a surface of at least one fluid passage upstream from the surface to be rinsed. The swirling flow then provides smooth, uniform wetting and sheeting action to accomplish rinsing with a significantly reduced risk of generating particle contamination.
US09263301B2	Semiconductor device and method of forming Fo-WLCSP with discrete semiconductor components mounted under and over semiconductor die A semiconductor die has first and second discrete semiconductor components mounted over a plurality of wettable contact pads formed on a carrier. Conductive pillars are formed over the wettable contact pads. A semiconductor die is mounted to the conductive pillars over the first discrete components. The conductive pillars provide vertical stand-off of the semiconductor die as headroom for the first discrete components. The second discrete components are disposed outside a footprint of the semiconductor die. Conductive TSV can be formed through the semiconductor die. An encapsulant is deposited over the semiconductor die and first and second discrete components. The wettable contact pads reduce die and discrete component shifting during encapsulation. A portion of a back surface of the semiconductor die is removed to reduce package thickness. An interconnect structure is formed over the encapsulant and semiconductor die. Third discrete semiconductor components can be mounted over the semiconductor die.
US09263292B2	Processing for overcoming extreme topography A process for overcoming extreme topographies by first planarizing a cavity in a semiconductor substrate in order to create a planar surface for subsequent lithography processing. As a result of the planarizing process for extreme topographies, subsequent lithography processing is enabled including the deposition of features in close proximity to extreme topographic surfaces (e.g., deep cavities or channels) and, including the deposition of features within a cavity. In a first embodiment, the process for planarizing a cavity in a semiconductor substrate includes the application of dry film resists having high chemical resistance. In a second embodiment, the process for planarizing a cavity includes the filling of cavity using materials such as polymers, spin on glasses, and metallurgy.
US09263285B2	Composition for forming a resist underlayer film including hydroxyl group-containing carbazole novolac resin There is provided a composition for forming a resist underlayer film having heat resistance for use in a lithography process in semiconductor device production. A composition for forming a resist underlayer film, comprising a polymer that contains a unit structure of formula (1) and a unit structure of formula (2) in a proportion of 3 to 97:97 to 3 in molar ratio: A method for producing a semiconductor device, including the steps of: forming an underlayer film using the composition for forming a resist underlayer film on a semiconductor substrate; forming a hard mask on the underlayer film; further forming a resist film on the hard mask; forming a patterned resist film and developing; etching the hard mask according to the patterned resist film; etching the underlayer film according to the patterned hard mask; and processing the semiconductor substrate according to the patterned underlayer film.
US09263282B2	Method of fabricating semiconductor patterns A method of fabricating semiconductor patterns includes steps as follows: Firstly, a substrate is provided and has at least a first semiconductor pattern and at least a second semiconductor pattern, wherein a line width of the first semiconductor pattern is identical to a line width of the second semiconductor pattern. Then, a barrier pattern is formed over a surface of the first semiconductor pattern, and the second semiconductor pattern is exposed. Then, a surface portion of the second semiconductor pattern is reacted to form a sacrificial structure layer. Then, the barrier pattern and the sacrificial structure layer are removed, and the line width of the second semiconductor pattern is shrunken to be less than the line width of the first semiconductor pattern. A third semiconductor pattern having a line width can be further provided.
US09263281B2	Contact plug and method for manufacturing the same A method for manufacturing a contact plug is provided. The method includes providing a silicon substrate having at least one opening. A titanium layer is conformably formed in the opening. A first barrier layer is conformably formed on the titanium layer in the opening. A rapid thermal process is performed on the titanium layer and the first barrier layer. After performing the rapid thermal process, a second barrier layer is conformably formed on the first barrier layer in the opening.
US09263279B2	Combining cut mask lithography and conventional lithography to achieve sub-threshold pattern features Features are fabricated on a semiconductor chip. The features are smaller than the threshold of the lithography used to create the chip. A method includes patterning a first portion of a feature (such as a local interconnect) and a second portion of the feature to be separated by a predetermined distance, such as a line tip to tip space or a line space. The method further includes patterning the first portion with a cut mask to form a first sub-portion (e.g., a contact) and a second sub-portion. A dimension of the first sub-portion is less than a dimension of a second predetermined distance, which may be a line length resolution of a lithographic process having a specified width resolution. A feature of a semiconductor device includes a first portion and a second portion having a dimension less than a lithographic resolution of the first portion.
US09263277B2	Metal gate structure of a semiconductor device The disclosure relates to integrated circuit fabrication, and more particularly to a metal gate structure. An exemplary structure for a semiconductor device comprises a substrate comprising an isolation region separating and surrounding both a P-active region and an N-active region; a P-work function metal layer in a P-gate structure over the P-active region, wherein the P-work function metal layer comprises a first bottom portion and first sidewalls, wherein the first bottom portion comprises a first layer of metallic compound with a first thickness; and an N-work function metal layer in an N-gate structure over the N-active region, wherein the N-work function metal layer comprises a second bottom portion and second sidewalls, wherein the second bottom portion comprises a second layer of the metallic compound with a second thickness less than the first thickness.
US09263274B2	Method for manufacturing semiconductor device In QFN packages for vehicles which are required to have high reliability, the side surface of leads is mostly covered with lead-to-lead resin protrusions, which prevent smooth formation of solder fillets during reflow mounting. When the lead-to-lead protrusions are mechanically removed using a punching die, there is a high possibility of causing cracks of the main body of the package or terminal deformation. When a spacing is provided between the punching die and the main body of the package in order to avoid such damages, a resin residue is produced to hinder complete removal of this lead-to-lead resin protrusion. The present invention provides a method for manufacturing semiconductor device of a QFN type package using multiple leadframes having a dam bar for tying external end portions of a plurality of leads. This method includes a step of removing a sealing resin filled between the circumference of a mold cavity and the dam bar by using laser and then carrying out surface treatment, for example, solder plating.
US09263271B2	Method for processing a semiconductor carrier, a semiconductor chip arrangement and a method for manufacturing a semiconductor device A method for processing a semiconductor carrier is provided, the method including: providing a semiconductor carrier including a doped substrate region and a device region disposed over a first side of the doped substrate region, the device region including at least part of one or more electrical devices; and implanting ions into the doped substrate region to form a gettering region in the doped substrate region of the semiconductor carrier.
US09263268B2	Joining device, joining system and joining method A joining device for joining substrates with an intermolecular force includes a first holding unit configured to hold a first substrate on a lower surface thereof, a second holding unit installed below the first holding unit and configured to hold a second substrate on an upper surface thereof, and a temperature adjustment mechanism configured to adjust a temperature of the first substrate before the first substrate is held in the first holding unit and a temperature of the second substrate before the second substrate is held in the second holding unit to a predetermined temperature.
US09263258B2	Method for producing group III nitride-based compound semiconductor, wafer, and group III nitride-based compound semiconductor device Provided is a method for producing a Group III nitride-based compound semiconductor having an M-plane main surface. The method employs a sapphire substrate having a main surface which is inclined by 30° with respect to R-plane about a line of intersection Lsapph-AM formed by R-plane and A-plane perpendicular thereto. R-plane surfaces of the sapphire substrate are exposed, and a silicon dioxide mask is formed on the main surface of the substrate. AlN buffer layers are formed on the exposed R-plane surfaces. A GaN layer is formed on the AlN buffer layers. At an initial stage of GaN growth, the top surface of the sapphire substrate is entirely covered with the GaN layer through lateral growth. The GaN layer is grown so that the a-axis of the layer is perpendicular to the exposed R-plane surfaces of the sapphire substrate; the c-axis of the layer is parallel to the axis direction Lsapph-AM of the sapphire substrate; and the m-axis of the layer, which is inclined by 30° from the a-axis thereof, is perpendicular to the main surface (inclined by 30° from the exposed R-plane surfaces) of the sapphire substrate.
US09263253B2	Method of manufacturing a SiOCN film, substrate processing apparatus, and recording medium A method of manufacturing a semiconductor device includes forming a thin film containing a predetermined element, oxygen, carbon, and nitrogen on a substrate by performing a cycle a predetermined number of times after supplying a nitriding gas to the substrate. The cycle includes performing the following steps in the following order: supplying a carbon-containing gas to the substrate; supplying a predetermined element-containing gas to the substrate; supplying the carbon-containing gas to the substrate; supplying an oxidizing gas to the substrate; and supplying the nitriding gas to the substrate.
US09263250B2	Method and apparatus of forming silicon nitride film Provided is a method of forming a silicon nitride film on a surface to be processed of a target object, which includes: repeating a first process a first predetermined number of times, the process including supplying a silicon source gas containing silicon toward the surface to be processed and supplying a decomposition accelerating gas containing a material for accelerating decomposition of the silicon source gas toward the surface to be processed; performing a second process of supplying a nitriding gas containing nitrogen toward the surface to be processed a second predetermine number of times; and performing one cycle a third predetermined number of times, the one cycle being a sequence including the repetition of the first process and the performance of the second process to form the silicon nitride film on the surface to be processed.
US09263249B2	Method and apparatus for manufacturing semiconductor device The present invention is directed to a method and an apparatus for manufacturing a semiconductor device including step S22 to form an insulating film on a front surface of a semiconductor wafer that is a surface on which a semiconductor element is to be formed and on a back surface that is a surface opposing the front surface, step S26 to remove the insulating film formed on the back surface by selectively providing a first chemical on the back surface of the semiconductor wafer, and step S30 to remove the insulating film formed on the front surface by simultaneously immersing the plurality of semiconductor wafers in a second chemical.
US09263248B2	Pseudo-substrate for use in the production of semiconductor components and method for producing a pseudo-substrate A pseudo-substrate (1, 11) for use in the production of semiconductor components, having a carrier substrate (2, 12) with a crystalline structure and a first buffer (3, 13), which is arranged on a surface of the carrier substrate (2, 12), if appropriate on further intervening intermediate layers, wherein the first buffer (3, 13) is embodied as a single layer or as a multilayer system and includes, at least at the surface facing away from the carrier substrate (2, 12), arsenic (As) and at least one of the elements aluminum (Al) and indium (In). The invention is characterized in that a second buffer (4, 14) is additionally arranged on a side of the first buffer (3, 13) facing away from the carrier substrate (2, 12), if appropriate on further intervening intermediate layers, said second buffer being embodied as a single layer or as a multilayer system, wherein the second buffer (4, 14) is embodied such that it includes, at a first surface facing the first buffer (3, 13) arsenic and at least one of the elements aluminum and indium and comprises, at a second surface facing away from the first buffer (3, 13) antimony (Sb) and at least one of the elements aluminum and indium, and wherein the second buffer is embodied with a decreasing proportion of arsenic and with an increasing proportion of antimony in each case proceeding from the first surface towards the second surface. The invention furthermore relates to a method for producing a pseudo-substrate (1, 11).
US09263246B2	Lamp A lamp includes a bulb, a filament, a gas, and a reflective film. The filament is disposed in the interior of the bulb along the tube axis. The gas is filled in the interior of the bulb. The reflective film is formed on the outer circumferential surface of the bulb and reflects a light from the filament toward the interior of the bulb. Further, the reflective film may be formed by depositing a reflective film material containing TiO2, SiO2, and BaSO4 on the outer circumferential surface of the bulb.
US09263245B2	Amalgam balls having an alloy coating Energy-saving lamps contain a gas filling of mercury vapour and argon in a gas discharge bulb. Amalgam balls are used for filling the gas discharge bulb with mercury. Novel coated balls whose operating life in the case of automatic metered introduction is increased by coating of the balls with an alloy powder and conglutination of the amalgam balls during storage and processing is prevented are proposed.
US09263237B2	Plasma processing apparatus and method thereof The following description relates to a plasma processing apparatus and a method thereof. The plasma processing apparatus comprises a first plasma chamber having a first plasma discharge space, a first plasma source for supplying a first activation energy to the first plasma discharge space within the first plasma chamber, a second plasma chamber which is connected to the first plasma chamber and has a second discharge space, and a second plasma source for supplying a second activation energy for inducing inductive coupled plasma to the second plasma discharge space within the second plasma chamber.
US09263228B2	Integrated photoemission sources and scalable photoemission structures A scalable, integrated photoemitter device and method of manufacture using conventional CMOS manufacturing techniques. The photoemitter device has a first semiconductor substrate having a plurality of photonic sources formed on top in a first material layer, the plurality of photonic sources and the material layer forming a planar surface. A second substrate is bonded to the planar surface, the second substrate having a plurality of photoemitter structures formed on top in a second material layer, each photoemitter structure in alignment with a respective photonic source of the first substrate and configured to generate particle beams responsive to light from a respective light source. Additionally provided is a multi-level photoemitter of tapered design for implementation in the scalable, integrated photoemitter device. Conventional CMOS manufacturing techniques are also implemented to build the multi-level photoemitter of tapered design.
US09263227B2	X-ray tube An X-ray tube includes a radiopaque substrate including a window portion, an X-ray transmission window closing the window portion, an X-ray target provided at the window portion from an inner surface side of the substrate, a highly-evacuated container portion attached to the inner surface of the substrate, a cathode, a first control electrode and a second control electrode provided inside the container portion. A shielding electrode is provided at the inner surface of the substrate so as to surround the window portion. Electrons collide with the X-ray target to generate X-rays. Electrons reflected on the X-ray target between the shielding electrodes are absorbed by the shielding electrodes, so an inner surface of the container portion is not charged. The electron emission from the cathode is not affected by the reflected electrons, so a change in target current is small, and thus X-rays of substantially constant intensity can be radiated.
US09263226B2	Radiation device installation housing and X-ray generator Embodiments include an X-ray generator including a radiation device installation housing and an X-ray generator. In various embodiments, the radiation device installation housing comprises a housing body, a flange fixedly provided on an inner wall of the housing body and shaped in circular and a compensation device fixedly or movably connected with the flange in a liquid tight manner; a liquid receiving cavity for receiving an insulating liquid formed between one side of two opposite sides of the compensation device and the inner wall of the housing body as well as the flange; a compensation device moving space formed between another side of the two opposite sides of the compensation device opposed to the inner wall of the housing body and an inner wall of the flange.
US09263223B2	Ion generation in mass spectrometers by cluster bombardment The invention relates to devices and methods in mass spectrometers for the generation of ions of heavy molecules, especially biomolecules, by bombarding them with uncharged clusters of molecules. The analyte ions which are generated or released by cluster bombardment of analyte substances on the surface of sample support plates show a broad distribution of their kinetic energies, which prevents good ion-optical focusing. In the invention, the kinetic energies are homogenized in a higher-density collision gas. The collision gas is preferably located in an RF ion guide, more preferably an RF ion funnel, which can transfer the ions to the mass analyzer. The collision gas may be introduced with temporal pulsing, coordinated or synchronized with the pulsed supersonic gas jet. The collision gas may be pumped off again before the next supersonic gas pulse. In an advantageous embodiment, the collision gas can originate from the supersonic gas jet itself.
US09263222B2	Target extender in radiation generator A radiation generator may include a generator housing, a target electrode carried by the generator housing, a charged particle source carried by the generator housing to direct charged particles at the target electrode based upon an accelerating potential, and a suppressor electrode carried by the generator housing having an opening therein to permit passage of charged particles to the target electrode. A target extender electrode may be between the suppressor electrode and the target electrode and have an opening therein to permit passage of charged particles to the target. At least one voltage source may be coupled to the target electrode, the suppressor electrode, and the target extender electrode to cause the target electrode to have a voltage greater than a voltage of the suppressor electrode and to cause the target extender electrode to have a voltage greater than the voltage of the suppressor electrode.
US09263220B2	Device for surge-current-resistant thermal contacting of electrical components The invention relates to a device for surge-current-resistant terminal contacting of electrical components (3), in particular components of rotationally symmetrical form, wherein the components, on the lateral surface thereof, have spaced-apart contacting portions (7), also comprising two U-shaped, electrically conductive contact pads (1) which have a partial surface (4) which is complementary to the contour of the respective contacting portion of the electrical component. According to the invention, each contact pad is assigned a U-shaped spring clip which likewise has a partial surface (5) which is complementary to the contour of the respective contacting portion of the electrical component, wherein said partial surface is provided in the connecting portion between legs (6, 6′) of the U-shaped spring clip. In the assembled state, the U legs of the spring clip protrude between the lateral surface of the electrical component and the respective U leg of the respective contact pad and are fixed with respect to one another in a latching manner.
US09263212B2	High voltage gas circuit breaker gas density monitoring system A gas density monitoring system for high voltage gas circuit breakers. The gas density monitoring system comprising a gas density device mounted directly on a circuit breaker tank end cover. When the gas density device is fully secured to the tank end cover, the gas density device works in conjunction with a self-sealing valve body to provide a self-sealing, direct pathway between the pressurized tank and a sensing element of the gas density device. This pathway permits the gas density device to sense the circuit breaker tank pressure via an angled port through the tank end cover that limits pressure transients that may result from the normal operation of the circuit breaker. The gas density device contact settings may be verified without removal of the density device from the gas circuit breaker or venting the enclosed gas inside the gas circuit breaker to the atmosphere.
US09263210B2	Two-shot injection molded housing with seats for keycaps in user-interface A device has a housing with a top part that accommodates one or more pressable keys forming the user-interface of the device. Each specific key has a specific keycap. The top part is formed from a harder plastic element and a softer rubber layer in a two-shot injection molding process. The harder plastic element has one or more openings occupied by the softer rubber layer. The harder plastic element has a specific pin positioned in a specific hole of the softer rubber layer. The specific keycap has a bottom face with a specific protruding sleeve configured for engaging with the specific pin. The bottom face of the specific key and an area at a top face of the softer rubber layer have complimentarily shaped profiles configured for accurately orienting the keycap relative to the top part.
US09263208B2	Tactile-surface control module, in particular for a motor vehicle The present invention relates to a tactile-surface control module comprising: a flexible protection layer (9), at least one monostable switch (11) and a rigid mechanical supporting member (13) letting through the light from at least one light source and defining regions for backlighting the flexible protection layer (9), characterized in that said supporting member (13) further includes at least one passage (21) for activating the monostable switch (11), by deformation of the flexible protection layer (9), and in that the module includes a sheet (19) made of incompressible material sandwiched between said rigid mechanical supporting member (13) and the flexible protection layer (9), the sheet (19) defining at least one pivoting arm (23) comprising a hinge (25), joined to said supporting member (13), and a pivoting free end (27) having an actuating lug (29) placed facing a passage (21) in said supporting member (13) for actuating the monostable switch (11).
US09263207B2	Switch device A switch device includes a switch operation unit to be mechanically operated so as to be in on or off state; a detecting unit configured to detect whether the switch operation unit is in the on or off state; a first mechanism to be configured to close electrical contacts of at least one circuit when the switch operation unit is operated to be in the on state; and a second mechanism configured to maintain the electrical contacts in an closed state and switch the electrical contacts to an open state in response to electrical signals indicating off, on, and, off to be received sequentially while the switch operation unit is in the off state.
US09263205B2	Electric switching apparatus The invention relates to an electric switching apparatus (1) comprising: a switching unit (10) having: an electromagnetic actuator (12) to command opening and/or closing of electric contacts (11), mechanical latching means (15) designed for connection of a detachable add-on unit (20), said latching means, in a first operating position, enabling fixing of said add-on unit on said switching unit, The switching apparatus comprises electric power supply means designed to supply power to the electromagnetic actuator (12) and being arranged to operate in a manner that is dependent on the position of the latching means (15). The electric power supply means are inoperational when the latching means are not in the first operating position, the actuating coil (17) of the electromagnetic actuator (12) not being able to be supplied.
US09263201B2	Planetary limit switch A planetary limit switch contains a front transmission module, at least one following transmission module, and at least one micro switch. The front transmission module couples with an external power source and includes a first planetary gear carrier and plural first planetary gears for matching with the first planetary gear carrier, a front driving gear meshes with the plural first planetary gears and connects with a driving shaft so as to be driven by the driving shaft. Each following transmission module includes a second planetary gear carrier and a plurality of second planetary gears, and the plurality of second planetary gears meshing with a following gear, wherein the second planetary gear carrier has a cam portion arranged on an outer peripheral side thereof. The at least one micro switch is fixed below at least one following transmission module and touched by the cam portion of the second planetary gear carrier.
US09263200B2	High-current switching arrangement An exemplary high-current switching arrangement in a generator duct arranged between a generator and a transformer is disclosed. This arrangement includes a pole frame which can be positioned on a base surface, a breaker pole of a generator circuit-breaker which is secured to the pole frame, and a drive which is secured to the pole frame. The breaker pole includes an active component arranged along an axis designed for the conduction and interruption of high currents and which incorporates a power switching point, with two axially spaced current terminals. The drive is arranged on a first of two end faces of the pole frame, and includes a linkage mechanism that transmits power from the drive to the power switching point.
US09263199B2	Electrical contact arrangement and air insulated medium voltage circuit breaker including the electrical contact arrangement An electrical contact arrangement for medium to high voltage applications includes a contact arm having a distal end section on which a circular shaped annulus arrangement having several axially and parallel directed contact fingers is arranged. The contact fingers are pressed on the contact arm via respective radially directed connection sections by a spring ring which is peripherally arranged around the contact fingers. The distal end section of the contact arm includes a first ring-shaped surface and an adjacent second ring-shaped surface, so that the connection section of each contact finger is pressed to at least both the first and second ring-shaped surfaces.
US09263198B2	Electrical storage device An electric double-layer capacitor having a capacitor element, a package defining a closed space accommodating the capacitor element, and electrolytic solution loaded in the closed space. The package includes a body and a lid, and the body has a metallic portion and a resin portion. The metallic portion includes two lead-out terminals electrically coupled to the capacitor element, and these two lead-out terminals are electrically isolated from each other by the resin portion. The resin portion includes two projections extending into the closed space, which make the closed space narrower and reduce the amount of loading of the electrolytic solution.
US09263196B2	Chemical vapor deposition graphene foam electrodes for pseudo-capacitors Technologies are generally described for a porous graphene electrode material is described herein that may incorporate a three-dimensional open-cell graphene structure fabricated via chemical vapor deposition onto a metal foam. After the graphene is deposited, the metal foam may be dissolved, leaving a three-dimensional open-cell graphene structure that may include single or few layer graphene. Pseudo-capacitive materials, such as RuO2, Fe3O4, or MnO2, may be deposited within the pores of the three-dimensional open-cell graphene structure to form the porous graphene electrode material. The porous graphene electrode material may have a specific capacitance comparable to chemically modified graphene (CMG) electrodes. The porous graphene electrode material may also have a conductivity greater than CMG electrodes of equivalent surface area. Use of the porous graphene electrode material in capacitors may result in significant improvements in specific power compared to CMG based capacitors.
US09263186B2	DC/ AC dual function Power Delivery Network (PDN) decoupling capacitor Some implementations provide a semiconductor device that includes a first substrate, a die coupled to the first substrate, and a set of solder balls coupled to the first substrate. The set of solder balls is configured to provide an electrical connection between the die and a second substrate. The semiconductor device also includes at least one decoupling capacitor coupled to the die through the first substrate. The at least one decoupling capacitor is configured to provide an electrical connection between the die and the second substrate. The at least one decoupling capacitor is coupled to the first substrate such that the at least one decoupling capacitor is positioned between the first substrate and the second substrate. In some implementations, the second substrate is a printed circuit board (PCB). In some implementations, the first substrate is a first package substrate, and the second substrate is a second package substrate.
US09263180B2	Coil component and board having the same A coil component may include: a magnetic body; and first and eighth external electrodes formed on one surface of the magnetic body, second and third external electrodes and sixth and seventh external electrodes that are formed on two surfaces adjacent to the one surface of the magnetic body, respectively, and fourth and fifth external electrodes formed on the other surface opposing the one surface of the magnetic body. The magnetic body includes upper and lower substrates and first to fourth coil parts disposed between the upper and lower substrates and enclosed by an insulation film, the first to fourth coil parts having coupled coils wound in parallel on the same plane, respectively, so that magnetic fluxes in the coupled coils are formed in directions opposite to each other, the coupled coils being composed of first to eighth coils.
US09263179B2	Common mode filter and method of manufacturing the same Disclosed herein are a common mode filter capable of implementing high inductance without deterioration of a moisture resistance load, and a method of manufacturing the same. The common mode filter includes: a magnetic substrate; an insulating layer disposed on the magnetic substrate; and a coil electrode layer disposed in the insulating layer, wherein the magnetic substrate has a groove part formed at an edge of an upper surface thereof, and a material of the insulating layer is filled into the groove part.
US09263178B2	Coil structure and electric power conversion device Disclosed is a coil structure including: a first wire rod including a first coil portion and a first lead wire connected to the first coil portion, the first coil portion winding around a coil axis in a first space; a second wire rod including a second coil portion, the second coil portion winding around the coil axis in a second space, the second space being aligned with the first space along the coil axis; and an insulating structure including a first insulating section that insulates the first coil portion from the second coil portion. The first lead wire portion extends through the second space. The insulating structure fixes the first lead wire portion at a position that is away from the second coil portion by not less than a minimum creepage distance between the first and second coil portions, the minimum creepage distance being defined by the first insulating section.
US09263175B2	Rare earth reduced garnet systems and related microwave applications Disclosed are synthetic garnets and related devices that can be used in radio-frequency (RF) applications. In some embodiments, such RF devices can include garnets having reduced or substantially nil Yttrium or other rare earth metals. Such garnets can be configured to yield high dielectric constants, and ferrite devices, such as TM-mode circulators/isolators, formed from such garnets can benefit from reduced dimensions. Further, reduced or nil rare earth content of such garnets can allow cost-effective fabrication of ferrite-based RF devices. In some embodiments, such ferrite devices can include other desirable properties such as low magnetic resonance linewidths. Examples of fabrication methods and RF-related properties are also disclosed.
US09263172B2	Wire constructs A method for forming a wire construct includes forming a groove in a polymer having a mouth that is narrower than a width of a deeper portion of the groove and placing a substantial length of wire in the groove, the wire having a larger cross-sectional dimension than the mouth of the groove. Encapsulant is placed over the polymer. The wire construct is to be used for implantable stimulation leads, such as a cochlear stimulation lead or a neurostimulation lead. Two wire constructs can be assembled to form a multilayer wire construct.
US09263166B2	Shell activated sintering of core-shell particles A sintered structure and method for forming it are disclosed. The method includes obtaining core-shell particles having a core material and a shell material, forming the particles into a powder compact, and annealing the powder compact at an annealing temperature. The shell material is a metal that diffuses faster than the core material at the annealing temperature and diffuses to the contacts between the core-shell particles during annealing to form sintered interfaces between the core-shell particles. The sintered structure can have discontinuous regions of shell material between the sintered interfaces. The core material can be a metal, semiconductor or ceramic. The core material can be copper and the shell material can be silver. The sintered interfaces can be almost purely shell material. The annealing temperature can be significantly lower than the temperature needed to form interfaces between particles of the core material without the shell material.
US09263165B2	Electrical wire and electrical wire with terminal The invention relates to an electrical wire and an electrical wire with a terminal capable of diminishing the adjustment of a crimping height. There is provided an electrical wire 1 including a conductor part 11 that is made of a precipitation strengthened copper alloy having a cross-sectional area of 0.13 sq in the ISO 6722 standard and is compressed, wherein the conductor part 11 has a rate of elongation of 7% or more, and a tensile strength of 500 MPa or more. In addition, the electrical conductivity of the conductor part is 70% IACS or more.
US09263164B2	Method and device for correcting artefacts during X-ray imagery, especially computer tomography, with a moving modulator field A method and a device produce X-ray images of objects, according to which artifacts caused by scattered radiation are corrected. To this end, a modulator field is used, that can be moved from a first position to a second position, thereby enabling modulator field areas with small and relatively large X-ray attenuation coefficients to be interchanged. An initial amplitude-modulated projection of the object is respectively produced in each of the two positions, and a scattered image associated with the projection is respectively calculated. This is especially suitable for rapid CT scans.
US09263163B2	Adaptive X-ray filter An adaptive X-ray filter for varying a local intensity of X-ray radiation includes a first chamber containing a magnetorheological or electrorheological first liquid, a second chamber containing a second liquid that absorbs X-ray radiation, and a flexible membrane that separates the first chamber from the second chamber. Using the flexible membrane, a layer thickness ratio of the first liquid and the second liquid may be varied. A heating apparatus that heats the second liquid is arranged in the adaptive X-ray filter. The second liquid is a liquid metal.
US09263161B2	Optical arrangement for EUV lithography and method for configuring such an optical arrangement An optical arrangement, e.g. projection lens, for EUV lithography, provided with: a first optical element (22) having a reflective surface (31a) and a first substrate (32) composed of TiO2-doped quartz glass, which has a temperature-dependent coefficient of thermal expansion having a zero crossing at a first zero crossing temperature (TZC1), and a second optical element (24) having a reflective surface (36a) and a second substrate (37) composed of TiO2-doped quartz glass, which has a temperature-dependent coefficient of thermal expansion having a zero crossing at a second zero crossing temperature (TZC2), which is different from the first. A gradient of the coefficient of thermal expansion of the first substrate (32) at the first zero crossing temperature (TZC1) and/or a gradient of the coefficient of thermal expansion of the second substrate (37) at the second zero crossing temperature (TZC2) have/has a negative sign.
US09263158B2	Determining data retention time in a solid-state non-volatile memory Method and apparatus for managing data in a memory, such as a flash memory array. In accordance with some embodiments, a test pattern is written to a selected block of solid-state non-volatile memory cells. The test pattern is read from the selected block and a total number of read errors is identified. A data retention time is determined in response to the total number of read errors and an elapsed time interval between the writing of the test pattern and the reading of the test pattern. Data in a second block of the solid-state non-volatile memory cells are thereafter refreshed in relation to the determined data retention time.
US09263155B2	Data storing system and operating method thereof A data storing system performs a test operation on a memory block on which a read operation is determined to be failed, and determines whether the memory block is or is not a bad block based on a result of the test operation. The data storing system may improve reliability and yield of a device.
US09263152B1	Address fault detection circuit A semiconductor memory device and method of operation are provided for a multi-bank memory array (100) with an address fault detector circuit (24, 28) connected to split word lines (WLn-WLm) across multiple banks, where the address fault detector circuit includes at least a first MOSFET transistor (51-54) connected to each word line for detecting an error-free operation mode and a plurality of different transient address faults including a “no word line select,” “false word line select,” and “multiple word line select” failure mode at one of the first and second memory banks. In selected embodiments, the address fault detector provides resistive coupling (33-40) between split word lines across multiple banks to create interaction or contention between split word lines to create a unique voltage level on a fault detection bit line during an address fault depending on the fault type.
US09263146B2	Flash multi-level threshold distribution scheme A threshold voltage distribution scheme for multi-level Flash cells where an erase threshold voltage and at least one programmed threshold voltage lie in an erase voltage domain. Having at least one programmed threshold voltage in the erase voltage domain reduces the Vread voltage level to minimize read disturb effects, while extending the life span of the multi-level Flash cells as the threshold voltage distance between programmed states is maximized. The erase voltage domain can be less than 0V while a program voltage domain is greater than 0V. Accordingly, circuits for program verifying and reading multi-level Flash cells having a programmed threshold voltage in the erase voltage domain and the program voltage domain use negative and positive high voltages.
US09263136B1	Data retention flags in solid-state drives Systems and methods for managing data retention in a solid-state storage system utilizing data retention flag bytes are disclosed. A data storage device includes a non-volatile memory comprising a plurality of non-volatile memory devices and a controller configured to write data to a memory unit of the non-volatile memory array and write a data retention flag value indicating a number of bits of the written data programmed in a first of a plurality of logical states. The controller is further configured to read the data and determine a number of bits having the first of the plurality of logical states in the read data, and determine a difference between the number of bits of the written data programmed in the first logical state and the number of bits having the first logical state in the read data. The difference is used to determine data retention characteristics of the non-volatile memory.
US09263135B2	Programming schemes for 3-D non-volatile memory A method includes providing data for storage in a memory, which includes multiple analog memory cells arranged in a three-dimensional (3-D) configuration having a first dimension associated with bit lines, a second dimension associated with word lines, and a third dimension associated with sections. The data is stored in the memory cells in accordance with a programming order that alternates among the sections, including storing a first portion of the data in a first section, then storing a second portion of the data in a second section different from the first section, and then storing a third portion of the data in the first section.
US09263134B2	Non-volatile memory which can increase the operation window A non-volatile memory cell includes a plurality of rows of memory cells, a plurality of bit lines coupled to the plurality of rows of memory cells for accessing data to the plurality of rows of memory cells, a plurality of word lines each coupled to a corresponding row of memory cells, and a decoder coupled to the plurality of word lines for enabling at least one row of memory cells of the plurality of rows of memory cells.
US09263129B2	Method for determining programming parameters for programming a resistive random access memory A method for determining programming parameters for programming a resistive random access memory switching from an OFF state to an ON state, the method including determining retention curves representing the increase in the ON state resistance as a function of time, for a given programming temperature and a given current limitation; determining a retention failure time for each of the retention curves; determining curves representing the decrease in the retention failure time as a function of the programming temperature, for a given current limitation; for at least one given programming temperature, determining, from the curves representing the decrease in the retention failure time, a current limiting value to be applied to the resistive random access memory in order to obtain a target retention failure time.
US09263126B1	Method for dynamically accessing and programming resistive change element arrays Methods for dynamically programming and dynamically reading one or more resistive change elements within a resistive change element array are disclosed. These methods include first pre-charging all of the array lines within a resistive change element array simultaneously and then grounding certain array lines while allowing other array lines to float in order to direct discharge currents through only selected cells. In this way, resistive change elements within resistive change element arrays made up of 1-R cells—that is, cells without in situ selection circuitry—can be reliably and rapidly accessed and programed.
US09263120B2	Dynamically configurable SRAM cell for low voltage operation An embodiment of a memory device of SRAM type is proposed. The memory device includes a plurality of memory cells each for storing a first logic value represented by a first reference voltage or a second logic value represented by a second reference voltage. Each memory cell includes a bistable latch—having a main terminal, a complementary terminal, a set of main storage transistors for maintaining the main terminal at the reference voltage corresponding to the stored logic value, and a set of complementary storage transistors to maintain the complementary terminal at the reference voltage corresponding to the complement of the stored logic value—a main access transistor and a complementary access transistor for accessing the main terminal and the complementary terminal, respectively. The memory device may further include biasing means for modifying a value of a threshold voltage of at least one of the main transistors to a first threshold voltage value or to a second threshold voltage value and for modifying a threshold voltage value of at least one of the complementary transistors to the second threshold voltage value or to the first threshold voltage value during a write operation of the first logic value or of the second logic value, respectively, in the memory cell.
US09263119B2	Semiconductor device having memory cell with electrostatic capacitance circuit A capacitance coupled to a memory node and a word line of an SRAM cell provides an electrostatic capacitance between the memory node and the word line. The capacitance has a first electrostatic capacitance when the word line is in a nonselective state (usually a LOW level) and the memory node retains a HIGH level; the capacitance has a second electrostatic capacitance which is smaller than the first electrostatic capacitance when the word line is in the nonselective state (usually the LOW level) and the memory node retains the LOW level.
US09263117B2	Writing method for solid state disk A writing method for a solid state disk is disclosed. The method comprises following steps: A writing unit is arranged in a buffer memory, wherein plane addresses of the writing unit are in one-to-one correspondence with non-volatile memories of the solid state disk. A writing data is received. A reordered plane address of the writing unit is obtained by using the residue of the logical allocation address of the writing data dividing the plane address number. Whether the reordered plane address is empty is checked. If the reordered plane address is not empty, the next plane address is shifted and the plane address is reordered. If the reordered plane address is empty, the writing data is buffered to the reordered plane address and the logical allocation address of the writing data is arranged in order.
US09263116B2	Memory device In a memory device, memory capacity per unit area is increased while a period in which data is held is ensured. The memory device includes a driver circuit provided over a substrate, and a plurality of memory cell arrays which are provided over the driver circuit and driven by the driver circuit. Each of the plurality of memory cell arrays includes a plurality of memory cells. Each of the plurality of memory cells includes a first transistor including a first gate electrode overlapping with an oxide semiconductor layer, and a capacitor including a source electrode or a drain electrode, a first gate insulating layer, and a conductive layer. The plurality of memory cell arrays is stacked to overlap. Thus, in the memory device, memory capacity per unit area is increased while a period in which data is held is ensured.
US09263114B2	Electronic device A semiconductor memory unit includes first to Nth variable resistance elements each having different resistance values according to values stored therein, wherein N is a natural number equal to or greater than 2; a reference resistance element having a first reference resistance value; and first to Nth comparison units which correspond to the first to Nth variable resistance elements, respectively, and each of which determines whether a resistance value of the corresponding variable resistance element is greater or less than a second reference resistance value, wherein the first to Nth comparison units are commonly coupled to the reference resistance element.
US09263110B2	Semiconductor memory device having selective activation circuit for selectively activating circuit areas A semiconductor memory device includes a plurality of memory banks each including a plurality of circuit areas selected based on an address signal, any one of which is selected by a corresponding bank selective signal (source transistor control signals), and a selective activation circuit that, from among circuit areas included in a memory bank that is selected based on the bank selective signal, activates any one of the circuit areas based on the address signal, and deactivates at least one of rest of the circuit areas. According to the present invention, the power consumption can be reduced in an active state by a dynamic power control in response to an address signal, not by entire power control by an external command.
US09263102B2	Apparatus, system, and method for data transformations within a data storage device Apparatuses, systems, and methods are disclosed for executing data transformations for a data storage device. A storage controller module controls a storage operation for a set of data within a data storage device. A transformation module determines to apply a data transformation to the set of data in response to a transformation indicator. A processing module applies the data transformation to the set of data internally on the data storage device prior to completing the storage operation.
US09263100B2	Bypass system and method that mimics clock to data memory read timing A bypass system and method that mimics read timing of a memory system which includes a self-timing circuit and a sense amplifier. When prompted, the self-timing circuit initiates the sense amplifier to evaluate its differential input. The bypass system includes a memory controller that is configured to provide a bypass enable, to prompt the self-timing circuit, and to disable normal read control when a bypass read operation is indicated. A bypass latch latches an input data value, converts the input data value into an input complementary pair, and provides the complementary pair to the differential input of the sense amplifier. The sense amplifier, when initiated, evaluates the input complementary pair after its self-timing period and provides an output data value. The bypass latch and self-timing circuit may operate synchronous with a read clock in a read domain of the memory for more accurate memory read timing.
US09263097B2	On-chip voltage generation for a programmable memory device The programming of programmable memory devices, e.g. one-time programmable (OTP) memory device is presented. In particular, efficient methods and systems for generating the supply voltage for programming a programmable memory device are described. A controller configured to control the programming of a data word into a programmable memory device is described. The controller is configured to set one or more digital control signals for programming the data word into the programmable memory device. Furthermore, the controller is configured to, subsequent to setting the one or more digital control signals, increasing a device supply voltage for the programmable memory device from a default operation level to a programming level.
US09263084B1	Selective sharing of body data Information from a position and/or gesture detection system can be transmitted to various devices in order to enable users to interact and/or view others users. In some embodiments, video is captured that includes a current view of the body of a user. In order to prevent an unauthorized, unintended, or undesired transmission of at least part of the body image data, one or more settings or policies can be specified that can control which portions are transmitted, received, and/or displayed. For example, a user can be prompted before body image or position data is transmitted, which enables a user to control the type of data that is sent. A recipient or intermediate entity or component can also specify one or more settings or policies to control the type of data that is transmitted and/or received. In some embodiments, an external service can be utilized to manage the transmission of data.
US09263077B2	Thermal retention structure for a data device A data device may have at least a magnetic lamination with a thermal retention structure deposited on a substrate and configured to maintain a predetermined temperature for a predetermined amount of time. Such predetermined temperature and amount of time may allow for the growth of a magnetic layer with a predetermined magnetic anisotropy.
US09263076B1	Heatsink for heat assisted magnetic recording media A magnetic stack includes a heatsink layer comprising (200) Cu or (200) CuX, a magnetic recording layer, and an interlayer disposed between the heatsink layer and the magnetic recording layer.
US09263072B2	Multi-channel tape head having asymmetric channel arrays In one general embodiment, an apparatus includes an inner module comprising an array of first transducers of a first type; and first and second outer modules flanking the inner module. Each outer module includes an array of second transducers of a second type that is different than the first type. Each of the second transducers in each array of second transducers being aligned with a corresponding one of the first transducers in a direction generally parallel to a path of tape travel thereacross. A number of active second transducers in each outer module is less than a number of active first transducers in the inner module.
US09263066B1	Data writer with magnetically hard front shield A data writer can be configured with at least a write pole separated from a front shield by a non-magnetic gap layer. The front shield may consist of at least a seed layer and a shielding layer with the shielding layer having an easy axis coercivity along a first direction of 4 Oe or more and a hard axis coercivity along a second direction of 0.5 Oe or more.
US09263064B2	Reading order search method and program for recording groups on tape The present invention provides a search method used to search for the reading order of a plurality of recording groups when the plurality of recording groups written on tape are continuously read by a tape drive which manages data on tape in recording units having a fixed data length for each recording. This search method includes the steps of: receiving information on a plurality of tape groups to be read; and sorting the plurality of recording groups to be read so the reading time is shortened. In the sorting step, the time required to sort the plurality of reading groups is reduced by combining two or more recording groups into a single object to be sorted in the sorting step when at least two or more contiguous recording groups have been assigned to the same region or are assigned across adjacent regions among the plurality of regions.
US09263062B2	Vibration sensor and acoustic voice activity detection systems (VADS) for use with electronic systems A voice activity detector (VAD) combines the use of an acoustic VAD and a vibration sensor VAD as appropriate to the conditions a host device is operated. The VAD includes a first detector receiving a first signal and a second detector receiving a second signal. The VAD includes a first VAD component coupled to the first and second detectors. The first VAD component determines that the first signal corresponds to voiced speech when energy resulting from at least one operation on the first signal exceeds a first threshold. The VAD includes a second VAD component coupled to the second detector. The second VAD component determines that the second signal corresponds to voiced speech when a ratio of a second parameter corresponding to the second signal and a first parameter corresponding to the first signal exceeds a second threshold.
US09263060B2	Artificial neural network based system for classification of the emotional content of digital music A system for classification of the emotional content of music is provided. An encoder receives a digital audio recording of a piece of music, and encodes it using musical notes and associated amplitudes. The artificial neural network is configured to take a plurality of encoded time slices and provide output indicative of the emotional content of the music.
US09263058B2	Communication system and method between an on-vehicle voice recognition system and an off-vehicle voice recognition system A vehicle based system and method for receiving voice inputs and determining whether to perform a voice recognition analysis using in-vehicle resources or resources external to the vehicle.
US09263045B2	Multi-mode text input Concepts and technologies are described herein for multi-mode text input. In accordance with the concepts and technologies disclosed herein, content is received. The content can include one or more input indicators. The input indicators can indicate that user input can be used in conjunction with consumption or use of the content. The application is configured to analyze the content to determine context associated with the content and/or the client device executing the application. The application also is configured to determine, based upon the content and/or the contextual information, which input device to use to obtain input associated with use or consumption of the content. Input captured with the input device can be converted to text and used during use or consumption of the content.
US09263034B1	Adapting enhanced acoustic models Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for enhancing speech recognition accuracy. In one aspect, a method includes receiving voice queries, obtaining, for one or more of the voice queries, feedback information that references an action taken by a user that submitted the voice query after reviewing a result of the voice query, generating, for the one or more voice queries, a posterior recognition confidence measure that reflects a probability that the voice query was correctly recognized, wherein the posterior recognition confidence measure is generated based at least on the feedback information for the voice query, selecting a subset of the one or more voice queries based on the posterior recognition confidence measures, and adapting an acoustic model using the subset of the voice queries.
US09263031B2	System and method of spoken language understanding in human computer dialogs A system and method are disclosed that improve automatic speech recognition in a spoken dialog system. The method comprises partitioning speech recognizer output into self-contained clauses, identifying a dialog act in each of the self-contained clauses, qualifying dialog acts by identifying a current domain object and/or a current domain action, and determining whether further qualification is possible for the current domain object and/or current domain action. If further qualification is possible, then the method comprises identifying another domain action and/or another domain object associated with the current domain object and/or current domain action, reassigning the another domain action and/or another domain object as the current domain action and/or current domain object and then recursively qualifying the new current domain action and/or current object. This process continues until nothing is left to qualify.
US09263027B2	Broadcast system using text to speech conversion A broadcast signal receiver comprises a text data receiver for receiving broadcast text data for display to a user in relation to a user interface; a text-to-speech (TTS) converter for converting received text data into an audio speech signal, the TTS converter being operable to detect whether a word for conversion is included in a stored list of words for conversion and, if so, to convert that word according to a conversion defined by the stored list; and if not, to convert that word according to a set of predetermined conversion rules; a conversion memory storing the list of words for conversion by the TTS converter; and an update receiver for receiving additional words and associated conversions for storage in the conversion memory.
US09263026B2	Screen reader having concurrent communication of non-textual information A screen reader software product for low-vision users, the software having a reader module collecting textual and non-textual display information generated by a web browser or word processor. Font styling, interface layout information and the like are communicated to the end user by sounds broadcast simultaneously rather than serially with the synthesized speech to improve the speed and efficiency in which information may be digested by the end user.
US09263025B2	Method for speech coding, method for speech decoding and their apparatuses A high quality speech is reproduced with a small data amount in speech coding and decoding for performing compression coding and decoding of a speech signal to a digital signal. In speech coding method according to a code-excited linear prediction (CELP) speech coding, a noise level of a speech in a concerning coding period is evaluated by using a code or coding result of at least one of spectrum information, power information, and pitch information, and various excitation codebooks are used based on an evaluation result.
US09263024B2	Circuit arrangement and method for active noise cancellation In an embodiment, a circuit arrangement for active noise cancellation, comprises a first input (E1) for supplying a playback signal (Spb), a second input (E2) for supplying a sensor signal (Sanc), a first and a second terminal (A1, A2) of an output that is designed for being connected to a loudspeaker (Lsp) and a compensating device for respectively generating a first and a second noise signal (Sanc1, Sanc2) as a function of the sensor signal (Sanc), wherein the first and the second input (E1, E2) are coupled to the first and the second terminal of the output (A1, A2) by means of the compensating device (Komp) in such a way that a virtual playback signal (Ssp1) is provided at the first terminal (A1) of the output (A1, A2) and a superposition signal (Ssp2) is provided at the second terminal (A2) of the output (A1, A2) such that a differential signal between the virtual playback signal (Ssp1) and the superposition signal (Ssp2) can be fed to the loudspeaker.
US09263022B1	Systems and methods for transcoding music notation A method for transcoding music, according to various aspects of the present invention, includes in any practical order: (a) reading pitches and respective durations; (b) reading indicia of a quantity of beats per measure; (c) determining a word for each beat wherein: each word has one or more syllables, each syllable is associated with each pitch having duration that is within the duration of the beat; each syllable for a pitch, when preceded by a rest, comprises an initial consonant selected from the set consisting of ‘d’ and ‘t’; and each syllable comprises a vowel corresponding to an ordinal of the beat, wherein the vowel is selected from a set of vowels in accordance with the respective duration of the pitch associated with the syllable; and (d) outputting, for use by a music engraving engine, indicia of the pitches and words, in a manner that each syllable will be engraved in vertical alignment with the indicia of the associated pitch.
US09263021B2	Method for generating a musical compilation track from multiple takes An apparatus for creating a musical composition comprising an audio interface, and audio converter module, and a multi-track compositor module is disclosed. The audio interface operably receives audio from an audio input device and outputting audio to an audio output device. The audio converter module is operably connected to the audio interface to convert audio received via the audio interface into an audio track having one or more partitions. The multi-track compositor module is configured to receive a first audio track and a second audio track and automatically score each partition of the first and second audio tracks based on one or more criteria. The multi-track compositor module is then configured to construct a third audio track from the partitions of the first and second audio tracks based on the scores for each partition. A method is also provided.
US09263020B2	Control information generating apparatus and method for percussion instrument Provided is a sound source control information generating apparatus, adapted for performing slapping techniques. According to the present invention, information based on an output value of a first sensor that detects striking on the housing is stored in a memory means. If striking on the struck head of a percussion instrument is detected based on an output value of a second sensor that detects striking on the struck head, whether an output value equal to or greater than a predetermined value is obtained from the first sensor in a predetermined time interval before a timing of detecting the striking on the struck head is determined based on the information stored in the memory means.
US09263016B2	Sorting a plurality of inputted sound generation instructions to generate tones corresponding to the sound generation instruction in a sorted order Provided is an electronic musical instrument comprising: an input device for inputting sound generation instructions of tones at predetermined pitches; a tone generation device that generates tones with predetermined pitches based on sound generation instructions inputted by the input device; a specifying device that specifies a plurality of sound generation instructions inputted by the input device in a predetermined period as a sound generation instruction group; a sorting device that sorts the plurality of sound generation instructions composing the sound generation instruction group specified by the specifying device in a predetermined pitch order; and a control device that controls generation of tones by the tone generation device such that tones corresponding to the sound generation instruction group are generated in the order sorted by the sorting device.
US09263014B2	Method and apparatus for audio effects chain sequencing An audio effects chain sequencing apparatus alters the sequence of effects units in an effects chain so that different sequences of effects units can be connected. In one example the audio effects chain sequencing apparatus can have an external input port and an external output port, at least two component ports each having an internal input port and an internal output port, where the at least two component ports receive an input from the external input port, transfer that input in a component sequence to the component ports, and transfer the input to the external output port at the end of the component sequence and having a sequence selection module which selects the component sequence in which the at least two component ports transfer the input.
US09263009B2	Sound insulation electronic pad for bass drum of jazz drum set The present disclosure illustrates a sound insulation electronic pad for a bass drum of a jazz drum set. The electronic pad is assembled with a drum frame of the bass drum of the jazz drum set by a support structure, and located between a drumhead of the bass drum and a drum pedal. The electronic pad does not contact with the drumhead of the bass drum. When the electronic pad is knocked by the drumstick and the drumhead of the bass drum is not knocked by the drumstick, the electronic pad and an external trigger module simulate an electronic drum sound of the bass drum and output the electronic drum sound via an output device such as earphones or a loudspeaker. Therefore, the electronic pad of the present disclosure can be used to remodel the bass drum of the jazz drum set as an electronic drum.
US09263008B2	Harmonica The present invention provides a harmonica having advanced functions and a simple structure, which can produce three fundamental chords in each of major and minor modes and which can be also used as a chromatic harmonica. The harmonica includes a pair of a blow reed and a draw reed in each of an upper part and a lower part of a hole and has four tone rows of a tone row for the upper blow reeds, a tone row for the upper draw reeds, a tone row for the lower blow reeds, and a tone row for the lower draw reeds. To three of the four tone rows are assigned three fundamental chords that each consist of four notes, and the remaining one tone row is used to supplement a note required to configure the chromatic scale.
US09263006B2	Non-electrical devices and methods for producing wah-wah and other effects with stringed instruments A non-electrical stringed instrument sound effects device includes a crosspiece, having a string interface, and a strapping system that is configured to removably fasten the crosspiece, including the string interface, around a plucking or strumming hand of a player of the stringed musical instrument. A method of creating a sound effect using the device includes attaching the device to a plucking or strumming hand of a player of a stringed musical instrument such that the strapping system extends around the hand and the crosspiece is disposed adjacent the outside of the hand, positioning the hand in a conventional plucking or strumming position such that the string interface of the crosspiece extends across at least one of the strings, and manipulating the string interface of the crosspiece against the strings while plucking or strumming to achieve a desired sound effect without use of electrical power.
US09263005B1	Apparatus and methods for altering tonal characteristics of a stringed musical instrument Apparatus and methods for altering the tonal characteristics of output of a stringed instrument are disclosed. The stringed instrument may include a neck and a plurality of strings, the plurality of strings disposed about the neck. The apparatus may include a slide bar, the slide bar for contacting one or more strings of the plurality of strings and a support arm attached to the slide bar. The apparatus includes a retractable string depressor retractably connected to the support bar, the retractable string depressor for depressing one or more strings of the plurality of strings at a location on the neck forward of the slide bar.
US09263004B1	Musical performance assembly A musical performance assembly includes a guitar that has a body and a neck. A control circuit is attached to the guitar and the control circuit is positioned within the body. A keyboard is attached to the guitar such that the keyboard may be manipulated in the convention of playing music. A first set of switches is attached to the guitar and each of the first set of switches is electrically coupled to the control circuit. A second set of switches is attached to the guitar and each of the second set of switches is electrically coupled to the control circuit. A microphone is attached to the guitar to record a voice. The microphone is electrically coupled to the control circuit. Each of the second set of switches is manipulated to actuate the control circuit such that the control circuit may modify a sound of the recorded voice.
US09263003B2	Method and system for displaying using buffer swapping Methods and systems which may implement buffer swapping are provided. The methods include rendering, onto screen locations of a display screen, data from a memory having a first buffer and a second buffer, each buffer having respective buffer memory locations which correspond to the screen locations of the display screen. The methods can include: rendering first data from the first buffer onto the display screen; writing, to the second buffer, second data based on at least some of the first data from the first buffer by performing at least one of transforming at least some first data and changing corresponding screen locations of at least some first data from the first buffer, by writing at most once to each buffer memory location of the second buffer; and rendering the second data from the second buffer onto the display screen.
US09262998B2	Display system and data transmission method thereof A display system and a data transmission method thereof are provided. When a first frame stored in a frame buffer and a plurality of second frames to be outputted by an audio and video (AV) source are the same, the AV source set a AV control signal corresponding to a self-refresh mode, and a timing controller controlled by the AV control signal accesses the first frame to output a display data. When the first frame and the second frames are different from each other, the AV source sets the AV control signal corresponding to a normal mode, and sets a AV data signal according to the second frames, and the timing controller controlled by the AV control signal outputs the display data corresponding to the received second frame or accesses the frame buffer to output the display data according to timings of the AV data signal and the display data.
US09262994B2	Information terminal, mobile information terminal, and video image display system An information terminal includes: a display section that displays an image; a light source that emits light; an optical signal generator that uses the light emitted from the light source to generate an optical signal with which an optical scanner scans an object; a drive signal generator that generates a drive signal for driving the optical scanner; and a switcher that switches the state of the information terminal between a first state in which the display section displays an image, the optical signal generator does not generate the optical signal, and the drive signal generator does not generate the drive signal and a second state in which the optical signal generator generates the optical signal, the drive signal generator generates the drive signal, and the display section displays no image.
US09262993B2	Display panel driver, method of driving display panel using the same and display apparatus having the same A display panel driver including a moving image determining part, a sensing part and a dithering part. The moving image determining part determines whether an input image data represents a moving image or a static image. The sensing part senses a movement of a display apparatus or a user of the display apparatus. The dithering part performs a dithering operation to the input image data when the input image data represents the moving image or when at least one of the display apparatus and the user moves when the input image data represents the static image.
US09262989B2	Image display apparatus and method of adjusting clock phase using a delay evaluation signal An image display apparatus has an A/D converter for sampling an analog video signal whose signal level changes at a frequency higher than the frequency of a synchronizing signal, based on a reproduced dot clock, and converting the sampled analog video signal into a digital video signal, a clock adjusting circuit for generating a clock in synchronism with the synchronizing signal, delaying the phase of the clock according to set delays, and outputting the delayed clock as the reproduced dot clock, a controller for dividing an area of an image displayed based on the converted digital video signal, into a plurality of image areas defined by display lines in a horizontal direction, and establishing different delays for the divided image areas, and a delay evaluating circuit for converting differential data between adjacent signal levels on the display lines for the respective image areas, into absolute values and accumulatively adding the absolute values, thereby producing accumulated sums. The controller judges the delay established for the divided area with the maximum accumulated sum, as an optimum delay.
US09262987B2	Compensation methods for display brightness change associated with reduced refresh rate A method is provided for compensating for brightness change in a display. The method includes storing a plurality of look-up tables (LUTs), where each table has a plurality of pixel levels at a variable refresh rate (VRR) and a plurality of brightness signals that provide compensation for the brightness change when refresh rate is changed during a panel self-refresh (PSR). The method also includes receiving an input signal from a graphics processing unit (GPU) and determining the VRR of the input signal from the GPU. The method further includes obtaining the LUT at the determined VRR of the input signal and adjusting the input signal to produce an output signal that compensates for the brightness change for each pixel or sub-pixel in a timing controller based upon the LUT at the determined VRR. The method further includes transmitting the output signal to the display. A system is also provided.
US09262986B2	Reference frame management for screen content video coding using hash or checksum functions Techniques are provided for reference frame management for screen content video coding using hash or checksum functions. A video data stream including a plurality of frames is received, each frame including a plurality of pixels that define content within the frame. A plurality of hash code values associated with partitioned portions of a current frame are determined, where each hash code value is determined as an output value from a hash or checksum function based upon an input value comprising pixel values for a corresponding partition within the current frame. The current frame is compared with a plurality of reference frames based upon a comparison of the hash code values of the current frame with hash code values of the reference frames. A reference frame is selected as a candidate reference frame for coding the current frame.
US09262985B2	Semiconductor circuit, driving circuit of electro-optical device, and electronic apparatus A semiconductor circuit includes a first circuit block, a second circuit block, and power wiring lines that supply a plurality of reference potentials. The first circuit block and the second circuit block are connected to a common power wiring line that is one of the power wiring lines and supplies a common reference potential. A width of the common power wiring line in the first circuit block is smaller than a width of the common power wiring line in the second circuit block.
US09262981B2	Display driving circuit, display driving method and display apparatus Provided is a display driving circuit comprising N gate driving units for being connected to N gate lines on an array substrate respectively, as well as a timing control unit, n pre-charging units and n scanning control units, the N gate driving units, the n pre-charging units and the n scanning control units are all connected to the timing control unit. Further provided is a display driving method, and a display apparatus. According to embodiments of the present disclosure, a time period for liquid crystal molecule being deflected to accurate positions corresponding to desired grayscale will be reduced when a voltage to be charged is supplied on the liquid crystal molecule, thereby accommodating a higher refresh frequency.
US09262977B2	Image processing method for reduced colour shift in multi-primary LCDs A method of processing an image comprises: receiving pixel data constituting an image, the pixel data including at least four sub-pixel color components having respective data values, and modifying one or more of the sub-pixel color component data values. The data values of corresponding sub-pixels from two pixels are modified in opposite directions to one another and such that the overall luminance of the display panel appears substantially unchanged to an on-axis viewer of the display panel.
US09262976B2	Chip on glass type liquid crystal display A chip on glass (COG) type liquid crystal display comprises: a glass substrate (3); two or more than two driving circuits, which are provided on the glass substrate (3) and are connected one another in series; a constant current source (9), which is separately connected to at least one of the two or more than two driving circuits to supply a constant current signal to each driving circuit; and converting circuits (8), which are provided in each driving circuit to convert the constant current signal received to a voltage signal.
US09262975B2	Display device, display method, and projection type display device Aspects of the invention can provide a display device, a display method, and a projection type display device that allow a characteristic of a display image such as brightness to be continuously changed. The display device can include a light source capable of emitting a plurality of different color lights and a white light, and an optical modulation device for modulating light corresponding to the lights emitted from the light source. The ratio of the period of emitting the white light relative to the total of the periods of emitting the lights from the light source can be variable.
US09262974B2	Image display device including driving integrated circuit for different pixel arrangement structures A driving integrated circuit capable of driving various image display panels having different pixel arrangements is described. A data driving unit alternately supplies analog image signals to one of two adjacent data lines. A data switching unit selects the data lines such that the image signals are alternately supplied to the adjacent data lines of the plurality of data lines and electrically connecting the data lines to the output channels of the data driving unit.
US09262971B2	Optical assembly, backlight unit including the same, and display apparatus including the backlight unit An optical assembly includes a plurality of light sources emitting light in a first direction at a predetermined orientation angle, and a light guide panel having a light incident section and a light emitting section. The light incident section has a first surface to receive the light emitted from the light sources in the first direction and the light emitting section is to emit light received from the light incident section in a second direction. Also included is at least one cover having a first surface adjacent the light sources and a second surface adjacent at least one portion of the light emitting section.
US09262966B2	Pixel circuit, display panel and display apparatus A pixel circuit, a display panel and a display apparatus are used to improve the lifetime of the light emitting devices in the display apparatus. The pixel circuit comprises: a charging sub-circuit (1), a first driving sub-circuit (2), a second driving sub-circuit (3), a first capacitor (C1) and a second capacitor (C2). A first terminal (A) of the first capacitor (C1) is connected to a first terminal of the first driving sub-circuit (2) and a first terminal of the second driving sub-circuit (3), and a second terminal (B) of the first capacitor (C1) is connected to the charging sub-circuit (1) and a first terminal (C) of the second capacitor; a second terminal of the first driving sub-circuit (2) is connected to a first light emitting device (D1), a second terminal of the second driving sub-circuit (3) is connected to a second light emitting device (D2), wherein the driving current flowing from the first driving sub-circuit (2) to the first light emitting device (D1) is in an opposite direction to the driving current flowing from the second driving sub-circuit (3) to the second light emitting device (D2).
US09262964B2	Organic light emitting display and method of compensating for image quality thereof Provided is an organic light emitting diode (OLED) display device including a plurality of pixels to display images, each of the pixels including an OLED, a driving transistor connected to the OLED, and a switching transistor configured to supply data signals to the OLED, the device including: a sensor configured to sense a change amount of a mobility of the driving transistor; a compensation value calculator configured to obtain a change amount of a threshold voltage of the driving transistor based on the sensed change amount of the mobility; and a data compensator configured to adjust the data signals based on the sensed change amount of mobility and the obtained change amount of the threshold voltage.
US09262962B2	Pixel and organic light emitting display device using the same A pixel and an organic light emitting display device using the same, which can improve display quality, are provided. An organic light emitting display device includes pixels, an emission control line, an initial power supply unit, a scan driver and a data driver. The pixels are at intersection portions of scan lines and data lines. The emission control line is commonly coupled to the pixels. The initial power supply unit is commonly coupled to gate electrodes of one or more transistors included in each of the pixels, and supplies a first voltage during a first period, a second voltage lower than the first voltage during a second period, and a third voltage higher than the first voltage during a third period in one frame period. The scan driver drives the scan lines and the emission control line. The data driver drives the data lines.
US09262954B2	Visible light communication signal display method and apparatus A visible light communication signal display method of displaying (i) an image represented by video signals and (ii) an image obtained by encoding visible light communication signals includes: encoding at least part of the visible light communication signals to generate an encoded image; generating a plurality of sub-images which correspond to respective partial images obtained by dividing the encoded image and each of which (i) includes a corresponding one of the partial images and (ii) except for the corresponding partial image, is an image having a substantially uniform luminance value lower than or equal to a predetermined luminance value; and displaying, in a video display period, the image represented by the video signals, and displaying the sub-images in time series in a communication period different from the video display period.
US09262953B2	Display device and display panel Disclosed are a display panel in which all or some portions of an inspection pad and an inspection wire for inspection of a panel are formed in the display panel, and a display device.
US09262950B2	Augmented reality extrapolation techniques Augmented reality extrapolation techniques are described. In one or more implementations, an augmented-reality display is rendered based at least in part on a first basis that describes a likely orientation or position of at least a part of the computing device. The rendered augmented-reality display is updated based at least in part on data that describes a likely orientation or position of the part of the computing device that was assumed during the rendering of the augmented-reality display.
US09262948B2	Deployable collapsible indoor-outdoor sign assembly A collapsible and deployable indoor-outdoor sign assembly that can easily and quickly be installed, taken down, and transported, and still have excellent stability, strength, and longevity.
US09262946B2	Profiles used in generating channel letters A profile for making channel letters is disclosed. The profile can have a rule having a top edge, a bottom edge, a first surface, and a protective coating. The top edge and the bottom edge can be separated by a profile height. The first surface can describe an interior surface of a completed channel letter. The profile can also have a first rib bonded to the first surface with an adhesive. The first rib can be disposed parallel to a profile axis and separated from the top edge by a face plate thickness. The first rib can be configured to receive one or more cuts allowing the profile to bend and form the channel letter. The profile can be made by bonding the first rib to the rule using an adhesive.
US09262942B2	MRI training device MRI training and adjustment device for positioning the tip of a medical implement in living tissue, comprising a dummy which contains in the space inside it target pieces that show up in the MRI and the other component parts of which are invisible in the MRI, wherein a further component part of the training device is a base plate, which can be fastened under an MRI coil for the living tissue to be examined and carries at least one fastening block, which can be moved linearly with respect to the tissue and to which there can be detachably fastened either the dummy and/or a tissue pressing frame, which has an opening that is crossed by at least one elongated pressing rail, wherein the base plate, the fastening block, the tissue pressing frame and the pressing rail are invisible in the MRI.
US09262940B2	Musical notation interface for the visually impaired Various systems to aid a visually impaired musician to learn musical notation. The system includes a microprocessor with a memory adapted to store musical notation. Multiple transducers are operatively attached to the microprocessor. The transducers are spatially located on and/or in contact with a part of the body of the visually impaired musician. Responsive to the musical notation, the microprocessor is configured to signal the transducers to provide a physical or tactile sensation to the part of the body of the visually impaired musician.
US09262939B2	Integrated live and simulation environment system for an aircraft A method and apparatus for training in an aircraft. A display system is associated with an aircraft. A sensor system is associated with the aircraft. A training processor is configured to be connected to the aircraft. The training processor is configured generate constructive data for a number of simulation objects and generate simulation sensor data using the constructive data. The training processor is further configured to present the simulation sensor data with live sensor data generated by the sensor system for an aircraft on a display system in the aircraft.
US09262938B2	Combining different type coercion components for deferred type evaluation In a method of answering questions, a question is received, a question LAT is determined, and a candidate answer to the question is identified. Preliminary types for the candidate answer are determined using first components to produce the preliminary types. Each of the first components produces a preliminary type using different methods. A first type-score representing a degree of match between the preliminary type and the question LAT is produced. Each preliminary type and each first type-score is evaluated using second components. Each of the second components produces a second score based on a combination of the first type-score and a measure of degree that the preliminary type matches the question LAT. The second components use different methods to produce the second score. A final score representing a degree of confidence that the candidate answer matches the question LAT is calculated based on the second score.
US09262932B1	Extended runway centerline systems and methods Extended runway systems and methods include generating a runway centerline that extends from a start point on the runway to an endpoint located at a predefined distance from the start point. One or more distance markers are also calculated for the runway centerline. Display data is provided to an electronic display that causes the display to show the runway centerline and the one or more distance markers.
US09262928B2	Prediction of flight path privacy A method of predicting an achievable level of privacy of a flight path can include receiving an indication of a flight route of an aircraft, receiving an indication of one or more privacy enhancement techniques, estimating an air traffic density for one or more airspaces along or near the flight route where the estimating is based on information obtained from one or more aviation information databases, and estimating an achievable level of privacy of the flight path based, at least in part, on the air traffic density for one or more airspaces and the one or more privacy enhancement techniques. The method can further include using the estimated achievable level of privacy of the flight path as a privacy layer in one or more flight planning and optimization problems.
US09262924B2	Adapting a warning output based on a driver's view A human machine interface (HMI) can communicate warnings and messages to a driver by selecting among a variety of warning devices based on information related to the driver's viewing angle. The variety of warning devices can include a primary-visual warning device (e.g., a heads up display), secondary-visual warning devices (e.g., an instrument cluster or a navigational screen), a portable device (e.g., a tablet or a cellular phone), an audio system, or a haptic device. The HMI apparatus displays warnings on visual warning devices within the driver's view, can signal an active portable device to output a warning. Visual warnings can include directional cues. Audio warnings may accompany the visual warnings, and can be output with greater intensity when no visual devices are within the driver's view.
US09262922B2	Parking management system including rail A parking management system including a rail is described. A camera module takes images of a parking area, has a chargeable battery, and moves along the rail using a motor and wheels. A charging and AP module charges the camera module, receives image information from the camera module, and is movable using a motor, a running rail and gears. A server processes the image information received from the charging and AP module. A computer is connected to the server, and contains management software which executes a parking situation search using a database of the server. The camera takes images from the parking area while moving along the rail, and is positioned on the charging rail so as to be charged from the charging and AP module.
US09262921B2	Route computation for navigation system using data exchanged with ticket vending machines A method for assisting a driver to locate a parking space includes identifying a user-selected destination with a navigation system of a first vehicle. While the driver of the first vehicle is being guided by the navigation system towards the selected destination, parking availability information is acquired from a first space allocation device (e.g., ticket vending machine), associated with a first parking zone. The parking availability information includes parking availability information for at least one second parking zone associated with a respective second, space allocation device, remote from the first space allocation device. The second parking availability information for the second parking zone(s) is communicated to the first space allocation device by at a respective second navigation system of at least one second vehicle. A parking zone is selected, based on the user-selected destination and acquired parking availability information transmitted from the first space allocation device.
US09262920B2	Methods and devices for outputting information in a motor vehicle A method and to a device are provided for outputting information in a motor vehicle, in which as a function of an event visual and/or acoustic information is output to a driver of the motor vehicle. In order to achieve an improved choice of the suitable timing of the outputting of the information it is provided that the time between registering of the event and outputting of the information is set as a function of the orientation of the driver's head.
US09262912B2	Localizing tagged assets using modulated backscatter Methods and systems for localizing an asset using the modulated backscatter from an asset tag and one or more marker tags are described. The system includes the reader, a location module and one or more marker tags. The location estimates for the asset tag are based partially on a prior knowledge of the location of each of the one or more marker tags. The location for each marker tag may be stored in a database. The location module determines a location estimate for the asset tag using the estimated parameters of the modulated backscatter signals received from one or more marker tags and from the asset tag. Using the known locations of the marker tags, a location estimate of the asset tag can be determined. The location estimate may be a relative location, an absolute location, and/or may be a zone including the marker tags. A mobile reader using the marker tags can localize asset tags throughout a large area and may, for example, take an inventory of assets throughout the large area.
US09262905B2	Portable compliance dispenser A portable compliance dispenser provides a compliance module that is removably attached to a replaceable refill container, which carries any suitable liquid material, such as sanitizer. The compliance module is configured to be worn or carried by an individual and communicates hygiene compliance data to a remote monitoring station when material from the refill container is dispensed.
US09262904B2	Personal identification system A method of monitoring objects such as offenders, the method including the steps of: providing an electronic monitoring device for attachment to an object to be monitored; providing a tamper evident tether for attachment of the electronic monitoring device to the object to be monitored; attaching the electronic monitoring device to the object to be monitored using the tamper evident tether; and remotely monitoring the electronic monitoring device in order to monitor the location of the object. The method further includes the steps of: providing the tamper evident tether with a unique identifier; providing an electronic data store remote from the electronic monitoring device; recording the unique identifier for the tether in the electronic data store, together with information about the object to be monitored and/or the associated electronic monitoring device; and performing an interrogation step at least once after the date on which the electronic monitoring device is first attached to the object, to determine whether the tether associated with the electronic monitoring device has the same unique identifier as that recorded in the electronic data store.
US09262902B2	Apparatus and method for tagging a perpetrator Apparatus and methods for tagging, or otherwise marking, a perpetrator or suspected perpetrator are provided. The apparatus includes a marker delivery device configured to mark the perpetrator, for example, with a canine scent or fluorescent marker; and a trigger configured to actuate the marker delivery device, for example, a button or switch. The marker delivery device may deliver a fluid or a solid to the clothes or accessories of a perpetrator when activated. The apparatus may also include a sensor adapted to detect the presence of the perpetrator, for example, an optical or mechanical sensor. The sensor may be adapted to detect the presence of the perpetrator in a target area of the marker delivery device. Methods of tagging are also disclosed. Aspects of the invention are uniquely adapted for convenience store or gas station security, but can also be applied in residential and office environments, among others.
US09262899B2	Method, device and system for implementing video recording retrieval Embodiments of the present invention disclose a method, a device, and a system for implementing video recording retrieval. The method includes receiving an alarm event, where the alarm event includes a device identifier of an alarm device and an alarm occurrence time. The method further includes generating a video recording index of a video recording corresponding to the alarm event according to the alarm event, where the video recording index includes video recording time information and video recording acquisition information. The method also includes generating a video recording bookmark of the video recording corresponding to the alarm event according to the alarm event, where the video recording bookmark includes a camera identifier and the alarm occurrence time.
US09262894B2	Gaming device having multiple symbols at a single symbol position A gaming device including a plurality of reels having a plurality of symbols including at least one replicator symbol. The replicator symbol includes at least two of the same symbols in a single symbol position on the reels. The replicator symbol may include any suitable number of the same symbols. The replicator symbol thereby increases the likelihood that a player will obtain a winning symbol combination on the reels and also an award in a game. In one embodiment, a winning symbol combination includes at least one replicator symbol and at least one other symbol at a plurality of symbol positions on a payline associated with the reels. In another embodiment, the winning symbol combination at least one replicator symbol and at least one other symbol at a plurality of symbol position in at least one symbol position on a plurality of paylines associated with the reels.
US09262893B2	Replacement reel gaming device and method Apparatuses and methods for facilitating participation in a gaming activity. A reel configuration of a plurality of reels is presented, where each of the reels includes one or more associated gaming symbols. The presentation of the gaming symbols is modified on the plurality of reels, such as by spinning the reels or otherwise changing which symbols are presented on the reels. A replacement reel is presented, to supersede or otherwise supplant at least one of the gaming symbols of the reel configuration. Results of the gaming activity are established using the gaming symbols of the plurality of reels and the replacement reel. The result is thereby based on a resulting presentation of symbols that includes both the symbols of the primary reel configuration and the symbol(s) of the replacement reel(s).
US09262892B2	Gaming system and method of gaming A gaming system is disclosed that comprises a symbol selector arranged to select a plurality of base symbols from a set of base symbols for display in a display area; and at least one set of additional symbols, each set of additional symbols including a plurality of additional symbols. The gaming system is arranged to incorporate the additional symbols of an additional symbol set into the base symbol set so as to define a combined symbol set, and the gaming system is arranged to select and display a plurality of base and/or additional symbols from the combined symbol set. The gaming system further comprises an outcome evaluator arranged to determine a game outcome based on the selected base and/or additional symbols.
US09262887B2	Gaming machines with player reservation feature A player reservation feature is provided for a casino gaming machine by a secondary controller of the casino gaming machine. The player reservation feature may be accessed at the gaming machine or remotely at another gaming machine or other device, e.g., a smart phone, tablet, personal computer, and the like. The gaming machine is locked and unavailable for play except by the player that made the reservation. Reserving a gaming machine may be free, or a fee may be accessed for a reservation. Where a fee is assessed, the fee may be waived for a reserving player. Where the reservation feature is being accessed remotely, a casino floor map may be displayed at the device that is being used, such as another casino machine, smart phone, tablet, personal computer, and the like, along with information about each gaming machine on the casino floor.
US09262880B2	Keyless entry system A keyless entry system includes a transmitter and a receiver. The transmitter includes an operation switch, transmission means, and transmission control means. The receiver includes receiving means and determination means. The transmission control means generates operation information including a function code corresponding to the operation switch and a count value corresponding to the number of operations of the operation switch. The transmission means transmits the operation information using a plurality of radio signals in different frequency bands. The receiving means receives the plurality of radio signals and detects the operation information from the plurality of received radio signals. The determination means specifies the content of an instruction to the device based on the function code and the count value included in the operation information.
US09262878B1	System and method for one-way remote activation with adaptive protocol A system and method for remote activation of a device includes, in one embodiment, transmitting a command signal according to one of a first transmission protocol and a second transmission protocol, and selecting the first transmission protocol for use in transmitting the command signal when a selected command is of a first type, and selecting the second transmission protocol for use in transmitting the command signal when a selected command is of a second.
US09262871B2	Methods and a system for dispensing In one example, the invention includes steps of: activating feeding and exiting motors of a dispensing device that cause corresponding rollers to rotate in forward direction, wherein the feeding motor is operatively connected to a displacement optical sensor, wherein the feeding and exiting rollers move a dispensing object; wherein an exit sensor generates a first signal, indicating that a leading edge of the dispensing object has activated the exit sensor, generating, by the stationary displacement optical sensor, a second signal, when, by passing at least one light beam over a surface of the portion of the dispensing object, the stationary displacement optical sensor determines that the portion of the dispensing object has traveled a pre-determined distance along the dispensing passage.
US09262868B2	Method for transforming mapping data associated with different view planes into an arbitrary view plane A computer-implemented method for rendering mapping data is provided. The method includes obtaining mapping data for displaying a map image, wherein the mapping data comprises data of an image corresponding to a view plane, the view plane comprising an imaginary plane formed perpendicular to a direction of a viewer's line of sight. The method also includes projecting the obtained mapping data onto a reference view plane, identifying a user-selected view plane in which to display the map image, transforming the projected mapping data to correspond to the identified user-selected view plane, and generating the map image based on the transformed mapping data. Systems and machine-readable media are also provided.
US09262865B2	Content creation tool A server for content creation is described. A content creation tool of the server generates an experience content dataset using a template to process a content identifier and virtual object content. An experience generator of the server provides the experience content dataset to a device that recognizes the content identifier, to generate an interactive experience with the virtual object content at the device.
US09262860B2	System and method for importance sampling of area lights in participating media Provided are systems and methods that address the problem of single scattering in homogeneous volumes. In one implementation, an importance sampling technique is provided that avoids a singularity near point light sources. The system and method can be extended to the situation of area lights of arbitrary shapes. The error caused by the non-constant distance to the finite-extent area light is distributed by using random sample points within the area light as points from which lighting is calculated for sampling points along the ray.
US09262857B2	Multi-linear dynamic hair or clothing model with efficient collision handling Systems and method for modeling hair in real-time with user interactive controls are presented. One embodiment may take the form of a method of hair motion modeling including representing hair with hair guides, each hair guide comprising a plurality of hair points and reducing a dimensionality of the hair guides to achieve a reduced sub-space. Additionally, the method includes generating a data tensor for multiple factors related to the hair guides and decomposing the tensor to create a model characterizing the multiple factors in a multi-linear hair framework. The hair may be hair, such as human hair, animal fur, or clothing fibers.
US09262856B1	Providing content responsive to performance of available actions solicited via visual indications Content may be provided within a virtual space responsive to user characters performing available actions solicited via visual indications within the virtual space. One or more available actions may be determined. A given available action may include an action that is available to be performed by one or more user characters within the virtual space. Individual ones of the one or more available actions may be solicited via visual indications of the respective available actions. Performance of individual available actions by one or more user characters may be effectuated responsive to one or more conditions being satisfied. Content may be presented in the virtual space responsive to performance of at least one of the available actions.
US09262853B2	Virtual scene generation based on imagery Techniques are disclosed for virtual scene generation. An image depicting a scene and annotated by a sparse set of labels is received. A dense set of labels annotating the image and a density map associated with the image are generated based on the sparse set of labels. A virtual scene is generated based on the dense set of labels and the density map, and the virtual scene is output.
US09262851B2	Heat mapping of defects in software products Systems, methods, and other embodiments associated with heat mapping of defects in software components are described. In one embodiment, a method includes receiving feedback data that describes errors reported from a software product, wherein the software product includes components. Records are retrieved that are associated with the errors reported, where a record links an error to a defect in a component from the software product. A heat map is generated that has regions assigned to represent different components from the software product. Graphical elements are generated and added to a region for each defect identified in a corresponding component, where a size of a visual area of the region is based, at least in part, on a number of graphical elements contained in the region.
US09262850B2	Descriptive framework for data visualization Described herein is a descriptive framework to facilitate data visualization. In accordance with one aspect of the framework, one or more module manifests are provided, wherein a module manifest describes a module that represents a particular component of a visualization. A chart manifest may be used to coordinate the one or more module manifests. A visualization may be rendered based on the chart manifest.
US09262849B2	Chart animation Chart animation control may be provided. Upon receiving a change to a displayed visualization comprising a plurality of data elements, a determination may be made as to whether to animate an update of the visualization according to the change to the displayed visualization. In response to determining to animate the update of the visualization according to the change to the data value, an animation of the update may be constructed and rendered and the updated visualization may be displayed.
US09262848B2	Method for stroking paths A method of stroking a curved path with a fill of pre-determined thickness, where the path has line segments defined by a number of points, the method being performed by forming a number of projection lines normal to the curved path at the points, where each of the projection lines has a length based on the fill thickness, determining an intersection between a set of the projection lines, the intersection indicating the occurrence of a void in stroking the curved path, and then constructing one or more polygons filling in the void in the stroked path.
US09262845B2	Image data reconstructed from undersampled higher resolution and incomplete lower resolution projection data A method includes generating higher resolution image data based on undersampled higher resolution projection data and incomplete lower resolution projection data. The undersampled higher resolution projection data and the incomplete lower resolution projection data are acquired during different acquisition intervals of the same scan. A system includes a radiation source configured to alternately modulate emission radiation flux between higher and lower fluxes during different integration periods of a scan, a detector array configured to alternately switch detector pixel multiplexing between higher and lower resolutions in coordination with modulation of the fluxes, and a reconstructor configured to reconstruct higher resolution image data based on projection data corresponding to undersampled higher resolution projection data and incomplete lower resolution projection data.
US09262842B2	Image processing apparatus and image compressing method Provided is an image processing apparatus for compressing an image. The apparatus includes a compressing section configured to compress an image based on N representative colors to generate N-representative-color-based compression data and calculate an indicator for evaluating an image quality of the image compressed based on M representative colors during compressing the image based on N representative colors, where M
US09262841B2	Front to back compositing In one embodiment, pixels that cannot change their color due to the alpha blend mode and the color already stored in a render target are detected. For example, if destination alpha blending is used and a target pixel has an alpha value of 1.0, it will not change color regardless of the computed color of subsequently composited objects. Both computing the object colors and accessing the frame buffer can be avoided when such a case is detected. This may save computations and bandwidth in some embodiments.
US09262838B2	Method and apparatus for detecting traffic video information The present invention provides a method and an apparatus for detecting traffic video information. The method includes: acquiring a traffic video stream; determining color features of each frame of image in the traffic video stream; calculating the inter-frame distance between adjacent frames according to the color features; calculating the boundary of an image clustered frames' group according to the inter-frame distance by adopting an image clustering evaluation standard in RGB space and an image clustering evaluation standard in YUV space respectively; and determining a final boundary of the image clustered frames' group according to the boundaries of the image clustered frames' group in RGB space and YUV space. By using the present invention, the stability of detection results in different environments may be improved.
US09262837B2	PCIE clock rate stepping for graphics and platform processors Circuits, methods, and apparatus for modifying the data rate of a data bus. In a circuit having two processors coupled by a data bus, the processors each learn that the other is capable of operating at a modified data rate. The data rate is then changed to the modified rate. Each processor may learn of the other's capability by reading a vendor identification, for example from a vendor defined message stored on the other processor. Alternately, each processor may provide an instruction to the other to operate at the modified rate, for example by writing to the other processor's extended capability registers. In another circuit having two processors communicating over a bus, it is determined that both are capable of transmitting and receiving data at a modified data rate. An instruction is provided to one or both of the processors to transmit at the modified rate.
US09262831B2	Method and device for joining a plurality of individual digital images to form a total image In a device and a corresponding method for joining a plurality of individual digital images to form a total image, a plurality of features is determined in a first individual image by means of a selection unit using a feature-based algorithm and then tracked in a second individual image by means of a tracking unit. A transformation matrix, with which the individual images are joined in an output unit to form the total image, is calculated from the determined feature correspondences in a transformation unit. The individual images can be joined in real time and with a high degree of accuracy by means of the feature-based algorithm in combination with a robust algorithm to calculate the transformation matrix.
US09262830B2	2D/3D image registration 2D images are registered with 3D volume data. In order to provide 2D/3D registration with a facilitated workflow 3D volume data (112) of an object, having a frame of reference is received. A transformation plane (116) is defined in relation to the 3D volume data. A 2D image of the object with an image plane is received. The transformation plane is projected on the image plane. The frame of reference is aligned with the 2D image. At least one alignment interaction value (128) is projected (130) on the transformation plane to determine (134) at least one transformed interaction value (132). The frame of reference is translated with the at least one transformed interaction value.
US09262826B2	Methods of non-touch optical detection of vital signs from multiple filters A microprocessor is operably coupled to a camera from which patient vital signs are determined. A temporal variation of images from the camera is generated from multiple filters and then amplified from which the patient vital sign, such as heart rate or respiratory rate, can be determined and then displayed or stored.
US09262824B2	Assessments of vascular permeability for biomedical imaging studies Described herein are methods and systems for analyzing biomedical images using new models. Example models include a linear reference region model and a reference agent model. In one example aspect, a computer-implemented method is provided. The method may involve determining, based on a set of biomedical images, a first concentration-activity curve and a second concentration activity-curve. Additionally, the method may further include determining a value of at least one pharmacokinetic (PK) parameter based on the first concentration-activity curve and the second concentration-activity curve and a linear model that relates the first concentration-activity curve to the second concentration-activity curve. The value of the at least one PK parameter may be determined based on application of a linear least square fitting algorithm to the linear model. Also, the method may include causing a graphical display to provide a visual indication of the value of the at least one PK parameter.
US09262821B2	Inspection recipe setup from reference image variation Systems and methods for generating information for use in a wafer inspection process are provided. One method includes acquiring output of an inspection system for die(s) located on wafer(s), combining the output for the die(s) based on within die positions of the output, determining, on a within die position basis, a statistical property of variation in values of characteristic(s) of the combined output, and assigning the within die positions to different groups based on the statistical properties determined for the within die positions. The method also includes storing information for the within die positions and the different groups to which the within die positions are assigned in a storage medium that is accessible to the inspection system for performing the wafer inspection process, which includes applying defect detection parameter(s) to additional output of the inspection system generated for a wafer based on the information thereby detecting defects on the wafer.
US09262816B2	Dynamic waveform region enhancement A system and method includes reception of a color image comprising a plurality of color pixels, conversion of the color image to a monochromatic image comprising a plurality of monochromatic pixels, performance of M erosion operations on the monochromatic image to generate an eroded monochromatic image, where M is equal to or greater than one, performance of N dilation operations on the eroded monochromatic image to generate a mask image, where N is equal to or greater than one, identification of one or more regions of the mask image based on the mask image, and modification of regions of the color image corresponding to the identified regions of the mask image.
US09262812B2	Method for reducing row and column noise in imaging systems A method for the reduction of noise in an image including identifying neighboring pixel values in pixels proximate to a subject pixel; comparing the neighboring pixel values to a preset tolerance range; using neighboring pixel values within the tolerance range to calculate a pixel intensity correction value; and applying the pixel intensity value to the subject pixel.
US09262811B2	System and method for spatio temporal video image enhancement A method for improving quality of low light video images including: receiving a current video frame; temporally enhancing it by applying a first weight matrix including higher weight factors for stationary regions and lower weight factors for moving regions to the received frame and a reference frame to generate an enhanced temporal video frame; spatially enhancing the enhanced temporal video frame by applying a second weight matrix including higher weight factors for stationary regions and lower weight factors for moving regions to generate an enhanced spatial video frame; and motion enhancing the enhanced temporal video frame by extracting matched rigid moving objects in a previous or future frame and processing each of the extracted matched rigid moving objects with a corresponding rigid object in the enhanced temporal or spatial or raw current video frame.
US09262810B1	Image denoising using a library of functions A method denoises a noisy image by, for each pixel in the noisy image, first constructing a key from a patch, wherein the patch includes locally neighboring pixels around the pixel. A function is selected from a function library using the key. Then, the function is applied to the patch to generate a corresponding noise free pixel for the pixel.
US09262808B2	Denoising of images with nonstationary noise An input image is denoised by first constructing a pixel-wise noise variance map from the input image. The noise has spatially varying variances. The input image is partitioned into patches using the noise variance map. An intermediate image is determined from the patches. Collaborative filtering is applied to each patch in the intermediate image using the noise variance map to produce filtered patches. Then, the filtered patches are projected to an output image.
US09262807B2	Method and system for correcting a distorted input image A method for correcting a distorted input image includes determining a local region of an image to be displayed and dividing the region into an array of rectangular tiles, each tile corresponding to a distorted tile with a non-rectangular boundary within the input image. For each tile of the local region, maximum and minimum memory address locations of successive rows of the input image sufficient to span the boundary of the distorted tile are determined. Successive rows of the distorted input from between the maximum and minimum addresses are read. Distortion of the non-rectangular portion of the distorted input image is corrected to provide a tile of a corrected output image which is stored.
US09262806B2	System and method for resolution enhancement The present invention relates to a system (1) and method (100) for resolution enhancement which enables the depth resolution to be enhanced without using gimbal, performs depth description independent from lighting conditions and camera parameters in high resolution.
US09262792B2	Rights management for content aggregators An arbitrator receives a request to use a plurality of content in an aggregation. The arbitrator determines whether there exist proper rights to use the plurality of content in the aggregation. The requestor is communicated whether permission is granted. The determination may include negotiating for extending right of use by an arbitrator. This negotiation may communicate with content hosting service(s) or the content author(s). The determining step retrieves, stores, and maintains rights information to and from an information store which is accessible by the rights management system.
US09262790B2	System and method for determining ranking of keywords for each user group Provided are a system and method for determining rankings of keywords according to a user group. The keyword ranking determining system includes a data grouping unit to group data of a weblog according to a predetermined theme, a weight application unit to calculate a document concentration that denotes a concentration degree, with respect to the theme, of a document corresponding to the data grouped according to the theme and to apply a weight corresponding to the document concentration to the data, a data set generation unit to generate at least one data set by grouping the data applied with the weight according to a search intention and a ranking determination unit to determine rankings of the at least one data set according to the theme, and a main keyword determination unit to determine a main keyword representing each of the at least one data set.
US09262783B1	System and method for evaluating input based on dynamic grammars A method and system for evaluating service definitions in a service-oriented architecture (SOA) system which provides service offerings categorized according to service categories using a taxonomy. A specification field receives a formal definition of a service. The formal definition is for inclusion to define one of service offerings of the SOA. A current grammar is determined which is currently in effect as a specification-requirement of acceptable definitions for a service category in which the service is categorized. The current grammar is a common grammar. The system determines whether the formal definition in the specification field is acceptable, by adhering to the current grammar determined to be currently in effect as the specification-requirement for the category of the service. The formal definition is accepted for the service when it is determined to be acceptable according to the current grammar. Otherwise, the formal definition is rejected.
US09262779B2	Data management system A data model and associated systems and methods enable comprehensive and robust analysis based on a member-, employee-, and branch-centric data model. The data model is integrated in a manner in which common data entities for member, branch, employee and time, are related centrally to other data entities. This data structure enables breadth in reporting and analysis. The data model also provides depth in analysis and insight that may be gained from the data quickly, in real-time and without manual manipulation. Automation of reporting and analysis processes is also supported.
US09262778B2	Methods and systems for storefront generation A method and a system to generate mobile storefronts are described. The storefront application is executable by a user device to allow a user of the user device to access the storefront and purchase an item from a merchant. The system comprises an initialization module that provides an initialization interface to an identified merchant that is used to initialize creation of a storefront application. A storefront module provides a generation interface that receives, from the merchant, an appearance for the storefront application. An inventory module receives an inventory information describing items for sale. A policy module provides a policy interface that receives policies of the storefront. A platform module generates source code that when compiled, becomes the storefront application. The source code is generated based at least on one or more templates and the inventory.
US09262777B2	Card reader with power efficient architecture that includes a wake-up circuit A card reader is provided with a read head with a slot and is configured to be coupled to a mobile device and has a slot for swiping a magnetic stripe of a card. The read head reads data on the magnetic stripe and produces a raw magnetic signal indicative of data stored on the magnetic stripe. A power supply is coupled to wake-up electronics and a microcontroller. An output jack is adapted to be inserted in a port of the mobile device and deliver an output jack signal to the mobile device. The wake-up electronics is powered by a microphone bias of a mobile device.
US09262776B2	System and method for concept development A computer implemented method, system, and computer program product include one or more processors providing a framework for building a visual representation of a product concept, the visual representation including one or more of a textual component and a graphical component; one or more processors receiving a designation of an element within at least one of the textual component and the graphical components as a dynamic element; one or more processors associating the dynamic element with a variant list including one or more element variants; one or more processors receiving a selection of a first element variant from the variant list; and one or more processors generating a first instantiation of the visual representation including the first element variant as the dynamic element.
US09262775B2	Methods, devices and systems for providing mobile advertising and on-demand information to user communication devices Methods, systems, software, computer-readable media, and the like relate to providing and receiving relevant data from one or more entities. Data is received by a wireless user device directly from a wireless transmitter. The data may be provided to a stationary or moving user. A consumer in a vehicle, for instance, may have a smartphone, mobile phone, tablet PC, navigation system, or other similar mobile device, and can use such device to interact with a geographically proximate advertising module having a wireless transmitter. The wireless transmitter may also be stationary or moving, and can be incorporated into structures such as a vehicle, a billboard, a building, a road sign, a traffic light, or the like.
US09262774B2	Method and systems for providing a digital display of company logos and brands Described herein are methods and systems allowing a company to market and advertise its brands, products and/or services in a mobile platform by use of an application converting words and texts into logos and displaying the same. Particularly, this application allows company logos to be inserted and displayed in any mobile texts and messages whenever corresponding keywords are entered or selected by end users in a mobile communication application, such as SMS/text, IM, iMessage, and any social networking application, for example, Facebook and Twitter.
US09262767B2	Systems and methods for generating statistics from search engine query logs A computer-implemented method includes calculating first statistics about a user-identified event within a first subset of a database of events; selecting a second subset of the database of events based on said first statistics; calculating second statistics about the user-identified event within the second subset of the database of events; merging the first and second statistics as statistics of the user-identified event within the entire database of events; and generating a result including at least a portion of the merged statistics of the user-identified event.
US09262763B2	Providing attachment-based data input and output Various embodiments of systems, methods, and software provide attachment-based mass data input and output for a distributed application system. Software for interactive, attachment-based data management may comprise computer readable instructions operable when executed to receive a request from a logically remote client via a network interface, where the request indicates a data file and a business object associated with a business application. The business object is then updated with a message in a format associated with the business application based on the data file. The data file is then stored in a repository and a dependent object (included in, or referenced by, or otherwise associated with the business object) is then updated with a logical location of the data file in the repository.
US09262758B2	Travel account A user can set up a travel account with a payment provider, to inform the payment provider of expected dates and locations of travel, along with limits or restrictions at the various locations and/or dates. When the user travels and attempts to make a payment, the payment provider can determine the location and date to aid in processing the payment request, resulting in an easier process for the user, while still providing additional security with the limits and restrictions.
US09262757B2	Method of transmitting information from a card reader with a power supply and wake-up circuit to a mobile device A method of transmitting information to a mobile device has a card reader with wake-up electronics and a microcontroller, and a power supply coupled to the wake-up electronics and the microcontroller. Data is read on the magnetic stripe. A raw magnetic signal is produced indicative of data stored on the magnetic stripe. The raw magnetic head signal is converted into a processed digital signal that the microcontroller can interpret. An output jack signal is sent to the mobile device.
US09262756B2	Point-of-sale (“POS”) controller Apparatus and methods are provided for adjusting a transaction cost and/or a transaction cost recovery amount. The adjusting may be based on a comparison of historical usage of a first payment instrument relative to use of a second payment instrument. Usage of the first or second payment instruments may be correlated to imposition of the transaction cost recovery amount. The adjusting may be based on determining a convenience fee and/or a transaction cost recovery amount for a funds transfer. The adjusting may be based on identifying a purchasing behavior. The purchasing behavior may include terminated or reduced spending, relative to historical spending, at a location that imposes a transaction cost recovery amount. The purchasing behavior may include identifying current payment instrument use at a location that imposes a transaction cost recovery amount.
US09262755B2	Mobile payment system During a financial transaction, a customer provides an identifier to a peripheral device (which may be a barcode scanner, a wireless receiver or a keyboard) coupled to the point-of-sale terminal. This identifier corresponds to a one-time payment credential token that includes financial information of the customer. Then, a service object executing on the point-of-sale terminal, which acts as a driver for the peripheral device, performs one or more operations based on at least the identifier to obtain the financial information. After providing the financial information and transaction information associated with the financial transaction to a financial institution specified in the financial information, the point-of-sale terminal receives a confirmation from the financial institution that the financial transaction has been completed.
US09262753B2	Video messaging A method for video messaging includes recording a video message, at a device, for a recipient; and selecting a contact as a recipient of the video message, at the device, without requiring typing at the device.
US09262750B2	System and method for creating an efficient and scalable cache mode for a collaboration suite application A system and method for creating a cached mode is created for some applications, such as for use with BES. Operations on the mailbox items are conducted off the cache, rather than off the collaboration suite server itself, thus reducing the load on the collaboration suite server. According to one aspect of the present invention, a filtered initial synchronization is performed with the cache in the client device to further reduce the load on the collaboration suite server as well as the required bandwidth. In one embodiment of the present invention, mailbox items on the local cache are periodically reaped so as to not over-burden the disk space in the client device. In one embodiment of the present invention, mailbox items not present in the cache can be requested on-demand from the collaboration suite server.
US09262749B2	System and method for generating permit reports A computer-implemented method for generating parking permits reports for a parking permit system. The method includes aggregating parking permit data for each zone within the parking permit system into a logical grouping in a database. Then processing data according to report generation instructions. The data is then parsed to obtain a requested report and the report is distributed to a specified party.
US09262739B2	Method, medium, and system for session based shopping The present disclosure involves a method of conducting a commercial transaction. In one aspect, the method of shopping includes receiving user information signifying the start of a shopping session; generating an electronic session identifier corresponding to the shopping session and a user identified by the user information; determining a selection of a product of a shopping facility; associating the product with the session identifier in response to the determining of the selection; and notifying the shopping facility of the associating of the product with the session. The receiving, the generating, the determining, the associating, and the notifying are each performed by a computing system.
US09262731B1	Service ticket analysis using an analytics device A device may receive ticket information associated with one or more service tickets. The ticket information may include a ticket category and ticket data associated with the one or more service tickets. The ticket data may be associated with the ticket category. The ticket data may describe information related to resolving the one or more service tickets. The device may identify, based on the ticket category or the ticket data, an association between the ticket category and an analysis category. The analysis category may be used to analyze the ticket information. The device may generate categorized ticket information based on the analysis category and the ticket information. The categorized ticket information may include the ticket data, and the ticket data may be associated with the analysis category. The device may provide the categorized ticket information.
US09262730B2	System and method for configuring dynamic service network based on netstore A dynamic service network creation apparatus includes a resource lookup and registration unit configured to look up and register network resource information of each of a plurality of network resource providers which are managed by a netstore apparatus; and a service network topology configuration unit configured to, in response to a service reservation request being received from each of a plurality of service providers through a service management system, dynamically configure a service network for providing a network-based service from the service provider to a service user that is to use the service of the service provider, wherein the dynamic service network creation apparatus is connected to the service management system that manages the network-based service provided by a plurality of the service providers and the netstore apparatus.
US09262725B2	Mental modeling for modifying expert model A mental modeling method and system may include providing at least one expert model, the at least one expert model including an analytical framework that summarizes subject matter expert-level knowledge. At least one mental model of at least one individual that summarizes subject matter individual-level knowledge is provided. The at least one expert model is modified based on the at least one mental model to provide at least one updated expert model.
US09262721B2	Automatically selecting analogous members for new population members based on incomplete descriptions, including an uncertainty characterzing selection A population comparison system, method and a computer program product. A stored list of population members, e.g., hydrocarbon reservoirs, includes parameters for corresponding known characteristics and analogous members for each member. A new population member input receives new member descriptions including parameters for each respective new member. A parameter extraction system automatically extracts an estimated value for each missing key parameter, providing a supplemented description. An analogous member selector automatically selects a subset of listed population members as analogous members for each new population member responsive to the supplemented description. The analogous members serve as a basis for uncertainty characterization from the joint parameter distribution and univariate distributions for each parameter.
US09262719B2	Reasoning engines A reasoning engine is disclosed. Contemplated reasoning engines acquire data relating to one or more aspects of various environments. Inference engines within the reasoning engines review the acquire data, historical or current, to generate one or more hypotheses about how the aspects of the environments might be correlated, if at all. The reasoning engine can attempt to validate the hypotheses through controlling acquisition of the environment data.
US09262717B2	Apparatus and a method for retrieving an object According to one embodiment, an object retrieval apparatus includes a query acceptance unit and a collision decision unit. The query acceptance unit is configured to accept a retrieval query indicating (N−1)-dimensional surface in N-dimensional space (N is an integral number larger than or equal to three). The collision decision unit is configured to decide whether the (N−1)-dimensional surface intersects N-dimensional cuboid positioned in the N-dimensional space. The collision decision unit decides by using a plurality of decision functions. The plurality of decision functions includes zero-th˜(N−1)-th decision functions to decide whether at least a part of at least one of X-dimensional face (X is all integral numbers larger than or equal to zero, and smaller than or equal to (N−1)) of the N-dimensional cuboid is included in the (N−1)-dimensional surface.
US09262716B2	Content response prediction Techniques for predicting a user response to content are provided. In example embodiments, one or more feature vectors are assembled into an assembled feature vector. A particular one of the feature vectors not being available is determined. In response to determining that the particular one of the feature vectors is not available, the particular feature vector is ignored based on an importance value associated with the particular feature vector. A substitute value associated with the particular feature vector is inserted into a portion of the assembled feature vector associated with the particular feature vector. A prediction modeling process based on the assembled feature vector and a prediction model is performed to predict a likelihood of a particular member performing a particular user action on a particular content item.
US09262714B2	Frequent pattern extraction apparatus frequent pattern extraction method and program There is provided a frequent pattern extraction apparatus. In the apparatus, time series data for an item operation is divided into a plurality of item operation sets. Using a set degree of similarity between the item operation sets, an abstract item operation set is generated. A pattern of sequences that frequently appear is extracted from the sequences in the abstract item operation set. Using the pattern of sequences that frequently appear, an item as well as an item operation are recommended to a user.
US09262712B2	Structural descriptions for neurosynaptic networks Embodiments of the invention provide a method comprising creating a structural description for at least one neurosynaptic core circuit. Each core circuit comprises an interconnect network including plural electronic synapses for interconnecting one or more electronic neurons with one or more electronic axons. The structural description defines a desired neuronal activity for the core circuits. The desired neuronal activity is simulated by programming the core circuits with the structural description. The structural description controls routing of neuronal firing events for the core circuits.
US09262710B2	Product identification tag and associated methods Exemplary embodiments are directed to a product identification tag, generally including a durable material that includes indicia thereon corresponding to useful information. The durable material is generally configured to be at least one of pierced and/or punched to capture distinctive identification information for a specific product. The distinctive identification information can be at least one of a serial number, an in-service date, and an inspection date. Exemplary embodiments are also directed to a method of product identification, comprising providing a durable material that includes indicia thereon corresponding to useful information. The exemplary method further includes at least one of piercing and/or punching the durable material to capture distinctive identification information for a specific product and detachably securing the durable material to the specific product.
US09262708B2	Low-capacity power supply, power supply system, and image forming apparatus A system for minimizing damage based on excess current or voltage is described in which a connection between an AC power supply and a smoothing circuit is interrupted. The system may include capacitors and relays located between the AC power supply and a rectifier. By determining that a voltage or current is greater than a threshold level, the relay or relays may be opened. For instance, the increased voltage or current may be due to a failure of one or the capacitors, resulting in a short circuit across the capacitor. By opening the relay or relays, damage due to the excess current or voltage may be prevented from damaging downstream components.
US09262706B2	Image forming apparatus that controls jetting of toner, image processing apparatus, control method therefor, and storage medium An image forming apparatus which is capable of obtaining stable and satisfactory cleaning performance and fixing performance without holding, in an image forming unit which forms an image on a recording material based on a video signal, data for performing maintenance of the image forming unit. A synchronization signal output from the image forming unit and indicative of timing with which the video signal is output is detected. It is determined whether the synchronization signal is a normal synchronization signal for outputting a video signal for use in forming an image on the recording material or a pattern synchronization signal for outputting a pattern signal that is a video signal for use in performing maintenance of the image forming unit. When the synchronization signal is the normal synchronization signal, the video signal is output. When the synchronization signal is the pattern synchronization signal, the pattern signal is output.
US09262705B2	Processing and printing apparatus, and processing method for suppressing bronzing in a printed image Differences in color change due to bronze colors and the optical interference state related to bronzing are suppressed among multiple print modes. The blue primary color “Blue” in the standard RGB gamut is mapped to a point (color) that has moved in the clockwise direction, and that color is taken to be the primary color “Blue-s” in the Standard mode gamut. As a result, when an observer observes this color, the color shifted in the counter-clockwise direction is perceived as a color of the same hue as the primary color “Blue-f” in the Fine mode gamut, suppressing the difference in perceived color between the Fine mode and the Standard mode.
US09262704B1	Rendering images to lower bits per pixel formats using reduced numbers of registers Methods and systems render higher bit per pixel contone images to lower bit formats using multiple registers of a SIMD processor. The rendering process uses a first register to maintain contone image values of all the pixels being simultaneously processed. A second register maintains a threshold value used during the conversion process. A third register maintains one value for the print ready format pixels (e.g., those having less bits per pixel), and a fourth register maintains the other value (e.g., 0) for the print ready format pixels. Also, a fifth register maintains the conversion error amount for all the pixels being simultaneously processed. Sixth through ninth registers maintain distributed conversion error amounts produced by the diffusing process (for different pixels being simultaneously processed); and a tenth register maintains the pixels in the print-ready format produced by the conversion for all the pixels being simultaneously processed.
US09262693B2	Object detection apparatus An object detection apparatus includes a storage section storing a plurality of selection patterns as combinations of one of a plurality of recognition dictionaries and one of a plurality of image recognition algorithms, a specifying means for specifying at least one of a distance from a position at which an input image is taken and a target corresponding to the detection object within the input image and a state of light of the input image, a selection means for selecting one from the plurality of the selection patterns based on at least one of the distance and the state of the light specified by the specifying means, and a detection means for detecting the detection object within the input image by performing an image recognition process using the image recognition dictionary and the image recognition algorithm included in the selection pattern selected by the selection means.
US09262692B2	Methods and systems for detection and identification of concealed materials Methods and systems for efficiently and accurately detecting and identifying concealed materials. The system includes an analysis subsystem configured to process a number of pixelated images, the number of pixelated images obtained by repeatedly illuminating regions with a electromagnetic radiation source from a number of electromagnetic radiation sources, each repetition performed with a different wavelength. The number of pixelated images, after processing, constitute a vector of processed data at each pixel from a number of pixels. At each pixel, the vector of processed data is compared to a predetermined vector corresponding to a predetermined material, presence of the predetermined material being determined by the comparison.
US09262690B2	Method and device for detecting glare pixels of image The present disclosure proposes a method and an electronic device for detecting glare pixels of an image including an object and an electronic device using the same. The method includes the following steps. First, the image is processed to remove overexposed pixels from the image to generate a first image. The first image is processed to remove non-object pixels from the first image to generate an object pixel image. The glare pixels are detected from the object pixel image according to a saturation distribution threshold and an intensity distribution threshold. The present disclosure is able to adjust the saturation distribution threshold and the intensity distribution threshold dynamically and adaptively to satisfy various kinds of objects and ambient lighting conditions so as to improve the probability of successful detection and reduce the probability of false alarms on the glare pixels.
US09262685B2	Method and apparatus for representing changes in shape and location of organ in respiration cycle Provided is a method of generating a model, the method including generating a first model representing a change in the location or the shape of the region of interest during the respiration cycle, using diagnostic images that are obtained at two points of time in the respiration cycle and that represent the region of interest; extracting shape information of one or more tissues included in the region of interest at a shape information extractor, using a 3D ultrasound image that is obtained at one point of time in the respiration cycle; determining a characteristic point of the 3D ultrasound image corresponding to a characteristic point of the first model by matching the first model with the extracted shape information; and generating a second model by updating the first model with the determined characteristic point.
US09262682B2	Extracting card data with card models Embodiments herein provide computer-implemented techniques for allowing a user computing device to extract financial card information using optical character recognition (“OCR”). Extracting financial card information may be improved by applying various classifiers and other transformations to the image data. For example, applying a linear classifier to the image to determine digit locations before applying the OCR algorithm allows the user computing device to use less processing capacity to extract accurate card data. The OCR application may train a classifier to use the wear patterns of a card to improve OCR algorithm performance. The OCR application may apply a linear classifier and then a nonlinear classifier to improve the performance and the accuracy of the OCR algorithm. The OCR application uses the known digit patterns used by typical credit and debit cards to improve the accuracy of the OCR algorithm.
US09262681B1	Probabilistic registration of interactions, actions or activities from multiple views Images of an environment that are captured from two or more imaging devices may be captured and evaluated in order to identify a state of the environment, or an interaction that placed the environment in the state. The content of the images may be analyzed in order to recognize observed information or data expressed therein. The information or data may be associated with a given state according to one or more observation functions, and the state may be used to identify an action according to one or more transition functions. The observation function uses conditional probabilities to transfer the probability of making an observation by one imaging device to the observation made by the other imaging device. The observation functions and the transition functions may be derived based on historical training data including clips that are labeled to identify states or interactions expressed therein.
US09262680B2	Point-of-gaze detection device, point-of-gaze detecting method, personal parameter calculating device, personal parameter calculating method, program, and computer-readable storage medium A point-of-gaze detection device according to the present invention detects a point-of-gaze of a subject toward a surrounding environment. The device includes: an eyeball image obtaining means configured to obtain an eyeball image of the subject; a reflection point estimating means configured to estimate a first reflection point, at which incoming light in an optical axis direction of an eyeball of the subject is reflected, from the eyeball image; a corrected reflection point calculating means configured to calculate a corrected reflection point as a corrected first reflection point by correcting the first reflection point on the basis of a personal parameter indicative of a difference between a gaze direction of the subject and the optical axis direction of the eyeball; and a point-of-gaze detecting means configured to detect the point-of-gaze on the basis of light at the corrected reflection point and light in the surrounding environment.
US09262674B2	Orientation state estimation device and orientation state estimation method Disclosed is an orientation state estimation device capable of estimating with high accuracy the orientation state of a jointed body. An orientation state estimation device (100) estimates the orientation state of a body on the basis of image data of the body having multiple parts connected by joints. The device is provided with: a likelihood map generation unit (150) which, from the image data, for at least two parts of the jointed body, generates a likelihood map showing the plausibility distribution of where each part is most plausibly positioned; and an orientation state estimation unit (160) which, when a learning likelihood map, which is associated in advance with an orientation state, and an estimated likelihood map, which is generated on the basis of the image data, coincide to a high degree, estimates that the orientation state associated with said learning likelihood map is the orientation state of the object.
US09262672B2	Pattern recognition apparatus and pattern recognition method that reduce effects on recognition accuracy, and storage medium A pattern recognition apparatus that is lightweight for mounting, and reduces the effects of registration conditions or check conditions on recognition accuracy. Similarity sets for respective local features are calculated from a local feature of input data and local features of a plurality of pieces of dictionary data corresponding to the local feature of the input data. Integrated similarities are calculated by integrating a plurality of similarity sets in the local features according to a registration condition or a check condition. Dictionary data corresponding to the input data is identified based on the calculated integrated similarities.
US09262666B2	Anti-shock relief print scanning One or more techniques, devices and/or systems are disclosed for mitigating a perceived electrical sensation for a relief print scanning device. A current determination component can be used to identify an electrical current configuration that provides a mitigated electrical sensation to the user, for use with an electroluminescent-based relief print scanning device. The electrical current configuration can be identified using one or more image characteristics of a relief print image, which is captured by the devices using the current configuration. A current adjusting component, can be operably coupled with the current determination component, and may be used to adjust the current configuration, where the adjustment can be based on current adjustment data that is provided by the current determination component, based on the image characteristics.
US09262665B2	Decoding method and decoding processing device In a decoding method, photoelectric conversion is performed on light reflected by a code image, a read signal indicating intensity of the reflected light is produced, and the produced read signal is differentiated to produce a derivative signal. The inflection points of intensity of the reflected light in the read signal are detected from the derivative signal and peak levels, each of which is an extreme value of the intensity of the reflected light, the peak level corresponding to a width between the detected inflection points, are detected. A difference between the detected peak levels is then obtained and threshold values for decoding the read signal are set from the obtained difference. This enables the read signal to be decoded even when the code image is spotted with a stain or its printing quality is inferior or even when the read signal is read in its defocus state.
US09262663B2	Image processing device, image processing method, and program There is provided an image processing device including an image composition unit that generates a composite image by compositing a plurality of color images having differing color components and acquired by image capture, and a code recognition unit that, from the composite image, recognizes an information code formed by a plurality of cells.
US09262660B2	Optical indicia reading terminal with color image sensor An optical indicia reading terminal can comprise a microprocessor, a memory, and an image sensor integrated circuit for decoding decodable indicia. The image sensor integrated circuit can be configured to output a plurality of digital signals, each digital signal being representative of light incident on at least one pixel of the two-dimensional image sensor. The optical indicia reading terminal can be configured to selectively acquire a plurality of luminance signals from the plurality of digital signals. Whether the output image data from the sensor is digitally stored as YUV data or YCBCR data, the terminal parses out the luminance signal, Y, in the data matrix to store a monochrome image for decoding. The optical indicia reading terminal can be configured to process the frame of image data for decoding decodable indicia.
US09262659B2	Tracking system for gamma radiation sterilized bags and disposable items A tracking system for items to be ionizing radiation sterilized is provided which utilizes an attached RF ID tag that is ionizing radiation proof or enclosed in an ionizing radiation proof holder. The RF ID tag is coded with a unique identification and certification data on the ionizing radiation sterilization. An RF ID tag reader is provided, which is usable by a user to obtain the identification and sterilization data from the RF ID tag on the item. The RF ID tag reader includes a user input for at least one trackable event and can write data based on the at least one trackable event back onto the RF ID tag. The RF ID tag reader is at least one of connectable to a PC or the internet, or is compatible for uploading the identification and any user input to an internet accessible device. A database is provided, having item related information. The database provides access to a user to obtain related information based on the identification from the RF ID tag and receives and stores data related to the at least one trackable event.
US09262654B2	Reading device for contactless communication with a transponder unit A reading device for contactless communication with a transponder unit includes a first antenna for generating a reading device field in the form of an alternating magnetic field. The reading device further contains one or more second antennas configured, and arranged in relation to the first antenna, such that during a contactless communication of the reading device with a transponder unit which generates communication signals by means of load modulation, a predetermined change of a detection signal is captured on the second antenna or antennas if the transponder unit is located in a predetermined zone around the reading device.
US09262652B2	Card reading device with a plurality of protecting mesh wires A card reading device with a plurality of protecting mesh wires includes a main board, an outer frame, a first mesh wire and a second mesh wire. The main board includes an electronic member region and a card inserting case. The outer frame is disposed on the main board and includes a first groove and a second groove. The first groove covers the electronic member region. The second groove covers the card inserting case. The first mesh wire is disposed in the first groove and includes a first wire end connected to the electronic member region. The second mesh wire is disposed in the second groove and includes a second wire and connected to the electronic member region. When the outer frame is damaged or destroyed, the first mesh wire or the second mesh wire is triggered to activate a circuit protecting procedure to shortcut or disconnect a signal circuit.
US09262651B2	Method for preventing unintended contactless interaction when performing contact interaction A system and method for enabling a dual interface smart card reader to be able to determine if data should be read from a smart card using wireless technology or touch technology, even when the data can be accessed through wireless technology.
US09262650B2	Communication control device, data security system, communication control method, and computer product A communication control device configured to access an information processing apparatus in which data is stored. The device and method acquires an operational condition of an information processing apparatus, and notifies the information processing apparatus of a security command for causing the information processing apparatus to execute a security process on the data in an event that an operational condition is activated and, in an event that the operational condition is a standby mode, a hibernate mode, or a shutdown mode, notifies the information processing apparatus of an activation command for activating the information processing apparatus, and notifies of a security command for causing the information processing apparatus to execute a security process on the data.
US09262649B2	Security between electronic components of a portable secured electronic unit A portable secured electronic unit includes at least two electronic components, one of which is embodied in the form of a primary electronic component and the second in the form of an interface electronic component, wherein the two electronic components are interconnected by communication elements and at least one electronic component includes security elements for securing the communication thereof the other electronic component.
US09262648B2	Display device with automatic viewing angle control A system of automatically changing a viewing angle of a display device based on a determination of content confidentiality includes a display device, an auditing application, and a privacy filter control. The auditing application is configured to analyze content to be displayed on the display device for confidentiality indicators. The privacy filter control is configured to automatically change a current viewing angle of the display device from a first viewing angle to a second viewing angle that is less than the first viewing angle when the content includes at least one confidentiality indicator and the current viewing angle of the display device is the first viewing angle.
US09262643B2	Encrypting files within a cloud computing environment A system, computer readable medium and a method for encrypting a file, the method may include retrieving the file from a storage service; segmenting the file into multiple file segments; calculating a file segment signature for each of the multiple file segments to provide multiple file segment signatures; encrypting each of the multiple file segments to provide multiple encrypted file segments by using encryption keys that are in response to the multiple file segment signatures; wherein the multiple encrypted file segments form an encrypted file; and sending the multiple encrypted file segments to the storage service.
US09262634B2	Memory content protection A method of protection of memory contents in a computer which includes the steps of loading a program into the computer and executing such program so that the memory contents of the computer are used to create and store on the same computer cryptographic hash tags uniquely identifying the contents for each of blocks of memory content of selected and consistent size and their location and applying this to all of the memory contents, analyzing the hash tags so as to identify those that have an identical memory content, recording such results of such analysis, then effecting a transfer to an independent memory a copy of the hash tags and the associated memory blocks as well as the other information regarding their location this being with the exception where the contents of a block are identical, and then transferring only one copy of such contents.
US09262632B2	Using power fingerprinting (PFP) to monitor the integrity and enhance security of computer based systems Procedures are described for enhancing target system execution integrity determined by power fingerprinting (PFP): by integrating PFP into the detection phase of comprehensive defense-in-depth security; by deploying a network of PFP enabled nodes executing untrusted devices with predefined inputs forcing a specific state sequence and specific software execution; by embedding module identification information into synchronization signaling; by combining signals from different board elements; by using malware signatures to enhance PFP performance; by automatic characterization and signature extraction; by providing secure signature updates; by protecting against side-channel attacks; performing real-time integrity assessment in embedded platform by monitoring their dynamic power consumption and comparing it against signatures from trusted code, including pre-characterizing power consumption of the platform by concentrating on trace sections carrying the most information about the internal execution status; by using PFP from sequence of bit transitions to detect deviations from authorized execution of software in a digital processor.
US09262631B2	Embedded device and control method thereof An embedded device including a random access memory (RAM) and a processor is provided. The processor includes a processor core and an authentication module. The RAM stores data-to-be-authenticated. The data includes a program code to be executed by the processor core. The authentication module periodically accesses and authenticates the data-to-be-authenticated in the RAM. When the authentication module deems that the program code in the RAM loses its integrity, the authentication module interrupts the processor from further executing the program code.
US09262629B2	Methods and systems for preventing malicious use of phishing simulation records Described herein are methods, network devices and machine-readable media for preventing the malicious use of phishing simulation records. Phishing simulation records often times can reveal which individuals are most susceptible to phishing attacks. In the event that an attacker gains access to these records, the attacker can exploit such information to send phishing attacks to those individuals who are the most susceptible. To address such vulnerabilities, a phishing simulation record of an individual is only associated with an e-mail alias of the individual. Further, such e-mail alias may be deactivated after phishing simulations have been completed. Therefore, even if an attacker were able to identify individuals most susceptible to phishing attacks, the attacker will be unable to send any phishing attacks to those individuals since their e-mail aliases will have been deactivated.
US09262628B2	Operating system sandbox An operating system sandbox may include an operating system isolation module configured to restrict an operating system from transmitting machine-readable data and/or machine-readable instructions to an application, based on at least one predefined rule corresponding to abnormal operating system behavior.
US09262627B2	Methods, devices, and systems for detecting return oriented programming exploits Methods, devices, and systems for detecting return-oriented programming (ROP) exploits are disclosed. A system includes a processor, a main memory, and a cache memory. A cache monitor develops an instruction loading profile by monitoring accesses to cached instructions found in the cache memory and misses to instructions not currently in the cache memory. A remedial action unit terminates execution of one or more of the valid code sequences if the instruction loading profile is indicative of execution of an ROP exploit involving one or more valid code sequences. The instruction loading profile may be a hit/miss ratio derived from monitoring cache hits relative to cache misses. The ROP exploits may include code snippets that each include an executable instruction and a return instruction from valid code sequences.
US09262625B2	Address translation/specification field for hardware accelerator Embodiments relate an address translation/specification (ATS) field. An aspect includes receiving a work queue entry from a work queue in a main memory by a hardware accelerator, the work queue entry corresponding to an operation of the hardware accelerator that is requested by user-space software, the work queue entry comprising a first ATS field that describes a structure of the work queue entry. Another aspect includes, based on determining that the first ATS field is consistent with the operation corresponding to the work queue entry and the structure of the work queue entry, executing the operation corresponding to the work queue entry by the hardware accelerator. Another aspect includes, based on determining that the first ATS field is not consistent with the operation corresponding to the work queue entry and the structure of the work queue entry, rejecting the work queue entry by the hardware accelerator.
US09262620B2	Secure communications kit and client device for securely communicating using the same A secure communication kit is disclosed. The secure communication kit may include a plurality of tangible security tokens; each security token storing one or more cryptographic keys and a group identifier. A first cryptographic key stored on each security token may correspond to one of the cryptographic key(s) stored on every of the other security tokens. The group identifier stored on each security token may correspond to each group identifier stored on every of the other security tokens. A client device for securely communicating using the secure communication kit is also disclosed.
US09262613B1	Anonymous biometric identification This disclosure describes methods for identifying an individual in an anonymous biometric authentication system, where an individual's biometric data is captured by a device, and the resulting probe is compared with the templates in a previously enrolled population. The system comprises a Biographic Identity Management System having a non-anonymous sector in communication with an anonymous sector through a network cloud. The anonymous sector or Anonymous Biometric Identity Management System contains an index of tokens associated, each associated uniquely with a biometric template, which may then be compared with a biometric probe to determine the identity of an individual.
US09262610B2	Imposter account detection and remediation in a social networking system When a request to connected a requesting user to a target user is received by the social networking system, information associated with the requesting user and with users connected to the target user is retrieved. A fraud probability score indicating a probability that the requesting user is impersonating a user connected to the target user is determined based on the information associated with the requesting user and with users connected to the target user. Based on the fraud probability score, a determination is made whether the requesting user is a suspected imposter and remedial action is taken if imposter is suspected.
US09262608B2	System for providing session-based network privacy, private, persistent storage, and discretionary access control for sharing private data The invention provides secure and private communication over a network, as well as persistent private storage and private access control to the stored information, which is accomplished by imposing mechanisms that separate a user's actions from their identity. The system provides (i) anonymous network browsing, in which event the anonymity system is unaware of both the user's identity and browsing activities, (ii) private network storage and retrieval of data such as passwords, profiles and files in a manner such that the data can be stored into the system and later retrieved without the system knowing the contents or owners of the data, and (iii) the ability of the user to control and manage access to the remotely stored data without the system knowing the contents, owners, or accessors of the data.
US09262606B2	Systems and methods for pairing identification data to a network-based service Disclosed are methods and systems of providing access, indexing, and/or connecting a user to a network-based service, associated with a particular entity, using an identifier that can be uniquely associated with the particular entity (e.g., with respect to a given scope of identification), can be proprietary to the entity, and/or issued by a third-party (i.e., a party not providing the method or system). A method can comprising receiving from a client computer system an entity identifier uniquely associated with a real world entity in a scope of identification, the entity identifier being issued by a third-party in association with the real world entity. The method can select a network-based service uniquely associated with the entity identifier, determine a public access parameter to the network-based service, and provide the client computer system with public access to the network-based service according to the public access parameter.
US09262604B2	Method and system for locking an electronic device A method and a system for locking an electronic device are provided. In one aspect, a method in an electronic device is provided comprising the steps of receiving, through a user input interface of the device when the device is in a locked state, a challenge response and a temporary automatic lock time indicator, and if the challenge response is accepted, unlocking the device, setting an automatic lock timer of the device to a temporary lock time value, and starting the automatic lock timer. In another aspect, an electronic device is provided for implementing the above method. According to another aspect, a locking mechanism is provided that utilizes information on an environment of the electronic device. According to another aspect, a stimulus based locking mechanism is provided that employs a different lock time after the device has issued a stimulus in response to an event on the device.
US09262602B2	Extensible bios interface to a preboot authentication module A computer-readable storage medium containing software that, when executed by a processor, causes the processor to implement a basic input/output system (BIOS). The BIOS comprises instructions that implement a BIOS core, instructions that implement a user authentication and enforcement engine (AEE), and instructions that implement an extensible interface to a preboot authentication module.
US09262600B2	Tamper proof mutating software System and method is disclosed for protecting client software running on a client computer from tampering using a secure server. Prior to or independent of executing the client software, the system integrates self-protection into the client software; removes functions from the client software for execution on the server; develops client software self-protection updates; and periodically distributes the updates. During execution of the client software, the system receives an initial request from the client computer for execution of the removed function; verifies the initial request; and cooperates with the client computer in execution of the client software if verification is successful. If verification is unsuccessful, the system can attempt to update the client software on the client computer; and require a new initial request. Client software can be updated on occurrence of a triggering event. Communications can be encrypted, and the encryption updated. Authenticating checksums can be used for verification.
US09262599B2	Method and system for distributing media content Aspects of the subject disclosure may include, for example, receiving from a communication system media content with metadata, recording the media content, detecting in the metadata a description of the media content correlating with a preference profile, presenting a first prompt requesting an acceptance or rejection of the media content, presenting a second prompt requesting a selection from a plurality of communication devices to direct in whole or in part the media content thereto, detecting the selection from the plurality of communication devices, and transmitting in whole or in part the media content to the selected communication device. Other embodiments are disclosed.
US09262596B1	Controlling access to captured media content Systems and methods for controlling access to captured media content may involve basing a user identifier's permissions on location and/or time data associated with the user identifier. The location data may be indicative of one or more geographical locations at which a user device associated with the user identifier was, or is, located. In some cases, the permissions of the user identifier may be based in part on a comparison between the location data associated with the user identifier and data indicative of where and/or when the media content was captured.
US09262594B2	Tamper evidence per device protected identity Various techniques are described to protect secrets held by closed computing devices. In an ecosystem where devices operate and are offered a wide range of services from a service provider, the service provider may want to prevent users from sharing services between devices. In order to guarantee that services are not shared between devices, each device can be manufactured with a different set of secrets such as per device identifiers. Unscrupulous individuals may try to gain access to the secrets and transfer secrets from one device to another. In order to prevent this type of attack, each closed computing system can be manufactured to include a protected memory location that is tied to the device.
US09262590B2	Prospective adaptive radiation therapy planning A therapy planner is configured to construct a therapy plan based on a planning image segmented into segments delineating features of a subject. A predictive plan adaptation module is configured to adjust the segments to represent a foreseeable change in the subject and to invoke the therapy planner to construct a therapy plan corresponding to the foreseeable change. A data storage stores a plurality of therapy plans generated for a subject by the therapy planner and the predictive plan adaptation module based on at least one planning image of the subject. A therapy plan selector is configured to select one of the plurality of therapy plans for use in a therapy session based on a preparatory image acquired preparatory to the therapy session.
US09262589B2	Semantic medical devices A semantic medical technology is disclosed. In various embodiments, the technology organizes an initial data collection to collect data from the one or more sensors; processes the data to obtain an initial diagnosis wherein the initial diagnosis can be a syntax diagnosis or a semantic diagnosis; identifies an organization for an additional data collection to collect additional data; analyzes the additional data to obtain a refined diagnosis; and repeats the identifying and analyzing until a stopping criterion is satisfied.
US09262588B2	Display of respiratory data graphs on a ventilator graphical user interface The disclosure describes improved systems and methods for configuring the layout of a graphical display in a ventilatory system. Specifically, the present methods provide a user interface for configuring one or more layout categories associated with data on the graphical display. Upon selection of a layout category, a clinician is provided with a preview of the layout of the layout category. The preview consists of one or more parameter positions. Each parameter position is associated with a parameter. The clinician is also provided with a listing of possible parameters. The parameter positions in the preview and the possible parameters in the listing are selectable elements. Once a parameter position is selected, a possible parameter can be chosen to replace the parameter associated with the selected parameter position. If this replacement is acceptable to the clinician, the clinician can access an accept button to implement the replacement in the graphical display.
US09262582B2	Detection of risk of pre-eclampsia A method for the early prediction of risk of hypertensive disorders in pregnant women, including for example eclampsia, mild pre-eclampsia, chronic hypertension, EPH gestosis, gestational hypertension, superimposed pre-eclampsia, HELLP syndrome, or nephropathy.
US09262581B2	Method and system for facilitating physiological computations A system for noninvasively determining at least one physiological characteristic of a patient may include at least one computer system configured to, using a three-dimensional surface mesh model created using patient-specific imaging data, create a three-dimensional combined surface and volume mesh model, including at least a first model portion that has a different spatial resolution than at least a second model portion. The computer system may be further configured to input the three-dimensional surface and volume mesh model into a fluid simulation system and determine a measurement of the physiological characteristic, using the fluid simulation system.
US09262578B2	Method for integrated circuit manufacturing Provided is an integrated circuit (IC) manufacturing method. The method includes receiving a design layout of an IC, wherein the design layout includes a plurality of non-overlapping IC regions and each of the IC regions includes a same initial IC pattern. The method further includes dividing the IC regions into a plurality of groups based on a location effect analysis such that all IC regions in a respective one of the groups are to have substantially same location effect. The method further includes performing a correction to one IC region in each of the groups using a correction model that includes location effect; and copying the corrected IC region to other IC regions in the respective group. The method further includes storing the corrected IC design layout in a tangible computer-readable medium for use by a further IC process stage.
US09262576B2	Method and apparatus for providing a layout defining a structure to be patterned onto a substrate A method provides a layout defining a structure to be patterned onto a substrate. The structure is registered with a predefined grid of the layout. The method includes locally stretching the grid in a first portion of a layout causing a problematic spot on the substrate.
US09262575B2	Circuit-level abstraction of multigate devices using two-dimensional technology computer aided design A method for predicting a condition in a circuit under design includes obtaining a set comprising first static noise margin curve for the circuit and a second static noise margin curve for the circuit, wherein the second static noise margin curve is complementary to the first static noise margin curve, matching the set to a two-dimensional model of a cell, and predicting the condition in accordance with hardware characterization data corresponding to the cell.
US09262571B2	Layout migration with hierarchical scale and bias method A method for migrating a hierarchical layout between manufacturing processes is accomplished without specification of a technology file and design rules. Different scaling factors and bias values in the X and Y directions may be applied to each layer in the source hierarchical layout during the migration. In addition, the target hierarchical layout maintains connectivity, and is free of notches, jogs and small edges. A cell hierarchy tree is created, which guides expansion of the target hierarchical database to resolve issues related to rounding of floating point numbers to integers. Boolean operations are performed to determine the differences between target flat database and the target hierarchical database. The differences are eliminated by modifying the target hierarchical database to match the layout in the flat database.
US09262568B2	Dummy pattern performance aware analysis and implementation Embodiments of the present invention are a system, a computer program product, and a method for implementing an integrated circuit design. The method for implementing an integrated circuit design includes accessing an original electronic representation of an integrated circuit layout from a first user file, and accessing a defined sensitivity index that characterizes an impact of the dummy pattern on the functional component. The impact of the dummy pattern on the functional component is analyzed and it is determined whether the impact is within a limit of the sensitivity index. One of a plurality of features of the dummy pattern is adjusted if the impact is not within the limit to form a generated electronic representation of a modified integrated circuit layout, and the generated electronic representation is output to a second user file. The integrated circuit layout includes a dummy pattern and a functional component.
US09262565B2	Computer-readable medium storing code A computer-readable medium storing code is disclosed. When executed by one or more processors of a computer system, the computer-readable medium storing code causes the system to implement the method of: Preparing for display a graphical user interface; Receiving a plurality of parameters into the plurality of input fields; Emulating a mechanical operation of the machine using the plurality of parameters inputted into the plurality of input fields by simulating the programmable logic control code; Generating the output response data based on the emulation of the mechanical operation of the machine; Calculating one or more predicted product values based at least in part on the output response data provided to the a product model; and, Preparing for display the one or more predicted product values.
US09262561B2	Modeling of non-newtonian fluids in subterranean reservoirs A computer-implemented reservoir prediction system, method, and software are provided for modeling the behavior of non-Newtonian fluids in subterranean reservoirs while accounting for shear-rate dependent viscosity and permeability reduction with a skin zone characterized by a traditional skin factor and an apparent skin factor. A non-Newtonian fluid injection pressure or a non-Newtonian fluid injection rate is computed at steady-state responsive to reservoir data associated with a subterranean reservoir, injection data for a non-Newtonian fluid, and fluid data for the non-Newtonian fluid. The shear-rate dependent viscosity can further be applied to a well model in numerical reservoir simulation to improve the well model.
US09262555B2	Machine for recognizing or generating Jabba-type sequences Example methods, apparatuses, or articles of manufacture are disclosed that may be implemented, in whole or in part, using one or more computing devices to facilitate or otherwise support one or more processes or operations for a machine for recognizing or generating one or more Jabba-type sequences.
US09262553B2	User-powered recommendation system Recommendation systems are widely used in Internet applications. In current recommendation systems, users only play a passive role and have limited control over the recommendation generation process. As a result, there is often considerable mismatch between the recommendations made by these systems and the actual user interests, which are fine-grained and constantly evolving. With a user-powered distributed recommendation architecture, individual users can flexibly define fine-grained communities of interest in a declarative fashion and obtain recommendations accurately tailored to their interests by aggregating opinions of users in such communities. By combining a progressive sampling technique with data perturbation methods, the recommendation system is both scalable and privacy-preserving.
US09262549B2	Modeled associations for business object data structures A service request to execute an operation on a business object is received. Thereafter, a metadata repository is polled to obtain a modeled association corresponding to the service request. The modeled association involves at least one node of the business object. The at least one node of the business object is then called using the modeled association to respond to the service request. Related apparatus, systems, techniques and articles are also described.
US09262546B2	Web browser adapted to render a web page based on an identity and a type of program within which a hyperlink was selected Exemplary embodiments of the present invention disclose a method and system for configuring a web browser executing in a computer to render a web page for display at the computer. A first hyperlink request is received from a first program executing in the computer to obtain and render a first web page corresponding to the first hyperlink. In response, the web browser obtains the first web page, and renders the first web page according to a first set of web page configuration parameters. A second hyperlink request is received from a second program executing in the computer to obtain and render a second web page corresponding to the second hyperlink. In response, the web browser obtains the second web page, and renders the second web page according to a second set of web page configuration parameters that differs in part from the first set of web page configuration parameters.
US09262539B2	Mobile device and system for recording, reviewing, and analyzing human relationship Two parties have three distinct viewpoints of their relationship, from which assumptions emerge and working hypotheses about how to manage their relationship. The system, device, and method described herein include using a computer system for understanding face-to-face human interactions. The process includes using a mobile device connected to a server in a network for reviewing an audio-video recording of an interaction with one or more other persons, whereby one or more of the participants use the mobile device to describe their viewpoints of the interaction. The participants use the mobile device to receive immediate feedback for analysis, to compare viewpoints, to examine how the viewpoints are arrived, and to explore the viewpoints' consequences for the participants' relationship.
US09262538B2	Apparatus and method for search and retrieval of documents A system for the support and management of search for documents is presents. The system includes knowledge-database, query interface and communication to a database of documents to be searched. Information generated during a search session is collected by the system and is added to the knowledge-database. The information is ranked automatically according to the usage of that information by the user. During successive search session, or during search made by other users, the system uses the knowledge-database to support the users with keywords, queries and reference to documents.
US09262536B2	Direct page view measurement tag placement verification Disclosed herein are strategies for verifying placement of a direct measurement tag useful for measuring Internet traffic of a plurality of users at a website. For example, a method may include receiving web page identification data that is derived from user clickstream data, determining a URL associated with a domain based on the webpage identification information, and providing a measurement code verification web crawler with the URL and the depth to which to explore the domain for verifying measurement code placement with the web crawler.
US09262535B2	Systems and methods for semantic overlay for a searchable space The embodiments of the present invention provide a novel way of searching and interacting with content available via a network, such as the Internet, and the World Wide Web. In some embodiments, systems and methods provide a semantically-oriented structure for organizing and accessing content items. The semantic organization can be derived by leveraging user interactions with the content items. The systems and methods leverage the semantics of the content items and to help the user find content items that are consistent with the purpose of the user's search. In addition, the embodiments provide a novel navigation paradigm of search results and content items so that the user can more intuitively and more efficiently get information form an information space.
US09262533B2	Context based data searching Data searching over a network is facilitated. A search request is received from a user device via the network. The search request includes information related to the user device. The search request is processed by identifying a context chain related to the user device based on information passed with the search request. The context chain is an array of contexts. Contexts are added to and subtracted from the context chain dependent upon communications received from the user device. The search request is responded to by providing at least one search result to the user device. The search result is obtained from at least one context in the plurality of contexts.
US09262531B2	System and method for chat message prioritization and highlighting A system and method is provided for chat message prioritization that uses a combination of machine-derived and user-supplied relevancy criteria to present a filtered, annotated, and/or highlighted chat stream.
US09262530B2	Search system using search subdomain and hints to subdomains in search query statements and sponsored results on a subdomain-by-subdomain basis A method and apparatus for generating search results including searching by subdomain and providing sponsored results by subdomain is provided. A search system according to embodiments of the present invention analyzes search queries to determine if they are to be routed to subdomains and presents results include sponsored hits sponsored on a subdomain by subdomain basis.
US09262518B2	Dynamically determining the relatedness of web objects A first cluster of web objects is identified from a click-through data structure. The click-through data structure can organize web objects into clusters based on query results of web objects selected by a user. Also, a second cluster of web objects can be identified from a metadata data structure. The metadata data structure can organize web objects into clusters based on metadata associated with the web objects. An output set of web objects is selected, in real time, from the identifier clusters.
US09262516B2	Automatic categorization of email in a mail system A sender-driven framework for enhancing the categorization of emails, wherein the sender is able to create or define rules that refine or augment those at the receiver's end. Particularly, the sender is enabled, in accordance with at least one embodiment of the present invention, to add information relating to the context of an email, which can help streamline categorization at the receiver's end.
US09262508B2	Industry vertical RFID database models An RFID event tracking and management system provides a standardized approach that can be utilized by various industry verticals. A series of industry-specific data models can be built upon a common data model using an object-oriented database and relational mapping tool. Using the industry-specific data models, an object-oriented database is generated that can be used by all vertical applications that sit on top of the database. The data models can be defined using a data model service, such that query and capture interfaces can interact with the respective data model. Such an approach allows the data models to be dynamic, which is desirable as a single static data model is not appropriate for all industries.
US09262504B2	Methods, systems, and products for maintaining data consistency in a stream warehouse Methods, systems, and products characterize consistency of data in a stream warehouse. A warehouse table is derived from a continuously received a stream of data. The warehouse table is stored in memory as a plurality of temporal partitions, with each temporal partition storing data within a contiguous range of time. A level of consistency is assigned to each temporal partition in the warehouse table.
US09262500B2	Memory system including key-value store According to one embodiment, a memory system including a key-value store containing key-value data as a pair of a key and a value corresponding to the key, includes a first memory, a control circuit and a second memory. The first memory is configured to contain a data area for storing data, and a table area containing the key-value data. The control circuit is configured to perform write and read to the first memory by addressing, and execute a request based on the key-value store. The second memory is configured to store the key-value data in accordance with an instruction from the control circuit. The control circuit performs a set operation by using the key-value data stored in the first memory, and the key-value data stored in the second memory.
US09262498B2	Generating optimized host placement of data payload in cloud-based storage network Embodiments relate to systems and methods for generating optimized host placement of data payload in a cloud-based storage network. In aspects, a user can maintain a user premise network including servers, clients, local area networks, data stores, and/or other network assets. An administrator or other user of the premise network may wish to extract data from the premise network and transfer that data payload to a set of host storage clouds to leverage cost, redundancy, consolidation, or other cloud advantages. The placement tool can evaluate potential target cloud-based data stores based on various or multiple parameters for the hosting features offered by different cloud providers. The tool can generate a determination of the target host or hosts which can provide the best-matched or optimized data hosting facilities or services for the user's data payload in the cloud. The selected target(s) can be based on cost, capacity, security, compatibility, or other parameters or specifications, which can be user-specified or user-weighted.
US09262497B2	Method and apparatus to manage files for a portable device A method and apparatus to manage files of a portable device such as an mp3 player, a mobile phone, or a game console, the method comprising copying files to be played from a source server and storing the files in a file system on a folder-by-folder basis; determining the presence of files which have been changed in the portable device by checking the file system when the files are completely copied; and creating a playlist of the files, folder-by-folder, according to file path information of the file system when there are the changed files.
US09262496B2	Unified access to personal data A method and system for providing unified access to data for multiple computing devices includes a system that associates multiple computing devices with a user of an information management system, assigns information management policies to data from the multiple computing devices within the information management system, and collects multiple data objects from the multiple computers. The system may generate a preview version of each collected data object, and provide at least one preview version of a collected data object to a computing device associated with the user. The system may also generate indexing information for each collected data object and distribute the indexing information with the preview version of the data object.
US09262495B2	Dimensional reduction mechanisms for representing massive communication network graphs for structural queries Mechanisms are provided for transforming an original graph data set into a representative form having a smaller number of dimensions that the original graph data set. The mechanisms generate a graph transformation basis structure based on an input graph data structure. The mechanisms further transform an original graph data set based on an intersection of the graph transformation basis structure and the input graph data structure to thereby generate a transformed graph data set data structure. The transformed graph data set data structure has a reduced dimensionality from that of the input graph data structure but represents characteristics of the original graph data set. Moreover, the mechanisms perform an application specific operation on the transformed graph data set data structure to generate an output of a closest similarity record in the transformed graph data set to a target component.
US09262494B2	Importing data into dynamic distributed databases The present invention extends to methods, systems, and computer program products for importing data into dynamic distributed databases. Embodiments of the invention include an import service that facilitates data imports without any distribution logic on a tenant. A tenant (caller) provides data in essentially any order. The import service understands the distribution of data across multiple databases and determines for any given piece of import data what database the import data is to be inserted into. Accordingly, the tenant (caller) is relieved from having to know how the data is distributed across a set (of potentially hundreds or thousands) of databases. The import service can group sets of data destined for a given database together and can use batch operations to increase efficiency.
US09262493B1	Data analytics lifecycle processes A data analytic plan is defined for analyzing a given data set associated with a given data problem. A test data set and a training data set are obtained from the given data set associated with the given data problem. At least one model is executed to confirm an adequacy of the at least one model for the data analytic plan by fitting the at least one model on the training data set and evaluating the at least one model fitted on the training data set against the test data set. The defining, obtaining and executing steps are performed on one or more processing elements associated with a computing system and automate at least part of a data analytics lifecycle.
US09262486B2	Fuzzy full text search A method and system for fuzzy full text search is disclosed. The system includes an inverted index where tokens are organized in a Next Valid Character (NVC) tree. Each path through the tree defines a token. The document lists for the tokens are stored at leaf nodes. When performing a fuzzy full text search, the system uses an edit distance greater than zero. After receiving search tokens, the system traverses the NVC tree to generate document error lists. The system then compares the error lists to identify relevant document identifiers and provides a result set.
US09262485B2	Identifying a sketching matrix used by a linear sketch Embodiments relate to identifying a sketching matrix used by a linear sketch. Aspects include receiving an initial output of the linear sketch, generating a query vector and inputting the query vector into the linear sketch. Aspects further include receiving an revised output of the linear sketch based on inputting the query vector and iteratively repeating the steps of generating the query vector, inputting the query vector into the linear sketch, and receiving an revised output of the linear sketch based on inputting the query vector until the sketching matrix used by the linear sketch can be identified.
US09262480B2	Ensuring small cell privacy at a database level A request is received for a set of entries that make up a small cell in a database, wherein the small cell is initially described at a fine granular level of detail by a set of descriptors. In response to the total number of entries in the small cell being below a predetermined limit, the set of descriptors are modified to reduce the fine granular level of detail to a coarse granular level of detail in order to protect the privacy of individuals described by the set of entries.
US09262472B2	Concatenation for relations Methods for generating a query input string include sorting a first input relation and a second input relation in order from the first relation to the second relation. The second input relation is concatenated to the first input relation, and the concatenated input relations are stored in a single string.
US09262469B1	Intelligent data integration system Data objects stored in a data store include data attribute(s) and associated value(s) for the attributes. Data analysis tools (DATs) stored in a data store are associated with reference data attribute(s). The data objects are identified by one or more DATs based on each reference data attribute(s) of a corresponding DAT matching one of the data attribute(s) of the corresponding data object(s) and independent of the value for the data attribute(s). The DATs generate an additional data object as a function of the identified data object, and the additional data object is stored in the data store.
US09262466B2	Data processor and a data processing method A data processor and a data processing method are provided. The data processor is arranged between a client and a database system to determine in advance whether a user instruction sent from the client updates data of the database system. When the data processor determines that the user instruction does not update data of the database system, the data processor sends the predefined data to the client and restrains the user instruction to the database system. Accordingly, the data processor can assist the database system to process the user instruction, so as to reduce in advance the enormous volume of data processing that the database system is requested upon.
US09262464B2	Cleaner with browser monitoring A cleaning application that can monitor one or more browser applications that are executed on a computer, and that can, for at least one browser application, clean at least one of one or more files or a registry associated with the at least one browser application is provided. The cleaning application can include a cleaning module. The cleaning module can monitor one or more browser applications that are executed on a computer. The cleaning module can further detect a closing of at least one browser application. The cleaning module can further perform a pre-defined action in response to the closing of the at least one browser application. The pre-defined action can include cleaning at least one of one or more files or a registry associated with the at least one browser application.
US09262462B2	Aggregation framework system architecture and method Database systems and methods that implement a data aggregation framework are provided. The framework can be configured to optimize aggregate operations over non-relational distributed databases, including, for example, data access, data retrieval, data writes, indexing, etc. Various embodiments are configured to aggregate multiple operations and/or commands, where the results (e.g., database documents and computations) captured from the distributed database are transformed as they pass through an aggregation operation. The aggregation operation can be defined as a pipeline which enables the results from a first operation to be redirected into the input of a subsequent operation, which output can be redirected into further subsequent operations. Computations may also be executed at each stage of the pipeline, where each result at each stage can be evaluated by the computation to return a result. Execution of the pipeline can be optimized based on data dependencies and re-ordering of the pipeline operations.
US09262461B2	Aggregating keys of dependent objects for a given primary object Keys are obtained and aggregated by storing a primary object as an entry in a parent keys storage and a child keys storage, the entry identified as unvisited in each. An object evaluation process is then performed until all unique entries in the parent keys storage and all unique entries in the child keys storage have been visited and by committing the keys of at least one related object as an entry to the hierarchical database. The object evaluation process visits each unvisited object in the parent keys storage and child keys storage by selecting, for the unvisited object, objects in the parent direction that have not already been visited and objects in the child direction that have not already been visited and by inserting the keys of the selected related objects as entries in the parent keys storage or child keys storage.
US09262458B2	Method and system for dynamically partitioning very large database indices on write-once tables Methods and systems for partitioning and dynamically merging a database index are described. A database index includes a single first-level index partition stored in a data cache. As the first-level index partition in the data cache reaches a predetermined size, it is copied to secondary storage and a new index partition is generated in the data cache. When the number of index partitions in secondary storage reaches some predetermined number, the index partitions are merged to create a single index partition of a higher level in a hierarchy of index partitions having an exponentially increasing size with each increase in level within the hierarchy.
US09262448B2	Data backup across physical and virtualized storage volumes Machines, systems and methods for backing up data, the method comprising retrieving identifying information about target data storage volumes from which target data is to be backed up; communicating the identifying information to a proxy application installed on a backup computing system utilized to backup the target data stored on the target data storage volumes, wherein the proxy application uses the identifying information to place the target data storage volumes in a first state in which write operations may not be performed to the target data storage volumes, wherein the proxy application causes snapshots to be taken of the target data storage volumes of a first type and a second type, in response to determining that the target data storage volumes are placed in the first state.
US09262447B2	Generating RDF expression technical field A set of ID for data of an existing tool is created as a parameter. A bulk access template that acquires a plurality of data is prepared. Access is provided to an existing tool path through the bulk access template. The bulk access template is prepared for each type of data that is acquired. The template is instantiated based on the URI that is requested. Entries that correspond to the operating table are filled in by executing the bulk access template that was created. When an RDF expression is requested for the URI of the template that is the same as one previously accessed, the entries would already be in the operating table, so that the RDF expression can be generated without accessing the existing tool.
US09262444B2	Systems and methods for applying series level operations and comparing images using a thumbnail navigator An example image layout and display navigator system includes a navigator that includes a miniature layout representation corresponding to the layout of images on the display. The navigator is to appear on the display based on user action with respect to displayed content and to allow a user to select an image series via the miniature layout and to select one or more series level operations for application to the image series via the miniature layout. The navigator is to apply a selected series level operation to the image series via the miniature layout based on user input. An action in one of the navigator and the display is to translate into a corresponding action on the other of the navigator and the display. The content display manager is to update the content displayed to reflect the selected series level operation applied to the image series.
US09262439B2	System for determining local intent in a search query A system and method determine local intent. Local intent may reflect whether a search query should receive results and advertisements that are geographically specific. The local intent may be determined using probabilistic models that analyze historical searches to determine which search terms tend to have local intent.
US09262438B2	Geotagging unstructured text Mechanisms are described to extract location information from unstructured text, comprising: building a language model from geo-tagged text; building a classifier for differentiating referred and physical location; given unstructured text, identifying referred location using the language model (that is, the location to which the unstructured text refers); given the unstructured text, identifying if referred location is also the physical location using the classifier; and predicting (that is, performing calculation(s) and/or estimation(s) of degree of confidence) of referred and physical location.
US09262435B2	Location-based data synchronization management In general, a data synchronization management system is disclosed in which files (and/or other data) are synchronized among two or more client computing devices in connection with a backup of those files. Synchronization polices specify files to be synchronized based on selected criteria including file data, metadata, and location information. In general, files are initially copied from a primary client computing device to secondary storage. Thereafter, files to be synchronized are identified from the secondary storage, and copied to other client computing devices. Additionally, synchronized files may be viewed and accessed through a cloud and/or remote file access interface.
US09262434B1	Preferential selection of candidates for delta compression A computer-implemented method and system for improving efficiency in a delta compression process in a data storage system selects a data chunk to delta compress and generates a sketch for the selected data chunk. The method and system search for a set of candidate data chunks with a matching sketch and rank the set of candidate data chunks by degree of sketch matching. The set of candidate data chunks are tie-braked using location status data for each candidate and the selected data chunk is delta compressed with a selected candidate data chunk. The delta compressed selected data chunk is then stored in a data storage system.
US09262431B2	Efficient data deduplication in a data storage network Machines, systems and methods of uploading data files, the method comprising a first client machine dividing a first file into N data chunks to be uploaded to a server, wherein the N data chunks are of size kX, where k is an integer and X is size of a minimal size data chunk, wherein X is known by the server and by at least a second client machine used for uploading a second file to the server in data chunks of size k′X; and uploading the first file to the server, wherein a first unique signature is calculated for the first file based on applying a signature function to a collection of signatures calculated for the minimal size data chunks of size X that make up the data chunks of size kX in the first file, wherein the uploading of the first file is accomplished by uploading the data chunks of size kX to the server in any order.
US09262430B2	Deduplication in a storage system A IO handler receives a write command including write data that is associated with a LBA. The IO handler reserves a deduplication ID according to the LBA with which the write data is associated, within the scope of each LBA, each deduplication ID is unique. The IO handler computes a hash value for the write data. In case a deduplication database does not include an entry which is associated with the hash value, the IO handler: provides a reference key which is a combination of the LBA and the deduplication ID; adds to the deduplication database an entry which is uniquely associated with the hash value and references the reference key; and adds to a virtual address database an entry, including: the reference key; a reference indicator indicating if there is an entry that is associated with the present entry; and a pointer to where the write data is stored.
US09262428B2	Preserving redundancy in data deduplication systems by designation of virtual address Various embodiments for preserving data redundancy of identical data in a data deduplication system in a computing environment are provided. A selected range of virtual addresses of a virtual storage device in the computing environment is designated as not subject to a deduplication operation. Other system and computer program product embodiments are disclosed and provide related advantages.
US09262427B2	Systems and methods for transformation of logical data objects for storage Systems and methods for transforming a logical data object for storage in a storage device operable with at least one storage protocol, creating, reading, writing, optimization and restoring thereof. Transforming the logical data object comprises creating in the storage device a transformed logical data object comprising one or more allocated storage sections with a predefined size; transforming one or more sequentially obtained chunks of obtained data corresponding to the transforming logical data object; and sequentially storing the processed data chunks into said storage sections in accordance with a receive order of said chunks, wherein said storage sections serve as atomic elements of transformation/de-transformation operations during input/output transactions on the logical data object. The processing may comprise two or more data transformation techniques coordinated in time, concurrently executing autonomous sets of instructions, and provided in a manner preserving the sequence of processing and storing the processed data chunks.
US09262426B2	File storage apparatus It is an objective of the present invention to provide a solution to automatically remove the redundancy among the user's files, and to efficiently use the memory area of the server without placing an unreasonable cost on a service provider and on a user. In order to attain the above objective, a file storage apparatus, which replaces a bit sequence, which matches a bit sequence correlated with a code and managed, with said code, thereby performing compression and storage of a file correlated with the user identification information and inputted, comprising a distribution unit for management cost, which performs distribution of management cost with respect to each user identification information, is provided. Here, the management cost for code and/or bit sequence corresponds to cost necessary for storage or maintenance of the code and/or bit sequence. Examples of the cost include cost for size of required storage area, and cost for required operation of CPU.
US09262423B2	Large scale file storage in cloud computing Storing and retrieving files based on hashes for the files. One method for storing files includes: identifying a file; identifying a hash calculated based on the file; renaming the file based on the hash based on the file; and storing the file in a particular location based on the hash calculated based on the file. Another method for retrieving files includes: identifying a hash for a given file; using the hash, traversing a hierarchical file structure to find a location where the given file should be stored; determining that the file is at the location; and as a result, retrieving the file.
US09262422B1	System and method of verifying a payment cardholder's identity using an interactive payment card The present invention relates generally to a system and method of interactive verification of a payment card user's identity. Specifically, by using an electronic payment card with a coded frame displayed thereon that includes one or more hot corners with one or more hyperlinks or icons embedded within the coded frame, activated for display when image capturing means scans the coded frame. Upon activation, a hyperlink or icon may be engaged for controlling interactive multimedia content pursuant to a control command associated with the one icon or hyperlink. The multimedia content may include authenticating information, e.g. security questions, a photograph and the like. Because the interactive multimedia content is not visible prior to the coded frame being scanned and the icons or hyperlinks in any one hot corner being engaged for retrieving the multimedia content, the payment card has varied layers of securitization of the information stored thereon.
US09262419B2	Syntax-aware manipulation of media files in a container format A container format processing tool performs syntax-aware manipulation of hierarchically organized syntax elements defined according to a container format in a media file. For example, a container format verifier checks conformance of a media file to a container format, which can help ensure interoperability between diverse sources of media content and playback equipment. Conformance verification can include verification of individual syntax elements, cross-verification, verification that any mandatory syntax elements are present and/or verification of synchronization. Or, a container format “fuzzer” simulates corruption of a media file, which can help test the resilience of playback equipment to errors in the media files. The container format fuzzer can simulate random bit flipping errors, an audio recording failure or incorrect termination of recording. Or, a container format editor can otherwise edit the media file in the container format.
US09262417B2	Document management server and document management method A document management server according to the present invention acquires entity data of a plurality of content documents specified to be downloaded by the client, and stores the acquired entity data of each of the plurality of content documents in a different folder generated in an archive file when there are content documents having a same name among the specified plurality of content documents. Further, the document management server generates an information file in which path information in the document management server and path information in the archive file with respect to each of the plurality of content documents specified to be downloaded are described in association with the corresponding content document, and stores the generated information file in the archive file. Further, the document management server transmits the archive file storing the entity data of each of the plurality of content documents and the information file to the client.
US09262416B2	Purity analysis using white list/black list analysis Memoizable functions may be identified by analyzing a function's side effects. The side effects may be evaluated using a white list, black list, or other definition. The side effects may also be classified into conditions which may or may not permit memoization. Side effects that may have de minimus or trivial effects may be ignored in some cases where the accuracy of a function may not be significantly affected when the function may be memoized.
US09262400B2	Non-transitory computer readable medium and information processing apparatus and method for classifying multilingual documents A non-transitory computer readable medium storing a program is provided. A process of the program includes: extracting, concerning first document information including texts, a word sense associated with a word in each text; setting a word sense to be a teacher signal; creating a first topic model by using the teacher signal; estimating a topic of each text by using the first topic model; generating a learning model by using the topic as a feature and the teacher signal as a category; extracting, concerning second document information including texts, a word sense associated with a word in each text; setting a word sense to be a teacher signal; creating a second topic model by using the teacher signal; estimating a topic of each text by using the second topic model; and estimating a category of each text by using the topic as a feature and the learning model.
US09262399B2	Electronic device, character conversion method, and storage medium An electronic device includes a processor configured to execute: accepting a character input; causing a display module to display a character or a character string, which has been input by the character input; causing the display module to display a plurality of words which are conversion candidates corresponding to the input character or character string; causing the display module to display, responding to designation by a user of a word of the plurality of words which are conversion candidates, at least one synonym corresponding to the designated word; and causing the display module to display, responding to selection by the user of a synonym of the displayed at least one synonym, the selected synonym in place of the input character or character string.
US09262398B2	Language set disambiguator A set of language tags in a backend application can be passed to a frontend application in the form of a language selection tool. The disclosure creates a mapping between the frontend and backend application of at least one non-default language descriptor string onto a language tag of the backend application. The frontend language selection tool then displays to the user the non-default language descriptor string. The use of non-default language descriptor strings clarifies to the user otherwise ambiguous language identifiers.
US09262396B1	Browser compatibility checker tool Browser compatibility checking of a web page source document is implemented on one or more servers. The browser compatibility checking of the web page source document involves receiving a request to render a web page source document for compatibility testing with different web browsers. The web page source document is then distributed to multiple rendering applications on a rendering server, in which each of the rendering application is to render the web page source document for one of the web browsers. The web page source document is then rendered at each of the rendering applications to generate rendered web page images.
US09262394B2	Document content analysis and abridging apparatus A requirement acquisition system for grasping requirements from related documents such as documents the client holds, investigation results of an interview or questionnaire, meeting minutes, specification and the like, in system or software development, by reduced efforts and hours is provided. In particular, from a document being a group of character strings, one or more partial string which is a common part of the plurality of character strings is extracted as an important phrase. When the important phrase does not exist, the processing is finished. When the important phrase exists, a representative character string of the document is extracted as a candidate character string, deleting the candidate character string is deleted from the document, and the important phrase is deleted from the candidate character string. When the number of the important phrase being deleted is one or more, the candidate character string is set as an important character string.
US09262386B2	Data editing for improving readability of a display Provides ability to analyze the readability of an image to be displayed on a screen as a web page, etc., and appropriately modify the image. It includes a rendering section for generating an image by rendering an HTML document; an image processing section for performing image processing on the image generated by the rendering section to simulate and evaluate how the image is viewed under a certain visual characteristic; and a result presentation section for locating an HTML element that needs to be modified in the HTML document to be processed based on the evaluation result of the image processing section and for presenting the HTML element to a web page creator. The result presentation section also retrieves a modification method for the HTML element that needs to be modified from a symptom model storage section. A document modification processing section actually modifies the HTML document.
US09262383B2	System, method, and computer program product for processing a markup document A system, method, and computer program product are provided for identifying a first markup document including first numerical values and first tags reflecting first characteristics of the first numerical values associated with a first unit of measure, and a second markup document including second numerical values and second tags reflecting second characteristics of the second numerical values associated with a second unit of measure. The first characteristics of the first numerical values associated with the first unit of measure are different from the second characteristics of the second numerical values associated with the second unit of measure. At least a portion of the numerical values of at least one of the first markup document or the second markup document are automatically transformed, so that the at least some of the first numerical values of the first markup document and at least some of the second numerical values of the second markup document have a common unit of measure. Further, at least a part of the first markup document and at least a part of the second markup document are processed, resulting in a single markup document, for display.
US09262382B2	Determination of where to crop content in a layout Examples disclose an apparatus comprising a processor to determine probabilities based on both a variable range of pages in a layout and a variable range of length of content in the layout. Additionally, the examples disclose the processor is further to identify a maximum probability from the determined probabilities. Also, the examples disclose the processor is further to identify values for a number of pages and a length of content associated with the maximum probability for determination of where to crop content in the layout.
US09262379B2	Matrix calculation device, matrix calculation method, and storage medium having matrix calculation program stored thereon A matrix calculation device includes a first partition position display unit configured to distinguishably display a partition position of the one matrix partitioned by the matrix partitioning unit, a partition position determination unit configured to determine, based on a partition position of the one matrix distinguishably displayed by the first partition position display unit and a definition of a product of matrices, a partition position of the other matrix, and a second partition position display unit configured to distinguishably display the partition position of the other matrix determined by the partition position determination unit.
US09262376B2	Test apparatus and test method A synchronization pattern generating unit generates a synchronization pattern required for a clock recovery unit which has been built into a DUT to maintain a link with an external circuit. A gate signal generating unit generates a gate signal which is asserted in a period in which a vector pattern is to be supplied to the DUT. In a first mode, a pattern selecting unit is configured such that it outputs the vector pattern during a period in which the gate signal is asserted and outputs a fixed output level during a period in which the gate signal is negated. In a second mode, the pattern selecting unit is configured such that it outputs the vector pattern during a period in which the gate signal is asserted and outputs the synchronization pattern during a period in which the gate signal is negated.
US09262373B2	Cloud-based software eco-system A novel eco-system is provided which first supplies a standardized template of one or more virtual machine images for software module providers/vendors. A plurality of modules executing on the virtual machine images is selected by a user to comprise a plurality of configurations. A suitable configuration may be determined according to a metric and the determined suitable configuration of software modules is subsequently used to build an end-to-end solution.
US09262371B2	System for monitoring multiple building automation systems A method for execution on a computing device includes transmitting first identification information to a server processing circuit via the Internet. The server processing circuit identifies a plurality of geographically dispersed systems corresponding to the first identification information. Information including geographical coordinates and system status information is received for each system. A set of geographical boundary coordinates are determined. Moreover, a visible characteristic value for each system is determined based on the corresponding system status information. A map presentation function executed by a second processing circuit displays a map based on the geographic boundary coordinates, and displays a plurality of visible indicators on the map. Each of the plurality of visible indicators has a position on the map corresponding the geographical coordinates of a corresponding system. Each of the plurality of visible indicators has a visible characteristic corresponding to the visible characteristic value of the corresponding system.
US09262367B2	Method and network node for distributing customized content By using embodiments of the present invention, a targeted advertisement, or other customized content, can be published to a consumer when visiting a website. The consumer is connected to a mobile broadband network and is authenticated and authorized to this broadband network. Further, the consumer is given an Internet Protocol (IP) address of the mobile broadband network and this IP address is used to identify the consumer when the targeted advertisement is determined according to a profile of the consumer.This is achieved according to embodiments by letting the publisher request a targeted advertisement for a consumer visiting a website of the publisher. The targeted advertisement is found by using the IP address allocated to the consumer device by the mobile broadband network, i.e. the consumer is identifiable by the IP address. By using the mobile broadband operator's ability to map the IP address and the consumer identity a consumer profile of the consumer is found and based on the consumer profile the targeted advertisement can be determined and shown to the consumer. The consumer profile is controlled by the mobile broadband network.
US09262356B2	Arbiter device and arbitration method An arbiter device arbitrating resource requests received at a plurality of input ports is proposed, which comprises an arbiter circuit that selects an input port to which a resource request is to be granted and successively grants a number of resource requests received at the selected input port.
US09262355B2	Controller configured to control timing of access request according to density of burst access and access load A controller as an embodiment of the present disclosure controls a timing of transmitting an access request that has been received from an initiator (or its transmission interval). The controller includes: transmitting and receiving circuitry configured to receive an access request related to burst accesses from a first initiator that is connected via a first bus to, and adjacent to, the transmitting and receiving circuitry and configured to transmit the access request to a second bus implemented as a network; and a transmission interval controller configured to control the timing of transmitting the access request that has been received from the first initiator according to density of the burst accesses during a period in which the burst accesses continue and an access load on the second bus.
US09262350B2	De-interleaving on an as-needed basis One embodiment is an apparatus having a memory, a controller, and a de-interleaving module. The memory is configured to store portions of a set of interleaved values, where the set of interleaved values correspond to a single application of an interleaving mapping to a set of un-interleaved values. The controller is configured to retrieve each portion from an other memory that stores the set of interleaved values by moving the portion from the other memory to the memory. The de-interleaving module is configured to de-interleave the interleaved values in at least one of the portions to generate a de-interleaved portion such that processing downstream of the de-interleaving module can begin processing the de-interleaved portion before all of the interleaved values in the set of interleaved values are de-interleaved by the de-interleaving module.
US09262341B2	Microcomputer and method for controlling memory access A microcomputer including a CPU, a plurality of protection information storages configured to store memory protection information specifying an access permission state or access prohibited state to a memory space by a program executed by the CPU, a memory access control apparatus configured to determine whether or not to allow a memory access request from the CPU according to the memory protection information, and a reset apparatus configured to output a reset signal to the plurality of protection information storages according to a reset request output from the CPU according to a switching of programs executed by the CPU. Each of the plurality of protection information storages is set to a second memory protection state according to the reset signal from a first memory protection state.
US09262338B1	Synchronizing a translation lookaside buffer with an extended paging table A processor including logic to execute an instruction to synchronize a mapping from a physical address of a guest of a virtualization based system (guest physical address) to a physical address of the host of the virtualization based system (host physical address), and stored in a translation lookaside buffer (TLB), with a corresponding mapping stored in an extended paging table (EPT) of the virtualization based system.
US09262333B2	Asymmetric memory migration in hybrid main memory Main memory is managed by receiving a command from an application to read data associated with a virtual address that is mapped to the main memory. A memory controller determines that the virtual address is mapped to one of the symmetric memory components of the main memory, and accesses memory use characteristics indicating how the data associated with the virtual address has been accessed, The memory controller determines that the data associated with the virtual address has access characteristics suited to an asymmetric memory component of the main memory and loads the data associated with the virtual address to the asymmetric memory component of the main memory. After the loading and using the memory management unit, a command is received from the application to read the data associated with the virtual address, and the data associated with the virtual address is retrieved from the asymmetric memory component.
US09262331B2	Memory management with priority-based memory reclamation A memory buffer with a set of one or more structures is created by a process of a first software program. The first memory buffer comprises a predetermined amount of memory. It is determined that a structure of the set of one or more structures has been or will be consumed by a second software program that supports the first software program. The consumption of the structure of the set of one or more structures indicates that memory associated with the structure of the set of one or more structures is being reclaimed. In response to the determination that the structure of the set of one or more structures has been or will be consumed, data is written from a first location to a second location. The first location is in memory allocated to the first software program and the second location is indicated for data storage.
US09262327B2	Signature based hit-predicting cache An apparatus may comprise a cache file having a plurality of cache lines and a hit predictor. The hit predictor may contain a table of counter values indexed with signatures that are associated with the plurality of cache lines. The apparatus may fill cache lines into the cache file with either low or high priority. Low priority lines may be chosen to be replaced by a replacement algorithm before high priority lines. In this way, the cache naturally may contain more high priority lines than low priority ones. This priority filling process may improve the performance of most replacement schemes including the best known schemes which are already doing better than LRU.
US09262319B2	Adusting flash memory operating parameters based on historical analysis of multiple indicators of degradation The present invention is directed to a method for increasing the operational lifetime of a flash memory device, wherein, the method comprises varying the operating parameters of the flash memory device over the lifetime of the flash memory device. The advantage of providing a method which varies the operating parameters of a flash memory device is that the operational lifetime of the flash memory device will be increased. Relatively low voltages and relatively short voltage periods may be used initially to write to, read from and erase the flash cells in the flash memory device. As time passes, the flash cells in the flash memory device will begin to degrade and it will be necessary to increase the voltage and the period of the voltage applied to the flash memory device in order to ensure that the correct write, read and/or erase commands are carried out. The invention is also directed towards a flash memory device.
US09262318B1	Serial flash XIP with caching mechanism for fast program execution in embedded systems A system including a processor, a memory controller, and a flash memory module. The processor is configured to generate a request to retrieve information corresponding to an address. The memory controller module includes a cache memory configured to store information, and a cache control logic module configured to determine whether the cache memory stores the information corresponding to the address, if the cache memory stores the information corresponding to the address, retrieve the information from the cache memory and provide the information to the processor, and if the cache memory does not store the information corresponding to the address, generate a flash memory read request based on the address. The flash memory module is configured to, in response to receiving the flash memory read request, provide the information corresponding to the address to the memory controller module.
US09262316B2	Recording dwell time in a non-volatile memory system In at least one embodiment, a data storage system includes a non-volatile memory array, such as a flash memory array, and a controller coupled to the memory array. The controller records, for each of a plurality of valid pages in the memory array, a respective indication of a dwell time of each valid page.
US09262309B2	Optimizing test data payload selection for testing computer software applications that employ data sanitizers and data validators Testing computer software applications is implemented by probing a computer software application to determine the presence in the computer software application of any data-checking features, and applying a rule to the data-checking features that are determined to be present in the computer software application, thereby producing a testing set of inputs. The testing set includes any sets of inputs that were used to test sets of data-checking software, where each of the sets of data-checking software includes one or more data sanitizers and/or data validators, and where the rule is configured to produce the testing set to include one or more of the sets of inputs when the rule is applied to any of the data-checking features. The computer software application is tested using the testing set.
US09262306B2	Software application testing An online marketplace for distributing software applications is established. From the online marketplace, devices are enabled to select respective ones of the software applications and initiate testing of the selected software applications in connection with testing tools operating in respective secure testing environments that shield the devices from potential adverse effects arising from testing the selected software applications. The testing tools generate testing data relating to one or more criteria for certifying the selected software applications. For each of one or more of the selected software applications, a determination is made whether or not to classify the software application as a certified software application based on an evaluation of the testing data generated during the testing of the software applications initiated by a plurality of the devices.
US09262304B2	Methods and systems for testing interactions between mobile applications A shared platform included in a device can be configured to execute instructions from a first application and a second application to operate the device. The shared platform can be configured to receive mode instructions from the first application indicative of operating in a test mode where the shared platform provides simulated responses to the first application. The shared platform can receive a request from the first application pertaining to an operation of the second application. The shared platform operating in the test mode can determine a response to the request from the first application based on a simulation of providing the request to the second application.
US09262303B2	Automated semiconductor design flaw detection system A simulation system enables comparison of a realized physical implementation against the simulation models that produce them, thereby detecting differences between an initial, logical design and the resulting physical embodiment. Errors introduced by an initial design, faulty Intellectual Property blocks, faulty programmable logic device silicon, faulty synthesis algorithms and software, and/or faulty place and route algorithms and software may be detected. As a result, the simulation system reflects both the accuracy of the actual implemented device with the capacity and performance of a purpose built hardware-assisted solution.
US09262301B2	Observability control with observability information file Methods of managing observability code in an application program include generating an application program including an observability point, the observability point including a location in the application at which observability code, or a call to observability code, can be inserted, loading the application program into a memory of a target system, retrieving observability information from an observability point information file, and inserting the observability code, or the call to the observability code, at the observability point in the memory of the target system using the observability information retrieved from the observability point information file.
US09262300B1	Debugging computer programming code in a cloud debugger environment A method for capturing breakpoint information from a debuggee software process includes generating a breakpoint condition based upon a breakpoint request received from a user computing device corresponding to a user and transmitting the generated breakpoint condition to debuglets, each corresponding to a software process executed by a debuggee service. The debuggee service executes on a distributed system, and each debuglet translates the generated breakpoint condition to a physical breakpoint condition set to the respective software process. The method also includes receiving a request from one of the debuglets to update active breakpoint information captured by the debuglet upon the physical breakpoint condition being hit by one of the software processes and transmitting a notification from the processing device indicating the physical breakpoint condition being hit to the user computing device.
US09262294B2	System and method for event detection and correlation from moving object sensor data An exemplary embodiment of the present techniques may detect and correlate events from moving object sensor data by receiving data from a sensor. The data received from the sensor may be mapped, and events may be detected based on the mapped sensor data. Events from the mapped sensor data may be correlated online.
US09262292B2	Test access system, method and computer-accessible medium for chips with spare identical cores Exemplary system, method and computer-accessible medium for testing a multi-core chip can be provided which can have and/or utilize a plurality of identical cores. This can be performed by comparing each core with as many as at least the number of spare cores plus 1 using a comparator; the number of comparators can equal the total number of cores multiplied by one-half the number of spare cores plus 1. A mismatch between two cores can identify at least one of the two cores as defective and a perfect match between two cores can identify both cores as not defective. The multi-core chip can fail the test if the number of defective cores can be greater than the number of spare cores.
US09262290B2	Flash copy for disaster recovery (DR) testing In one embodiment, a system includes a processor and logic integrated with and/or executable by the processor, the logic being configured to cause the processor to define a disaster recovery (DR) family, the DR family having one or more DR clusters accessible to a DR host and one or more production clusters accessible to a production host, wherein the DR host is configured to replicate data from the one or more production clusters to the one or more DR clusters, create a backup copy of data stored to the one or more production clusters, store the backup copy to the one or more DR clusters, establish a time-zero in the DR family, and share a point-in-time data consistency at the time-zero among all clusters within the DR family. Other systems, methods, and computer program products are presented for DR testing, according to more embodiments.
US09262287B2	Computer information system and dynamic disaster recovery method therefor The method is performed as a client device and includes receiving a first message that includes a first data usage value. The first message is formatted according to a respective format. After receiving the first message, the method further includes acquiring a data usage template corresponding to the respective format. The method further includes receiving a second message that includes a second data usage value. The second message is formatted according to the respective format. The method further includes parsing the second message according to the data usage template so as to obtain a second data usage value.
US09262286B2	Failover in a data center that includes a multi-density server Failover in a data center that includes a multi-density server, where the multi-density server includes multiple independent servers, includes; detecting, by a management module, a failure of one of the independent servers of the multi-density server; identifying, by the management module, a failover target; determining, by the management module, whether the failover target is a non-failed independent server included in the multi-density server; and responsive to determining that the failover target is a non-failed independent server included in the multi-density server, migrating, by the management module, the failed independent server's workload to another server that is not included in the multi-density server.
US09262284B2	Single channel memory mirror Embodiments of the invention address deficiencies of the art in respect to memory fault tolerance, and provide a novel and non-obvious method, system and apparatus for single channel memory mirroring. In one embodiment of the invention, a single channel memory mirroring system can be provided. The single channel memory mirroring system can include a memory controller, a single communications channel, and an operational data portion of memory, and a duplicate data portion of memory, both portions being communicatively coupled to the memory controller over the single communications channel. Finally, the system can include single channel memory mirror logic. The logic can include program code enabled to mirror data in the operational data portion of memory in the duplicate data portion of memory.
US09262277B2	Method for extracting and storing records of data backup activity from a plurality of backup devices A method and system for requesting, cross-referencing, extracting and storing historical records of data backup activity by using a software component that interfaces to a plurality of data backup software devices is disclosed. Through the use of a system and method in accordance with the present invention, the aforementioned database can be made self-refreshing, requiring minimal ongoing intervention subsequent to initial configuration. In addition, the aforementioned data refreshes can be manually invoked at any time.
US09262276B2	Storage device as buffer for unreliable storage A system and method for managing storage of a digital stream including writing data of the stream to a network storage device, while monitoring availability of the network storage device, switching to writing additional data of the stream to a standby storage device while continuing monitoring the availability of the network storage device, if the network storage device becomes unavailable, switching back to writing additional data of the stream to the network storage device while continuing monitoring the availability of the network storage device, when the network storage device becomes available, and writing to the network storage device the additional data that was written to the standby storage device while the network storage device was unavailable, concurrently with the writing of the additional data of the stream to the network storage device.
US09262275B2	Archiving data objects using secondary copies A system for archiving data objects using secondary copies is disclosed. The system creates one or more secondary copies of primary copy data that contains multiple data objects. The system maintains a first data structure that tracks the data objects for which the system has created secondary copies and the locations of the secondary copies. To archive data objects in the primary copy data, the system identifies data objects to be archived, verifies that previously-created secondary copies of the identified data objects exist, and replaces the identified data objects with stubs. The system maintains a second data structure that both tracks the stubs and refers to the first data structure, thereby creating an association between the stubs and the locations of the secondary copies.
US09262272B2	Data center power adjustment A power cap agent establishes a power cap. The power cap agent throttles a first power priority virtual machine. The power cap agent determines that the first power priority virtual machine and the additional power priority virtual machine contribute to power consumption above the power cap among the plurality of servers. The power cap agent throttles the additional power priority virtual machine, wherein the first power priority virtual machine has a first power priority lower than an additional power priority of the additional power priority virtual machine. The power cap agent determines that the first power priority virtual machine and the additional power priority virtual machine contribute to power consumption above the power cap, responsive to throttling the first power priority virtual machine and throttling the additional virtual machine.
US09262270B2	Live error recovery A packet is identified at a port of a serial data link, and it is determined that the packet is associated with an error. Entry into an error recovery mode is initiated based on the determination that the packet is associated with the error. Entry into the error recovery mode can cause the serial data link to be forced down. In one aspect, forcing the data link down causes all subsequent inbound packets to be dropped and all pending outbound requests and completions to be aborted during the error recovery mode.
US09262267B2	Error correction in solid state drives (SSD) A paging scheme for a Solid State Drive (SSD) error correction mechanism that exchanges portions of a parity component, such as a page, between SRAM and less expensive DRAM, which stores the remainder of a context of pages. A parity operation applies an XOR function to corresponding memory positions in the pages of the context. Dedicated error correction (parity) SRAM need only enough memory for portions of memory, typically a cache line of a page, upon which the parity operation (XOR) is operating. The remaining portions in the context are swapped, or paged out, by cache logic such that the entire context is iteratively processed (XORed) by the parity operation.
US09262266B2	Nonvolatile memory devices with age-based variability of read operations and methods of operating same Integrated circuit memory systems and methods include comparing a number of erase cycles of a memory block corresponding to a read request to a first value and reading data stored in the memory block according to a first read condition corresponding to a first reliability improvement operation when the number of erase cycles of the memory block is less than the first value. An error of the data read according to the first read condition may be corrected using an error correction code (ECC) when the error of the data read according to the first read condition is correctable.
US09262263B2	Bit recovery system A particular device includes a resistance-based memory device, a tag random-access memory (RAM), and a bit recovery (BR) memory. The resistance-based memory device is configured to store a data value and error-correcting code (ECC) data associated with the data value. The tag RAM is configured to store information that maps memory addresses of a main memory to wordlines of a cache memory, where the cache memory includes the resistance-based memory device. The BR memory is configured to store additional error correction data associated with the data value, where the BR memory corresponds to a volatile memory device.
US09262262B2	Memory device with retransmission upon error A controller includes a link interface that is to couple to a first link to communicate bidirectional data and a second link to transmit unidirectional error-detection information. An encoder is to dynamically add first error-detection information to at least a portion of write data. A transmitter, coupled to the link interface, is to transmit the write data. A delay element is coupled to an output from the encoder. A receiver, coupled to the link interface, is to receive second error-detection information corresponding to at least the portion of the write data. Error-detection logic is coupled to an output from the delay element and an output from the receiver. The error-detection logic is to determine errors in at least the portion of the write data by comparing the first error-detection information and the second error-detection information, and, if an error is detected, is to assert an error condition.
US09262259B2	One-time programmable integrated circuit security One-time programmable integrated circuit security is described. An example of a method of protecting memory assets in an integrated circuit includes sampling values of multiple OTP memory arrays and comparing the sampled value of each OTP memory array with the sampled value of each other OTP memory array and with an unprogrammed OTP memory array value. The method further includes determining if an integrated circuit performance fault has occurred based on the compared sampled values, booting the integrated circuit, and operating the integrated circuit with access to memory determined by the fault occurrence determination.
US09262258B2	Handling faults in a continuous event processing (CEP) system The concept of faults and fault handling are added to the execution of continuous event processing (CEP) queries. By introducing fault handling techniques to the processing of CEP queries, users are enabled to instruct a CEP query processor to respond to faults in a customized manner that does not necessarily involve the halting of the CEP query relative to which the faults occurred. For example, a fault might be due to a temporary problem. Under such circumstances, the CEP query processor can be instructed to ignore the fault and allow the execution of the CEP query to continue relative to the remainder of the event stream. Alternatively, if the fault is due to a problem with the CEP query itself, then the CEP query processor can be instructed to propagate the fault through the query processing system until the fault ultimately causes the problematic CEP query to be halted.
US09262253B2	Middlebox reliability The discussion relates to middlebox reliability. One example can apply event filters to a dataset of middlebox error reports to separate redundant middlebox error reports from a remainder of the middlebox error reports of the dataset. The example can categorize the remainder of the middlebox error reports of the dataset by middlebox device type. The example can also generate a graphical user interface that conveys past reliability and predicted future reliability for an individual model of an individual middlebox device type.
US09262251B1	Detecting memory failures in computing systems Systems and methods for the analysis of memory information of a computing device are provided. One or more user computing devices may transmit memory information to a memory analysis system. The memory analysis system may generate a weighted object graph based on the received memory information, and identify subgraphs to inspect for potential memory use patterns. If such patterns are common in an identified subgraph, they may indicate a potential memory leak. The memory analysis system may further analyze a larger portion of the weighted object graph based on a detected common pattern. Each detected pattern may be ranked based on the likelihood that it corresponds to a memory leak.
US09262247B2	Updating data stored in a dispersed storage network A method begins by a dispersed storage (DS) processing module receiving a modified data object, wherein the modified data object is a modified version of a data object and the data object is divided into a plurality of data segments and stored in the DSN. The method continues with the DS processing module mapping portions of the modified data object to the plurality of data segments that includes creating a middle data segment of a second plurality of data segments based on a corresponding middle data segment of the plurality of data segments when the a portion of the portions corresponds to middle data of the modified data object. The method continues with the DS processing module encoding the middle data segment using a dispersed storage error coding function to produce an encoded data segment and overwriting the corresponding middle data segment with the encoded data segment in the DSN.
US09262245B2	Computing system and method for processing user input in a world wide web application In one embodiment, the invention is a computing system comprising a World Wide Web application with a user interactive record field is described. The record field receives a record field entry. The application receives a context change request. Responsive to the context change request, the application dynamically transmits the record field entry to a server for storage in a database.
US09262242B2	Machine-to-machine (“M2M”) device client systems, methods, and interfaces Exemplary machine-to-machine (“M2M”) device client systems, methods, and interfaces are described herein. An exemplary M2M device includes an M2M device client configured to provide 1) a platform messaging interface through which the M2M device client communicates with an M2M platform and 2) an application interface that includes a set of application program interfaces (“APIs”) through which an application installed on the M2M device interfaces with the M2M device client. The set of APIs may include one or more of the exemplary APIs and/or API function calls described herein. Corresponding systems, methods, and interfaces are also described.
US09262236B2	Warning track interruption facility A program (e.g., an operating system) is provided a warning that it has a grace period in which to perform a function, cleanup (e.g., complete, stop and/or move a dispatchable unit). The program is being warned, in one example, that it is losing access to its shared resources. For instance, in a virtual environment, a guest program is warned that it is about to lose its central processing unit resources, and therefore, it is to perform a function, such as cleanup.
US09262233B1	Second-order tuning of spin loops A method and/or computer for a tuned spin count in a multithreaded system determines a re-calculation time interval at which to re-calculate a current spin lock value. Then, a spin-lock-re-calculation is repeatedly executed at the re-calculation time interval to perform:observing a current environment of the multithreaded system, determining, using a second-order tuning and values of the current environment, a dynamically calculated heuristic to provide the newly-recalculated spin lock value, and memorizing the newly re-calculated spin lock value, in a memory, as the current spin lock value. Meanwhile, thread(s) in the multithreaded system which want to execute a spinlock will obtain the current spin lock value which is memorized in the memory, and execute the spin lock using the current spin lock value to set a length of the spin lock.
US09262232B2	Priority build execution in a continuous integration system A mechanism for priority build execution in a continuous integration system is disclosed. A method includes executing, by a computing device in a continuous integration system, a low priority job of the continuous integrations system using a resource of the computing device. The method also includes receiving a high priority job to be executed by the computing device and identifying a conflict at the resource when the high priority job is assigned to execute using the same resource that is currently being used for executing the low priority job. When the conflict is identified, the method further includes suspending the execution of the low priority job, recording a state of the low priority job at a time of the suspension of the execution and executing the high priority job using the resource.
US09262229B2	System and method for supporting service level quorum in a data grid cluster A system and method is described for use with a data grid cluster, for supporting service level quorum in the data grid cluster. The data grid cluster includes a plurality of cluster nodes that support performing at least one service action. A quorum policy, defined in a cache configuration file associated with the data grid cluster, can specify a minimum number of service members that are required in the data grid cluster for performing the service action. The data grid cluster uses the quorum policy to determine whether the service action is allowed to be performed, based on a present state of the plurality of cluster nodes in the data grid cluster.
US09262228B2	Distributed workflow in loosely coupled computing A method that can be used in a distributed workflow system that uses loosely coupled computation of stateless nodes to bring computation tasks to the compute nodes is disclosed. The method can be employed in a computing system, such as cloud computing system, that can generate a computing task separable into work units and performed by a set of distributed and decentralized workers. In one example, the method arranges the work units into a directed acyclic graph representing execution priorities between the work units. The plurality of distributed and decentralized workers query the directed acyclic graph for work units ready for execution based upon the directed acyclic graph. In one example, the method is included in a computer readable storage medium as a software program.
US09262226B2	Data storage resource allocation by employing dynamic methods and blacklisting resource request pools A resource allocation system begins with an ordered plan for matching requests to resources that is sorted by priority. The resource allocation system optimizes the plan by determining those requests in the plan that will fail if performed. The resource allocation system removes or defers the determined requests. In addition, when a request that is performed fails, the resource allocation system may remove requests that require similar resources from the plan. Moreover, when resources are released by a request, the resource allocation system may place the resources in a temporary holding area until the resource allocation returns to the top of the ordered plan so that lower priority requests that are lower in the plan do not take resources that are needed by waiting higher priority requests higher in the plan.
US09262225B2	Remote memory access functionality in a cluster of data processing nodes A server apparatus comprises a plurality of server on a chip nodes interconnected to each other through a node interconnect fabric. Each one of the server on a chip nodes has respective memory resources integral therewith. Each one of the server on a chip nodes has information computing resources accessible by one or more data processing systems. Each one of the server on a chip nodes is configured with memory access functionality enabling allocation of at least a portion of said memory resources thereof to one or more other ones of the server on a chip nodes and enabling allocation of at least a portion of said memory resources of one or more other ones of the server on a chip nodes thereto based on a workload thereof.
US09262219B2	Distributed processing system, distributed processing method, and distributed processing program The present invention includes application execution units (1a) and (1b) that perform distributed execution of one application while referencing a processing target file F in a distributed shared storage DS; a processing step monitoring unit (3) that monitors the processing step of the application that is being executed by the application execution units; a resource isolation determination unit (4) that determines whether the processing step being monitored by the processing step monitoring unit is a resource isolation step that requires resource isolation; and resource provision units (2)a and (2b) that generate an isolated file CF if the resource isolation determination unit determined that the processing step is the resource isolation step.
US09262218B2	Methods and apparatus for resource management in cluster computing Embodiments of an event-driven resource management technique may enable the management of cluster resources at a sub-computer level (e.g., at the thread level) and the decomposition of jobs at an atomic (task) level. A job queue may request a resource for a job from a resource manager, which may locate a resource in a resource list and grant the resource to the job queue. After the resource is granted, the job queue sends the job to the resource, on which the job may be partitioned into tasks and from which additional resources may be requested from the resource manager. The resource manager may locate additional resources in the list and grant the resources to the resource. The resource sends the tasks to the granted resources for execution. As resources complete their tasks, the resource manager is informed so that the status of the resources in the list can be updated.
US09262216B2	Computing cluster with latency control A computing cluster operated according to a resource allocation policy based on a predictive model of completion time. The predictive model may be applied in a resource control loop that iteratively updates resources assigned to an executing job. At each iteration, the amount of resources allocated to the job may be updated based on of the predictive model so that the job will be scheduled to complete execution at a target completion time. The target completion time may be derived from a utility function determined for the job. The utility function, in turn, may be derived from a service level agreement with service guarantees and penalties for late completion of a job. Allocating resources in this way may maximize utility for an operator of the computing cluster while minimizing disruption to other jobs that may be concurrently executing.
US09262215B2	Selective constant complexity dismissal in task scheduling A strictly increasing function is implemented to generate a plurality of unique creation stamps, each of the plurality of unique creation stamps increasing over time pursuant to the strictly increasing function. A new task to be placed with the plurality of tasks is labeled with a new unique creation stamp of the plurality of unique creation stamps. The one of the list of dismissal rules holds a minimal valid creation (MVC) stamp, which is updated when a dismissal action for the one of the list of dismissal rules is executed.
US09262213B1	Dynamic suggestion of next task based on task navigation information A device may receive task navigation information, identify a selection of a first task, of multiple tasks, based on the task navigation information, and provide a list of a group of tasks from the multiple tasks. The list of the group tasks may be based on information identifying tasks historically selected subsequent to the selection of the first task. The device may identify a selection of a second task, of the multiple tasks subsequent to identifying the selection of the first task; and store information identifying that the second task has been selected subsequent to the first task based on identifying the selection of the second task subsequent to the selection of the first task. The information identifying that the second task has been selected subsequent to the first task may include a number of times that the second task has been selected subsequent to the first task.
US09262205B2	Selective checkpointing of links in a data flow based on a set of predefined criteria Techniques are disclosed for qualified checkpointing of a data flow model having data flow operators and links connecting the data flow operators. A link of the data flow model is selected based on a set of checkpoint criteria. A checkpoint is generated for the selected link. The checkpoint is selected from different checkpoint types. The generated checkpoint is assigned to the selected link. The data flow model, having at least one link with no assigned checkpoint, is executed.
US09262203B2	Processing execution requests within different computing environments A computerized method, computer system, and computer program product for processing an execution request within different computing environments. Execution requests and generated reference information are forwarded to the different computing environments, where the requests are executing using the reference information. Results of the processed execution requests are collected from the different computing environments. The results are compared to identify whether a discrepancy exists giving indication of a software or hardware error.

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