最新美国发明专利第2016-02-09期 - 专利汇|PatentHub专利检索|专利查询网|发明专利查询分析

Document	Document Title
US09258239B2	Method for managing and sharing symmetric flow and asymmetric flow in duplexed network Provided is a network duplexing apparatus and method. The network duplexing apparatus includes a plurality of network interface units configured to store information of a flow flowing in the network interface units, provide the information of the flow to a master unit when the flow corresponds to an asymmetric flow, and request information of an opposite side flow of the flow from the master unit to receive the requested information, and the master unit configured to store the information of the flow provided from the network interface unit, determine whether the information of the opposite side flow of the flow is stored, and provide the information of the opposite side flow to the network interface unit when the information of the opposite side flow is stored.
US09258238B2	Dynamic end-to-end network path setup across multiple network layers A centralized controller provides dynamic end-to-end network path setup across multiple network layers. In particular, the centralized controller manages end-to-end network path setup that provisions a path at both the transport network layer (e.g., optical) and the service network layer (e.g., IP/MPLS). The centralized controller performs path computation for an optical path at the transport network layer and for a path at the service network layer that transports network traffic on the underlying optical transport path, based on information obtained by the centralized controller from the underlying network components at both layers.
US09258237B1	Enhancing DOCSIS services through network functions virtualization This disclosure describes techniques for provisioning a CMTS to re-direct customer traffic into virtualized network functions (NFVs) service chains. This disclosure describes, in one example, techniques for providing linkage between DOCSIS service flows and NFV service chains in the DOCSIS provisioning system by embedding information within cable modem boot files used to configured cable modems within the broadband system. In one example, the techniques facilitate the definition of an NFV service-chain in the DOCSIS cable modem boot file provisioning system. A supported CMTS, CCAP or Edge Router intercepts and interprets the configuration to install packet classifiers that steer specific subscriber flows, as detailed in the DOCSIS cable modem boot file, through the service-chain.
US09258236B2	Per-class scheduling with rate limiting Providing network access is disclosed. Use of a provider equipment port via which network access is provided to two or more downstream nodes, each having one or more classes of network traffic associated with it, is scheduled on a per class basis, across the downstream nodes. The respective network traffic sent to each of at least a subset of the two or more downstream nodes is limited, on a per downstream node basis, to a corresponding rate determined at least in part by a capacity of a communication path associated with the downstream node.
US09258235B2	Edge node for a network domain A system for managing congestion within a network domain includes an ingress node, an interior node, and an egress node. The ingress node receives and routes data units entering the network domain. The interior node detects whether a load exceeds one or more load thresholds and generates congestion marked data units. The egress node detects the presence of congestion marked data units and reacts to the detection of the presence of congestion marked data units by invoking a congestion control process.
US09258234B1	Dynamically adjusting liveliness detection intervals for periodic network communications In general, techniques are described to dynamically adjust a session detection time defined by a timer in accordance with a bidirectional forwarding detection (BFD) protocol. The techniques utilize existing hardware and BFD software infrastructure. An example network device includes a memory, programmable processor(s), and a control unit configured to execute a timer, receive one or more packets provided by the BFD protocol, detect, based on the received one or more packets, a congestion condition associated with a link via which the network device is coupled to a network, adjust, based on the detected congestion condition, a session detection time defined by the timer, and in response to a failure to receive a packet provided by the BFD protocol within the session detection time defined by the timer, detect a failure associated with the link.
US09258233B2	Adjusting rate limits for transmission rates of data flows having a certain priority in a transmitter A method for adjusting a set of primary rate limits for transmission rates of data flows having a certain priority in a transmitter is provided. A mean value is determined of a duty cycle of the certain priority at the port as obtainable from the transmission or flow control, wherein the data flows having different priorities including said certain priority are transmitted by a port of the transmitter, transmissions for rate-limited data flows having the certain priority are limited by secondary rate limits (r1′, r2′, . . . rn′) per data flow, and transmissions for all data flows having the certain priority are controlled by a transmission or flow control per priority. The secondary rate limits (r1′, r2′, . . . rn′) are obtained by adjusting the primary rate limits for the transmission rates of the data flows having the certain priority based on the determined mean value of the duty cycle.
US09258231B2	Bandwidth allocation management Bandwidth allocation management includes determining current available bandwidth of a network within which a computer system is operating. The bandwidth allocation management also includes using the current available bandwidth and applied feature delivery settings to determine an adjustment in feature delivery to the computer system. At least a portion of the feature delivery settings is specified by an end user of the computer system.
US09258229B2	Systems and methods for accessing a multi-bank SRAM A device may include at least one processor which may access, using a lookup key, a ternary content addressable memory to acquire a lookup result that includes information identifying a group of addresses for accessing a group of static random access memories. The at least one processor may parse the lookup result to identify the group of addresses and may simultaneously access, using the group of addresses, the group of static random access memories, to simultaneously read data from the group of static random access memories. The at least one processor may process a group of packets based on the data.
US09258227B2	Next hop chaining for forwarding data in a network switching device A route for a data unit through a network may be defined based on a number of next hops. Exemplary embodiments described herein may implement a router forwarding table as a chained list of references to next hops. In one implementation, a device includes a forwarding table that includes: a first table configured to store, for each of a plurality of routes for data units in a network, a chain of links to next hops for the routes; and a second table configured to store the next hops. The device also includes a forwarding engine configured to assemble the next hops for the data units based on using the chain of links in the first table to retrieve the next hops in the second table and to forward the data units in the network based on the assembled next hops.
US09258222B2	Implementing a shortest path bridging (SPB) network using a virtual routing and forwarding (VRF) identifier A method, apparatus and computer program product for using Backbone Virtual Local Area Network (BVLAN) as Virtual Routing and Forwarding (VRF) Identifier and shared Backbone Media Access Control (BMAC) tables to implement a Shortest Path Bridging (SPB) Layer 3 (L3) Virtual Services Network (VSN) is presented. For routed traffic, a Layer 3 (L3) Virtual Services Network (VSN) is associated with a unique Virtual Local Area Network Identifier (VLAN_ID) value in a first Shortest Path Bridging (SPB) network for routed traffic. The routed traffic comprises traffic sent over an SPB network interface, traffic received from an SPB interface, or traffic forwarded from a first SPB Network interface to a second SPB Network interface.
US09258221B2	System and method for rapid protection of RSVP based LSP Various exemplary embodiments relate to a method performed by a network node in a resource reservation protocol (RSVP) based label switch path (LSP) network, the method including: receiving a message to establish a LSP; receiving a resv message; initiating the establishment of a backup path; determining that the establishment of the backup path failed; setting a backup timer; and initiating the establishment of a backup path upon the expiration of the backup timer.
US09258220B2	Communication system, node, control server, communication method and program A packet contains an array of processing operations that are to be performed by a node. Each node in a data forwarding network performs the processing it has to perform in accordance with the array of the processing operations contained in the packet.
US09258216B2	Methods and systems for transmitting packets through network interfaces A method carried out by a first communications device for transmitting data packets, wherein the first communications device comprises a plurality of network interfaces. Data packets are transmitted through a first network interface when a first condition is satisfied, and through a second network interface when a second condition is satisfied. In one of the embodiments, the plurality of network interfaces are classified into a plurality of groups of network interfaces according to a first group of conditions, and the first network interface and second network interface belong to two different groups of network interfaces.
US09258215B2	Optical layer protection switching applications Systems and methods are disclosed for modulating, with circuitry of a source node in a communication network, at least one optical carrier to carry data utilizing a format of a soft decision forward error correction (SD-FEC) data field of an overhead portion of a data frame; encoding, with the circuitry of the source node, first data being SD-FEC data and second data being additional data into the SD-FEC data field, the first and second data being accessible without accessing client data traffic; and transmitting, with the circuitry of the source node, the data frame including the soft decision forward error correction data field. In one implementation, the second data comprises automatic protection switching bytes.
US09258214B2	Optimized distributed routing for stretched data center models through updating route advertisements based on changes to address resolution protocol (ARP) tables A method, apparatus and computer program product for performing optimized distributed routing for stretched data center models through updating route advertisements based on changes to Address Resolution Protocol (ARP) Tables is presented. Port members of an Internet Protocol I (IP) interface or Virtual Local Area Network (VLAN) are distinguished into Access Interfaces which only lead to hosts on said subnet and Trunk Interfaces which lead to other redundant routers on said subnet. In the subnet of a network a network route for the subnet is always advertised. A separate host route corresponding to an Internet Protocol (IP) address of each Address Resolution Protocol (ARP) table record that points to an Access Interface is advertised and route advertisements are changed for a host in said subnet for tracked access interfaces.
US09258211B1	Extending VPLS support for CE lag multi-homing Techniques are described for forwarding packets in a VPLS using multi-homing PE routers configured in an “active-active” link topology. As described herein, a PE router receives a packet from a multi-homed VPLS customer site, and processes the packet to determine a portion of a MAC domain to which the packet corresponds. When the packet is determined to correspond to a portion associated with the PE router, the PE router forwards the packet to the destination in accordance with forwarding protocols executing on the PE router. When the packet is determined to correspond to a portion associated with a second PE router, the PE router forwards the packet to the second PE router via a pseudowire that is external to the VPLS domain, and the second PE router forwards the packet to the destination in accordance with forwarding protocols executing on the second PE router.
US09258208B2	Multiple path availability between walkable clusters In one embodiment, a method comprises creating, in a computing network, a hierarchal routing topology for reaching a destination, the hierarchal routing topology comprising a single parent supernode providing reachability to the destination, and a plurality of child supernodes, each child supernode comprising one or more exit network devices each providing a corresponding link to the parent supernode; receiving, in one of the child supernodes, a data packet for delivery to the destination; causing the data packet to traverse along any available data link in the one child supernode independent of any routing topology established by network devices in the one child supernode, until the data packet reaches one of the exit network devices; and the one exit network device forwarding the data packet to the parent supernode, via the corresponding link, for delivery to the destination.
US09258207B2	System and method for detecting active streams using a heartbeat and secure stop mechanism One embodiment of the present invention sets forth a technique for identifying active streaming connections associated with a particular user account. Each active streaming connection transmits heartbeat packets periodically to a server that tracks the receipt of the heartbeat packets. If, for a particular streaming connection, the server stops receiving heartbeat packets, then the server is able to infer that the streaming connection has been terminated.
US09258200B2	Method and apparatus for acquiring quality of experience and method and apparatus for ensuring quality of experience A method for acquiring quality of experience QOE of a telecommunication service is provided. The method includes: acquiring multiple groups of original KQI vectors and a QOE value corresponding to each group of original KQI vectors in the multiple groups of original KQI vectors; analyzing a relationship between the multiple groups of original KQI vectors and QOE values corresponding to the multiple groups of original KQI vectors to establish a function relationship between KQI vectors and QOE values corresponding to the KQI vectors; acquiring a current KQI vector, and applying the function relationship between the KQI vectors and the QOE values corresponding to the KQI vectors to obtain a current QOE value corresponding to the current KQI vector.
US09258196B2	Composite service pre-provisioning Composite service provisioning is provided. A processor receives a first demand value of a first composite service. The processor identifies a sub-service based on the first composite service. The processor pre-provisions a first pool of service instances corresponding to the first composite service, the first pool of service instances having a quantity of service instances based, at least in part, on the first demand value. The processor determines a second demand value of the sub-service based, at least in part, on the quantity of service instances of the first pool of service instances. The processor pre-provisions a second pool of service instances corresponding to the sub-service, the second pool of service instances having a quantity of service instances based, at least in part, on the second demand value. The processor modifies each of the first pool of service instances with placeholder credentials that identify the second pool of service instances.
US09258195B1	Logical topology visualization A graphical user interface (GUI) for visualization of a logical topology of a system can include a plurality of node user interface elements to represent respective components in the system. The GUI can include a plurality of link user interface elements, each connected between an associated pair of the node user interface elements to represent a logical connection between a given component and at least one other component in the system. In response to a user input for a selected node user interface element, at least a portion of the plurality of link user interface elements can be modified to represent the logical connectivity and associated status such as from a perspective of the component represented by the selected node user interface element.
US09258194B2	Method and apparatus to display a transport service between point A and point Z Common techniques for displaying graphical representations of networks that summarize the network by representing the network at high level views, typically as physical network elements. In contrast, an example embodiment of the present invention simultaneously displays graphical representations for a transport service within a network by displaying network elements and connections between network entities to form graphical representations, where the graphical representations show intra-element connections, inter-element connections, and relationships between the network entities to display a transport service from point A to point Z in the network. Thus, a user can visualize a transport service and identify faults in the transport service efficiently and on a substantially real-time basis.
US09258193B2	Method, apparatus, and computer program product for wireless network cluster discovery and concurrency management Embodiments enable discovery of networks in a wireless communications medium. In example embodiments, a method comprises identifying, by an apparatus, a plurality of wireless network clusters by receiving wireless synchronization messages from one or more member devices of each of the plurality of wireless network clusters; calculating, by the apparatus, a cluster grade for each of the plurality of identified wireless network clusters based on information of the received wireless synchronization messages; selecting, by the apparatus, a wireless network cluster from the plurality of identified wireless network clusters, having a highest cluster grade for joining and operating in said wireless network cluster; and ranking, by the apparatus, non-selected wireless network clusters based on predefined criteria applied to information received by the apparatus characterizing the non-selected wireless network clusters.
US09258185B2	Fibre channel over Ethernet support in a trill network environment An example method for Fibre Channel over Ethernet (FCoE) support in a Transparent Interconnection of Lots of Links (TRILL) network environment is provided and includes configuring at least two virtual storage area networks (SANs) in a TRILL network environment, which includes a plurality of leaf switches and spine switches, with each leaf switch being configured as a FCoE forwarder (FCF) enabled to forward frames according to FCoE protocol, and configuring at least an edge broadcast domain and a transport broadcast domain for each virtual SAN at each leaf switch. The edge broadcast domain includes end device links between the leaf switch and one or more end devices, and the transport broadcast domain includes spine links between the leaf switch and the spine switches.
US09258183B2	Method, device, and system for realizing disaster tolerance backup Embodiments of the present invention provide a method, a device, and a system for realizing disaster tolerance backup. The method includes the following steps: a device with an active-standby function determines a current state of the device with the active-standby function, after it is determined that the current state is an active state, the device with the active-standby function issues reachable route information to a connected routing device, where the device with the active-standby function and a device of which a current state is a standby state have a same IP address, the reachable route information includes route information relevant to the IP address, so that the IP address is reachable, and the device with the active-standby function and the device of which the current state is the standby state are backup devices for each other. The present invention can realize remote disaster tolerance backup and avoid service interruption.
US09258177B2	Storing a data stream in a set of storage devices A set of storage devices coordinates selection of dispersed storage error encoding parameters for storing a stream of data and coordinates selection of encoded data storage devices and redundancy encoded data storage devices of the set of storage devices. The encoded data storage devices coordinates storage of a decode threshold amount of encoded data of the stream of data in accordance with the dispersed storage error encoding parameters. The encoded data storage devices send information regarding the decode threshold amount of encoded data to the redundancy encoded data storage devices. The redundancy encoded data storage devices generates redundancy encoded data based on the information regarding the decode threshold amount of encoded data and in accordance with the dispersed storage error encoding parameters. The redundancy encoded data storage devices store the redundancy encoded data to provide error encoded reliable storage of the stream of data.
US09258176B2	Device management method, server and system and mobile equipment A method and system remotely manage a Mobile Equipment (ME). All the different service provider DM servers interconnected with each other to perform data recovery and locking operations in the ME. The DM servers of multiple service providers collaborate and provide interoperable services to the connected mobile equipments.
US09258175B1	Method and system for sharing playlists for content stored within a network A system and method for sharing playlists within a network includes a first storage device having a first playlist comprising first playlist data corresponding to stored content and a second storage device having a second playlist comprising second playlist data corresponding to stored content. The system also includes an aggregation server in communication with the first storage device and the second storage device that receives the first playlist and the second playlist. The aggregation server aggregates the first playlist data and the second playlist data to form an aggregated playlist having aggregated playlist data and forms an index list corresponding to the aggregated playlist. A first aggregation client is in communication with the aggregation server and receives the index list from the aggregation server.
US09258172B2	Calling an unready terminal A voice or video call is to be established between a caller and a callee based on a call flow that involves a call establishment request and a corresponding call acceptance response. A first call establishment request is sent to a called terminal (of the callee) that is unready to accept the call upon receiving this first call establishment request. Once the called terminal is ready to accept the call, instead of the call acceptance response, a reverse call establishment request for the call is received back from the called terminal. The reverse call establishment request is automatically accepted on behalf of the caller on condition that the reverse call establishment request was received back from the called terminal within a certain time limit. If so, the call is accepted by sending an instance of the call acceptance response to called terminal.
US09258171B2	Method and system for an OS virtualization-aware network interface card Aspects of a method and system for an operating system (OS) virtualization-aware network interface card (NIC) are provided. A NIC may provide direct I/O capabilities for each of a plurality of concurrent guest operating systems (GOSs) in a host system. The NIC may comprise a GOS queue for each of the GOSs, where each GOS queue may comprise a transmit (TX) queue, a receive (RX) queue, and an event queue. The NIC may communicate data with a GOS via a corresponding TX queue and RX queue. The NIC may notify a GOS of events such as down link, up link, packet transmission, and packet reception via the corresponding event queue. The NIC may also support unicast, broadcast, and/or multicast communication between GOSs. The NIC may also validate a buffered address when the address corresponds to one of the GOSs operating in the host system.
US09258170B2	Converter/multiplexer for serial bus This disclosure relates to a converter/multiplexer and associated method of use therefor or converting and multiplexing parallel inputs, a modem, a GPS, or even modem information into a single multimaster broadcast serial bus standard for connecting electronic control units, and more specifically, to a multiplexer for transforming analog, digital, frequency, GPS, or modem inputs into a CAN bus data transmittal over LAN and/or PAN and interrelation with a similarly equipped receiving module. Further, the converter/multiplexer is used alone or in a group as part of a larger system for multiplexing and demultiplexing signals for serial bus processing and also for guidance when the converters are cabled by operators using stored configurations.
US09258167B2	Transmitting apparatus, receiving apparatus and control methods thereof A transmitting apparatus is disclosed. The transmitting apparatus includes a preamble symbol inserter configured to insert to a frame a preamble symbol including a signaling information, a guard interval inserter configured to insert guard intervals to both ends of the preamble symbol, and a transmitter configured to transmit a frame including the preamble symbol and the guard intervals, wherein one of the guard intervals which are inserted to both ends of the preamble symbol comprises a pseudo random noise (PN) sequence and another guard interval includes one between the PN sequence and a part of the signaling information. Accordingly, no separate algorithm to estimate size of FFT of the preamble symbol and the guard interval is necessary, robust signal detection and synchronization is enabled by the PN sequence inserted to the guard interval, and compensation of interference which is generated under multipath channel environment deems to be easier.
US09258166B2	Timing synchronization apparatus and method for multi-carrier modulation signals Embodiments of the present invention provide a timing synchronization apparatus and method for multi-carrier modulation signals. Wherein the apparatus includes: a predicting unit configured to denoise delay of symbols received before a currently received symbol, and to predict delay of the currently received symbol or of a symbol received after the currently received symbol according to the denoised symbol delay and a sampling clock frequency offset; and a timing synchronization unit configured to perform timing synchronization according to a predicted value of the delay of the currently received symbol or of the symbol received after the currently received symbol. With the apparatus and method, a signal to noise ratio of multi-carrier modulation signals may be effectively improved, and an effect of a timing error on a communication system may be lowered, thereby improving performance of the communication system.
US09258164B2	Apparatus for transmitting and receiving a signal and method of transmitting and receiving a signal A method for transmitting and receiving a signal and an apparatus for transmitting and receiving a signal are disclosed. The method for receiving the signal includes receiving (S210) the signal in a first frequency band, identifying (S220) a first pilot signal including, a cyclic prefix obtained by frequency-shifting a firstportion of an useful portion of the first pilot signal and a cyclic suffix obtained by frequency-shifting a second portion of the useful portion of the first pilot signal from the received signal, demodulating (S220) a signal frame including a physical layer pipe (PLP) to which a service stream is converted, by an orthogonal frequency division multiplexing (OFDM) scheme, using information set in the first pilot signal, parsing (S230) the signal frame and obtaining the PLP and obtaining (S240) the service stream from the PLP.
US09258163B2	Systems and methods for phase rotating duplicate frames in wireless LAN transmission Methods, devices, and computer program products for optimally phase rotating duplicate frames in wireless LAN transmissions are disclosed. In one aspect, phase rotation sequences may be chosen in order to minimize a peak-to-average power ratio (PAPR) of a frame or data unit, or of a portion of a frame or data unit, where the frame contains a plurality of identical frequency segments, such as a duplicate frame. The method involves selecting a frame bandwidth, and then selecting a phase rotation sequence based upon the frame bandwidth. The method further includes generating a frame including a number of identical 1 MHz frequency segments, and rotating some of those segments relative to other segments, based on the selected phase rotation sequence. The method further includes transmitting the frame.
US09258156B2	Baseband envelope predistorter Digital predistortion circuity is disclosed including digital interface circuitry configured to receive a digital input signal having a signal bandwidth (BW) centered about a frequency f0 and provide a digital transmission signal based on the digital input signal. The digital predistortion circuitry includes circuitry configured to generate a digital correction signal based at least in part on the digital input signal, one or more first signal transmission paths configured to transmit the digital transmission signal, and one or more second signal transmission paths separate from the one or more first signal transmission paths and configured to transmit the correction signal.
US09258154B2	Method and apparatus for low power chip-to-chip communications with constrained ISI ratio An efficient communications apparatus is described for a vector signaling code to transport data and optionally a clocking signal between integrated circuit devices. Methods of designing such apparatus and their associated codes based on a new metric herein called the “ISI Ratio” are described which permit higher communications speed, lower system power consumption, and reduced implementation complexity.
US09258152B2	Systems, circuits and methods for adapting parameters of a linear equalizer in a receiver A receiver is optimized by adapting parameters of a linear equalizer component within the receiver. Data decisions and error decisions are generated. These data decision and error decisions are used to derive an error rate of data by measuring the number of margin hits that occur. A balance value is also calculated from the data decisions and the error decisions. The balance value is used to update parameters of the linear equalizer. The updating of the parameter continues until the number of margin hits has been minimized.
US09258151B2	Receiver in wireless communication system and diversity combining method thereof A diversity combining method applied by a receiver in a wireless communication system is provided, including: acquiring baseband signals of receiving channels corresponding to multiple receiving antennas, and combining multiple acquired baseband signals according to a Maximal-Ratio Combining (MRC) principle at an intermediate frequency and/or within an equalizer and/or after the equalizer. Further a receiver in a wireless communication system is provided. By means of the technical solutions of the disclosure, it is possible to improve a demodulation threshold and the demodulation sensitivity of a microwave system.
US09258149B2	Refinement of channel response calculation A scheme for determining which of a set of taps that can potentially be used to measure a channel impulse response should be used to estimate the channel impulse response.
US09258146B2	Methods and systems for providing secure access to a hosted service via a client application The present invention discloses methods and systems for providing secure user access to services offered by a service provider to a client application over a network. One embodiment includes receiving an application cookie from the client application and populating a service cookie based on information in the application cookie. Information in the service cookie is utilized as a basis for regulating a provision of services to the client application.
US09258145B2	Method and system for distribution of information contents and corresponding computer program product The interfacing of coded media data packets in the transfer from and to a peer-to-peer network envisages that the data packets are included in groups of packets that may have lengths different from one another. Each group of data packets is encapsulated in a group of chunks of given length. The media data is made available in the network as a multiplicity of different descriptions of a multiple-description coding of one and the same media content. The terminals of the peer-to-peer network are configured for accessing selectively the multiplicity of different descriptions of said media contents, combining them with one another, or else accessing one of the different descriptions in substitution for another preserving access to the media contents. The data may be made available as base layer and at least one enhancement layer of one and the same media content.
US09258143B2	Contextual summary of recent communications method and apparatus The present invention provides mechanisms for determining contextual information and including at least some of the determined contextual information in a communication. As an example, a multi-modal communications thumbnail providing context and prior communications summary as an attachment to a communication may be provided. The context and prior communications summary may supplement or replace one or more of a typical communications identifier such as subject, title, and distribution information.
US09258137B2	Bridge apparatus and bridge system with a virtual device for protocol conversion A bridge apparatus is disclosed, the bridge apparatus being connected between a first network and a second network and achieving a communication between equipment connected to the first network and equipment connected to the second network. This apparatus accepts communication from the equipment over the first network to equipment disconnected from the second network, and then, preserves contents of the communication even in the case where the equipment over the second network has been disconnected from the second network for reasons such as electric power cut. In the case where the disconnected equipment has been connected to the second network again, this apparatus transmits the accepted contents of the communication to the reconnected equipment.
US09258134B2	System and method for recording communication interaction over a mobile device A system includes a recording server connected to a private branch exchange (PBX) and/or an interface device, where the connected PBX and/or interface device are each connected to an electronic communication network. The PBX provides at least a first portion of a mobile communication on the electronic communication network to the recording server, and the interface device provides a second portion of the mobile communication to the recording server, wherein the recording server, the PBX, and, if connected to the recording server, the interface device are each assigned to a same organization. A method provides a mobile device and a PBX each registered to an organization, a smart client enforces a policy regarding at least one of incoming mobile communications and outgoing mobile communications on the mobile device, providing a recording server connected to the PBX and simulating an extension of the PBX, conferencing a recording server and recording content.
US09258133B2	Anonymous digital identification Methods and systems for anonymous digital identification are disclosed and may include detecting the presence of a first communication device associated with a first set of content that is distinguishable from an identifier associated with the first communication device, detecting the presence of a second communication device associated with a second set of content that is distinguishable from an identifier associated with the second communication device, and in response to a determination that the devices are geographically proximate to one another, providing matched content to at least one of the first and second devices. The matched content may be based at least in part on the first set of content, the second set of content, and a shared or complementary interest associated with the first and second devices. The interest may have been previously expressed by a user of the first or second devices.
US09258132B2	NETCONF SNMP gateway Various exemplary embodiments relate to a network configuration protocol (NETCONF) and simple network management protocol (SNMP) gateway (NSG). The NSG may include: a first interface configured as a NETCONF server, the first interface configured to connect to a NETCONF client and receive NETCONF messages, at least one NETCONF message identifying a managed object; a buffer configured to store the identified managed object; and a second interface configured to send an SNMP message to an SNMP agent, the SNMP message including the managed object stored in the buffer. Various exemplary embodiments relate to a method performed by a network gateway, the method comprising: receiving a NETCONF message from a NETCONF client; translating the NETCONF message into a SNMP message; and sending the SNMP message to a configurable node.
US09258127B2	System and method for providing cryptographic video verification A method is provided in one example embodiment and includes generating a first document and a second document associated with video data that includes a group of pictures (GOPs). The method also includes hashing a plurality of video frames associated with the video data. Additionally, the method includes appending each of the video frames' respective hash and respective display times to the first document, and appending each of a plurality of I-frames' respective hash and respective display times to the second document. The method further includes communicating the first document and the second document in a reliable manner over a network to a next destination.
US09258126B2	Method for non-repudiation of ad-hoc workflows Described herein is a technique in which the proof that an object (e.g., a document) was processed within a certain task by an entity in a workflow is chain-linked to another proof of the next task. The chain of proofs embedded within the document serves to irrefutably prove that a certain set of tasks were completed before the next task was executed on the object. It is thus difficult, if not impossible, for a user to alter the actions on previous tasks without destroying the chain of proofs.
US09258121B2	Method to manage modification of encryption credentials A method to manage modification of encryption credentials for an encryption server. The encryption server is used to encrypt data uploaded by a user after provision of user encryption credentials associated with an encryption account. The data is encrypted by using a user encryption key stored in a cloud storage server.
US09258117B1	Mutual authentication with symmetric secrets and signatures A client and server negotiate a secure communication channel using a pre-shared key where the server, at the time the negotiation initiates, lacks access to the pre-shared key. The server obtains the pre-shared key from another server that shares a secret with the client. A digital signature or other authentication information generated by the client may be used to enable the other server to determine whether to provide the pre-shared key.
US09258116B2	System and methods for permitting open access to data objects and for securing data within the data objects A system and methods for permitting open access to data objects and for securing data within the data objects is disclosed. According to one embodiment of the present invention, a method for securing a data object is disclosed. According to one embodiment of the present invention, a method for securing a data object is disclosed. The method includes the steps of (1) providing a data object comprising digital data and file format information; (2) embedding independent data into a data object; and (3) scrambling the data object to degrade the data object to a predetermined signal quality level. The steps of embedding and scrambling may be performed until a predetermined condition is met. The method may also include the steps of descrambling the data object to upgrade the data object to a predetermined signal quality level, and decoding the embedded independent data.
US09258115B2	Securing information exchanged via a network A privacy key is provided over a network. An information page is provided over the network. A submission of data that is to be transmitted over the network in response to the information page is detected. A subset of the data is to be encrypted using the privacy key is determined. The privacy key is used to encrypt the subset of the data.
US09258106B2	Communication apparatus, time synchronization system, and time synchronization method A communication apparatus (13) according to the present invention is provided with: a storage unit (131) that stored in advance difference information (1311), which is the difference between first time information (t1) and second time information (t2), said first time information (t1) being received from a synchronization source communication apparatus (11) as a time synchronization source connected to a transmission system (12) wherein transmission delay time is different depending on the direction of transmission, and said second time information (t2) obtained from a time synchronization origin (14) other than the transmission system (12); and a time synchronization means (132) that carries out, when the second time information (t2) cannot be obtained from the time synchronization origin (14), time synchronization with the synchronization source communication apparatus (11) using the difference information (1311) read out from the storage unit (131).
US09258101B2	Method and apparatus for allocating OFDM subcarriers for next codeword pointers or other signaling messages An apparatus for communication. A headend supports a plurality of customer premises equipment (CPEs) in a cable service network. An NCP carrier selector selects at least one orthogonal frequency division multiplex (OFDM) subcarrier taken from a radio frequency (RF) spectrum available for broadcasting signals over the cable service network using a plurality of profiles, wherein each selected OFDM subcarrier comprises a corresponding bit loading for each supported profile that meets or exceeds a minimum number of bits used for delivering next codeword pointer (NCP) messages that is acceptable for each of a plurality of profiles used in the plurality of CPEs for receiving signals over the cable service network. A profile generator generates an NCP profile identifying one or more selected OFDM subcarriers, wherein the NCP profile indicates which OFDM subcarriers within the RF spectrum are usable to carry NCP messages, and an associated bit loading for each selected subcarrier.
US09258093B2	Estimating tone maps in a communication network A network device may be configured to iteratively modify an initial tone map for each communication region of a powerline cycle to minimize the time before application data can be transmitted. A first network device estimates an initial tone map for each communication region based, at least in part, on sounding messages received from a second network device. The first network device determines whether to estimate a modified tone map for the first communication region based on at least one performance measurement associated with a data packet generated using the initial tone map for the first communication region. If so, the second network device retransmits the sounding messages in the first communication region that will be used to modify the initial tone map for the first communication region, and the second network device continues to transmit the data packets using the initial tone maps in the remaining communication regions.
US09258081B2	High dynamic range AMAM predistortion A predistortion function is evaluated with in-phase (I) and quadrature (Q) data words as arguments, while additive I and Q data words are generated in accordance with a comparison of the I and Q data words with a full scale value that generates maximum current in a digital power amplifier. The additive I and Q data words are added to the computed I and Q data words to produce predistorted I and Q data words. The predistorted I and Q data words are provided in a sequence to the digital power amplifier, which generates a corresponding radio-frequency (RF) analog signal.
US09258080B2	Communication terminal and method for use in a communication terminal The present invention describes a method for configuring a measurement report type to be used by a receiver to report a measurement to a transmitter, wherein the measurement is reported to the transmitter in a report signal over a control channel. The method includes selecting a first measurement report type and at least one second measurement report type to be used by the receiver to report the measurement, generating a measurement reporting pattern defining an occurrence of the first measurement report type and the at least one second measurement report type in the report signal transmitted by the receiver to the transmitter over control channel, and notifying the first measurement report type, the at least one second measurement report type, and the generated measurement reporting pattern to the receiver.
US09258076B2	Amortization of expensive optical components A laser system includes an array of lasers that emit light at a number of different, fixed wavelengths. A group of optical transport systems connect to the laser system. Each of the optical transport systems is configured to modulate data signals onto the light from the laser system to create optical signals and transmit the optical signals on one or more optical fibers.
US09258075B2	Communication apparatus and communication method for discrete-fourier-transforming a time domain symbol to a frequency domain signal and mapping the transformed signal on frequency bands Provided is a radio communication device which can reduce ISI caused by destruction of an orthogonal DFT matrix even when an SC-FDMA signal is divided into a plurality of clusters and the clusters are respectively mapped to discontinuous frequency bands. The radio communication device includes a DFT unit (110), a division unit (111), and a mapping unit (112). The DFT unit (110) uses the DFT matrix to execute a DFT process on a symbol sequence in a time region to generate a signal (SC-FDMA signal) of the frequency region. The division unit (111) generates a plurality of clusters by dividing the SC-FDMA signal with a partially orthogonal bandwidth corresponding to the vector length of some of the column vectors constituting the DFT matrix used in the DFT unit (110) and orthogonally intersecting at least partially. The mapping unit (112) maps the clusters to discontinuous frequency bands.
US09258074B2	Wireless communication system A wireless communication system that includes a base station and one or more terminals carries out wireless data communication by use of a first frequency band. The wireless communication system includes a wireless access system that employs a CSMA/CA and/or TDMA/TDD system as the wireless access system of the wireless communication system and a control signal at the first frequency band is periodically broadcasts from the base station, where the control signal includes a control information configured to manage wireless data transmission by the one or more terminals. In addition to the first frequency band, one or more frequency bands different from the first frequency band for the wireless data transmission by the one or more terminals can be allocate by the base station, where the control signal at the first frequency band indicate the location of the one or more frequency bands which can be used.
US09258068B2	RRM measurements for UEs with interference suppression receiver An apparatus and a method are described, in which a plurality of signals is received via plurality of receiver units of a receiver, signal quality and/or power related measurements are performed, and a signal quality and/or power related measurement result is generated based on a combination of signals received by the receiver units.
US09258060B2	Method and apparatus for compensating nonlinear distortions in intensity modulation-direct detection system The embodiments of the present invention provide a method and an apparatus for compensating nonlinear distortions in an intensity modulation-direct detection (IM-DD) system; wherein the method comprises: calculating, according to nonlinear coefficients and differences between values of an input signal at different time, nonlinear distortions of the input signal, so as to eliminate the nonlinearity distortions. By applying the method and the apparatus provided by the embodiments of the present invention, nonlinear cost of the IM-DD system can be effectively reduced, thereby improving the system capacity.
US09258058B2	Signal transmitting apparatus for transmitting information by bright line pattern in image A signal transmitting apparatus is provided that includes a light emitter and a circuit that controls the light emitter change in luminance in frequency to transmit a signal to a receiving apparatus. The receiving apparatus includes a processor and a recording medium having a program, the program causing the processor to execute operations. The operations include obtaining first image data with a first exposure time; setting a second exposure time of the image sensor so that, in an image obtained by capturing a subject by the image sensor, a plurality of bright lines corresponding to the plurality of exposure lines included in the image sensor appear according to a change in luminance of the subject; obtaining a bright line image including the plurality of bright lines; and obtaining information by demodulating data specified by a pattern of the plurality of bright lines.
US09258057B2	Visible light communication system A server is configured to manage second positional information, which shows a location of the lighting device, so that the second positional information is associated with the ID information of the lighting device. The server is configured to determine whether or not the ID information received from the receiving terminal is justifiable based on the second positional information, which corresponds to the ID information received from the receiving terminal, and the first positional information, which is received from the receiving terminal. The server is configured to reply, to the receiving terminal, the service information corresponding to the ID information received from the receiving terminal when determining that the ID information received from the receiving terminal is justifiable. The server is configured not to reply the service information to the receiving terminal when determining that the ID information received from the receiving terminal is not justifiable.
US09258056B2	Methods and apparatus for monitoring and controlling the performance of optical communication systems In some embodiments, an apparatus includes an optical detector that can sample asynchronously an optical signal from an optical component that can be either an optical transmitter or an optical receiver. In such embodiments, the apparatus also includes a processor operatively coupled to the optical detector, where the processor can calculate a metric value of the optical signal without an extinction ratio of the optical signal being measured. The metric value is proportional to the extinction ratio of the optical signal. In such embodiments, the processor can define an error signal based on the metric value of the optical signal and the processor can send the error signal to the optical transmitter such that the optical transmitter modifies an output optical signal.
US09258053B2	Interface module for a unit of an antenna distribution system, and antenna distribution system An interface module for a unit designed to transmit and/or amplify communication signals inside an antenna distribution system includes a first analog interface for forwarding and receiving communication signals from mobile terminals and a second interface for forwarding and receiving communication signals from the antenna distribution system. A signal path forwards the received communication signals between the first and second interfaces. A controllable digital unit in the signal path is configured for digitizing incoming communication signals to digital signals and converting outgoing communication signals to analog signals. The digital unit is configured to evaluate characteristic signal parameters of the digital communication signals and select a subset of signals from the digital communication signals. The controllable digital unit is further configured for forwarding the selected subset of signals.
US09258052B2	Reducing location-dependent interference in distributed antenna systems operating in multiple-input, multiple-output (MIMO) configuration, and related components, systems, and methods Components, systems, and methods for reducing location-based interference in distributed antenna systems operating in multiple-input, multiple-output (MIMO) configuration are disclosed. Interference is defined as issues with received MIMO communications signals that can cause a MIMO algorithm to not be able to solve a channel matrix for MIMO communications signals received by MIMO receivers in client devices. These issues may be caused by lack of spatial (i.e., phase) separation in the received MIMO communications signals. Thus, to provide phase separation of received MIMO communication signals, multiple MIMO transmitters are each configured to employ multiple transmitter antennas, which are each configured to transmit in different polarization states. In certain embodiments, one of the MIMO communications signals is phase shifted in one of the polarization states to provide phase separation between received MIMO communication signals. In other embodiments, multiple transmitter antennas in a MIMO transmitter can be offset to provide phase separation.
US09258051B2	Optimization of transmit signal polarization of an adaptive polarization array (APA) An Adaptive Polarization Array (APA) Algorithm is described for analyzing a wireless signal transmitted by an entity to determine a received polarization of the received wireless signal at a non-coherent receiver. The APA Algorithm determines a transmit polarization state for a transmitter to transmit signals to the entity based in part on the determined received polarization. The transmitter is an arbitrary-polarized transmitter configured to transmit signals at any polarization.
US09258050B2	Transceiving module, antenna, base station and signal receiving method Embodiments of the present invention relate to the field of wireless communication technologies, and provide a transceiving module, an antenna, a base station and a signal receiving method, which are capable of implementing receiving of four dual-band signals and improving uplink network performance of a base station. The transceiving module includes a combining-splitting network, a set of transceiving unit arrays and a signal processing unit that are connected to each other in sequence, and further includes a combining network setting with a connection point connected to another transceiving module, a co-element filter unit separately connected to the combining-splitting network and the combining network, and a pair of receiving units connected to the signal processing unit, where the pair of receiving units in the transceiving module is disposed with a connection point connected to the another transceiving module. The embodiments of the present invention apply to the field of communication.
US09258044B2	Method for feeding back precoding matrix indicator, receive end and transmit end The present disclosure provides a method for feeding back a precoding matrix indicator, a receive end and a transmit end, where the method includes: selecting, by a receive end, a precoding matrix W from a codebook based on a reference signal, where W ∈ [ X 1 ⁡ ( θ 1 ) X 2 ⁡ ( θ 2 , φ n ) ] , the θ1 and the θ2 indicate a phase difference of weighted values for signal transmission between two neighboring antennas in a first antenna group of a transmit end and a phase difference of weighted values for signal transmission between two neighboring antennas in a second antenna group of the transmit end, the φn indicates a phase difference of weighted values for signal transmission between the first antenna group and the second antenna group, where the signal transmission between the first antenna group and the second antenna group is for a same transmission layer, φ n = ⅇ j ⁢ ⁢ 2 ⁢ π ⁢ ⁢ n M , and sending, by the receive end, a precoding matrix indicator PMI to the transmit end.
US09258041B2	Methods and systems for combined cyclic delay diversity and precoding of radio signals In a transmitter or transceiver, signals can be precoded by multiplying symbol vectors with various matrices. For example, symbol vectors can be multiplied with a first column subset of unitary matrix which spreads symbols in the symbol vectors across virtual transmit antennas, a second diagonal matrix which changes a phase of the virtual transmit antennas, and a third precoding matrix which distributes the transmission across the transmit antennas.
US09258039B2	Devices for sending and receiving quantization quality feedback A wireless communication device for sending quantization quality feedback is described. The wireless communication device includes a receiver that receives a signal. The wireless communication device also includes channel estimation circuitry coupled to the receiver. The channel estimation circuitry generates a channel estimate based on the signal. The wireless communication device also includes feedback determination circuitry coupled to the channel estimation circuitry. The feedback determination circuitry generates quantization quality feedback based on the channel estimate. The wireless communication device also includes a transmitter coupled to the feedback determination circuitry. The transmitter transmits the quantization quality feedback.
US09258035B2	Multi-mode communication ingestible event markers and systems, and methods of using the same A device including an integrated circuit, a partial power source, including first and second materials associated with the integrated circuit is disclosed. The first and second materials are configured to provide a voltage potential difference when in contact with a conductive fluid to power up the device. A signal amplification element secured around the integrated circuit relative to the first and second materials is configured to facilitate extension of a current flow path between the first and second materials. A modulator is configured to control conductance between the first and second materials to generate a detectable signal that is partially defined by the current flow extending through the conductive fluid. A communication module is coupled to the partial power source and is configured to communicate with a receiver and an antenna electrically coupled to the communication module, which uses the antenna to communicate with the receiver.
US09258033B2	Docking system and method using near field communication A method and system for configuring a mobile computing device to a docking station using near field communication is disclosed. A mobile computing device may scan an NFC tag integrated with the docking station to gather docking-station information. This docking-station information may be used by the mobile computing device to (i) configure its interface connector to match the docking connector, (ii) establish a communication link with the docking station and/or a host computer connected to the docking station, or (iii) authenticate the docking station to the mobile computing device or vice versa.
US09258026B2	Mobile communication device with human body recognition function A mobile communication device with a human body recognition function includes sensing pad and a sensor. The sensing pad is electrically connected to the sensor. When a target object approaches the mobile communication device, an induction signal is generated between the sensing pad and the target object. The sensor receives the induction signal, and the sensor includes a first sensitivity and a second sensitivity. When no target object approaches the mobile communication device, the sensor is set at the first sensitivity. When the sensor receives the induction signal, the first sensitivity is switched to the second sensitivity. The induction signal is converted into a first signal and the first sensitivity is compared with a default value. If the first signal is greater than the default value, the target object is determined as a human body and a power adjustment unit is adjusted to reduce an output power.
US09258025B2	Antenna structure and wireless communication device using the same Antenna structure includes a feed section, a first radiator, and a second radiator. The first radiator includes a first radiation portion, a ground end, a second radiation portion, the first radiation portion is spaced from the feed end, the ground end is connected between the first radiation portion and the second radiation portion. The second radiator is located below the second radiation portion, and includes a first extending strip, a ground portion, a second extending strip, and a third extending strip. The first extending strip is spaced from the feed end, the second extending strip is connected to the first extending strip and extends along the first extending strip, and the ground portion is connected to a junction of the first extending strip, the second extending strip, and the third extending strip.
US09258023B2	Diversity antenna apparatus of mobile terminal and implementation method thereof Provided is a diversity antenna apparatus of a mobile terminal including a main antenna and a sub-antenna for performing an auxiliary function using a separate sub-antenna processing module, and an implementation method thereof. When the auxiliary function is not performed, a controller of the mobile terminal disconnects the sub-antenna from the sub-antenna processing module and electrically connects the sub-antenna to an RF module through a switch such that the sub-antenna operates as a diversity antenna.
US09258019B2	Communication device An RFID device provided at a transmission and reception circuit processes an RFID carrier signal belonging to a band of about 902 MHz to about 928 MHz or about 865 MHz to about 868 MHz to execute near field radio communication. An RFIC provided at a transmission and reception circuit processes a GSM carrier signal belonging to a band of about 824 MHz to about 894 MHz or about 880 MHz to about 960 MHz to execute mobile communication. A filter circuit provided at the transmission and reception circuit takes the band of about 850 MHz to about 940 MHz where RFID carrier signals appear as the pass band, and takes the band greater than or equal to about 1.2 GHz where a harmonic wave component of GSM carrier signals appears as the attenuation band.
US09258015B2	Decoder with selective iteration scheduling A method includes decoding a code word of an Error Correction Code (ECC), which is representable by a set of check equations, by performing a sequence of iterations, such that each iteration involves processing of multiple variable nodes. For one or more selected variable nodes, a count of the check equations that are defined over one or more variables held respectively by the one or more selected variable nodes is evaluated, and, when the count meets a predefined skipping criterion, the one or more selected variable nodes are omitted from a given iteration in the sequence.
US09258014B2	Using parity data for concurrent data authentication, correction, compression, and encryption A system for software error-correcting code (ECC) protection or compression of original data using ECC data in a first memory is provided. The system includes a processing core for executing computer instructions and accessing data from a main memory, and a non-volatile storage medium for storing the computer instructions. The software ECC protection or compression includes: a data matrix for holding the original data in the first memory; a check matrix for holding the ECC data in the first memory; an encoding matrix for holding first factors in the main memory, the first factors being for encoding the original data into the ECC data; and a thread for executing on the processing core. The thread includes a Galois Field multiplier for multiplying entries of the data matrix by an entry of the encoding matrix, and a sequencer for ordering operations using the Galois Field multiplier to generate the ECC data.
US09258012B2	Compression of state information for data transfer over cloud-based networks Aspects of the present disclosure describe systems and methods for compressing a set of RAM data that may have some portions duplicated in a set of ROM data. The ROM data may be divided into a plurality of data chunks and hashed to obtained unique key values. Then a second hash may be performed on the RAM to see if there are any RAM data chunks that match the ROM data chunks. RAM data chunks with matching key values are replaced with pointers to the location of the data in the ROM. It is emphasized that this abstract is provided to comply with the rules requiring an abstract that will allow a searcher or other reader to quickly ascertain the subject matter of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims.
US09258010B1	Monotonic segmented digital to analog converter In one implementation, a digital analog converter (DAC) is monotonic because the output moves only in the direction of the input and segmented because a more significant portion of the DAC is separated from a less significant portion. The DAC receives an input binary word that includes multiple most significant bits and multiple least significant bits. The DAC decodes the input binary word to an intermediate signal that includes a bit width equal to or greater than a bit width of the binary word. The intermediate signal sets output switches and current source switches. The DAC provides an analog output signal that represents the input binary word.
US09258009B2	AD converter A successive approximation type AD converter includes: a comparator comparing an analog input signal and a DA-converted comparison code; and a control circuit. When an output of the comparator settles before a limit time period has passed since the comparator started a comparison operation, the control circuit updates the comparison code on the basis of the settled output of the comparator. When the limit time period has passed before the output of the comparator settles, the control circuit updates the comparison code not on the basis of the present output of the comparator.
US09258006B2	Semiconductor integrated circuit device A digital-correction-type A/D converter which is a charge sharing type and performing successive approximation is realized in a small area. The A/D converter is configured with an A/D conversion unit which is a charge sharing type and performing successive approximation, a digital correction unit which receives a digital output of the A/D conversion unit and performs digital correction to the digital output, and a holding unit which holds a test signal. A test signal of a common value from the holding unit is inputted into the A/D conversion unit in the first period and the second period. The A/D conversion correction coefficient for the digital correction unit is calculated on the basis of the digital correction result of the digital correction unit in the first period, and the digital correction result of the digital correction unit in the second period.
US09258004B2	Customized data converters A method is provided for supplying a customized data converter fabricated from a universal function die. The method initially fabricates a plurality of universal data converter dice. Each universal data converter die is capable of performing a first plurality of data conversion algorithms. After the dice are made, each universal data converter die is tested to verify the performance of the first plurality of data conversion algorithms. Subsequently, a request is received for a customized data converter capable of performing a first data conversion function, which is selected from among the first plurality of data conversion algorithms. The method then fabricates a customized data converter capable of performing the first data conversion function, using a tested universal data converter die. The unselected data converter functions are disabled (not enabled). A configuration interface may be used to enable the requested data conversion function.
US09258003B2	Electronic system and operating method thereof To compensate for non-linearity of an AD conversion unit and non-linearity of a DA conversion unit in an electronic system including the DA conversion unit and the AD conversion unit, an electronic system includes an A/D conversion unit, a D/A conversion unit, an AD conversion compensation unit, a DA conversion compensation unit, and a calibration unit. During a calibration operation period, the calibration unit sets an operating characteristic of the AD conversion compensation unit and an operating characteristic of the DA conversion compensation unit. The operating characteristic of the AD conversion compensation unit set during the calibration operation period compensates for non-linearity of AD conversion of the A/D conversion unit. The operating characteristic of the DA conversion compensation unit set during the calibration operation period compensates for non-linearity of DA conversion of the D/A conversion unit.
US09258002B2	Interference filter, optical module, and electronic apparatus An optical module for an atomic oscillator using a quantum interference effect includes a first light source unit that emits first resonance light, a gas cell in which an alkali metal atom is sealed, a first light detection unit that detects the intensity of the first resonance light having passed through the gas cell, a determination unit that determines whether or not the first light source unit has failed, a second light source unit that irradiates the gas cell with second resonance light when the determination unit determines that the first light source unit has failed, and a second light detection unit that detects the intensity of the second resonance light having passed through the gas cell, and the optical path length of the first resonance light in the gas cell and the optical path length of the second resonance light in the gas cell are equal to each other.
US09257994B2	Apparatus and system for digitally controlled oscillator Described herein is apparatus and system for a digitally controlled oscillator (DCO). The apparatus comprises a voltage regulator to provide an adjustable power supply; and a DCO to generate an output clock signal, the DCO including one or more delay elements, each delay element operable to change its propagation delay via the adjustable power supply, wherein each delay element comprising an inverter with adjustable drive strength, wherein the inverter is powered by the adjustable power supply. The apparatus further comprises a digital controller to generate a first signal for instructing the voltage regulator to adjust a voltage level of the adjustable power supply.
US09257989B2	Electronic device for implementing digital functions through molecular functional elements An electronic device for implementing digital functions comprising a first and a second electrode regions, separated by an interposing region comprising a dielectric region, is described. The first and the second electrode regions comprise at least one first electrode and at least one second electrode, respectively, configured to generate in the interposing region an electric field depending on an electric potential difference applied thereto. In the interposing region, a molecular layer is comprised, which is composed of a plurality of molecules, each being capable of assuming one or more states, in a controllable manner, depending on a sensed electric field. The dielectric region has a spatially variable dielectric profile, to determine a respective spatially variable field profile of the sensed electric field at the molecular layer.
US09257988B2	Configurable decoder with applications in FPGAs The invention relates to hardware decoders that efficiently expand a small number of input bits to a large number of output bits, while providing considerable flexibility in selecting the output instances. One main area of application of the invention is in pin-limited environments, such as field programmable gates array (FPGA) used with dynamic reconfiguration. The invention includes a mapping unit that is a circuit, possibly in combination with a reconfigurable memory device. The circuit has as input a z-bit source word having a value at each bit position and it outputs an n-bit output word, where n>z, where the value of each bit position of the n-bit output word is based upon the value of a pre-selected hardwired one of the bit positions in the x-bit word, where the said pre-selected hardwired bit positions is selected by a selector address. The invention may include a second reconfigurable memory device that outputs the z-bit source word, based upon an x-bit source address input to the second memory device, where x
US09257982B2	Error resilient packaged components A packaged component may include an interposer and integrated circuit dies mounted on the interposer. At least one of the dies may be a radiation-hardened integrated circuit die, whereas the remaining dies may be non-radiation-hardened dies. If desired, the interposer may be a radiation-hardened interposer whereas the integrated circuit dies may be non-radiation-hardened dies. The radiation-hardened die or the radiation-hardened interposer may include monitor circuitry that is used to test non-radiation-hardened circuitry of the packaged component. Test results may be stored in a database at the monitor circuitry or transmitted to external devices such as a server. The monitor circuitry may be used to reconfigure failed circuitry or may control multiplexing circuitry in the interposer to functionally replace the failed circuitry. If desired, the monitor circuitry may adjust power consumption of non-radiation-hardened circuitry based on the test results.
US09257981B2	Low consumption logic circuit with mechanical switches Adiabatic logic circuit having a first and a second inputs, a first and a second outputs and at least one supply and synchronization input (Phi), with this circuit comprising: a first logic device comprising at least one first microelectromechanical and/or nanoelectromechanical switch, referred to as first mechanical switch, controlled by a first input and connected to the first output and to the supply and synchronization input, a second logic device opposite the first logic device comprising at least one second microelectromechanical or nanoelectromechanical switch, referred to as second mechanical switch, controlled by the second input and connected to the second output and to the supply and synchronization input, first and second devices for partial discharging connected respectively between the first output and the supply and synchronization input and between the second output and the supply and synchronization input.
US09257976B2	Semiconductor device with touch sensor circuit A semiconductor device includes a terminal to which a touch electrode may be coupled; a source voltage drop circuit generating a constant voltage; a phase shift circuit generating a phase shifted clock in response to a first clock and a phase control signal; and a switching circuit to which the constant voltage is supplied. The switching circuit generates drive pulses for applying the constant voltage to the terminal in response to the phase shifted clock. The phase shift circuit varies the phase of the drive pulses based on the phase control signal.
US09257975B2	Semiconductor apparatus for transmitting and receiving signals among a plurality of chips A semiconductor apparatus is provided. The apparatus includes a transmission control unit configured to generate, in response to a received pulse signal having a first pulse width, transmission control signals with a second pulse width larger than the first pulse width and synchronization control signals with a third pulse width larger than the second pulse width. The apparatus also includes a reception control unit configured to generate reception control signals in response to the synchronization control signals.
US09257971B2	Integrated circuit, method for driving the same, and semiconductor device A semiconductor device includes a first latch, a second latch and a transistor whose semiconductor layer contains an oxide semiconductor. An input of the first latch is electrically connected to one of a source and a drain of the transistor, an output of the first latch is electrically connected to an input of the second latch, and an output of the second latch is electrically connected to the other of the source or the drain of the transistor.
US09257968B2	Duty cycle correction circuit and operation method thereof A duty cycle correction circuit includes a clock adjustment unit configured to adjust a duty ratio of an input clock signal in response to a duty control signal and generate an output clock signal, a tracking type setting unit configured to generate an tracking type selection signal for setting a first or second tracking type based on a duty locking state of the output clock signal, and a control signal generation unit configured to generate the duty control signal, into which the first or second tracking type is incorporated, in response to the tracking type selection signal and the output clock signal.
US09257964B2	Low frequency oscillator for burst-mode dimming control for CCFL driver system Oscillator system and method thereof. The oscillator system includes a first voltage-to-current converter configured to receive a first voltage and generate a first current based on at least information associated with the first voltage, and a second voltage-to-current converter configured to receive a second voltage and generate a second current based on at least information associated with the second voltage. Additionally, the oscillator system further includes a current-mode N-bit digital-to-analog converter configured to receive at least the second current and a first clock signal and to generate a third current based on at least information associated with the second current and the first clock signal. N is a first integer. The first clock signal is associated with a first clock frequency corresponding to a first clock period. Moreover, the oscillator system further includes a current comparator coupled to the first voltage-to-current converter and the current-mode N-bit digital-to-analog converter.
US09257963B1	Impedance tuners with rotating probes A new slide-screw impedance tuner structure uses rotating metallic probes. This ensures high resolution in the area where the gap between center conductor and probe is small (high GAMMA), a smooth increase of proximity between probe and center conductor (basic anti-corona form) and the possibility to compensate for the negative phase slope at higher GAMMA, native to traditional slide screw tuners. Additionally the new structure simplifies the tuner mechanics by eliminating the need for a precise vertical axis.
US09257962B2	Elastic wave device An elastic wave device includes a piezoelectric substrate, a pair of reflectors disposed on the piezoelectric substrate along the propagation direction of an elastic wave, and first to fifth comb electrode pairs disposed in this order between the pair of reflectors. Ground comb electrodes of adjacent comb electrode pairs are connected by an even number of connection electrode fingers or by an odd number of connection electrode fingers.
US09257958B2	Methods for noise reduction and quality factor improvement in resonators A low phase noise dual mode resonator and a method of making and using said resonator is disclosed. The dual mode resonator is capable of sustaining two frequency vibration modes simultaneously. The two frequency vibration modes are capable of exhibit non-linear coupling when one is driven at a higher voltage than the other. The dual mode resonator is configured such that the ratio of the two vibration frequency modes is a value that maximizes the non-linear coupling effect. As a result of the non-linear effect, the phase noise on the mode that is not overdriven is reduced.
US09257953B2	Digital equalizing filters with fixed phase response An equalization filter structure for filtering an audio signal within an audio system is disclosed. The equalization filter comprises a first and a second shelving filter each having a fixed first and a fixed second phase response, each of which is determined by a respective cut-off frequency and Q factor which represent the transfer characteristic of the corresponding shelving filter. The first and the second shelving filters are coupled in series and each shelving filter comprises at least one fourth order low-pass filter having a cut-off frequency, a Q factor and a first broadband gain and further at least one fourth order high-pass filter having a second broadband gain and the same cut-off frequency and the same Q factor as the low-pass filter. The fourth order low-pass filter and the fourth order high-pass filter are connected in parallel, such that both filters receive the same input signal and the corresponding filtered signals are summed to form a respective shelving filter output signal. Each fourth order low-pass and high-pass filter is composed of a cascade of two second order low-pass or high-pass filters, respectively, and each second order filter has the same cut-off frequency and Q factor as the corresponding shelving filter.
US09257950B2	Charge preamplifier A charge preamplifier for converting an electric charge generated in a charge source sensor into a voltage signal, including: a phase inverting amplifier including an input related to the charge source sensor, and an output for providing the voltage signal; a storage capacitor connected between the input and the output of the phase inverting amplifier; a reset system connected to the input of the phase inverting amplifier, for providing to the storage capacitor a discharging current as a function of a control signal, and a control element including: a first input connected to the output of the phase inverting amplifier, for withdrawing the voltage signal, a second input subjected to a reference voltage, a set of components configured and arranged to generate a control signal proportional to the deviation between the voltage signal and the reference voltage, the proportionality coefficient being lower than one in a high frequency band, an output connected to the reset system to provide thereto the control signal.
US09257949B2	Linear amplifier The invention relates to a “push-pull” amplifier, comprising an input (12) and an output (14), which includes: a main amplification branch comprising two amplification transistors (18, 20) connected in opposite series between two supply voltages (V+, V−), the amplifier output (14) being connected between the two transistors (18, 20), and a control circuit (22, 24) for each amplification transistor (18, 20) connected to the input (12) to each receive as an input the signal to be amplified. The main amplification branch comprises, between each transistor (18, 20) and the output (14), a member having a nonlinear response (38, 40) and means (30, 32) for introducing at the input of the control circuit (22, 24) of each transistor (18, 20), a nonlinear compensating signal suitable for bringing about the circulation of a minimum current in the member having a nonlinear response (38, 40).
US09257947B2	Semiconductor device A semiconductor device includes a power amplifier for amplifying RF signals in multiple frequency bands, an output matching circuit connected to an output of the power amplifier, a first capacitor connected at a first end to an output of the output matching circuit, multiple output paths, a switch connected to a second end of the first capacitor and directing each of the RF signals to a respective one of the output paths in accordance with frequency band of the each of the RF signals, and multiple second capacitors. Each second capacitor is connected in series to a respective one of the output paths. The switch and either the first capacitor or the second capacitors, or both the first and second capacitors, are integrated as a single monolithic microwave integrated circuit.
US09257945B2	Amplifier apparatus Disclosed is a technique for reducing noise superimposed on an output signal while keeping loop gain constant without increasing the circuit scale and without changing the transfer function of the amplifier apparatus (frequency characteristics of gain and phase). According to the technique, there are included a power-supply voltage control unit 7 for detecting the amplitude level S9 of an input audio signal S1 and outputting power with a voltage value indicated by target set voltage value information Vs corresponding to this amplitude level S9, and a PWM modulation unit 2 including a PWM converter 23 for converting the pulse width of the input audio signal S1 and a correction unit for correcting the signal modulated by the PWM converter 23. The PWM modulation unit 2 corrects the pulse width of a PWM signal S5 modulated by the PWM converter 23 so that the correction unit will cancel out a change in amplification gain of a power amplification unit 4 according to the target set voltage value information Vs.
US09257944B2	Method and arrangement for driving a microphone Disclosed is a differential microphone pre-amplifier circuit (120) for providing an amplified differential signal at a first (A) and a second (B) output terminal of the microphone pre-amplifier (120), including a first voltage controlled current generator (101), a second voltage controlled current generator (102) and a third voltage controlled current generator (103) all being configured to receive, amplify and convert a voltage signal generated by an associated microphone (110) to a current signal output.
US09257943B2	Amplifier circuit and wireless communication equipment Distortion compensation is performed taking into account a memory effect that occurs in a signal path other than an input-to-output path of an amplifier. An amplifier circuit 1 includes an amplifier 2 that amplifies a signal, a variable power supply 3 that varies a power supply voltage of the amplifier 2 in accordance with envelope change, and a distortion compensation section 4 that performs compensation for distortion characteristics. The distortion compensation section 4 performs the distortion compensation, based on an amplifier model which represents a memory effect that occurs on a path from a signal input port 2a of the amplifier 2 to a signal output port 2b thereof, and a memory effect that occurs on a path from a power supply port 2c of the amplifier 2 to the signal output port 2b thereof.
US09257933B2	Variable speed induction motor with single external power supply and control method thereof A single external power supply variable speed induction motor and a control method thereof are disclosed. An induction motor includes: a stator in which coils directly connected to a single-phase or 3-phase or more systematic power supply are wound; a rotor that is supported to be rotatable in the stator; a power conversion device that is attached to the rotor and controls a rotor current without connection of a separate external power supply; and a control circuit that is connected to the power conversion device and controls the power conversion device.
US09257930B2	Controller for multiple-phase rotating machine A controller for a multiple-phase rotating machine includes power converters for supplying alternating current to winding sets of the rotating machine. A pair of each electrical power converter and a corresponding winding set forms a system. The controller further includes a failure detector for detecting a failure in each system. The failure causes a braking current in the rotating machine. The controller further includes a control section for setting a d-axis current and a q-axis current to drive the power converter in each system. When the failure detector detects the failure in any one of the systems, the control section stops the power converter in the failed system and sets the d-axis current in the normal system in such a manner that an electric current in the failed system is reduced.
US09257929B2	Excitation control circuit, control method and electrically excited wind power system having the same The present invention provides an excitation control circuit, a control method using the same and an electrically excited wind power system having the same. The excitation control circuit comprises at least one converter and at least one AC/DC conversion module. The converter is located between an AC electric grid and a wind power generator, so as to convert AC power generated by the wind power generator into AC power corresponding to the AC electric grid. The input side of the AC/DC conversion module is electrically connected between the converter and the wind power generator, and the output side is coupled to an excitation device. The AC/DC conversion module is used to convert the AC power from the wind power generator into a DC voltage, and provides an excitation current for the wind power generator using the DC voltage.
US09257926B2	Method and control system for controlling mobility vehicles A method of controlling at least one motor in a motorized mobility vehicle, wherein the motor is part of a drive circuit for mobilizing the mobility vehicle, the method comprising the steps of: utilizing a stored profile of a motor performance parameter to develop a compensation term for controlling the motor, wherein the stored profile is of a resistance based variable associated with the motor as a function of a further variable and dynamically updating the compensation term when the mobility vehicle is in use.
US09257923B2	Control system for synchronous motor including abnormality detection and diagnosis function A control system includes a current control unit providing, in accordance with the magnetic pole position of a rotor in which permanent magnets are disposed, a first current command to a first excitation phase of a stator winding and providing a second current command to a second excitation phase, a current error calculator calculating a current error which is a difference between a current flowing through the motor during the first period and the first current command or a difference between a current flowing through the motor during the second period and the second current command, and an abnormality detection and diagnosis unit detecting an abnormality based on the speed, the direction of movement and the amount of movement of the motor and the magnitude of the current error.
US09257921B2	Lithography apparatus and method of manufacturing article The present invention provides a lithography apparatus for forming a pattern on a substrate, including a motor configured to drive a table for holding the substrate in accordance with a driving profile, a setting unit configured to set one of a normal mode and a power saving mode as an operation mode of the motor, and a controller configured to change the driving profile when the power saving mode is set, such that an amount of generated heat of the motor caused by driving of the table is smaller than that in the normal mode, and the number of substrates to be processed by the lithography apparatus per unit time is satisfied.
US09257918B2	Vehicle window opening and closing control device A vehicle window opening and closing control device has a driver seat unit that is provided in a driver seat of a vehicle, and a sub-switch that is provided in a seat other than the driver seat. The driver seat unit includes a main switch that operates opening and closing of a first window of the driver seat and a second window of the seat other than the driver seat and a controller that controls a driver seat motor provided in the driver seat and an other-seat motor provided in the seat other than the driver seat to perform manual opening and closing and automatic opening and closing of the first and second windows based on the operation of the main switch. The sub-switch is a switch that performs only the manual opening and closing of the second window using the other-seat motor.
US09257917B1	Efficient power conversion apparatuses, methods and systems The EFFICIENT POWER CONVERSION APPARATUSES, METHODS AND SYSTEMS include circuits for efficiently converting electrical energy to mechanical energy and vice-versa, such as within a multitude of ElectroActive Polymer (EAP) transducers. Embodiment may support a multitude of EAP transducers while also being capable of directing the movement of energy between electrical and mechanical forms in either direction. In another aspect, an efficient mode of transferring mechanical energy is discussed, via one or more strained and paired elastic transducers coupled to a potential energy reservoir.
US09257913B1	LLC converter and loss of inductive mode detection circuit Methods, control apparatus and series resonant or LLC power conversion systems are presented in which a resonant series circuit current is compared with a threshold during a portion of a modulation switching cycle following turn on of a corresponding switching device and one or more indications or remedial actions are undertaken to modify modulation control of a switching circuit in response to a determination that the resonant current is below the threshold to facilitate our promote zero voltage switching or near-zero voltage switching and provide current reversal protection.
US09257911B2	Switching power source device with timing control of synchronous rectifier A synchronous rectification switching power source device accurately determines the timing of the turning off of a synchronous rectifier switching element regardless of the state of the load, and a synchronous rectification period is utilized to the maximum. The switching power source device is configured of a main FET connected to a primary winding of a transformer, a snubber circuit connected to the primary winding, a synchronous rectifier FET connected to a secondary winding of the transformer, a diode connected to the synchronous rectifier FET, a synchronous rectifier FET drain voltage detection unit, an output voltage detection unit, and a drive control unit. The drive control unit accurately determines the timing of the turning off of the synchronous rectifier switching element using a unit that detects the on/off state of the main FET, a variable pulse generator unit, a count value generated by a counter unit, and a threshold value.
US09257910B2	Isolated boost flyback power converter An isolated boost power converter comprises a magnetically permeable multi-legged core (102) comprising first and second outer legs (132; 136) and a center leg (134) having an air gap (138) arranged therein. A boost inductor (Lboost) is wound around the center leg (134) or the first and second outer legs (132; 136) of the magnetically permeable multi-legged core (102). The boost inductor (Lboost) is electrically coupled between an input terminal (104) of the boost converter and a transistor driver (106) to be alternatingly charged and discharged with magnetic energy. A first and second series connected secondary transformer windings (SW1; SW2) with a center-tap (116) arranged in-between are wound around the first and second outer legs (132; 136), respectively, of the magnetically permeable multi-legged core (102). In a first discharge state, the magnetic energy stored in the boost inductor (Lboost) is discharged by directing a discharge current from the boost inductor through a primary transformer winding (PW1; PW2) and in a second discharge state, the magnetic energy stored in the boost inductor (Lboost) is discharged by discharging a magnetic flux through the first and second secondary transformer windings (SW1; SW2).
US09257909B2	Switching power supply with switching frequency controlled to prevent harmonic interference with received radio broadcast A switching power supply determines the order n (a natural number) of the power supply higher harmonic component near the receiving frequency fc of an AM radio broadcast, and judges whether the higher harmonic component of the order n is higher or lower than the receiving frequency fc of the AM radio broadcast. According to the judgment result, the switching power supply determines an upper limit value and a lower limit value for the power supply frequency fs that does not interfere with the receiving frequency fc of the AM radio broadcast from the values of the fundamental power supply frequency fso of the switching operation, the order n of the higher harmonic component, the receiving frequency fc of the AM radio broadcast, and the bandwidth BW of the receiving frequency. The power supply frequency fs is set within the range specified by the upper and lower limit values.
US09257908B2	Systems and methods to auto-adjust zero cross circuits for switching regulators Various embodiments of the present invention provide for an adaptive and accurate zero cross circuit that can operate without directly sensing an inductor current. Certain embodiments allow adjustment of a zero crossing condition while eliminating the need for a blanking time. In certain embodiments this is accomplished by detecting the effects of turning off a switch on a switching node voltage of a buck converter. Some embodiments use a counter to lengthen or shorten the delay time between an inductor crossing a zero value and the effect of the switching event. In one embodiment, the effect of the switching event includes a change in the direction of the switching node voltage from which the direction of a current flowing in the buck converter inductor.
US09257902B2	Device for power conversion using switching element A converter is provided as a power conversion device. The converter includes a switching circuit that performs switching on the basis of switching signals; and a control circuit that changes switching frequency of switching signals in a predetermined pattern with the elapse of time, and repeats the changes in switching frequency in the predetermined pattern at every repetition time. The converter sets the repetition time such that a repetition frequency that is the inverse of the repetition time does not coincide with a frequency band that can be demodulated as sound by a radio that receives radio broadcasts.
US09257901B2	DC power supply circuit In a DC power supply circuit, a first period and a second period are alternately repeated a plurality of times during each half cycle of AC supplied to the DC power supply circuit. The first period is a period during which current flows along a first current path extending from an output terminal at a high-potential side of a rectifier circuit to an output terminal at a low-potential side of the rectifier circuit, via an inductor and a switching element. The second period is a period during which current flows along a second current path extending from the output terminal at the high-potential side of the rectifier circuit to the output terminal at the low-potential side of the rectifier circuit, via the inductor, a charging current supply path, and a capacitor.
US09257900B2	Signal peak detector and detection method, and control IC and method for a PFC converter A control integrated circuit for a power factor correction converter has a pin for detecting an alternating-current information and a direct-current information of an input signal. The control integrated circuit comprises a signal peak detector for detecting a peak value of the input signal to the pin to obtain the direct-current information of the input signal. Since the alternating-current information and the direct-current information of the input signal can be obtained through the same pin, the pin count of the control integrated circuit can be decreased.
US09257895B2	Distributed gap inductor filter apparatus and method of use thereof The invention comprises a high frequency inductor filter apparatus coupled with an inverter yielding high frequency harmonics and/or non-sixty Hertz output. For example, an inductor/converter apparatus is provided that uses a silicon carbide transistor to output power having a carrier frequency, modulated by a fundamental frequency, and a set of harmonic frequencies. A filter, comprising an inductor having a distributed gap core material and optional magnet wires, receives power output from the inverter/converter and processes the power by passing the fundamental frequency while reducing amplitude of the harmonic frequencies.
US09257894B2	Reconfigurable passive filter A passive filter for connection between an AC source and a load, in either three-phases or in a single-phase arrangement. The filter includes, for each phase, a trap circuit having an inductor in series with a capacitor, the trap circuit having at least two terminals. A line reactor is connected between the AC source and the load, the line reactor having at least an input terminal, an output terminal and a tap terminal. A switch selectively connects at least one of the trap circuit terminals to a selected one of the line reactor terminals. The switch is capable of selecting which of the trap circuit terminals to connect to which of the line reactor terminals on the basis of a level of voltage distortion being experienced by the AC source, or on the basis of a calculated level of background voltage total harmonic distortion.
US09257889B2	EPGS architecture with multi-channel synchronous generator and common field regulated exciter A generator system includes a generator having a stationary portion and a rotating portion. The generator includes an exciter field winding disposed on the stationary portion. A first channel includes a first main field winding and a first main field power converter disposed on a rotating portion. The first main field power converter selectively delivers voltage from the exciter winding to the first main field winding. A second channel includes a second main field winding and a second main field power converter disposed on the rotating portion. The second main field power converter selectively delivers voltage from the exciter winding to the second main field winding. A generator control unit is connected to the first channel and the second channel. The generator control unit monitors an output voltage at each of the first channel and the second channel and generates the first and second control signals based on the output voltage.
US09257886B2	Rotating rectifier assembly bus bar A rectifier assembly includes a diode pack. A bus bar includes a first layer electrically connected to the diode pack. The first layer has a first yield strength and a first coefficient of thermal expansion. A second layer of copper is joined to the first layer and includes a second yield strength less than the first yield strength. In one example, the second layer has a second coefficient of thermal expansion within 5% of the first coefficient of thermal expansion.
US09257885B2	Motor A motor is provided with an insert nut 10 that has a knurled part 101 at two places on the surface thereof along an axial direction thereof with projections 103 for whirl stop and slip-off stop formed on the knurled part, and that is embedded between the motor rotor 3 and the magnet assembly 7 to perform fastening between the motor rotor 3 and the magnet assembly 7, and in the insert nut 10, a concave part 104 between the knurled parts 101 is situated at a mounting boundary between the motor rotor 3 and the magnet assembly 7.
US09257884B2	Cooling system and geared motor A cooling system for a geared motor, and a geared motor having electric motors and a gear unit as well as an adapter which is disposed between the electric motors and the gear unit, the electric motors having ducts for a coolant, in particular, a coolant, especially a cooling liquid, being able to flow through each of the motors which, in particular, are liquid-cooled, the streams of coolant emerging from the ducts being brought together and being fed at least proportionally by a first distributor to the gear unit in order to lubricate and cool the toothing parts of the gear unit.
US09257881B2	Rotating electric machine A rotating electric machine includes a stator, a rotor, and a coolant supply passage. Coils are wound on the teeth of the stator. The rotor is disposed coaxially with the stator, and has an outer circumferential surface that faces respective distal end faces of the teeth with a constant gap formed therebetween. The coolant supply passage is disposed inside the rotor, and is configured to eject a coolant from a coolant outlet of the outer circumferential surface of the rotor toward the distal end face of a corresponding one of the teeth so as to supply the coolant to the gap. A discharge groove is formed in the distal end face of the corresponding tooth. The discharge groove is inclined radially outwardly of the stator, from a coolant supply position as an axial position of the stator facing the coolant outlet, toward one edge of the distal end face of the corresponding tooth.
US09257879B2	Motor for environment-friendly vehicle Discloses is a motor for an environmentally friendly vehicle. In particular, the motor includes a stator core including a first coating portion and a second coating portion. The first portion and the second coating portion are adjacent to each other, wound with a coil on an outside thereof and fixedly installed in a motor case and the first coating portion is thinner than the second coating portion. The motor also includes a rotor core configured to move between the first coating portion and the second coating portion depending upon a speed of the motor. A controller is configured to control an operation of an actuator to move the rotor between the first coating portion and the second coating portion to maximize the efficiency of the motor depending upon the speed of the motor.
US09257878B2	Arrangement of conducting bar ends An arrangement includes conducting bar ends connected together and a cap) covering them filled with a putty. The cap is made of a resin containing a high thermal conductivity filler. The putty is a silicone elastomer containing a high thermal conductivity filler.
US09257876B2	Motor integrated to electronic device An electronic device includes a first structural part, a first electronic substrate correspondingly mounted on the first structural part, and a motor. The motor includes a second structural part and a second electronic substrate, a base directly formed on the second structural part, a rotor having at least one load, and a stator. The first and second structural parts are integrally made. The first and second structural parts are combined to a single electronic structural part. The stator has a plurality of winding coils and a driving circuit directly shaped on the second electronic substrate respectively for driving the rotor. The first and second electronic substrates are integrally made. The first and second electronic substrates are combined to a single electronic substrate. Alternatively, the driving circuit is directly shaped in the second electronic substrate.
US09257871B1	Transfer switch A transfer switch has a mounting seat, and a main no-fuse circuit breaker, an auxiliary no-fuse circuit breaker, a switching control assembly, and a transmission mechanism mounted on the mounting seat. The switching control assembly selectively switches the main no-fuse circuit breaker and the auxiliary no-fuse circuit breaker. The transmission mechanism has a main transmission set and an auxiliary transmission set. When the switching control assembly is switched to form electrical conduction of the main no-fuse circuit breaker, the main transmission set drives the auxiliary transmission set via a transmission rod to prevent electrical conduction of the auxiliary no-fuse circuit breaker from forming. Likewise, when the electrical conduction of the auxiliary no-fuse circuit breaker is formed, the electrical conduction of the main no-fuse circuit breaker cannot be formed. Accordingly, safety of the transfer switch can be improved when switching between power sources.
US09257870B2	Battery energy storage, battery energy storage system, method, computer program and computer program product A battery energy storage arranged to be connected to a capacitor link, which is connected in parallel to a power converter. The battery energy storage includes a battery module and a direct current energy source connected in series with a voltage source converter. The voltage source converter is adapted to insert a positive voltage when the voltage of the battery module falls below a first threshold value, and to insert a negative voltage when the voltage of the battery module exceeds a second threshold value. The direct current energy source is adapted to be either charged or discharged during the voltage insertion by the voltage source converter. The disclosure also provides a battery energy storage system including such battery energy storage.
US09257864B2	Input power controller for AC/DC battery charging A control approach of adjusting the input power of a power factor correction (PFC) stage so that the output voltage (DC-link) of the input AC/DC stage to an intermediate DC voltage (DC-Bus voltage) is adjusted based on the amount of power required to charge a high energy battery is disclosed. The present invention controls the input power of the PFC instead of the DC-bus voltage as is common in conventional methods. Therefore, a very fast response compared to the conventional sluggish voltage loop can be achieved. Also, having different DC-bus voltages for different output load conditions allows the DC/DC converter to work with an optimal duty cycle for a whole range of load variations.
US09257858B2	Apparatus and method for controlling a charging circuit in a power over ethernet device A charging circuit and method for charging a power storage device in a power over Ethernet environment are necessary to prevent unnecessary power consumption. Power sourcing equipment continuously supplies power to a connected device after determining that the device is compatible. In order to prevent supply of power after a power storage device attains full charge, a charging circuit may include an interface for supplying electric power; a sensing circuit including a switch in series with a resistor; and a voltage detection circuit. The voltage detection circuit may communicate with the sensing circuit and may output a first signal that turns the switch OFF when the voltage of the power storage device is greater than or equal to a first voltage and may output a second signal that turns the switch ON when the voltage of the power storage device is less than or equal to a second voltage.
US09257856B2	Wireless power transmitter and method of controlling the same A method and a wireless power transmitter for transmitting charging power to a wireless power receiver are provided. The method includes applying the charging power to the wireless power receiver; determining whether a current value of the charging power is greater than a predetermined threshold; and driving the overcurrent protection circuit upon a determination that the current value of the charging power is greater than the predetermined threshold.
US09257854B2	Electronic device and protection circuit thereof An electronic device includes a charging socket, a protection circuit, and a battery. The charging socket includes a charging pin. The charging pin is detachably connected to a charging plug of a power supply device, receives power from the power supply device, and transmits the power to the battery. The protection circuit is connected between the battery and the charging socket, and controls whether the battery is electrically connected to the charging pin. During a process of disconnecting the charging socket from the charging plug, the protection circuit disconnects the battery from the charging pin before the charging pin is disconnected from the charging plug.
US09257853B2	Battery pack The battery pack includes: a charging terminal receiving power from a charger while connected to the charger; a battery connected to the charging terminal and recharged by power from the charger via the charging terminal; a protective circuit performing a protective operation of detecting an overcharge of the battery by using power from the battery while receiving a driving signal, and terminating the protective operation when receiving no driving signal; an activation terminal receiving an activation signal from the charger while connected to the charger; an activation circuit connected to the activation terminal and configured to output the driving signal to the protective circuit while receiving the activation signal from the charger via the activation terminal; and an auxiliary activation circuit connected to the charging terminal and configured to provide the driving signal to the protective circuit while the battery receives power from the charger via the charging terminal.
US09257851B2	Inductive power supply with duty cycle control An inductive power supply that maintains resonance and adjusts duty cycle based on feedback from a secondary circuit. A controller, driver circuit and switching circuit cooperate to generate an AC signal at a selected operating frequency and duty cycle. The AC signal is applied to the tank circuit to create an inductive field for powering the secondary. The secondary communicates feedback about the received power back to the primary controller. The power transfer efficiency may be optimized by maintaining the operating frequency substantially at resonance, and the amount of power transferred may be controlled by adjusting the duty cycle.
US09257850B2	Power transmission apparatus, power reception apparatus and power transmission system A power transmission apparatus including a power transmitting unit which includes an induction unit which receives an electrical energy from an external power source by induction and a magnetic resonance unit which transmits the electrical energy to an external receiving unit by magnetic resonance.
US09257848B2	Method for controlling single-phase DC/AC converters and converter arrangement A method is disclosed for controlling single-phase DC/AC converters, along with a converter arrangement having at least two single-phase DC/AC converters. A controller is provided which can control the at least two single-phase DC/AC converters, and an isolation transformer, wherein outputs of the at least two single-phase DC/AC converters are cascade-connected with each other and an input of the isolation transformer. The controller is configured to control the at least two single-phase DC/AC converters to deliver power from their inputs to their outputs by turns.
US09257847B2	Photovoltaic system with managed output Photovoltaic systems with managed output and methods for managing variability of output from photovoltaic systems are described. A system includes a photovoltaic module configured to receive and convert solar energy to DC power. The system also includes a sensor configured to detect a future change in solar energy to be received by the photovoltaic module. The system further includes a power conditioning unit coupled with the photovoltaic module and the sensor.
US09257842B2	Set-top-box having a built-in master node that provides an external interface for communication and control in a power-line-based residential communication system A set-top-box (STB) provides capability for monitoring and control of power usage and the ability to establish communications. A smart residential service system (SRSS) is provided that uses power line communication (PLC) technology to provide secure in-home LAN communication and also to monitor and provide remote control of connected appliances in the home. An embodiment combines the STB with a master unit (MST) that is used with PLC to meet the requirements of the central device in the SRSS.
US09257840B2	Synchronized PWM randomization for coordinated load management A method of controlling a power consuming device includes receiving a control signal from a power supplying utility. The control signal signals a beginning of a control period. A length of time to operate the power consuming device during the control period is determined and an offset time is identified. A start time for operation of the power consuming device is identified as a function of the beginning of the control period and the offset time. A stop time for operation of the power consuming device is identified as a function of the start time and the determined length of time to operate the power consuming device.
US09257837B2	Power balancing in a multi-phase system Some embodiments of the invention provide a method for balancing the power output to each phase of a set of micro-inverters. The method of some embodiments is performed by a gateway, which receives output messages from a plurality of micro-inverters. The gateway identifies the phase of each micro-inverter and calculates the output of the plurality of micro-inverters to each power line of a multi-phase system. The gateway then sends control signals to the micro-inverters to control the output of each micro-inverter to maintain a balanced aggregate power output to each phase of the power grid.
US09257832B2	Resettable circuit protection system and vehicle with same A resettable circuit protection system for a vehicle includes a power outlet, a resettable circuit protection device, a resettable switch, a control module, and a user interface. The resettable circuit protection device is disposed in power communication with the power outlet, is operable between open and closed positions, and is configured to automatically open in response to an electrical overload condition at the power outlet. The resettable switch is electrically disposed in series with the circuit protection device, and operates between open and closed positions. The control module is disposed in signal communication with the circuit protection device and the switch. The user interface is disposed in signal communication with the control module. When the circuit protection device is open, the control module is responsive to facilitate display of a message at the user interface indicative of the circuit protection device being open, and to facilitate opening of the switch.
US09257831B2	Electrical circuit for cutting off an electric power supply comprising transistors and fuses having redundant logic The invention relates to an electric circuit suitable for cutting off an electric power supply of an electric device, the circuit including an electrical device and a supply voltage source of the electrical device, also having as inputs at least two discrete electrical signals, the values of which condition the cutting off of the electric power supply of the device, the electric circuit being characterized in that same includes: at least two modules for cutting of the electric power supply connected between the voltage source and the electrical device, each module tar cutting off the electric power supply being controlled in accordance with the values of the discrete electrical signals; and at least two modules for comparing discrete electrical signals in parallel, in which at least one of the modules for cutting off the electric power supply is controlled by the outputs of the modules for comparing discrete signals.
US09257828B2	Three-pole lightning arrestor integrated into a residential gateway with lightning impact detector An electronic appliance powered by a power supply unit connected to a mains type electricity network, and for connection to a transmission line having two conductor elements and to a terminal in order to transfer data between the line and the terminal. The appliance has a front-end component connected to the line via an isolating transformer. Also, various additional components are connected to an electrical ground of the appliance. A discharge component is connected to the conductor elements of the line and becomes conductive in the event of a voltage surge due to a lightning strike. This eliminates the surge by establishing a flow of current from the line to electrical ground. A capacitive and/or resistive type divider component is interposed between the discharge component and electrical ground in order to co-operate with the power supply unit and/or one or more additional components to constitute a divider bridge.
US09257827B2	Electrical power system phase and ground protection using an adaptive quadrilateral characteristic A quadrilateral distance module may be used to detect faults in an electrical power system. A resistive coverage of the quadrilateral distance module may be defined by an adaptive resistance blinder. The adaptive resistance blinder may be adapted to certain power system conditions, such as forward load flow and/or reverse load flow. A forward adaptive resistance blinder may be calculated in parallel with a reverse adaptive resistance blinder. The forward adaptive resistance blinder may use a polarizing quantity adapted for forward load flow conditions, and the reverse adaptive resistance blinder may use a polarizing quantity adapted for reverse load flow conditions. Fault detection may be performed by comparing both the forward and reverse adaptive resistance blinders to power system stimulus and detecting a fault when the stimulus satisfy either blinder.
US09257826B2	Cable organizing apparatus A cable organizing apparatus includes a housing member having a base member, one or more posts extended from the base member for winding or engaging with one or more cables, and one or more flaps extended outwardly from the base member and foldable relative to the base member for forming and defining a chamber in the flaps of the housing member and for receiving and accommodating the post within the chamber in the flaps of the housing member, and the flaps are foldable relative to the base member for receiving the post and the cable within the chamber in the flaps of the housing member and for preventing the cable from being disengaged from the post.
US09257820B2	Wire and tube pulling tool A hand tool (10), including: a handle (14) at a handle end (16) of an elongated main body (12); an arcuate shaped contact surface (20) on a base end (22) of the elongated main body opposite the handle end; a support strut (35) extending laterally from the elongated main body; and a connection structure (26) disposed at a distal end of the support strut, between the handle end and the arcuate shaped contact surface. The handle is positioned on a concave side (18) of the arcuate shaped contact surface along a line (50) perpendicular to a tangent (52) of the arcuate shaped contact surface, and the perpendicular line traverses a middle 80% of the arcuate shaped contact surface.
US09257817B2	Spark plug having fusion zone A spark plug (1) includes a center electrode (5), an insulator (2), a metallic shell (3), a ground electrode (27), and a noble metal tip (32) provided on at least one object member of the center electrode and the ground electrode. One end surface of the noble metal tip is joined to the object member via a fusion zone (35). The fusion zone includes a first fusion zone (351) formed through radiation of a laser beam or the like to the boundary between the object member and the one end surface of the noble metal tip along a perimetrical direction of the noble metal tip, and a second fusion zone (352) formed through radiation of the laser beam or the like from the side from which the laser beam or the like has been radiated in forming the first fusion zone, and intersecting with the first fusion zone.
US09257814B1	Temperature-insensitive optical component A hybrid optical source that provides an optical signal having a wavelength is described. This hybrid optical source comprises an optical amplifier (such as a III-V semiconductor optical amplifier) that is butt-coupled or vertically coupled to a silicon-on-insulator (SOI) platform, and which outputs an optical signal. The SOI platform comprises an optical waveguide that conveys the optical signal. A temperature-compensation element included in the optical waveguide compensates for temperature dependence of the indexes of refraction of the optical amplifier and the optical waveguide. In addition, a reflector, included in or in-line with the optical waveguide and after the temperature-compensation element, reflects a portion of the optical signal and transmits another portion of the optical signal that has the wavelength.
US09257809B2	Laser device for exposure apparatus A laser device for an exposure apparatus may include: a MOPA-type or MOPO-type laser device including a seed laser and at least one gas discharge-pumped amplifier stage that receives output light from the seed laser as an input, amplifies the light, and outputs the amplified light; and at least one of a laser gas control device that at least changes the total pressure of a laser gas in said amplifier stage in accordance with requested energy and a laser power source control device that at least changes pump intensity of discharge electrodes in said amplifier stage in accordance with said requested energy, in a case where the energy of laser output light from said laser device is to be changed discontinuously in response to a request from an exposure apparatus.
US09257804B1	Pitch agnostic bus-bar with pitch agnostic blind mate connector The present disclosure provides various bus bar connectors configured to draw power from a bus bar at non-discrete locations. In one aspect, a bus bar connector may include a connector housing having a slot. The slot may be configured to allow the connector housing to grip a bus bar at different locations. First and second electrical contacts may be disposed on opposite sides of the slot. The bus bar connector includes mounting members for securing the connector housing against an enclosure for the bus bar and a spring clip that can be to attach to upper and lower outer surfaces of the connector housing to provide an amount of contact force onto the outer surface of the connector housing. The amount of contact force enables the first and second electrical contacts to securely grip the bus bar.
US09257794B2	High speed bypass cable for use with backplanes A cable bypass assembly is disclosed for use in providing a high speed transmission line for connecting a chip, processor or circuitry mounted on a circuit board to other similar components. The bypass cable assembly has a structure that maintains the geometry of the cable in place from the chip to the connector and then through the connector. The connector includes a plurality of conductive terminals and shield members arranged within an insulative support frame in a manner that approximates the structure of the cable so that the impedance and other electrical characteristics of the cable may be maintained as best is possible through the cable termination and the connector.
US09257793B2	High frequency electrical connector An electrical connector includes a body, two rows of terminals, and a grounding sheet. The body has a base and a tongue extending forwards from the base. The two rows of terminals are disposed in the tongue. At least one row of terminals includes a differential signal terminal pair and a grounding terminal that are disposed neighboring to each other. The grounding sheet is disposed in the tongue and located between the two rows of terminals. The grounding sheet has an open slot located between the differential signal terminal pair and the grounding terminal that are in the same row.
US09257786B2	Electrical connector having elastic element An electrical connector, for mating with a mating plug, includes an insulative housing (1), a number of contacts (2) received in the insulative housing (1), a shell (3) mounted to the insulative housing (1) and an elastic element (4) mounted to the receiving space (100). The insulative housing includes a top wall (12), a lower wall (13), two side walls (14) and a receiving space surrounded by the top wall, the lower wall and the two side walls. The shell (3) comprises a pair of elastic arms (342). The elastic element (4) resists against the elastic arm (342) upon inserting a mating plug to move the pair of least arms outward.
US09257784B2	Power plug with male contact displacement prevention A plug includes male contacts, a core and an envelope. Each of the male contacts includes a stopper. The core includes a first member and a second member. The stoppers are in contact with the first member and the male contacts are in contact with the second member, so that the male contacts are prohibited from being displaced with respect to the core in a first direction along which the male contacts protrude from an end face of the core.
US09257783B2	Hermetic cable adapter A hermetic adapter includes an adapter body, a hermetic seal disposed between the adapter body and a pin, a contact connected to the pin which is disposed within a dielectric, the dielectric being disposed within the adapter body. A sealing ring is press-fit into the adapter body and includes a sharp edge configured to deform a surface of an external adapter to which the hermetic adapter is attachable.
US09257781B2	Tight-sealing embodiment of a plug A plug is provided for producing an electrical connection with a plug module, such as a wiring harness plug for creating an electrical connection with a control device in a motor vehicle. The plug includes a plug body that has a multiplicity of channels for accommodating electrical lines; a mat seal that has a multiplicity of channels for guiding electrical lines accommodated in the channels of the plug body and that is situated on the at least one laterally circumferential radial seal in order to seal the plug; and a pressure plate that has a multiplicity of channels for guiding electrical lines accommodated in the channels of the plug body.
US09257779B2	Intermediate connection electrical connector An intermediate connection electrical connector includes a plurality of blades and a supporting member for supporting the blades arranged in an arrangement direction. The supporting member includes a surrounding wall portion for surrounding the blades and a regulating portion for positioning the blades. The surrounding wall portion includes a side wall portion and an edge wall portion. The side wall portion is at least partially formed of an electromagnetic wave absorbing material. The regulating portion is disposed inside the surrounding wall portion to define a blade accommodating space for accommodating the blades.
US09257776B2	Reduced profile pop-up electrical receptacle assembly A pop-up enclosure system (30) for electronic equipment, includes a receptacle (31) adapted for mounting in a work-surface (15) and containing one or more electrical outlets (32) for connection of equipment thereto, and a bezel (33) supported by the receptacle and adapted for countersinking in said work-surface. A top plate (34) is dimensioned for closing an opening defined by the bezel, and a hinge (35) is mounted at an edge of the top plate and the bezel for hingedly attaching the top plate to the bezel so as to allow rotation of the top plate from a closed position to a fully open position wherein the edge of the top plate abuts an upper surface of the bezel. A releasable resilient opening force (37) is fixed to the receptacle and articulated to the top plate for opening the top plate.
US09257775B2	Charger device for a portable electronic device A device having an electrical plug, such as a charger device, includes a locking member coupled to a carriage that is movable into a housing. Prongs of the device are movable between a retracted position and an extended position along two different travel paths by actuating the prongs or by actuating the carriage.
US09257772B2	Electric connector with a lock to retain a terminal within a housing An electric connector includes an outer housing and an inner housing located within the outer housing. A connector terminal is located within the inner housing. A primary lock retains the connector terminal within the inner housing, and a secondary lock also retains the connector terminal within the inner housing.
US09257771B2	Card connector and electronic apparatus According to one embodiment, a card connector in which a card-shaped storage medium having card terminals is inserted so as to be extracted includes connector terminals configured to contact the card terminals and a terminal protecting member. The terminal protecting member includes a coated portion configured to maintain the connector terminals in a state of being in no contact with the card-shaped storage medium while the card-shaped storage medium is inserted in the card housing module up to contact positions where the card terminals contact the connector terminals.
US09257770B2	Electrical connector with a plurality of contacts recived in a plurality of slots in a plurality of elastic bodies integrally formed with an insulating body An electrical connector for connecting a first electronic element and a second electronic element, includes an insulating body, multiple elastic bodies integrally formed with the insulating body, and multiple conductors. Each of the elastic bodies has a receiving slot, and each conductor is received in a corresponding receiving slot in an inclined manner. The receiving slot has a first urging portion and a second urging portion respectively providing an inclined upward elastic counterforce and an inclined downward elastic counterforce against the conductor, so that the conductor has a large normal force. Multiple stopping portions of the receiving slot and multiple shoulder portions of the conductor are in clearance fit, so that the conductor can be displaced vertically in the receiving slot when receiving a force.
US09257767B2	Connector adaptor to facilitate coupling of a mating card edge with a female card-edge connector A connector adaptor facilitates coupling of a mating card edge with a corresponding female card-edge connector disposed on a circuit board. A gathering bevel at the face of the connector adaptor guides the mating card edge from the face of the connector adaptor to the slot at the connection surface of the female card-edge connector, thereby reducing the risk of damage to the female card-edge connector or the mating card edge during a blind mating attempt. In some embodiments the connector adaptor includes at least one connector tab such that the adaptor can be securely inserted into a cage preceding the slot opening of the female card-edge connector. In another embodiment the connector adaptor overlies the female card-edge connector to protect at least the connection surface of the female card-edge connector and can be fastened to the circuit board with any variety of fastening components.
US09257766B2	Circuit board connecting device A circuit board connecting device comprising a first connector which having a first fixing metallic member attached to a first housing, a second connector having a second fixing metallic member attached to a second housing, and holding means operative to prevent the second housing from being undesirably separated from the first housing under a condition in which the first and second housings are coupled with each other, wherein end portions of a resilient movable holding member provided on the first connector to be movable in a predetermined direction are supported respectively by the first fixing metallic member to engage respectively with portions of the second fixing metallic member for holding the second housing when the second housing is coupled with the first housing, so that the end portions of the resilient movable holding member and the portions of the second fixing metallic member constitute the holding means.
US09257763B2	Hybrid interconnect A connector for connection to terminals of an integrated circuit. The connector consists of a dielectric substrate having a first side and a second side. The connector has wire bond terminals which are attached to the first side of the substrate and configured to receive wire bonds connected to a first set of the terminals of the integrated circuit. The connector also has solder bump terminals, attached to the second side of the substrate so as to be insulated from the wire bond terminals, the solder bump terminals being configured to be coupled via solder balls with a second set of the terminals of the integrated circuit.
US09257762B1	Cable connector for covering a cable A cable connector having an outer tube, a first inner tube, a metal ring, a second inner tube and a grip portion is provided. The outer tube has an upper receiving space and a lower receiving space. The first inner tube is disposed in the upper receiving space from up to down. The metal ring is utilized for covering the first inner tube. The second inner tube is disposed in the lower receiving space from down to up. The grip portion is disposed between the outer tube and the first inner tube.
US09257759B2	Connection structure for ground terminal fitting A connection structure connects a plate-like terminal main body (11) on the ground terminal fitting (10) in surface contact with a grounding member (20) that has female screw holes (41, 42) and a receiving portion (23). A wire connecting portion (12) on the ground terminal fitting (10) is connected to a wire (60). A lock (13) on the terminal main body (11) engages the receiving portion (23) and is on an axis line extension (70) of the wire (60). Mounting holes (151, 152) formed on the terminal main body (11) and aligned with the female screw holes (41, 42) by locking the lock (13) to the receiving portion (23). The ground terminal fitting (10) is connected to the grounding member (20) by screwing bolts (51, 52) inserted through the mounting holes (151, 152) into the female screw holes (41, 42).
US09257758B2	Integrated cord tie and signal conducting device In one embodiment, an integrated extension cable/cord tie device includes male jack, a female jack, and a cable connected to the male jack and female jack. The cable comprises at least one electrical conductor forming an electrical connection between the male jack and the female jack, and a mechanical component that allows the cable to be bent to at least partially around an object upon the application of a first force, to substantially retain its shape after removal of the first force so as to remain at least partially around the object after removal of the first force, and to be unbent upon the application of a second force to be removed from the object. In another embodiment, the mechanical component is integrated directly into a non-detachable cord of a device or a detachable cord usable with one or more devices.
US09257757B2	Crimp terminal, crimp body, and method for manufacturing crimp body In a holding portion of a contact fitting, in a state before crimping of core wires, the thickness of a first distal end portion and the thickness of a second distal end portion are both 70% or less of the thickness of the bottom portion. The thicknesses are both smaller than the diameter of core wires of a lead wire to be crimped. The first distal end portion and the second distal end portion are formed by compression processing. Using the holding portion, a first side portion and a second side portion are curved such that they face the bottom portion, and the plurality of core wires are surrounded and crimped with the bottom portion, the first side portion, and the second side portion.
US09257754B2	Integrated millimeter wave transceiver A millimeter wave transceiver including a plate forming an interposer having its upper surface supporting an interconnection network and having its lower surface intended to be assembled on a printed circuit board by bumps; an integrated circuit chip assembled on the upper surface of the interposer; antennas made of tracks formed on the upper surface of the interposer; and reflectors on the upper surface of the printed circuit board in front of each of the antennas, the effective distance between each antenna and the reflector plate being on the order of one quarter of the wavelength, taking into account the dielectric constants of the interposed materials.
US09257752B2	Tunable projected artificial magnetic mirror and applications thereof A tunable projected artificial magnetic minor (PAMM) includes a plurality of artificial magnetic minor (AMM) cells and a control module. The AMM cells collectively produce an artificial magnetic conductor (AMC) having a geometric shape a distance from a surface of the tunable PAMM for an electromagnetic signal in a given frequency range. The control module is operably coupled to the plurality of AMM cells and provides control information to one or more of the AMM cells to tune at least one of the geometric shape of the AMC and the distance of the AMC from the surface of the tunable PAMM.
US09257749B2	Antenna assembly An antenna assembly includes a feed end, a pair of ground ends, a first antenna, and a second antenna connected to the ground ends. The first antenna is connected to the feed end. The first antenna activates a high frequency band resonance mode. The second antenna is connected to the ground ends, and coupled with the first antenna to activate a low frequency band resonance mode. The feed end and the pair of ground ends are parallel to each other. The feed end and the pair of ground ends are coplanar to form a coplanar-waveguide feed structure.
US09257745B2	Photonic system and method for tunable beamforming of the electric field radiated by a phased array antenna This invention discloses a photonic system to beamform the electric field yield by a phased array antenna. The system function relies on a photonic tunable delay line, which consists on an optical Mach-Zehnder interferometer with a predefined time delay difference between arms. The time delay is tuned by adjusting the coupling ratio between the power applied to each one of the interferometer's delay lines. Three embodiments are proposed, wherein one of them just uses a single delay line and a single monochromatic light source, independently of the quantity of the array elementary antennas.
US09257744B2	Devices, systems, and methods for adjusting probing distances A wireless communication apparatus includes a first antenna, a second antenna, a first receive circuit coupled to the first antenna and a second receive circuit coupled to the second antenna. The first receive circuit is configured to measure one or more downlink performance characteristics of the first antenna and the second receive circuit is configured to measure one or more downlink performance characteristics of the second antenna during at least part of a same time period. The wireless communication apparatus further includes a controller configured to determine a difference between the one or more downlink performance characteristics of the first antenna and the second antenna, and determine a next time to use the second receive circuit to measure the one or more downlink performance characteristics of the second antenna based on the determined difference between the one or more downlink performance characteristics of the first antenna and the second antenna.
US09257743B2	System and method for providing a frequency selective radome A system including a first dielectric layer comprising a solid material configured to form a first layer of a radome, and a second dielectric layer comprising a solid material configured to form a second layer of the radome. The first dielectric layer and the second dielectric layer are spaced apart to provide an inner gap configured as a third layer of the radome. The inner gap is exclusively filled with a gas. The radome is configured to provide for the radome to be frequency selective. A radome and method are also disclosed.
US09257740B2	Watch with bezel antenna configuration A wrist-worn electronic device comprises a housing, a display, a location determining element, a first antenna, and second antenna. The housing includes a lower surface configured to contact a wearer's wrist, an opposing upper surface, and an internal cavity. The display is visible from the upper surface of the housing. The location determining element is configured to process a location signal to determine a current geolocation of the electronic device. The first antenna is positioned on the upper surface of the housing adjacent a perimeter of the display and electrically connected with the second antenna positioned at least partially within the internal cavity. The first antenna and second antenna function in cooperation to receive the location signal from a satellite-based positioning system and communicate the location signal to the location determining element.
US09257739B2	Antenna device and communication apparatus An antenna device includes: a line-shaped antenna conductor with a predetermined length; an actuator member that directly supports the line-shaped antenna or supports the line-shaped antenna via an auxiliary member and is displaceable integrally with the antenna conductor, where the actuator member is displaced to change a position of the antenna conductor in a space; and an attaching member that attaches the actuator member and the antenna member in one longitudinal end of the antenna conductor to a communication apparatus. The actuator member performs displacement control in which one longitudinal end of the antenna conductor serves as a fixed support and the other end thereof serves as a free end to be displaceable depending on the control voltage.
US09257738B2	Mobile terminal, and method for improving radiation performance and specific absorption rate of an antenna of a mobile terminal A method and a mobile terminal of improving radiation performance and Specific Absorption Rate (SAR) of an antenna are provided. The mobile terminal includes a controller for generating a control signal for switching a ground according to a frequency band used by an antenna, and a switch unit for switching a contact point for each frequency band according to the control signal.
US09257732B2	Battery cell assembly A battery cell assembly having a first battery cell and a cooling fin is provided. The first battery cell has a first housing and first and second electrical terminals. The cooling fin is disposed against the first housing. The cooling fin has a substantially rectangular-shaped plate that extends along a longitudinal axis. The substantially rectangular-shaped plate has a plate portion with a first side and a second side. The first side has a first plurality of recessed regions and a first plurality of flat regions. Each recessed region of the first plurality of recessed regions is disposed between two flat regions of the first plurality of flat regions along the longitudinal axis. The first housing of the first battery cell is disposed against the first side such that the first housing contacts the first plurality of flat regions.
US09257731B2	Method for implementing full cycle regeneration of waste lead acid batteries A method for implementing full cycle regeneration of a waste lead acid battery is provided. The method includes the following steps. Step (1): the waste lead acid battery is smashed and separated so as to obtain grid lead, diachylon, plastic and waste electrolyte. Step (2): the obtained diachylon after being dried is positioned into an airtight reactor for desulphurization and deoxidation, wherein lead sulfate and the lead dioxide both in the diachylon react to obtain lead monoxide (PbO) and sulfur trioxide (SO3). Step (3): the obtained lead monoxide is reduced by solid phase electrolysis in a wet way so that the lead monoxide is reduced into sponge lead.
US09257730B2	Heater module A heater module (22L, 22R) of the present invention is provided along a heated surface (13CLa) of an object to be heated (13CL, 13CR). The heater module includes: a plate-like heater body (34) that faces the heated surface of the object to be heated; an L-shaped member (31) including a module main surface (31m) to which the plate-like heater body is provided, and a bent arm portion (31c) bent with respect to the module main surface; and a power source connection terminal (35) provided in the bent arm portion and connected to the plate-like heater body.
US09257729B2	Response to over-current in a battery pack A controller identifies a condition of a hazardous internal short by comparing patterns of series element voltages to the last known balance condition of the series elements. If the loaded or resting voltage of one or more contiguous series elements uniformly drop from the previously known condition by an amount consistent with an over-current condition, an over-current internal short circuit fault is registered. The desired response is to prevent the affected series elements from heating to a hazardous temperature by summoning the maximum heat rejection capability of the system until the short ceases and the affected elements cool, the cooling function is no longer able to operate due to low voltage, or the affected series string has drained all of its energy through the short. Also includes are responses that allow the battery pack to continue to power the cooling system even though it may enter an over-discharged state.
US09257727B2	Assembled battery and battery pack An assembled battery includes a conductive filler, a first cell, a second cell. The first cell includes a flat first electrode tab made of aluminum or an aluminum alloy. The second cell includes a flat second electrode tab made of aluminum or an aluminum alloy. The second electrode tab is electrically connected to the first electrode tab through the conductive filler intervening between the first cell and the second cell and through weld surfaces of the first cell and the second cell which are at least partly welded to each other.
US09257725B2	Separator for lithium cells having porous and cured layers on a non-woven support In an embodiment of the disclosure, a separator utilized in a lithium battery is provided. The separator includes a non-woven polyester support, a porous layer of polyvinylidene fluoride (PVDF) or its derivatives formed on the non-woven polyester support, a layer of UV-curing or thermal-curing polymers formed on top of the porous layer of polyvinylidene fluoride (PVDF) or its derivatives.
US09257718B2	Secondary battery A secondary battery that can avoid reduction in battery capacity over the lapse of charge-discharge cycles and can exhibit high performance is provided. The secondary battery includes a laminated body having a pair of electrodes and an electrolyte layer provided between the pair of electrodes, the electrolyte layer including electrolyte particles, the laminated body having an end portion, and a restrictor provided so as to cover at least the end portion of the laminated body for restricting expansion of the electrolyte layer in the plane direction thereof.
US09257711B2	Integrated carbon capture and chemical production using fuel cells In various aspects, systems and methods are provided for operating a molten carbonate fuel cell, such as a fuel cell assembly, with increased production of syngas or hydrogen while also reducing or minimizing the amount of CO2 exiting the fuel cell in the cathode exhaust stream. This can allow for improved efficiency of syngas production while also generating electrical power.
US09257707B2	Apparatus and method for fuel cell standby An apparatus for placing a fuel cell stack in a standby mode is provided. The apparatus comprises a compressor, a fuel cell stack, a cathode valve and a controller. The compressor is operably coupled to an air induction system for providing a cathode stream. The fuel cell stack provides electrical power to a load in response to the cathode stream. The cathode valve is operably coupled to an outlet of the fuel cell stack for controlling a flow of the cathode stream to the fuel cell stack. The controller is configured to receive a power request amount for the load and to compare the power request amount to a predetermined amount. The controller is further configured to control the compressor to operate at a minimum speed and the cathode valve to close in response to determining that the power request amount is similar to the predetermined amount.
US09257706B2	Composite separator for polymer electrolyte membrane fuel cell and method for manufacturing the same The present invention provides a method for manufacturing a composite separator for a polymer electrolyte membrane fuel cell. The method comprises: preparing a prepreg as a continuous carbon fiber-reinforced composite and a graphite foil; allowing the cut prepreg and graphite foil to pass through a stacking/compression roller to be compressed; allowing the prepreg in which the graphite foil is integrally stacked to be heated and pressed by a hot press such that hydrogen, air, and coolant flow fields are formed or to pass through a hot roller to be formed into a separator; removing unnecessary portions from the heated and pressed separator using a trim cutter; and post-curing the thus formed separator, wherein the graphite foil may be stacked on the prepreg as the continuous carbon fiber-reinforced composite such that a graphite layer is integrally formed with the prepreg.
US09257704B2	Carbon nanotube composite structures and methods of manufacturing the same A current conductor for an electrochemical power device that includes an array of carbon nanotubes (CNT) anchored in a carbon nanotube metal composite layer and a structure that may incorporate nanoscale particles or thin film onto the current conductor is described. Additionally, a process for creating the structure using electrochemical plating of the metal layer onto the CNT array followed by separation of the structure from the substrate is provided. Another process includes creating the structure using co-electrodeposition of the CNT and metal from an electroplating bath using surfactants, physical energy, and a magnetic and/or electric field to orient the CNT and enhance the CNT density in the composite.
US09257701B2	Electrochemical cell The present invention relates to a positive active material for an electrochemical cell including a compound having a nano-shape and represented by the following Formula 1. Lix[Li1-y-zM1yM2z]O2-αDα [Formula 1] wherein, 0.8≦x≦1.1, 0≦y≦0.5, 0≦z≦0.5, and 0≦α≦0.05, M1 and M2 are independently selected from transition elements, and D is selected from the group consisting of O, F, S, P, and combinations thereof. The positive active material of the present invention has high reversible capacity and an excellent cycle life characteristic, and in particular, an excellent cycle life characteristic at a high rate.
US09257699B2	Sulfur cathode hosted in porous organic polymeric matrices A composite material includes a porous organic polymer and an electrochemically active material, wherein the porous organic polymer contains a plurality of pores having a diameter of from about 0.1 nm to about 100 nm, and the electrochemically active material is disposed within the pores.
US09257698B2	Composition, energy storage device, and related process A positive electrode composition is provided. The positive electrode composition includes at least one electroactive metal selected from the group consisting of titanium, vanadium, niobium, molybdenum, nickel, iron, cobalt, chromium, manganese, silver, antimony, cadmium, tin, lead, copper, zinc, and combination thereof, an alkali metal halide, and aluminum, present in an amount of at least 0.5 weight percent, based on the weight of the positive electrode composition. Optionally, an amount of sodium iodide of up to about 1.0 weight percent, based on the weight of the sodium halide in the positive electrode composition, is included. The composition may be included in a positive electrode with a molten electrolyte salt comprising the reaction product of an alkali metal halide and an aluminum halide. An energy storage device including the composition is provided, as well as a method of operating the device.
US09257696B2	Positive electrode mixture slurry for lithium secondary batteries, and positive electrode and lithium secondary battery that use said slurry The invention provides a stable positive-electrode mixture slurry that is not subject to gelation, a positive electrode with abundant flexibility, and a lithium secondary battery with excellent battery characteristics. The slurry comprises a positive-electrode active material, a binder, and an organic solvent, the positive-electrode active material is a lithium-containing complex metal oxide represented by Formula: Lix M1yM21-yO2 (wherein 0.4≦x≦1; 0.3≦y≦1; M1 is at least one selected from Ni or Mn; and M2 is at least one selected from Co, Al, or Fe); and the binder comprises a fluorine-containing polymer represented by Composition Formula: (VDF)m(TFE)n(HFP)l (wherein VDF is a structural unit from vinylidene fluoride; TFE is a structural unit from tetrafluoroethylene; HFP is a structural unit from hexafluoropropylene; and 0.45≦m≦1; 0≦n≦0.5; and 0≦l≦0.1, and m+n+l=1).
US09257695B2	Localized heat treatment of battery component films A battery fabrication method includes forming on a substrate, at least a portion of a battery cell having a plurality of battery component films that include an underlying film with an overlying metal-containing film. A beam incident area of the metal-containing film is locally heated by directing onto the metal-containing film, an energy beam maintained at a fluence of at least about 800 J/cm2. The metal-containing film is heated to a temperature that is at least 100° C. higher than the temperature attained by the underlying film.
US09257689B2	Battery pack A battery pack includes one or more bare cells and an exterior member. Each of the bare cells has a pair of long side surfaces opposite to each other, and short side surfaces that connect the long side surfaces. The exterior member is composed of an adhesive layer provided adjacent to the bare cells while surrounding a portion of the bare cells, and a base material layer provided on the adhesive layer. In the battery pack, the adhesive layer has one or more openings therein, and the opening is provided adjacent to a portion at which the long and short side surfaces of the bare cell come in contact with each other.
US09257688B2	Battery pack having an inner frame and an outer frame A battery pack including a bare cell, the bare cell having a pair of first side portions opposite to each other, a pair of second side portions opposite to each other, and a pair of plane portions opposite to each other, the second side portions and the plane portions being connected to ends of the first side portions; a protection circuit module electrically connected to the bare cell; an inner frame between the bare cell and the protection circuit module, the inner frame accommodating the bare cell and exposing one side portion of the pair of first side portions; and an outer frame, the outer frame accommodating the bare cell, the protection circuit module, and the inner frame and exposing the pair of plane portions.
US09257687B2	Battery assembly A battery assembly includes a plurality of electric cells each having an external terminal at one end thereof, a first cap attached to the one end of each of the electric cells and a first holder attached to the plurality of electric cells and is in contact with the first caps.
US09257686B2	Secondary battery A secondary battery including a case; an electrode assembly and electrolyte accommodated in the case; an electrode terminal electrically connected to the electrode assembly, the electrode terminal including a terminal body; a cap plate sealing the case, the terminal body penetrating through the cap plate; and a seal gasket surrounding a lower portion of the terminal body, wherein the electrode terminal includes a laterally protruding part on a portion of the terminal body protruding outside the case, and the seal gasket is in close contact with a lower end of the protruding part.
US09257685B2	Rechargeable battery A rechargeable battery includes an electrode assembly including a first electrode, a second electrode, and a separator provided between the first electrode and the second electrode; a first current collecting plate electrically connected to the first electrode; a second current collecting plate electrically connected to the second electrode; and a case for receiving the electrode assembly, the first current collecting plate, and the second current collecting plate, wherein the first current collecting plate is electrically connected to an inner wall of the case.
US09257684B2	Battery block and manufacturing method therefor The purpose of the present invention is to provide a battery block that serves as a member that contains a plurality of battery cells, wherein if abnormal heat generation occurs, the resulting heat is evenly, rapidly, and efficiently distributed throughout the entire block, and the portions in which the battery cells are accommodated have high dimensional precision. The present invention provides a battery block that contains the following: a metal case that contains a plurality of pipe-shaped members; and battery cells accommodated, respectively, in said plurality of pipe-shaped members. The pipe-shaped members are joined to each other, forming a single unit, and join parts that join adjacent pipe-shaped members to each other are at least 70% as long as the pipe-shaped members themselves.
US09257681B2	Organic electroluminescent display and method of manufacturing the same In a method of manufacturing an organic electroluminescent display, a substrate, in which a plurality of pixel areas is defined, is prepared, and first electrodes are formed in the pixel areas. Organic light emitting layers are formed on the first electrodes and a second electrode is formed on the organic light emitting layers. Resonant controllers are formed to control a resonant distance between each of the first electrodes and the second electrode. The resonant controllers are formed by providing solutions to at least two pixel areas, which emit lights having different colors, with a same amount in a one-to-one correspondence, and removing a solvent from the solutions. The solutions have different concentrations from each other.
US09257679B2	Manufacturing method for flexible display device A method of manufacturing a flexible display device, the method including depositing a separation layer on a supporting substrate; depositing a display panel on the separation layer; cutting the display panel to have a predetermined shape; cutting the supporting substrate and the separation layer to have a wider area than an area where the display panel, that is cut with the predetermined shape, contacts the supporting substrate and the separate layer; and separating the separate layer and the display panel from each other.
US09257677B2	Organic light emitting diode display having low refraction protrusions An organic light emitting diode display is provided. The organic light emitting diode display includes a flexible substrate, an organic light emitting diode disposed on the flexible substrate, a thin film encapsulator disposed on the organic light emitting diode, a plurality of low refraction protrusions disposed on at least one of a surface of the flexible substrate and the thin film encapsulator, wherein each of the low refraction protrusions is formed having an isosceles trapezoid shape, and a high refraction layer disposed covering the plurality of low refraction protrusions.
US09257667B2	Organic light-emitting display apparatus, method of manufacturing the same, and mask that is used for the manufacturing An organic light-emitting display apparatus includes a substrate including a display area and a peripheral area surrounding the display area, a plurality of pixels being disposed in the display area, a plurality of first electrodes in the display area, a plurality of stripe-shaped second electrodes in the display area, the second electrodes extending in a first direction and being spaced apart from each other in a second direction crossing the first direction, and each of the plurality of the second electrodes having an uneven thickness along a third direction inside the display area, an intermediate layer between corresponding first and second electrodes, the intermediate layer having a light-emitting layer, and a connection wiring in the peripheral area, the connection wiring electrically connecting the plurality of the second electrodes with each other.
US09257666B2	Optoelectronic devices The present invention relates integrated optoelectronic devices comprising light emitting field-effect transistors. We describe an optoelectronic device comprising a light-emitting field effect transistor (LFET) with an organic semiconductor active layer and a waveguide integrated within the channel of the light-emitting field effect transistor, wherein said waveguide comprises a material which has a higher refractive index than said organic semiconductor. We also describe a light-emitting organic field transistor integrated with a ridge or rib waveguide incorporated within the channel of the LFET; and a similar light-emitting organic field effect transistor in which the waveguide incorporates an optical feedback mechanism.
US09257663B2	Organic electroluminescent element and display device An organic electroluminescence device that includes, between an anode 41 and a cathode 42, an organic layer stacked structure 43 that comprises stacked plural emitting layers that emit light of different colors, wherein the organic electroluminescent device comprises, between the emitting layers, at least one intermediate layer that comprises a compound represented by the following formula (1) in which at least one of Ar1, Ar2 and Ar3 is a group represented by the following formula (2):
US09257661B2	Light emitting device In an electroluminescence device, highly efficient light emission is realized without reducing the durability thereof. The electroluminescence device includes electrodes, a plurality of layers deposited between the electrodes, a light emitting region between the plurality of layers, the light emitting region emitting light by application of an electric field between the electrodes. The plurality of layers include a metal thin-film in the vicinity of the light emitting region. The metal thin-film induces plasmon resonance on the surface thereof by the emitted light. Surface modification is provided on at least one of the surfaces of the metal thin-film. The surface modification includes an end group having polarity that makes the work function of the metal thin-film become close to the work function of at least a layer next to the metal thin-film.
US09257659B2	Organometallic complex, and light-emitting element, light-emitting device, electronic device and electronic device using the organometallic complex An object is to provide a novel organometallic complex capable of emitting phosphorescence, an organometallic complex which exhibits deep red emission, and a light-emitting element which provides deep red emission. Provided is an organometallic complex having a structure represented by the following General Formula (G1). In the formula, R1, R2, R3, R4, R5, R6, R7, R8, and R9 represent substituents, and M is a central metal and represents either a Group 9 element or a Group 10 element.
US09257656B2	Organic light-emitting diodes Provided is an organic light-emitting diode including a first electrode, a second electrode, and an organic layer between the first electrode and the second electrode, the organic layer including an emission layer and at least one first material represented by Formula 1 and at least one second material represented by Formula 2.
US09257654B2	Anthracene derivative, light-emitting element, light-emitting device, and electronic appliance Novel anthracene derivatives are provided. Further, a light-emitting element, a light-emitting device, and an electronic appliance each using the novel anthracene derivative are provided. Anthracene derivatives represented by general formulae (G11) and (G21) are provided. The anthracene derivatives represented by the general formulae (G11) and (G21) each emit blue light with high color purity and have a carrier-transporting property. Therefore, each of the anthracene derivatives represented by the general formulae (G11) and (G21) is suitable for use in a light-emitting element, a light-emitting device, and an electronic appliance.
US09257652B2	Photoelectric conversion material, method for producing the same, and organic photovoltaic cell containing the same A photoelectric conversion material, which acts as an electron donor for donating an electron or an electron acceptor for accepting an electron, contains a polymer having at least one structural unit selected from graphenes represented by the following general formulae (1) to (4):
US09257650B2	Method for producing display device A method for producing a display device includes forming a resin film on a substrate, forming a plurality of light emitting elements above the resin film, forming a plurality of first grooves in a surface of the resin film, the plurality of first grooves enclosing the plurality of light emitting elements individually in a multiple-fold manner, cutting the substrate at a position overlapping any one of the plurality of first grooves other than the first groove closest to one of the plurality of light emitting elements, and peeling off the substrate from the resin layer.
US09257647B2	Phase change material switch and method of making the same A phase change material (PCM) switch is disclosed that includes a resistive heater element, and a PCM element proximate the resistive heater element. A thermally conductive electrical insulating barrier layer positioned between the PCM heating element and the resistive heating element, and conductive lines extend from ends of the PCM element and control lines extend from ends of the resistive heater element.
US09257645B2	Memristors having mixed oxide phases A memristor includes a first electrode; a second electrode; and a switching layer interposed between the first electrode and the second electrode, wherein the switching layer includes an electrically semiconducting or nominally insulating and weak ionic switching mixed metal oxide phase for forming at least one switching channel in the switching layer. A method of forming the memristor is also provided.
US09257644B1	3D variable resistance memory device and method of manufacturing the same A variable resistance memory device includes a plurality of cell gate electrodes extending in a first direction, wherein the plurality of cell gate electrodes are stacked in a second direction that is substantially perpendicular to the first direction. A gate insulating layer surrounds each cell gate electrode of the plurality of cell gate electrodes and a cell drain region is formed on two sides of the each cell gate electrode of the plurality of cell gate electrodes. A channel layer extends in the second direction along the stack of the plurality of cell gate electrodes, and a variable resistance layer contacting the channel layer.
US09257641B2	Via structure, memory array structure, three-dimensional resistance memory and method of forming the same Provided is a three-dimensional resistance memory including a stack of layers. The stack of layers is encapsulated in a dielectric layer and is adjacent to at least one opening in the encapsulating dielectric layer. At least one L-shaped variable resistance spacer is disposed on at least a portion of the sidewall of the opening adjacent to the stack of layers. An electrode layer fills the remaining portion of the opening.
US09257639B2	Phase-change memory cells Improved phase-change memory cells are provided for storing information in a plurality of programmable cell states. A phase-change material is located between first and second electrodes for applying a read voltage to the phase-change material to read the programmed cell state. An electrically-conductive component extends from one electrode to the other in contact with the phase-change material. The resistance presented by this component to a cell current produced by the read voltage is less than that of the amorphous phase and greater than that of the crystalline phase of the phase-change material in any of the cell states.
US09257638B2	Method to etch non-volatile metal materials A method for etching a stack with an Ru containing layer disposed below a hardmask and above a magnetic tunnel junction (MTJ) stack with pinned layer is provided. The hardmask is etched with a dry etch. The Ru containing layer is etched, where the etching uses hypochlorite and/or O3 based chemistries. The MTJ stack is etched. The MTJ stack is capped with dielectric materials. The pinned layer is etched following the MTJ capping.
US09257632B2	Physical quantity sensor and process for production thereof A physical quantity sensor (100), which can detect multiple physical quantities simultaneously has flexibility or bendability over the entire body thereof. The sensor (100) has a first electrode layer (2) formed on a substrate (1) and first and second piezoelectric elements (3a, 3b) arranged in parallel on the electrode layer (2). Two additional electrode layers (4a, 4b) are formed on the piezoelectric elements (3a, 3b). The substrate (1), the electrode layer (2), first piezoelectric element (3a), one of the additional electrode layers (4a) and protective layers (5a, 5b, 5c, 5d, 5e) constitute a first physical quantity detection unit (6), and the substrate (1), the first electrode layer (2), the second piezoelectric element (3b) and the other additional electrode layer (4b) (a fourth electrode layer) constitute a second physical quantity detection unit (7).
US09257626B2	Light emitting device package A light emitting device package is disclosed. The light emitting device package includes a package body, a heat radiating member disposed in the package body, a light emitting device disposed on the heat radiating member, a bonding member disposed between the light emitting device and the heat radiating member, and a bonding member fixing layer disposed around the bonding member, wherein the bonding member fixing layer has at least one through region.
US09257622B2	Light-emitting structure A light-emitting structure includes a package substrate and a light emitter disposed on the package substrate. The package substrate includes a carrier substrate and a plurality of metal units disposed on the carrier substrate. A distance between two arbitrary points on a periphery of the metal unit is defined as a peripheral endpoint distance. The light emitter includes a first electrical metal and a second electrical metal that have different electrical polarities and are separate from each other. A shortest distance between the first electrical metal and the second electrical metal is defined as an electrical metal interval. The electrical metal interval between the first electrical metal and the second electrical metal is greater than the longest peripheral endpoint distance of the metal unit.
US09257621B2	Epoxy resin composition and light-emitting device package comprising the same An epoxy resin composition according to an embodiment of the present invention comprises an epoxy resin, 0.05-190 parts by weight, based on 10 parts by weight of the epoxy resin, of a polyester-based curing agent, wherein the epoxy resin comprises a triazine derivative epoxy compound and a siloxane compound containing an alicyclic epoxy group and a siloxane group.
US09257620B1	Package structure of light-emitting diode module and method for manufacturing the same The present invention provides a package structure of LED module and the method for manufacturing the same. The method comprises steps of providing a light-emitting module; disposing a light-pervious member on the light-emitting path of the light-emitting module; and dripping a colloid member on the light-pervious member. The light-pervious member is a transparent structure; and the colloid member forms a transparent structure with a thick center and a thin periphery using the surface tension of colloid material. In the above structure, the light-pervious member and colloid member are used for reducing the total reflection effect in the package.
US09257617B2	Wavelength converted light emitting device Embodiments of the invention include a semiconductor structure including a light emitting layer. The semiconductor structure is attached to a support such that the semiconductor structure and the support are mechanically self-supporting. A wavelength converting material extends over the sides of the semiconductor structure and the support. In some embodiments, a thickness of the wavelength converting material on a side of the semiconductor structure is at least 25% of a thickness of the wavelength converting material over a top of the semiconductor structure.
US09257615B2	Light emitting device package and method of manufacturing the same The present invention relates to a light emitting device package and a method of manufacturing the same. There is provided a light emitting device package including a metal core; an insulating layer formed on the metal core; a metal layer formed on the insulating layer; a first cavity formed by removing parts of the metal layer and the insulating layer to expose a top surface of the metal core; and a light emitting device directly mounted on the top surface of the metal core in the first cavity and further there is provided a method of manufacturing the light emitting device package.
US09257613B2	Semiconductor light emitting device Disclosed is a semiconductor light emitting device. The light emitting device includes a first conductive type semiconductor layer; an active layer on the first conductive type semiconductor layer; and a first electrode pad including a plurality of reflective layers on the first conductive type semiconductor layer.
US09257612B2	Method for producing an optoelectronic semiconductor chip, and optoelectronic semiconductor chip A method for producing an optoelectronic semiconductor chip is specified, comprising the following steps: providing an n-conducting layer (2), arranging a p-conducting layer (4) on the n-conducting layer (2), arranging a metal layer sequence (5) on the p-conducting layer (4), arranging a mask (6) at that side of the metal layer sequence (5) which is remote from the p-conducting layer (4), in places removing the metal layer sequence (5) and uncovering the p-conducting layer (4) using the mask (6), and in places neutralizing or removing the uncovered regions (4a) of the p-conducting layer (4) as far as the n-conducting layer (2) using the mask (6), wherein the metal layer sequence (5) comprises at least one mirror layer (51) and a barrier layer (52), and the mirror layer (51) of the metal layer sequence (5) faces the p-conducting layer (4).
US09257611B2	Radiation emitting or receiving optoelectronic semiconductor chip An optoelectronic semiconductor chip includes a multiplicity of active regions, arranged at a distance from one another, and a reflective layer arranged at an underside of the multiplicity of active regions, wherein at least one of the active regions has a main extension direction, one of the active regions has a core region formed with a first semiconductor material, the active region has an active layer, covering the core region at least in directions transversely with respect to the main extension direction of the active region, the active region has a cover layer formed with a second semiconductor material and covers the active layer at least in directions transversely with respect to the main extension direction of the active region, and the reflective layer reflects electromagnetic radiation generated during operation in the active layer.
US09257609B2	Light-emitting diode chip A light-emitting diode (LED) chip is disclosed. The chip includes a light-emitting diode and an electrode layer on the light-emitting diode. The electrode layer includes a reflective metal layer. The reflective metal layer includes a first composition and a second composition. The first composition includes aluminum or silver, and the second composition includes copper, silicon, tin, platinum, gold or a combination thereof. The weight percentage of the second composition is greater than 0% and less than 20%.
US09257607B2	Red emitting luminescent materials The invention relates to a novel red emitting material of (Ba1—x—y—zSrxCayEuz)2Si5—a−bAlaN8−a−4bOa+4b having an average particle size distribution d50 of >6 μm, with 0.3≦x≦0.9, 0.01≦y≦0.1, 0.005≦z≦0.04, 0≦a≦0.2 and 0≦b≦0.2.
US09257605B2	Nano-structure semiconductor light emitting device A method of manufacturing a light emitting device having a plurality of nano-light emitting structures is provided. The method comprises depositing a first conductivity-type semiconductor material on a substrate to form a base layer. A mask having a plurality of openings is formed on the base layer. The first conductivity-type nitride semiconductor material is deposited in the openings of the mask to form a plurality of nanocores having a main portion bounded by the mask and an exposed tip portion. A current blocking layer is deposited on the tip portion of the nanocores. A portion of the mask is removed to expose the main portion of the nanocore. An active material layer is deposited on the plurality of nanocores. A second conductivity-type nitride semiconductor layer is deposited on the active material layer.
US09257603B2	Light emitting diode A light emitting diode includes a substrate, a first semiconductor layer, an active layer, a second semiconductor layer, a first electrode, and a second electrode. The first semiconductor layer, the active layer, and the second semiconductor layer are orderly stacked on the substrate. The first electrode is electrically connected to the first semiconductor layer. The second electrode electrically is connected to the second semiconductor layer. The first semiconductor layer has a number of three-dimensional nano-structures, and each of the number of three-dimensional nano-structures has a stepped structure.
US09257601B2	Light emitting diodes and substrates A thin layer substrate has a plurality of micron sized electrically conductive whisker components which are arranged in parallel and extending from one surface of the substrate to another surface to provide electrically conductive paths through the substrate. Such a substrate may be usable for micron sized LEDs.
US09257599B2	Semiconductor light emitting device including hole injection layer According to example embodiments, a semiconductor light emitting device includes a first semiconductor layer, a pit enlarging layer on the first semiconductor layer, an active layer on the pit enlarging layer, a hole injection layer, and a second semiconductor layer on the hole injection layer. The first semiconductor layer is doped a first conductive type. An upper surface of the pit enlarging layer and side surfaces of the active layer define pits having sloped surfaces on the dislocations. The pits are reverse pyramidal spaces. The hole injection layer is on a top surface of the active layer and the sloped surfaces of the pits. The second semiconductor layer doped a second conductive type that is different than the first conductive type.
US09257585B2	Methods of hermetically sealing photovoltaic modules using powder consisting essentially of glass In various embodiments, photovoltaic modules are hermetically sealed by providing a first glass sheet, a photovoltaic device disposed on the first glass sheet, and a second glass sheet, a gap being defined between the first and second glass sheets, disposing a glass powder within the gap, and heating the powder to seal the glass sheets.
US09257581B2	Integrated image sensor The present disclosure relates to a back-side illuminated CMOS image sensor (BSI CIS). In some embodiments, the BSI CSI has a semiconductor substrate with a front-side and a back-side. A plurality of photodetectors are located within the front-side of the semiconductor substrate. An implantation region is located within the semiconductor substrate at a position separated from the plurality of photodetectors. The implantation region is disposed below the plurality of photodetectors and has a non-uniform doping concentration along a lateral plane parallel to the back-side of the semiconductor substrate. The non-uniform doping concentration allows for the BSI CSI to achieve a small total thickness variation (TTV) between one or more photodetectors and a back-side of a thinned semiconductor substrate that provides for good device performance.
US09257578B2	Inorganic reaction system for electroconductive paste composition The invention provides an inorganic reaction system for the preparation of electroconductive paste. Particularly, an inorganic reaction system comprises conductive glass. The inorganic reaction system may comprise a silver containing matrix forming composition. The silver containing matrix composition may comprise at least one of silver oxide or silver halide, or both. The invention also provides solar cells manufactured utilizing an electroconductive paste comprising an inorganic reaction system comprising conductive glass, and methods of manufacturing solar cells utilizing an electroconductive paste comprising an inorganic reaction system comprising conductive glass.
US09257575B1	Foil trim approaches for foil-based metallization of solar cells Foil trim approaches for the foil-based metallization of solar cells and the resulting solar cells are described. For example, a method involves attaching a metal foil sheet to a metallized surface of an underlying supported wafer to provide a unified pairing of the metal foil sheet and the wafer. Subsequent to attaching the metal foil sheet, a portion of the metal foil sheet is laser scribed from above to form a groove in the metal foil sheet. Subsequent to laser scribing the metal foil sheet, the unified pairing of the metal foil sheet and the wafer is rotated to provide the metal sheet below the wafer. Subsequent to the rotating, the unified pairing of the metal foil sheet and the wafer is placed on a chuck with the metal sheet below the wafer. The metal foil sheet is torn at least along the groove to trim the metal foil sheet.
US09257568B2	Structure for flash memory cells A flash memory cell structure is provided. A semiconductor structure includes a semiconductor substrate, a floating gate overlying the semiconductor substrate, a word-line adjacent to the floating gate, an erase gate adjacent to a side of the floating gate opposite the word-line, a first sidewall disposed between the floating gate and the word-line, and a second sidewall disposed between the floating gate and the erase gate. The first sidewall has a first characteristic and the second sidewall has a second characteristic. The first characteristic is different from the second characteristic.
US09257561B2	Semiconductor device and manufacturing method thereof To reduce parasitic capacitance between a gate electrode and a source electrode or drain electrode of a dual-gate transistor. A semiconductor device includes a first insulating layer covering a first conductive layer; a first semiconductor layer, second semiconductor layers, and an impurity semiconductor layer sequentially provided over the first insulating layer; a second conductive layer over and at least partially in contact with the impurity semiconductor layer; a second insulating layer over the second conductive layer; a third insulating layer covering the three semiconductor layers, the second conductive layer, and the second insulating layer; and a third conductive layer over the third insulating layer. The third conductive layer overlaps with a portion of the first semiconductor layer, which does not overlap with the second semiconductor layers, and further overlaps with part of the second conductive layer.
US09257556B2	Silicon germanium FinFET formation by Ge condensation A method of forming a semiconductor fin of a FinFET device includes conformally depositing an amorphous or polycrystalline thin film of silicon-germanium (SiGe) on the semiconductor fin. The method also includes oxidizing the amorphous or polycrystalline thin film to diffuse germanium from the amorphous or polycrystalline thin film into the semiconductor fin. Such a method further includes removing an oxidized portion of the amorphous or polycrystalline thin film.
US09257551B2	Semiconductor device and method for manufacturing same An N type well (NW) is formed over a prescribed depth from a main surface of a semiconductor substrate (SUB), and a P type well (PW) and an N type drain region (ND) are formed in the N type well (NW). An N type source region (NS), an N+ type source region (NNS), and a P+ type impurity region (BCR) are formed in the P type well (PW). The N type source region (NS) is formed on a region situated directly below the N+ type source region (NNS), and not on a region situated directly below the P+ type impurity region (BCR), and the P+ type impurity region (BCR) is in direct contact with the P type well (PW).
US09257550B2	Integrated electronic device and method for manufacturing thereof An embodiment of an integrated electronic device formed in a body of semiconductor material, which includes: a substrate of a first semiconductor material, the first semiconductor material having a first bandgap; a first epitaxial region of a second semiconductor material and having a first type of conductivity, which overlies the substrate and defines a first surface, the second semiconductor material having a second bandgap wider than the first bandgap; and a second epitaxial region of the first semiconductor material, which overlies, and is in direct contact with, the first epitaxial region. The first epitaxial region includes a first buffer layer, which overlies the substrate, and a drift layer, which overlies the first buffer layer and defines the first surface, the first buffer layer and the drift layer having different doping levels.
US09257547B2	III-N device structures having a non-insulating substrate Embodiments of the present disclosure includes a III-N device having a substrate layer, a first III-N material layer on one side of the substrate layer, a second III-N material layer on the first III-N material layer, and a barrier layer disposed on another side of the substrate layer, the barrier layer being less electrically conductive than the substrate layer.
US09257544B2	Semiconductor device and fabrication method of semiconductor device A semiconductor device includes semiconductor layers of a first conductivity-type and a second conductivity-type stacked on a silicon carbide semiconductor and having differing impurity concentrations. Trenches disposed penetrating the semiconductor layer of the second conductivity-type form a planar striped pattern; and a gate electrode is disposed therein through a gate insulation film. First and second semiconductor regions respectively of the first and the second conductivity-types have impurity concentrations exceeding that of the semiconductor layer of the second conductivity-type and are selectively disposed therein. The depth of the second semiconductor region exceeds that of the semiconductor layer of the second conductivity-type, but not that of the trenches. The second semiconductor region is arranged at given intervals along the length of the trenches. In the silicon carbide semiconductor below the trench bottoms, a third semiconductor region of the second conductivity-type and having a floating potential is disposed covering the trench bottoms.
US09257539B2	Method for manufacturing transistor and associated device A method for manufacturing a transistor device is provided, comprising providing a plurality of parallel nanowires on a substrate; providing a dummy gate structure over a central portion of the parallel nanowires; epitaxially growing extension portions of a second material, selectively on the parallel nanowires, outside a central portion; providing a filler layer around and on top of the dummy gate structure and the extension portions; removing the dummy gate structure to create a gate trench, exposing the central portion of the parallel nanowires; providing spacer structures on the sidewalls of the gate trench, to define a final gate trench; thinning the parallel nanowires, thereby creating free space in between the nanowires and spacer structures; and selectively growing a quantum well layer on or around the parallel nanowires, at least partially filling the free space, to thereby provide a connection between the quantum well layer and extension portions.
US09257536B2	FinFET with crystalline insulator FinFET structures and methods of formation are disclosed. Fins are formed on a bulk substrate. A crystalline insulator layer is formed on the bulk substrate with the fins sticking out of the epitaxial oxide layer. A gate is formed around the fins protruding from the crystalline insulator layer. An epitaxially grown semiconductor region is formed in the source drain region by merging the fins on the crystalline insulator layer to form a fin merging region.
US09257534B2	Single poly plate low on resistance extended drain metal oxide semiconductor device A semiconductor device, in particular, an extended drain metal oxide semiconductor (ED-MOS) device, defined by a doped shallow drain implant in a drift region. For example, an extend drain n-channel metal oxide semiconductor (ED-NMOS) device is defined by an n doped shallow drain (NDD) implant in the drift region. The device is also characterized by conductive layer separated from a substrate in part by a thin oxide layer and in another part by a thick/thin oxide layer. A method of fabricating a semiconductor device, in particular an ED-NMOS device, having a doped shallow drain implant of a drift region is also provided. A method is also provided for fabricating conductive layer disposed in part across a thin oxide layer and in another part across a thick/thin oxide layer.
US09257528B2	Graphene electronic device and method of fabricating the same A graphene electronic device includes a graphene channel layer on a substrate, a source electrode on an end portion of the graphene channel layer and a drain electrode on another end portion of the graphene channel layer, a gate oxide on the graphene channel layer and between the source electrode and the drain electrode, and a gate electrode on the gate oxide. The gate oxide has substantially the same shape as the graphene channel layer between the source electrode and the drain electrode.
US09257526B2	Method for manufacturing a vertical bipolar transistor compatible with CMOS manufacturing methods The present disclosure relates to a method for manufacturing a bipolar transistor. The method forms a trench to isolate a first region from a second region in a semiconductor wafer, and to isolate these regions from the rest of the wafer. The method forms first P-doped well in the second region and produces a collector region of second and third wells by a P doping in the first region. The second well is in contact with the first well below the trench. The method also produces an N-doped base well on the collector region and, at the wafer surface, and forms a CMOS transistor gate on the first region and delimiting a third region and a fourth region. The method also forms a P+-doped collector contact region in the first well, forms a P+ doped emitter region in the third region, and forms an N+-doped base contact region in the fourth region.
US09257521B2	Semiconductor device A semiconductor device includes a semiconductor layer made of first conductivity type SiC; a second conductivity type well region formed on the semiconductor layer and having a channel region; a first conductivity type source region formed on the well region and including a first region adjacent to the well region and a second region adjacent to the first region; a gate insulating film formed on the semiconductor layer and having a first portion that contacts the first region; a second portion that contacts the well region and that has a thickness that is the same as that of the first portion; and a third portion that contacts the second region and that has a thickness that is greater than that of the first portion; and a gate electrode formed on the gate insulating film and opposed to the channel region where a channel is formed through the gate insulating film.
US09257520B2	Semiconductor devices including a stressor in a recess and methods of forming the same Semiconductor devices including a stressor in a recess and methods of forming the semiconductor devices are provided. The methods may include forming a trench in an active region and the trench may include a notched portion of the active region. The methods may also include forming an embedded stressor in the trench. The embedded stressor may include a lower semiconductor layer and an upper semiconductor layer, which has a width narrower than a width of the lower semiconductor layer. A side of the upper semiconductor layer may not be aligned with a side of the lower semiconductor layer and an uppermost surface of the upper semiconductor layer may be higher than an uppermost surface of the active region.
US09257517B2	Vertical DMOS-field effect transistor A vertical diffused metal oxide semiconductor (DMOS) field-effect transistors (FET) comprises a substrate of a first conductivity type forming a drain region; an epitaxial layer of the first conductivity type on said substrate; first and second base regions of the second conductivity type within said epitaxial layer, spaced apart by a predefined distance; first and second source regions of a first conductivity type arranged in said first and second base regions, respectively, wherein said first and second base region is operable to form first and second lateral channels between said source region and said epitaxial layer; a gate structure insulated from said epitaxial layer by an insulation layer and arranged above the region between the first and second base regions and wherein the gate structure comprises first and second gate regions, each gate region only covering the first and second channel, respectively within said first and second base region.
US09257515B2	Split gate flash cell semiconductor device A split gate flash cell device with floating gate transistors is provided. Each floating gate transistor is formed by providing a floating gate transistor substructure including an oxide disposed over a polysilicon gate disposed over a gate oxide disposed on a portion of a common source. Nitride spacers are formed along sidewalls of the floating gate transistor substructure and cover portions of the gate oxide that terminate at the sidewalls. An isotropic oxide etch is performed with the nitride spacers intact. The isotropic etch laterally recedes opposed edges of the oxide inwardly such that a width of the oxide is less than a width of the polysilicon gate. An inter-gate dielectric is formed over the floating gate transistor substructure and control gates are formed over the inter-gate dielectric to form the floating gate transistors.
US09257514B2	Semiconductor device with plural electrodes formed on substrate A semiconductor device includes: a first electrode; a second electrode; an interlayer insulating film made of a porous insulating material and formed above the first electrode and the second electrode; and connection parts electrically connected to the first electrode and the second electrode respectively, wherein a cavity is formed between the interlayer insulating film and a surface of the first electrode, a surface of the second electrode, and parts of surfaces of the connection parts.
US09257511B2	Silicon carbide device and a method for forming a silicon carbide device A silicon carbide device includes a silicon carbide substrate, an inorganic passivation layer structure and a molding material layer. The inorganic passivation layer structure laterally covers at least partly a main surface of the silicon carbide substrate and the molding material layer is arranged adjacent to the inorganic passivation layer structure.
US09257508B2	Transistors and methods of manufacturing the same Transistors and methods of manufacturing the same may include a gate on a substrate, a channel layer having a three-dimensional (3D) channel region covering at least a portion of a gate, a source electrode over a first region of the channel layer, and a drain electrode over a second region of the channel layer.
US09257505B2	Structures and formation methods of finFET device A semiconductor device includes a semiconductor substrate and an isolation structure over the semiconductor substrate. The semiconductor device also includes a first epitaxial fin and a second epitaxial fin over the semiconductor substrate, and the first epitaxial fin and the second epitaxial fin protrude from the isolation structure. The semiconductor device further includes a gate stack over and traversing the first epitaxial fin and the second epitaxial fin. In addition, the semiconductor device includes a recess extending from a top surface of the isolation structure. The recess is between the first epitaxial fin and the second epitaxial fin.
US09257503B2	Superjunction semiconductor device and method for producing thereof A method of forming a superjunction device includes forming at least one trench in a first surface of a first semiconductor layer of a first doping type, and a semiconductor mesa region adjoining the at least one trench. A second semiconductor layer is formed at least on sidewalls and a bottom of the at least one trench. The second semiconductor layer is etched by filling the at least one trench with an etchant, and applying a voltage between the first semiconductor layer and the etchant such that a space charge region expands in the second semiconductor layer and in the first semiconductor layer. The voltage is adjusted such that there is a first region in the semiconductor mesa region that is free of the space charge region when the voltage is applied.
US09257502B2	Level shift power semiconductor device In one general aspect, a power semiconductor device can include a semiconductor substrate of a first conductivity type, and a semiconductor layer of a second conductivity type disposed on the semiconductor substrate. The semiconductor layer can include a high voltage unit, a low voltage unit disposed around the high voltage unit, and a level shift unit disposed between the high voltage unit and the low voltage unit. The power semiconductor device can include a first isolation region of the first conductivity type disposed between the high voltage unit and the level shift unit, and a second isolation region of the first conductivity type disposed between the low voltage unit and the level shift unit where the first isolation region and the second isolation region each are vertically aligned in the semiconductor layer and each extends to at least the semiconductor substrate.
US09257500B2	Vertical gallium nitride power device with breakdown voltage control A method for fabricating a vertical GaN power device includes providing a first GaN material having a first conductivity type and forming a second GaN material having a second conductivity type and coupled to the first GaN material to create a junction. The method further includes implanting ions through the second GaN material and into a first portion of the first GaN material to increase a doping concentration of the first conductivity type. The first portion of the junction is characterized by a reduced breakdown voltage relative to a breakdown voltage of a second portion of the junction.
US09257495B2	Organic light emitting diode display and method for manufacturing the same An organic light emitting diode (OLED) display and a method for manufacturing the same are described. An exemplary embodiment provides an OLED display including: a substrate including a plurality of pixel areas; a light emitting unit including an organic light emitting diode and a plurality of first thin film transistors, the light emitting unit being formed in each of the plurality of pixel areas; and a sensor unit including a photosensor and a plurality of second thin film transistors, the sensor unit being formed in at least some of the plurality of pixel areas. Each of the plurality of first thin film transistors and the plurality of second thin film transistors includes an oxide semiconductor layer, and the photosensor includes an oxide photoelectric conversion layer that are made of a same material on a same layer as the oxide semiconductor layer.
US09257489B2	Electronic appliance and light-emitting device An EL element having a novel structure is provided, which is suitable for AC drive. A light-emitting element of the invention is provided with material layers (material layers each having approximately symmetric I-V characteristics with respect to the zero point in a graph having the abscissa axis showing current values and the ordinate axis showing voltage values) between a first electrode and a layer including an organic compound and between the layer including the organic compound and a second electrode respectively. Specifically, each of the material layers is a composite layer including a metal oxide and an organic compound.
US09257488B2	Organic light emitting diode display panel and portable display including the same An organic light emitting display panel that includes a substrate, a plurality of pixels disposed on the substrate and forming a matrix, and an auxiliary organic light emitting element disposed at a distance from the pixel.
US09257485B2	Memory device and apparatus including the same A memory device may include a first electrode and a second electrode spaced apart from the first electrode. The memory device may further include a memory element disposed between the first electrode and the second electrode and a switching element disposed between the first electrode and the second electrode. The switching element may be configured to control signal access to the memory element. The memory device may further include a barrier layer disposed between the memory element and the switching element, the barrier layer including an insulation material.
US09257479B2	Solid state image pickup device and manufacturing method therefor A method of manufacturing an active pixel sensor having a plurality of pixels, each of the pixels having a photodiode formed by a part of a first semiconductor region of a first conductive type and a second semiconductor region of a second conductive type, and a transfer transistor for transferring a charge carrier from the photodiode, includes the steps of preparing a substrate on which the first semiconductor region of the first conductive type is formed, forming a mask to form the second semiconductor region on the substrate, forming the second semiconductor region using the mask, and forming a gate of the transferring transistor after forming the second semiconductor region. The gate of the transferring transistor overlaps the second semiconductor region in a planar view.
US09257478B2	Spatially resolved spectral-imaging device A spatially resolved spectral device comprising a dispersive array to receive an incident light comprising a principal ray. The dispersive array comprising a plurality of dichroic layers, each of the plurality of dichroic layers disposed in a path of a direction of the principal ray. Each of the plurality of dichroic layers configured to at least one of reflect or transmit a different wavelength range of the incident light. The device further comprising a detection array operatively coupled with the dispersive array. The detection array comprising a photosensitive component including a plurality of detection pixels, each of the plurality of detection pixels having a light-receiving surface disposed parallel to the direction of the principal ray to detect a respective one of the different wavelength ranges of incident light reflected from a corresponding one of the plurality of dichroic layers.
US09257475B2	Image sensor An apparatus includes a three dimensional array of light receptors disposed within a substrate having a light receiving surface, where light receptors disposed closer to the light receiving surface are responsive to light having shorter wavelengths than light receptors disposed further from the light receiving surface, and where each light receptor is configured to output a binary value and to change state between an off-state and an on-state by the absorption of at least one photon.
US09257472B2	Solid-state imaging device, camera, and design method for solid-state imaging device A solid-state imaging device including two semiconductor substrates arranged in layers is provided. Each semiconductor substrate has a semiconductor region in which a circuit constituting a part of a pixel array is formed. The circuits in the two semiconductor substrates are electrically connected to each other. Each semiconductor substrate includes one or more contact plugs for supplying a voltage to the semiconductor region. The number of the contact plugs of one semiconductor substrate in the pixel array is different from the number of the contact plugs of the other semiconductor substrate in the pixel array.
US09257465B2	Solid-state imaging device and electronic apparatus with increased length of amplifying portion A solid-state imaging device includes pixels each of which has a photoelectric conversion portion that senses light and converts the sensed light into a charge; and an amplifying portion which is shared by a predetermined number of the pixels, amplifies the generated charge in the photoelectric conversion portion, and outputs a level of signal corresponding to the charge, wherein the a predetermined number of the pixels which share the amplifying portion are arranged in a first direction extending along a signal line via which the amplifying portion outputs the signal, and wherein a length of an area where the amplifying portion is formed along a second direction substantially intersecting the first direction is set to be equal to or more than a length of one pixel and to be less than a length of two pixels in the second direction.
US09257464B2	Solid-state image device, method of fabricating the same, and electronic apparatus There is provided a solid-state image device, including a semiconductor substrate, a circuit formed on a first face of the semiconductor substrate, a grid pattern provided on a second face of the semiconductor substrate, and a semiconductor layer formed within the grid pattern and having a shape whose cross-sectional surface area in a plane parallel to a surface of the semiconductor substrate decreases with increasing distance from the semiconductor substrate.
US09257460B2	Image capturing apparatus and control method therefor An image capturing apparatus having pixels is provided. Each pixel includes a photoelectric conversion unit including a charge accumulation region, an output unit configured to output a signal based on a potential of a node electrically connected to the charge accumulation region, and a connection unit configured to electrically connect a capacitance to the node. The charge accumulation region includes a first portion and a second portion. Charge is configured to be first accumulated in the first portion, and, after the first portion is saturated, be accumulated in the second portion. The output unit is configured to output a first signal based on the potential of the node before the capacitance is connected thereto, and, then a second signal based on the potential of the node after the capacitance is connected thereto.
US09257455B2	Gate drive circuit having reduced size, display substrate having the same, and method of manufacturing the display substrate A gate drive circuit includes plural stages connected together one after each other. Each of the plural stages includes a circuit transistor, a capacitor part, a first connection part and a second connection part. The circuit transistor outputs the gate signal through a source electrode in response to a control signal applied through a gate electrode. The capacitor part includes a first electrode, a second electrode formed on the first electrode, and a third electrode formed on the second electrode. The first connection part electrically connects the gate electrode of the circuit transistor and the second electrode of the capacitor part. The second connection part electrically connects the source electrode of the circuit transistor and the first electrode of the capacitor part. Thus, an integrated size of a gate drive circuit may be decreased, and a reliability of a gate drive circuit may be enhanced.
US09257454B2	Thin film transistor array substrate A pixel electrode is connected to a drain electrode of TFT via a first aperture formed on a second interlayer insulating film, a second aperture, which includes a bottom portion of the first aperture and is formed on a common electrode, and a third aperture, which is included in the bottom portion of the first aperture and is formed on a first interlayer insulating film and a third interlayer insulating film. The common electrode is connected to a common wiring via a fourth aperture formed on the second interlayer insulating film, and a fifth aperture that is included in a bottom portion of the fourth aperture and is formed on the first interlayer insulating film, and a contact electrode that is formed in the fourth aperture and the fifth aperture.
US09257452B2	Portable semiconductor device including transistor with oxide semiconductor layer An object of one embodiment of the disclosed invention is to provide a semiconductor device having a novel structure in which stored data can be held even when power is not supplied and the number of times of writing is not limited. The semiconductor device is formed using an insulating layer formed over a supporting substrate and, over the insulating layer, a highly purified oxide semiconductor and single crystal silicon which is used as a silicon on insulator (SOI). A transistor formed using a highly purified oxide semiconductor can hold data for a long time because leakage current thereof is extremely small. Further, by using an SOI substrate and utilizing features of thin single crystal silicon formed over an insulating layer, fully-depleted transistors can be formed; therefore, a semiconductor integrated circuit with high added values such as high integration, high-speed driving, and low power consumption can be obtained.
US09257448B2	Integrated semiconductor device having an insulating structure and a manufacturing method An integrated semiconductor device is provided. The integrated semiconductor device has a first semiconductor region of a second conductivity type, a second semiconductor region of a first conductivity type forming a pn-junction with the first semiconductor region, a non-monocrystalline semiconductor layer of the first conductivity type arranged on the second semiconductor region, a first well and at least one second well of the first conductivity type arranged on the non-monocrystalline semiconductor layer and an insulating structure insulating the first well from the at least one second well and the non-monocrystalline semiconductor layer. Further, a method for forming a semiconductor device is provided.
US09257447B2	Semiconductor device and method of manufacturing the same A semiconductor device includes word lines and interlayer insulating layers alternately stacked, a channel layer penetrating the word lines and the interlayer insulating layers, a tunnel insulating layer surrounding the channel layer, and first charge trap layers surrounding the tunnel insulating layer, interposed between the word lines and the tunnel insulating layer, respectively, and doped with first impurities.
US09257443B1	Memory device and method for manufacturing the same According to an embodiment, a semiconductor memory device includes a semiconductor pillar, a first electrode film, a second electrode film, a first insulating film, a second insulating film, and a wiring film. The semiconductor member is extending in a first direction. The first electrode film is disposed at the lateral side of the semiconductor member away from the semiconductor member. The second electrode film is provided between the semiconductor member and the first electrode film. The first insulating film is provided between the semiconductor member and the second electrode film. The second insulating film is provided between the second electrode film and the first electrode film. The wiring film is disposed in a wiring lead-out region adjacent to the memory cell region. And the first electrode film is formed of a material different from a material of the wiring film, and being electrically connected to the wiring film.
US09257442B2	3-D non-volatile memory device and method of manufacturing the same A three dimensional (3-D) non-volatile memory device includes a pipe gate including a first pipe gate, a second pipe gate formed on the first pipe gate, and a first interlayer insulating layer interposed between the first pipe gate and the second pipe gate, word lines alternately stacked with second interlayer insulating layers on the pipe gate, a pipe channel buried within the pipe gate, and memory cell channels coupled to the pipe channel and arranged to pass through the word lines and the second interlayer insulating layers.
US09257441B2	Semiconductor memory devices and methods of forming the same Methods of forming semiconductor devices may be provided. A method of forming a semiconductor device may include patterning first and second material layers to form a first through region exposing a substrate. The method may include forming a first semiconductor layer in the first through region on the substrate and on sidewalls of the first and second material layers. In some embodiments, the method may include forming a buried layer filling the first through region on the first semiconductor layer. In some embodiments, the method may include removing a portion of the buried layer to form a second through region between the sidewalls of the first and second material layers. Moreover, the method may include forming a second semiconductor layer in the second through region.
US09257438B2	Semiconductor device structure and method of manufacturing the same In accordance with some embodiments, a semiconductor device structure is provided. The semiconductor device structure includes a substrate, and the substrate has a cell region and a logic region. The semiconductor device structure also includes an isolation feature formed in the substrate and a first gate stack structure formed on the isolation feature and at the cell region. The semiconductor device structure further includes a second gate stack structure formed on the isolation feature and at the cell region, and the first gate stack structure is adjacent to the second gate stack structure. The isolation feature between the first gate stack structure and the second gate stack structure has a substantially planar topography.
US09257437B2	Semiconductor device and method of manufacturing the same A semiconductor device includes a bit line structure on a substrate, the bit line structure having a polysilicon layer pattern doped with impurities, and a metal layer pattern on the polysilicon layer pattern, a first spacer surrounding and contacting a sidewall of the bit line structure, the first spacer having a constant thickness, and a capacitor contact structure on the substrate, an air gap being defined between the capacitor contact structure and the first spacer.
US09257436B2	Semiconductor device with buried gates and fabrication method thereof A semiconductor device includes a substrate having a cell region and a peripheral region, a buried gate formed over the substrate of the cell region, a peripheral gate formed over the substrate of the peripheral region and comprising a conductive layer, an inter-layer dielectric layer that covers the substrate, and a peripheral bit line formed inside the inter-layer dielectric layer and contacting the conductive layer.
US09257433B2	Structure and method of forming enhanced array device isolation for implanted plate EDRAM A memory device is provided including a semiconductor on insulator (SOI) substrate including a first semiconductor layer atop a buried dielectric layer, wherein the buried dielectric layer is overlying a second semiconductor layer. A capacitor is present in a trench, wherein the trench extends from an upper surface of the first semiconductor layer through the buried dielectric layer and extends into the second semiconductor layer. A protective oxide is present in a void that lies adjacent the first semiconductor layer, and a pass transistor is present atop the semiconductor on insulator substrate in electrical communication with the capacitor.
US09257429B2	N-channel and P-channel end-to-end finFET cell architecture with relaxed gate pitch A finFET block architecture uses end-to-end finFET blocks in which the fin lengths are at least twice the contact pitch, whereby there is enough space for interlayer connectors to be placed on the proximal end and the distal end of a given semiconductor fin, and on the gate element on the given semiconductor fin. A first set of semiconductor fins having a first conductivity type and a second set of semiconductor fins having a second conductivity type can be aligned end-to-end. Interlayer connectors can be aligned over corresponding semiconductor fins which connect to gate elements.
US09257427B2	Merged tapered finFET According to a structure herein, parallel fins comprise channel regions and source and drain regions. Parallel gate conductors are over and intersecting the channel regions of the fins. Electrical insulator material surrounds sides of the gate conductors. Each of the fins has a main fin body and wider regions extending from the main fin body between the electrical insulator material surrounding the sides of the gate conductors. The wider regions comprise a first wider region extending a first width from the main fin body and a second wider region extending a second width from the main fin body. The material of the second wider region is continuous between adjacent fins.
US09257426B2	Integrated high-k/metal gate in CMOS process flow A semiconductor device includes a semiconductor substrate that has a first-type active region and a second-type active region, a dielectric layer over the semiconductor substrate, a first metal layer having a first work function formed over the dielectric layer, the first metal layer being at least partially removed from over the second-type active region, a second metal layer over the first metal layer in the first-type active region and over the dielectric layer in the second-type active region, the second metal layer having a second work function, and a third metal layer over the second metal layer in the first-type active region and over the second metal layer in the second-type active region.
US09257421B2	Transient voltage suppression device and manufacturing method thereof The present invention discloses a transient voltage suppression (TVS) device and a manufacturing method thereof. The TVS device limits a voltage drop between two terminals thereof not to exceed a clamp voltage. The TVS device is formed in a stack substrate including a semiconductor substrate, a P-type first epitaxial layer, and a second epitaxial layer stacked in sequence. In the TVS device, a first PN diode is connected to a Zener diode in series, wherein the series circuit is surrounded by a first shallow trench isolation (STI) region; and a second PN diode is connected in parallel to the series circuit, wherein the second PN diode is surrounded by a second STI region. The first STI region and the second STI region both extend from an upper surface to the second epitaxial layer, but not to the first epitaxial layer.
US09257420B2	Overvoltage protection device An overvoltage protection device including: a doped substrate of a first conductivity type having a first doping level, coated with a doped epitaxial layer of the second conductivity type having a second doping level; a first doped buried region of the second conductivity type having a third doping level greater than the second level, located at the interface between the substrate and the epitaxial layer in a first portion of the device; and a second doped buried region of the first conductivity type having a fourth doping level greater than the first level, located at the interface between the substrate and the epitaxial layer in a second portion of the device.
US09257419B2	Leadframe-based system-in-packages having sidewall-mounted surface mount devices and methods for the production thereof Embodiments of a method for fabricating System-in-Packages (SiPs) are provided, as are embodiments of a SiP. In one embodiment, the method includes producing a first package including a first molded package body having a sidewall. A first leadframe is embedded within the first molded package body and having a first leadframe lead exposed through the sidewall. In certain implementations, a semiconductor die may also be encapsulated within the first molded package body. A Surface Mount Device (SMD) is mounted to the sidewall of the first molded package body such that a first terminal of the SMD is in ohmic contact with the first leadframe lead exposed through the sidewall.
US09257418B2	Semiconductor package having heat slug and passive device Provided is a semiconductor package including a substrate, a semiconductor chip and a passive device disposed on the substrate, and a heat slug configured to cover the semiconductor chip and the passive device. The substrate and a first electrode of the passive device are electrically connected to each other, and the heat slug and a second electrode of the passive device are electrically connected to each other. The semiconductor package may include multiple passive devices in which a vertical height of each passive device is greater than a horizontal width thereof. Also disclosed is an electronic system, which may include a power supply unit, a microprocessor unit, a function unit, and a display controller unit to receive one or more power supply voltages from the power supply unit. At least one of the microprocessor unit, the function unit, or the display controller unit may further include the described semiconductor package.
US09257416B2	Semiconductor light emitting device and method for manufacturing same According to one embodiment, a semiconductor light emitting device includes not less than three chips. Each of the chips includes a semiconductor layer having a first face, a second face formed on a side opposite to the first face, and a light emitting layer, a p-side electrode, and an n-side electrode. The chips include a central chip centrally positioned in a plan view, and at least two peripheral chips arranged symmetrically to each other sandwiching the central chip in the plan view. A thickness of the fluorescent body layer on the first face is same among the peripheral chips, and the fluorescent body layer on the first face of the central chip and the fluorescent body layers on the first faces of the peripheral chips have thicknesses different from each other.
US09257415B2	Stacked microelectronic packages having sidewall conductors and methods for the fabrication thereof Embodiments of a method for fabricating stacked microelectronic packages are provided, as are embodiments of stacked microelectronic packages. In one embodiment, the method includes producing a partially-completed stacked microelectronic package including a package body having a vertical package sidewall, a plurality microelectronic devices embedded within the package body, and package edge conductors electrically coupled to the plurality of microelectronic devices and extending to the vertical package sidewall. A flowable conductive material is applied on the vertical package sidewall and contacts the package edge conductors. Selected portions of the flowable conductive material are then removed to define, at least in part, electrically-isolated sidewall conductors electrically coupled to different ones of the package edge conductors.
US09257412B2	Stress reduction apparatus A structure comprises a plurality of connectors formed on a top surface of a first semiconductor die, a second semiconductor die formed on the first semiconductor die and coupled to the first semiconductor die through the plurality of connectors and a first dummy conductive plane formed between an edge of the first semiconductor die and the plurality of connectors, wherein an edge of the first dummy conductive plane and a first distance to neutral point (DNP) direction form a first angle, and wherein the first angle is less than or equal to 45 degrees.
US09257408B2	Semiconductor device and method of manufacturing the same A soldering portion (4) and a Ni plating mark (5) are simultaneously forming by plating on a wiring pattern (2) of an insulating substrate (1). A semiconductor chip (6) is mounted on the insulating substrate (1). A position of the insulating substrate (1) is recognized by the Ni plating mark (5) and a wire (7) is bonded to the semiconductor chip (6). An electrode (8) is joined to the soldering portion (4) by solder (9). The insulating substrate (1), the semiconductor chip (6), the wire (7), and the electrode (8) are encapsulated in an encapsulation material (13).
US09257407B2	Heterogeneous channel material integration into wafer Methods for integrating heterogeneous channel material into a semiconductor device, and semiconductor devices that integrate heterogeneous channel material. A method for fabricating a semiconductor device includes processing a first substrate of a first material at a first thermal budget to fabricate a p-type device. The method further includes coupling a second substrate of a second material to the first substrate. The method also includes processing the second substrate to fabricate an n-type device at a second thermal budget that is less than the first thermal budget. The p-type device and the n-type device may cooperate to form a complementary device.
US09257394B2	Shield, package structure and semiconductor package having the shield and fabrication method of the semiconductor package A fabrication method of a semiconductor package is disclosed, which includes the steps of: providing a substrate having at least a carrying region and a cutting region defined on a surface thereof, wherein the cutting region surrounds the carrying region; disposing at least an electronic element on the carrying region of the substrate; disposing a shield having a recess portion and at least a positioning member extending outwards, on the carrying region of the substrate with the electronic element received in the recess portion and the positioning member extending outwards to the cutting region; and performing a cutting process along the cutting region to remove portions of the positioning member and the substrate. Therefore, the shield is precisely positioned on the substrate.
US09257393B1	Fan-out wafer level packages containing embedded ground plane interconnect structures and methods for the fabrication thereof Fan-Out Wafer Level Packages (FO-WLPs) and methods for fabricating FO-WLPs containing Embedded Ground Planes (EGPs) and backside EGP interconnect structures are provided. In one embodiment, the method includes electrically coupling an EGP to a backside terminal of a first microelectronic device through a backside EGP interconnect structure. A molded package body is formed around the first microelectronic device, the EGP, and the EGP interconnect structure. The molded package body has a frontside at which the EGP is exposed. One or more Redistribution Layers are formed over the frontside of the molded packaged body and contain at least one interconnect line electrically coupled to the backside contact through the EGP and the backside EGP interconnect structure.
US09257392B2	Semiconductor package with through silicon via interconnect The invention provides a semiconductor package with a through silicon via (TSV) interconnect. An exemplary embodiment of the semiconductor package with a TSV interconnect includes a semiconductor substrate, having a front side and a back side. A contact array is disposed on the front side of the semiconductor substrate. An isolation structure is disposed in the semiconductor substrate, underlying the contact array. The TSV interconnect is formed through the semiconductor substrate, overlapping with the contact array and the isolation structure.
US09257390B2	Semiconductor device with dual damascene wirings A semiconductor device includes a semiconductor substrate, an insulating film formed above the semiconductor substrate, and a multilayered wiring formed in a prescribed area within the insulating film. The multilayered wiring includes a dual damascene wiring positioned on at least one layer of the multilayered wiring. The dual damascene wiring includes an alloy having copper as a principal component. A concentration of at least one metallic element contained as an added component of the alloy in a via connected to the dual damascene wiring is 10% or more higher in a via connected to a wiring whose width exceeds by five or more times a diameter of the via than that in another via connected to another wiring of a smallest width in a same upper wiring layer of the multilayered wiring.
US09257388B2	Stacked multilayer structure and manufacturing method thereof A stacked multilayer structure according to an embodiment of the present invention comprises: a stacked layer part including a plurality of conducting layers and a plurality of insulating layers, said plurality of insulating layers being stacked alternately with each layer of said plurality of conducting layers, one of said plurality of insulating layers being a topmost layer among said plurality of conducting layers and said plurality of insulating layers; and a plurality of contacts, each contact of said plurality of contacts being formed from said topmost layer and each contact of said plurality of contacts being in contact with a respective conducting layer of said plurality of conducting layers, a side surface of each of said plurality of contacts being insulated from said plurality of conducting layers via an insulating film.
US09257386B2	Wiring substrate and semiconductor device A wiring substrate includes first and second wiring structures. The first wiring structure includes a core substrate, first and second insulation layers each formed from a thermosetting insulative resin including a reinforcement material, and a via wire formed in the first insulation layer. The second wiring structure includes a wiring layer formed on upper surfaces of the first insulation layer and the via wire, an insulation layer formed on the upper surface of the first insulation layer, and an uppermost wiring layer including a pad used to electrically connect a semiconductor chip and the wiring layer. An outermost insulation layer stacked on a lower surface of the second insulation layer exposes a portion of a lowermost wiring layer stacked on the lower surface of the second insulation layer as an external connection pad. The second wiring structure has a higher wiring density than the first wiring structure.
US09257383B2	Method and device for an integrated trench capacitor A methodology for forming trench capacitors on an interposer wafer by an integrated process that provides high-capacitance, ultra-low profile capacitor structures and the resulting device are disclosed. Embodiments include forming a polymer block on a front side of an interposer wafer, patterning and etching the polymer block to form one or more trenches, and forming a capacitor on an upper surface of the polymer block and in the one or more trenches.
US09257375B2	Multi-die semiconductor package A multi-die package has a plurality of leads and first and second semiconductor dies in superimposition and bonded together defining a die stack. The die stack has opposed first and second sides, with each of the first and second semiconductor dies having gate, drain and source regions, and gate, drain and source contacts. The first opposed side has the drain contact of the second semiconductor die, which is in electrical communication with a first set of the plurality of leads. The gate, drain and source contacts of the first semiconductor die and the gate and source contacts of the second semiconductor die are disposed on the second of said opposed sides and in electrical communication with a second set of the plurality of leads. The lead for the source of the first semiconductor die may be the same as the lead for the drain of the second semiconductor die.
US09257369B2	Semiconductor device having a base film and manufacturing method for same The present invention is directed to a semiconductor device including a semiconductor substrate, a through hole penetrating the semiconductor substrate, a base film covering the through hole, a conductive layer disposed on the base film, an insulating film formed on the side wall of the through hole, and a conductive material embedded in the through hole via the insulating film, in which the base film has a stepped portion formed by an opening pattern that selectively exposes the conductive layer therethrough into the through hole, and in which the conductive material is connected electrically to the conductive layer through the opening pattern.
US09257364B2	Integrated heat spreader that maximizes heat transfer from a multi-chip package In at least some embodiments, an electronic package to maximize heat transfer comprises a plurality of components on a substrate. A stiffener plate is installed over the components. The stiffener plate has openings to expose the components. A plurality of individual integrated heat spreaders are installed within the openings over the components. A first thermal interface material layer (TIM1) is deposited between the components and the plurality of individual integrated heat spreaders. In at least some embodiments, the thickness of the TIM1 is minimized for the components.
US09257358B2	Chip stacking packaging structure A chip stacking packaging structure is provided for achieving high-density stacking and improving a heat dissipation efficiency of the chip stacking packaging structure. The chip stacking packaging structure includes a main substrate and at least one stacking substrate in which a main chip is disposed in the main substrate, at least one stacking chip is disposed on the stacking substrate, and a side edge of the stacking substrate is disposed on the main substrate, so that the stacking chip is connected to the main chip.
US09257357B2	Semiconductor device and method of forming prefabricated heat spreader frame with embedded semiconductor die A semiconductor device is made by mounting a prefabricated heat spreader frame over a temporary substrate. The heat spreader frame includes vertical bodies over a flat plate. A semiconductor die is mounted to the heat spreader frame for thermal dissipation. An encapsulant is deposited around the vertical bodies and semiconductor die while leaving contact pads on the semiconductor die exposed. The encapsulant can be deposited using a wafer level direct/top gate molding process or wafer level film assist molding process. An interconnect structure is formed over the semiconductor die. The interconnect structure includes a first conductive layer formed over the semiconductor die, an insulating layer formed over the first conductive layer, and a second conductive layer formed over the first conductive layer and insulating layer. The temporary substrate is removed, dicing tape is applied to the heat spreader frame, and the semiconductor die is singulated.
US09257354B2	Wiring substrate, light emitting device, and method for manufacturing wiring substrate A wiring substrate includes a substrate, a first insulating layer formed on the substrate, wiring patterns formed on a first surface of the first insulating layer, and a second insulating layer formed on the first surface of the first insulating layer. The second insulating layer covers the wiring patterns and includes a first opening that partially exposes adjacent wiring patterns as a pad. A projection is formed in an outer portion of the substrate located outward from where the first opening is arranged. The projection rises in a thickness direction of the substrate.
US09257353B1	Integrated circuits with test structures including bi-directional protection diodes Integrated circuits that include bi-directional protection diode structures are disclosed. In one example, an integrated circuit includes a test circuit portion for testing the functionality of the integrated circuit during or after fabrication of the integrated circuit. The test circuit portion includes first, second, and third diode structures and a resistor structure. The first and third diode structures are in parallel with one another and in series with the resistor, and the resistor and the first and third diode structures are in series with the second diode structure. The first and third diode structures are configured for current flow in a first direction and the second diode structure is configured for current flow in a second direction that is opposite the first direction.
US09257352B2	Semiconductor test wafer and methods for use thereof A test wafer is disclosed with a first side configured to have integrated circuits formed thereon and a second side with a test structure formed thereon. The test wafer can include electrical test structures embedded in the second side of the wafer. An electrical test of the test wafer can be performed after handling by a tool used in a wafer manufacturing process to determine if the tool caused a defect on the second side of the wafer. The test structure can include a blanket layer disposed on the second side of the wafer. The test wafer can then be exposed to a wet etch and inspected thereafter for the presence of an ingress path caused from the etch chemistry. The presence of an ingress path is an indication that the tool used prior to the wet etch caused a defect in the wafer.
US09257350B2	Manufacturing process for finFET device A method for fabricating a field effect transistor device includes removing a portion of a first semiconductor layer and a first insulator layer to expose a portion of a second semiconductor layer, wherein the second semiconductor layer is disposed on a second insulator layer, the first insulator layer is disposed on the second semiconductor layer, and the first semiconductor layer is disposed on the first insulator layer, removing portions of the first semiconductor layer to form a first fin disposed on the first insulator layer and removing portions of the second semiconductor layer to form a second fin disposed on the second insulator layer, and forming a first gate stack over a portion of the first fin and forming a second gate stack over a portion of the second fin.
US09257347B2	System and method for a field-effect transistor with a raised drain structure A method for forming a field-effect transistor with a raised drain structure is disclosed. The method includes forming a frustoconical source by etching a semiconductor substrate, the frustoconical source protruding above a planar surface of the semiconductor substrate; forming a transistor gate, a first portion of the transistor gate surrounding a portion of the frustoconical source and a second portion of the gate configured to couple to a first electrical contact; and forming a drain having a raised portion configured to couple to a second electrical contact and located at a same level above the planar surface of the semiconductor substrate as the second portion of the transistor gate. A semiconductor device having a raised drain structure is also disclosed.
US09257344B2	FinFETs with different fin height and EPI height setting An integrated circuit structure includes a first semiconductor strip, first isolation regions on opposite sides of the first semiconductor strip, and a first epitaxy strip overlapping the first semiconductor strip. A top portion of the first epitaxy strip is over a first top surface of the first isolation regions. The structure further includes a second semiconductor strip, wherein the first and the second semiconductor strips are formed of the same semiconductor material. Second isolation regions are on opposite sides of the second semiconductor strip. A second epitaxy strip overlaps the second semiconductor strip. A top portion of the second epitaxy strip is over a second top surface of the second isolation regions. The first epitaxy strip and the second epitaxy strip are formed of different semiconductor materials. A bottom surface of the first epitaxy strip is lower than a bottom surface of the second epitaxy strip.
US09257342B2	Methods of singulating substrates to form semiconductor devices using dummy material In one embodiment, a method of forming a semiconductor device includes forming openings in a substrate. The method includes forming a dummy fill material within the openings and thinning the substrate to expose the dummy fill material. The dummy fill material is removed.
US09257341B2	Method and structure of packaging semiconductor devices A method for fabricating packaged semiconductor devices; attaching a batch-sized metallic grid with openings onto an adhesive tape having an insulating clear core covered by a layer of UV-releasable adhesive, the openings sized larger than a semiconductor chip; attaching a semiconductor chip onto the tape of each window, the chip terminals facing the adhesive surface; laminating insulating material of low coefficient of thermal expansion to fill gaps between each chip and respective grid; turning over assembly to place a carrier under backside of chips and lamination and to remove the tape; plasma-cleaning the assembly front side and sputtering uniform at least one metal layer across the assembly; optionally plating metal layers; and patterning the metal layers to form rerouting traces and extended contact pads for assembly.
US09257333B2	Interconnect structures and methods of forming same Embodiments of the present disclosure include interconnect structures and methods of forming interconnect structures. An embodiment is an interconnect structure including a post-passivation interconnect (PPI) over a first substrate and a conductive connector on the PPI. The interconnect structure further includes a molding compound on a top surface of the PPI and surrounding a portion of the conductive connector, a top surface of the molding compound adjoining the conductive connector at an angle from about 10 degrees to about 60 degrees relative to a plane parallel with a major surface of the first substrate, the conductive connector having a first width at the adjoining top surface of the molding compound, and a second substrate over the conductive connector, the second substrate being mounted to the conductive connector.
US09257332B2	Through-assembly via modules and methods for forming the same A discrete Through-Assembly Via (TAV) module includes a substrate, and vias extending from a surface of the substrate into the substrate. The TAV module is free from conductive features in contact with one end of each of the conductive vias.
US09257330B2	Ultra-thin structure to protect copper and method of preparation Methods of depositing thin, low dielectric constant layers that are effective diffusion barriers on metal interconnects of semiconductor circuits are described. A self-assembled monolayer (SAM) of molecules each having a head moiety and a tail moiety are deposited on the metal. The SAM molecules self-align, wherein the head moiety is formulated to selectively bond to the metal layer leaving the tail moiety disposed at a distal end of the molecule. A dielectric layer is subsequently deposited on the SAM, chemically bonding to the tail moiety of the SAM molecules.
US09257328B2	Glass-ceramic-based semiconductor-on-insulator structures and method for making the same Methods and apparatus for forming a semiconductor on glass-ceramic structure provide for: subjecting an implantation surface of a donor semiconductor wafer to an ion implantation process to create an exfoliation layer of the donor semiconductor wafer; bonding the implantation surface of the exfoliation layer to a precursor glass substrate using electrolysis; separating the exfoliation layer from the donor semiconductor wafer to thereby form an intermediate semiconductor on precursor glass structure; sandwiching the intermediate semiconductor on precursor glass structure between first and second support structures; applying pressure to one or both of the first and second support structures; and subjecting the intermediate semiconductor on precursor glass structure to heat-treatment step to crystallize the precursor glass resulting in the formation of a semiconductor on glass-ceramic structure.
US09257322B2	Method for manufacturing through substrate via (TSV), structure and control method of TSV capacitance A method for manufacturing a through substrate via (TSV) structure, a TSV structure, and a control method of a TSV capacitance are provided. The method for manufacturing the TSV structure includes: providing a substrate having a first surface and a second surface; forming a trench in the first surface of the substrate; filling a low resistance material into the trench; forming an insulating layer on the first surface of the substrate; forming at least one opening in the first surface of the substrate, wherein the opening is located differently the trench; forming an oxide liner layer, a barrier layer and a conductive seed layer on a sidewall and a bottom of the opening and on the insulating layer of the first surface; and filling a conductive material into the opening, wherein the opening is used to form at least one via.
US09257316B2	Semiconductor testing jig and transfer jig for the same A semiconductor testing jig is provided with a conductive stage including a plurality of mounting portions on which a plurality of vertical semiconductor devices are each individually disposed with lower surface electrodes being in contact with the plurality of mounting portions, an insulating frame portion having a lattice pattern that is disposed on the stage and surrounds each of the plurality of mounting portions in plan view to define each of the mounting portions, and an abrasive layer disposed in a position in the frame portion, the position facing each of the vertical semiconductor devices disposed on the mounting portions.
US09257312B2	Metal oxide thin film substrate, method of fabricating the same, photovoltaic cell and OLED including the same A metal oxide thin film substrate which can increase light trapping efficiency and light extraction efficiency, a method of fabricating the same and a photovoltaic cell and organic light-emitting device (OLED) including the same. The metal oxide thin film substrate includes a base substrate, and a metal oxide thin film formed on the base substrate. The metal oxide thin film has voids which are formed inside the metal oxide thin film to scatter light.
US09257311B2	Method of fabricating a semiconductor package with heat dissipating structure having a deformed supporting portion A method of fabricating a semiconductor package is provided, including: providing a heat dissipating structure having a heat dissipating portion, a deformable supporting portion coupled to the heat dissipating portion, and a coupling portion coupled to the supporting portion; coupling a carrier having a semiconductor element carried thereon to the coupling portion of the heat dissipating structure to form between the carrier and the heat dissipating portion a receiving space for the semiconductor element to be received therein; and forming in the receiving space an encapsulant that encapsulates the semiconductor element. The use of the supporting portion enhances the bonding between the heat dissipating structure and a mold used for packaging, thereby preventing the heat dissipating structure from having an overflow of encapsulant onto an external surface of the heat-dissipating portion.
US09257310B2	Method of manufacturing circuit board and chip package and circuit board manufactured by using the method Provided is a method of manufacturing a circuit board. The method includes: preparing a base substrate including a core layer and a first conductive layer that is formed on at least one surface of the core layer and includes an internal circuit pattern; forming a build-up material to cover the first conductive layer; forming in the build-up material at least one cavity through which the core layer and the first conductive layer are exposed; forming a laminated body by curing the build-up material in which the at least one cavity is formed; and forming a second conductive layer including an external circuit pattern on an outer surface of the laminated body.
US09257309B2	Multi-chip package and method of manufacturing the same A multi-chip package may include a package substrate, a first semiconductor chip, a second semiconductor chip and a supporting member. The first semiconductor chip may be arranged on an upper surface of the package substrate. The first semiconductor chip may be electrically connected with the package substrate. The second semiconductor chip may be arranged on an upper surface of the first semiconductor chip. The second semiconductor chip may be electrically connected with the first semiconductor chip. The second semiconductor chip may have a protrusion overhanging an area beyond a side surface of the first semiconductor chip. The supporting member may be interposed between the protrusion of the second semiconductor chip and the package substrate to prevent a deflection of the protrusion. Thus, the protrusion may not be deflected.
US09257307B2	Thermal interface material on package A packaged assembly is disclosed, including thermal interface material dispensed on an organic package and methods of manufacturing. The method includes dispensing a thermal interface material (TIM) on an electronic assembly. The method further includes removing volatile species of the TIM, prior to lid placement on the electronic assembly. The method further includes placing the lid on the TIM, over the electronic assembly. The method further includes pressing the lid onto the electronic assembly.
US09257305B2	Methods of forming a thin film and methods of fabricating a semiconductor device including using the same Provided are methods of forming a thin film and methods of fabricating a semiconductor device including the same. The thin film forming methods may include supplying an organic silicon source to form a silicon seed layer on a lower layer, the silicon seed layer including silicon seed particles adsorbed on the lower layer, and supplying an inorganic silicon source to deposit a silicon film on the lower layer adsorbed with the silicon atoms.
US09257301B2	Method of etching silicon oxide film Provided is a method of etching a silicon oxide film. The method includes exposing a workpiece including the silicon oxide film and a mask formed on the silicon oxide film to plasma of a processing gas to etch the silicon oxide film. The mask includes a first film formed on the silicon oxide film and a second film formed on the first film, and the second film is constituted by a film having an etching rate lower than that of the first film with respect to active species in the plasma.
US09257300B2	Fluorocarbon based aspect-ratio independent etching A method for etching features into an etch layer disposed below a patterned mask is provided. At least three cycles are provided, where each cycle comprises providing an ion bombardment, by creating a plasma, of the etch layer to create activated sites of surface radicals in parts of the etch layer exposed by the patterned mask, extinguishing the plasma, exposing the etch layer to a plurality of fluorocarbon containing molecules, which causes the fluorocarbon containing molecules to selectively bind to the activated sites, wherein the selective binding is self limiting, and providing an ion bombardment of the etch layer to initiate an etch reaction between the fluorocarbon containing molecule and the etch layer, wherein the ion bombardment of the etch layer to initiate an etch reaction causes the formation of volatile etch products formed from the etch layer and the fluorocarbon containing molecule.
US09257298B2	Systems and methods for in situ maintenance of a thin hardmask during an etch process Methods of patterning a target material layer are provided herein. The method includes steps of positioning a semiconductor wafer having the target material layer thereon in an etch chamber and of providing a flow of etch gases into the etch chamber, the flow of etch gases etchant gas comprising a plurality of gases. The semiconductor wafer has a patterned hardmask feature formed from a compound on the target material layer. The method also includes steps of etching the target material layer using the patterned hardmask feature as a mask feature, wherein one of the gases chemically alters the patterned hardmask feature and at least one of the gases chemically repairs the patterned hardmask feature so that the patterned hardmask feature retains its dimensions during the etching. Associated semiconductor wafer are also provided herein.
US09257293B2	Methods of forming silicon nitride spacers Embodiments of methods of forming silicon nitride spacers are provided herein. In some embodiments, a method of forming silicon nitride spacers atop a substrate includes: depositing a silicon nitride layer atop an exposed silicon containing layer and an at least partially formed gate stack disposed atop a substrate; modifying a portion of the silicon nitride layer by exposing the silicon nitride layer to a hydrogen or helium containing plasma that is substantially free of fluorine; and removing the modified portion of the silicon nitride layer by performing a wet cleaning process to form the silicon nitride spacers, wherein the wet cleaning process removes the modified portion of the silicon nitride layer selectively to the silicon containing layer.
US09257283B2	Device having reduced bias temperature instability (BTI) A semiconductor device is disclosed along with methods for manufacturing such a device. In certain embodiments, the semiconductor device includes a source electrode formed using a metal that limits a shift, such as due to bias temperature instability, in a threshold voltage of the semiconductor device during operation. In certain embodiments the semiconductor device may be based on silicon carbide.
US09257279B2	Mask treatment for double patterning design A method of forming a semiconductor device, and a product formed thereby, is provided. The method includes forming a pattern in a mask layer using, for example, double patterning or multi-patterning techniques. The mask is treated to smooth or round sharp corners. In an embodiment in which a positive pattern is formed in the mask, the treatment may comprise a plasma process or an isotropic wet etch. In an embodiment in which a negative pattern is formed in the mask, the treatment may comprise formation of conformal layer over the mask pattern. The conformal layer will have the effect of rounding the sharp corners. Other techniques may be used to smooth or round the corners of the mask.
US09257277B2	Methods for extreme ultraviolet mask defect mitigation by multi-patterning Methods for extreme ultraviolet (EUV) mask defect mitigation by using multi-patterning lithography techniques. In one exemplary embodiment, a method for fabricating an integrated circuit including identifying a position of a defect in a first EUV photolithographic mask, the photolithographic mask including a desired pattern and transferring the desired pattern to a photoresist material disposed on a semiconductor substrate. Transferring the desired pattern further transfers an error pattern feature to the photoresist material as a result of the defect in the first EUV photolithographic mask. The method further includes, using a second photolithographic mask, transferring a trim pattern to the photoresist material, wherein the trim pattern removes the error pattern feature from the photoresist material.
US09257276B2	Organic thin film passivation of metal interconnections Electronic assemblies and their manufacture are described. One embodiment relates to a method including depositing an organic thin film layer on metal bumps on a semiconductor wafer, the organic thin film layer also being formed on a surface adjacent to the metal bumps on the wafer. The wafer is diced into a plurality of semiconductor die structures, the die structures including the organic thin film layer. The semiconductor die structures are attached to substrates, wherein the attaching includes forming a solder bond between the metal bumps on a die structure and bonding pads on a substrate, and wherein the solder bond extends through the organic thin film layer. The organic thin film layer is then exposed to a plasma. Other embodiments are described and claimed.
US09257274B2	Gapfill of variable aspect ratio features with a composite PEALD and PECVD method Provided herein are methods and apparatus for filling one or more gaps on a semiconductor substrate. The disclosed embodiments are especially useful for forming seam-free, void-free fill in both narrow and wide features. The methods may be performed without any intervening etching operations to achieve a single step deposition. In various implementations, a first operation is performed using a novel PEALD fill mechanism to fill narrow gaps and line wide gaps. A second operation may be performed using PECVD methods to continue filling the wide gaps.
US09257271B2	Semiconductor device manufacturing method, substrate processing apparatus, and non-transitory recording medium A method of manufacturing a semiconductor device includes: accommodating a substrate having an oxide film formed thereon into a processing chamber; supplying a process gas to the substrate; performing a preprocessing step in which the process gas is excited in a state that a pressure within the processing chamber is kept at a first pressure and an electric potential of the substrate is kept at a first electric potential; and performing a main processing step by which the process gas is excited in a state that the pressure within the processing chamber is kept at a second pressure and the electric potential of the substrate is kept at a second electric potential, wherein the first pressure is lower than the second pressure and the first electric potential is lower than the second electric potential.
US09257265B2	Methods for reducing etch nonuniformity in the presence of a weak magnetic field in an inductively coupled plasma reactor Methods and apparatus for plasma-enhanced substrate processing are provided herein. In some embodiments, a method is provided for processing a substrate in a process chamber having a plurality of electromagnets disposed about the process chamber to form a magnetic field within the process chamber at least at a substrate level. In some embodiments, the method includes determining a first direction of an external magnetic field present within the process chamber while providing no current to the plurality of electromagnets; providing a range of currents to the plurality of electromagnets to create a magnetic field within the process chamber having a second direction opposing the first direction; determining a desired magnitude in the second direction of the magnetic field over the range of currents; and processing a substrate in the process chamber using a plasma while statically providing the magnetic field at the desired magnitude.
US09257261B2	Method for rapid switching between a high current mode and a low current mode in a charged particle beam system A method for rapid switching between operating modes with differing beam currents in a charged particle system is disclosed. Many FIB milling applications require precise positioning of a milled pattern within a region of interest (RoI). This may be accomplished by using fiducial marks near the RoI, wherein the FIB is periodically deflected to image these marks during FIB milling. Any drift of the beam relative to the RoI can then be measured and compensated for, enabling more precise positioning of the FIB milling beam. It is often advantageous to use a lower current FIB for imaging since this may enable higher spatial resolution in the image of the marks. For faster FIB milling, a larger beam current is desired. Thus, for optimization of the FIB milling process, a method for rapidly switching between high and low current operating modes is desirable.
US09257258B2	Method of making transmission electron microscope micro-grid A method of making a transmission electron microscope micro-grid includes following steps. A carbon nanotube layer is provided, and the carbon nanotube layer includes a first surface and a second surface opposite to each other. A first metal layer is electroplated on the first surface and a second metal layer is electroplated on the second surface. A number of first through holes are formed by etching the first metal layer, and a number of second through holes are formed by etching the second metal layer, wherein the carbon nanotube layer is exposed through the number of first through holes and the number of second through holes.
US09257253B1	Systems and methods utilizing a triode hollow cathode electron gun for linear particle accelerators The present invention generally relates to systems and methods for generating controllable beam of electrons using a hollow-cathode triode electron gun that substantially mitigate impact of back-streaming electrons.
US09257252B2	Intelligent magnetic latching miniature circuit breaker and control method therefor This invention discloses a type of intelligent magnetic-hold miniature circuit breaker and its control method, comprising a casing, a magnetic-hold relay, and a drive circuit, wherein said drive circuit receives control signal and then drives operation of said magnetic-hold relay; said magnetic-hold relay comprises a dynamic spring assembly, a static spring assembly, a deflector rod, a pushing piece, and a magnetic steel assembly; rotation of said magnetic steel assembly drives said deflector rod and then closing or opening of contacts of said dynamic spring assembly and said static spring assembly via said pushing piece; said miniature circuit breaker also includes a central processor, a communication chip, and a voltage state circuit; and said deflector rod extends out through a hole on said casing to allow manual operation. This invention breaks through traditional miniature circuit breaker design concept, and in terms of functions, realizes manual operation with priority and coordination between manual operation and remote operation in normal state, as well as protection in abnormal state, i.e. in case of interruption of commercial power supply followed by its restoration, clearing and addition of manual opening record.
US09257250B2	Magnetic relay device made using MEMS or NEMS technology A magnetic relay device having a substrate of semiconductor material houses two through magnetic vias of electrically conductive ferromagnetic material. At least one coil is arranged underneath a first surface of the substrate in proximity of at least one between the first and second magnetic vias, and a contact structure, of ferromagnetic material, is arranged over a second surface of the substrate and is controlled by the magnetic field generated by the coil so as to switch between an open position, wherein the contact structure electrically disconnects the first and second magnetic vias, and a close position, wherein the contact structure electrically connects the first and second magnetic vias.
US09257249B2	Power supply control device The power supply control device in accordance with the present invention includes: a power reception terminal for receiving power; a power supply terminal for supplying power; a relay configured to make and break an electrical connection between the power reception terminal and the power supply terminal; a control circuit configured to control the relay; a power supply circuit configured to supply power to the control circuit by use of power received via the power reception terminal; and a printed wiring board. The control circuit and the power supply circuit are mounted on the printed wiring board.
US09257247B2	Low-G MEMS acceleration switch A motion-sensitive low-G MEMS acceleration switch, which is a MEMS switch that closes at low-g acceleration (e.g., sensitive to no more than 10 Gs), is proposed. Specifically, the low-G MEMS acceleration switch has a base, a sensor wafer with one or more proofmasses, an open circuit that includes two fixed electrodes, and a contact plate. During acceleration, one or more of the proofmasses move towards the base and connects the two fixed electrodes together, resulting in a closing of the circuit that detects the acceleration. Sensitivity to low-G acceleration is achieved by proper dimensioning of the proofmasses and one or more springs used to support the proofmasses in the switch.
US09257246B2	Stepping switch with vacuum switching tubes A tap changer with vacuum-switching tubes for controlling a transformer having taps has a selector for power-free selection of a one of the taps to be switched and a load-changeover switch for actual switching over from the connected tap to a new, pre-selected one of the taps. A first cam disk is fixed against rotation on a rotatable switch shaft, and a rocker lever arrangement has a first roller for actuating the vacuum-switching tubes. A second cam disk is also rotationally fixed on the switch shaft, and there are two further arms of U-shaped construction on the rocker lever arrangement. A lever has a free end provided with a second roller that co-operates with the second cam disk. This lever is between the further arms and mounted to be rotatable about an axis. A compression spring is provided between the lever and the further arms.
US09257242B2	Work vehicle An operation unit cover moves between a position of covering an operation lever and a position of exposing the operation lever and holding the operation lever at a first operational position while being at the position of covering. A housing covers lateral sides and a top side of a case that cross a front side of the case and exposes the operation unit cover from the front side. A pivoting member pivots about a pivoting member's pivot shaft located above the operation unit cover, between a closed position of covering the operation unit cover and an opened position of exposing the operation unit cover and, while the pivoting member is at the closed position, the pivoting member forms a closed space between the pivoting member and the housing for accommodating at least the operation unit cover and holds the operation unit cover at the position of covering the operation lever.
US09257229B2	Cast split low voltage coil with integrated cooling duct placement after winding process A coil for a transformer includes first and second coil segments with each coil segment being defined by successive layers of wound conductor sheeting. The coil segments are electrically connected together and are adjacent, defining a space there-between. A plurality of cooling duct pairs are disposed between certain of the layers in each of the first and second coil segments such that, for each cooling duct pair, an end of a cooling duct disposed in the first coil segment is adjacent to an end of a cooling duct disposed in the second coil segment, with the ends being disposed in the space. A connector connects the adjacent ends of each pair of cooling ducts.
US09257228B2	Method of manufacturing a transformer core assembly A method is provided for making a transformer core assembly using a work table positioned proximate to a rotatable rack assembly having first and second racks. Core segments are created by a segment forming machine. The core segments are transferred to a core block of the second rack. After a predetermined number of core segments are stacked on the core block to form a core segment assembly, the rack assembly is rotated so that the second rack is positioned proximate to the work table. The second rack is then moved onto the work table and one or more finishing steps are performed on the core segment assembly. During the performance of the one or more finishing steps, core segments may be transferred to a core block attached to the first rack.
US09257226B2	Rotary transformer and associated devices, systems, and methods for rotational intravascular ultrasound Rotational intravascular ultrasound (IVUS) imaging devices, systems, and methods are provided. The present disclosure is particularly directed to rotary transformers incorporating flex circuits that are suitable for use in rotational IVUS systems. In one embodiment, a rotary transformer for a rotational IVUS device includes: a rotational component and a stationary component. At least one of the rotational and stationary components includes a core formed of a magnetically conductive material and a flex circuit coupled to the core. In some instances, the flex circuit is coupled to the core such that a coil portion of the flex circuit is received within a recess of the core and an extension of the flex circuit extending from the coil portion extends through an opening of the core.
US09257224B2	Shield for toroidal core electromagnetic device, and toroidal core electromagnetic devices utilizing such shields A shield for a toroidal transformer that includes a toroidal assembly that comprises a toroidal magnetic core and a first winding includes a sheet of flexible non-magnetic conductive material. The sheet of flexible non-magnetic conductive material comprises a trunk portion extending along a longest dimension of the sheet of flexible non-magnetic conductive material and configured to wrap along an outer dimension of the toroidal assembly, and a plurality of fingers extending outwardly from the trunk portion and configured to wrap around portions of the first winding along portions of sides of the toroidal assembly in a direction towards the center of the toroidal magnetic core and folding into an inner dimension of the toroidal assembly.
US09257222B2	Inverter housing system A housing system can comprise a plastic cover (12); a plastic base (14) comprising a floor (20) having sidewalls (22, 24); a first elevation (26); a second elevation (34); a first mounting column (40) located in a transformer end (32) of the plastic base (14) adjacent a major axis first sidewall (22); a second mounting column (42) located in the transformer end (32) of the plastic base (14) adjacent a major axis second sidewall (22); wherein the first and second mounting columns (40,42) have a top surface (44) that protrudes a distance from the floor (20), in the Z direction, in an amount greater than or equal to elevation walls (28,36), wherein the top surface (44) is configured to receive an attachment element (46). The housing system can also comprise a transformer (72), physically attached to the mounting columns; a capacitor (74); a fan (78), and a printed circuit board (80).
US09257221B2	Through-hole via inductor in a high-frequency device The invention discloses a high-frequency device having a through-hole via inductor in a substrate. The through-hole via inductor has an integral body. The inductance of the through-hole via inductor is greater than that of the horizontal inductor. The through-hole via inductor comprises at least two materials, wherein one of said at least two materials is a conductive material. The present invention also discloses a method for manufacturing the structure of the high-frequency device, wherein the method mainly includes via-drilling and via-filling in the substrate, and lithography process on the substrate.
US09257219B2	System and method for magnetization A system and a method are described herein for magnetizing magnetic sources into a magnetizable material. In one embodiment, the method comprises: (a) providing an inductor coil having multiple layers and a hole extending through the multiple layers; (b) positioning the inductor coil next to the magnetizable material; and (c) emitting from the inductor coil a magnetic field that magnetizes an area on a surface of the magnetizable material, wherein the area on the surface of the magnetizable material that is magnetized is in a direction other than perpendicular to the magnetizable material such that there is a magnetic dipole with both a north polarity and a south polarity formed on the surface of the magnetizable material.
US09257218B2	Using magnets to position cables/flexes during system assembly Methods and tools for positioning cables using magnets during assembly of a consumer electronic product are described. Methods described are well suited in the manufacture of portable electronic devices such as mobile phones, computer tablets and the like. Methods involve attaching magnetic components to cables and to one or more surfaces within the enclosure of the electronic devices. During assembly, the magnetic components on the cables magnetically couple with corresponding magnetic components on the surfaces within the enclosure. In this way, the cables can be secured in certain positions and out of the way during the assembly of the electronic device. In some instances, the cables can remain magnetically secured after assembly and during the operation of the electronic device. In other instances, the magnetic components are decoupled after assembly thereby releasing the cables from their secured positions during operation of the electronic device.
US09257211B2	Process of forming transparent conductive coatings with sintering additives A process is disclosed for the delayed sintering of metal nanoparticles in a self-assembled transparent conductive coating by incorporating a sintering additive into the water phase of the emulsion used to form the coating. The sintering additive reduces the standard reduction potential of the metal ion of the metal forming the nanoparticles by an amount greater than 0.1V but less than the full reduction potential of the metal ion. Emulsion compositions used in the process are also disclosed.
US09257207B2	Multi focal spot collimator An x-ray collimator can be constructed from multiple subassemblies, which at least includes a first subassembly that reduces the leakage of x-ray radiation between adjacent apertures and a second subassembly that reduces the spill of x-ray radiation around the detector face. Each of these subassemblies has numerous apertures. In the first subassembly these apertures correspond to focal spots on an x-ray source, and in the second subassembly, these apertures are shaped such that the dimensions increase from smaller entrances to larger exits.
US09257206B2	Adiabatic rapid passage atomic beamsplitter using frequency-swept coherent laser beam pairs Methods and apparatus for providing coherent atom population transfer using coherent laser beam pairs in which the frequency difference between the beams of a pair is swept over time. Certain examples include a Raman pulse adiabatic rapid passage sweep regimen configured to be used as a beamsplitter and combiner in conjunction with an adiabatic rapid passage mirror sweep or a standard Raman mirror pulse in a 3-pulse interferometer sequence.
US09257204B2	Read voltage setting method, and control circuit, and memory storage apparatus using the same A read voltage setting method for a rewritable non-volatile memory module is provided. The method includes: reading test data stored in memory cells of a word line to obtain a corresponding critical voltage distribution and identifying a default read voltage corresponding to the word line based on the corresponding critical voltage distribution; applying a plurality of test read voltages obtained according to the default read voltage to the word line to read a plurality of test page data; and determining an optimized read voltage corresponding to the word line according to the minimum error bit number among a plurality of error bit numbers of the test page data. The method further includes calculating a difference value between the default read voltage and the optimized read voltage as a read voltage adjustment value corresponding to the word line and recording the read voltage adjustment value in a retry table.
US09257197B2	Apparatuses and/or methods for operating a memory cell as an anti-fuse Embodiments disclosed herein relate to operating a memory cell as an anti-fuse, such as for use in phase change memory, for example.
US09257193B2	Memory with output control An apparatus, system, and method for controlling data transfer to an output port of a serial data link interface in a semiconductor memory is disclosed. In one example, a flash memory device may have multiple serial data links, multiple memory banks and control input ports that enable the memory device to transfer the serial data to a serial data output port of the memory device. In another example, a flash memory device may have a single serial data link, a single memory bank, a serial data input port, a control input port for receiving output enable signals. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices.
US09257190B2	Level shifter A level shifter includes a differential input pair circuit, a current mirror circuit, a switching circuit, a first keeper circuit, a second keeper circuit, and an output buffering circuit. The differential input pair circuit is connected with a first node, a second node and a first voltage. The differential input pair circuit receives an input signal and an inverted input signal. The current mirror circuit is connected with a third voltage, and includes a first current output terminal connected with a third node and a second current output terminal generating an output signal. The switching circuit includes a first control terminal receiving the inverted output signal. The second keeper circuit is connected between the third voltage and the second node, and includes a third control terminal receiving the inverted input signal and a fourth control terminal receiving the inverted output signal.
US09257189B2	Non-volatile semiconductor memory adapted to store a multi-valued data in a single memory cell A non-volatile semiconductor memory device includes an electrically data rewritable non-volatile semiconductor memory cell and a write circuit for writing data in the memory cell, the write circuit writing a data in the memory cells by supplying a write voltage Vpgm and a write control voltage VBL to the memory cell, continuing the writing of the data in the memory cell by changing the value of the write control voltage VBL in response to an advent of a first write state of the memory cell and inhibiting any operation of writing a data to the memory cell by further changing the value of the write control voltage VBL to Vdd in response to an advent of a second write state of the memory cell.
US09257188B2	Nonvolatile memory and memory system According to one embodiment, in a nonvolatile memory, the determination unit determines whether a change process is executable or not. The change process is a process based on characteristics of the memory cell array when a first write process is performed. The change process changes at least one of a value of a write start voltage and an increase amount in a write voltage in a second write process. The second write process is a process where a write operation of writing data to upper pages of at least part of the plurality of nonvolatile memory cells and a verification operation are alternately repeated. The setting unit sets a maximum value for determining whether the second write process succeeds or fails to a first value when the change process is executable, and sets the maximum value to a second value when the change process is not executable.
US09257184B2	Nonvolatile memory systems with embedded fast read and write memories A nonvolatile memory system is described with novel architecture coupling nonvolatile storage memory with random access volatile memory. New commands are included to enhance the read and write performance of the memory system.
US09257181B2	Sense amplification circuits, output circuits, nonvolatile memory devices, memory systems, memory cards having the same, and data outputting methods thereof An output circuit of a nonvolatile memory device includes a sense amplification circuit configured to, during a sensing operation, generate output data based on a comparison between a first voltage on a data line and a reference voltage on a reference data line during a sensing operation, the first voltage corresponding to data read from at least one memory cell, and the sense amplification circuit being further configured to connect the reference data line with a ground terminal during the sensing operation.
US09257177B2	Write control circuits and write control methods According to various embodiments, a write control circuit configured to control writing to a memory cell by applying a writing current to the memory cell may be provided. The write control circuit may include: a current application circuit configured to apply the writing current to the memory cell; a determination circuit configured to determine whether writing to the memory cell is finished; and a stop writing circuit configured to cut off the writing current from the memory cell if it is determined that writing to the memory cell is finished.
US09257176B1	3D variable resistance memory device and method of manufacturing the same A variable resistance memory device includes a plurality of cell gate electrodes extending in a first direction, wherein the plurality of cell gate electrodes are stacked in a second direction that is substantially perpendicular to the first direction. A gate insulating layer surrounds each cell gate electrode of the plurality of cell gate electrodes and a cell drain region is formed on two sides of the each cell gate electrode of the plurality of cell gate electrodes. A channel layer extends in the second direction along the stack of the plurality of cell gate electrodes, and a variable resistance layer contacting the channel layer.
US09257175B2	Refresh of data stored in a cross-point non-volatile memory Embodiments including systems, methods, and apparatuses associated with refreshing memory cells are disclosed herein. In embodiments, a memory controller may be configured to perform a read operation on one or more memory cells in a cross-point non-volatile memory such as a phase change memory (PCM). The one or more memory cells may have voltage values respectively set to a first threshold voltage or a second threshold voltage. Based on the read, the memory controller may identify the memory cells in the cross-point non-volatile memory that are set to the second threshold voltage, and refresh the voltage values of those cells without altering the voltage values of the memory cells in the cross-point non-volatile memory that are set to the first threshold voltage. Other embodiments may be described or claimed.
US09257171B2	Semiconductor storage apparatus with mask selection gates for data write A semiconductor memory device, including a plurality of pairs of bit lines; a plurality of memory cells coupled to a plurality of word lines and the plurality of pairs of bit lines; a plurality of sense amplifiers each coupled between a corresponding pair of bit lines; a plurality of first driver transistors coupled between at least one of the sense amplifiers and a first power supply line; a plurality of second driver transistors coupled between at least two of the sense amplifiers and a second power supply line; a pair of common data lines; a plurality of column selection gates each coupled between a corresponding one of pair of bit lines and a corresponding one of pair of common data lines, and a plurality of mask selection gates each coupled between a corresponding one of pair of bit lines and a corresponding one of column selection gates.
US09257170B2	Semiconductor devices The semiconductor device includes a pre-internal refresh signal generator and an internal refresh signal generator. The pre-internal refresh signal generator receives a first periodic signal during a refresh operation to generate a pre-internal refresh signal including pulses which are periodically created. The internal refresh signal generator receives a second periodic signal during the refresh operation to generate first and second internal refresh signals sequentially enabled by the pulses of the pre-internal refresh signal.
US09257169B2	Memory device, memory system, and operating methods thereof A memory device, a memory system, and operating methods thereof are provided. The method of operating the memory device, which includes a first memory cell and a second memory cell neighboring the first memory cell, includes counting a disturbance value of the second memory cell each time the first memory cell is accessed, updating a disturbance count value of the second memory cell based on the counting, adjusting a refresh schedule based on the disturbance count value of the second memory cell, a desired threshold and a maximum disturbance count value, and resetting the disturbance count value of the second memory cell and the maximum disturbance count value when the second memory cell is refreshed according to the adjusted refresh schedule.
US09257168B2	Magnetic recording device and magnetic recording apparatus An example magnetic recording device includes a magnetic recording section and a magnetization oscillator and a first nonmagnetic layer disposed between the magnetic recording section and the magnetization oscillator. The magnetic recording section includes a first ferromagnetic layer with a magnetization substantially fixed in a first direction; a second ferromagnetic layer with a variable magnetization direction; and a second nonmagnetic layer disposed between the first ferromagnetic layer and the second ferromagnetic layer. The magnetization oscillator includes a third ferromagnetic layer with a variable magnetization direction; a fourth ferromagnetic layer with a magnetization substantially fixed in a second direction; and a third nonmagnetic layer disposed between the third ferromagnetic layer and the fourth ferromagnetic layer.
US09257163B2	Strobe acquisition and tracking A memory controller includes an interface to receive a data strobe signal and corresponding read data. The data strobe signal and the read data correspond to a read command issued by the memory controller, and the read data is received in accordance with the data strobe signal and an enable signal. A circuit in the memory controller is to dynamically adjust a timing offset between the enable signal and the data strobe signal, and control logic is to issue a supplemental read command in accordance with a determination that a time interval since a last read command issued by the memory controller exceeds a predetermined value.
US09257159B2	Low power memory device A method of operation within a memory device is disclosed. The method comprises receiving address information and corresponding enable information in association with a memory access request. The address information includes a row address that specifies a row of storage cells within a storage array of the memory device, and the enable information includes first and second enable values that correspond respectively to first and second storage locations within the row of storage cells. The method involves selectively transferring data between the first and second storage locations and sense amplifier circuitry according to states of the first and second enable values. This includes transferring data between the first storage location and the sense amplifier circuitry if the first enable value is in an enable state and transferring data between the second storage location and the sense amplifier circuitry if the second enable value is in the enable state. The states of the first and second enable values may be separately controlled.
US09257156B2	Electromagnetic wave signal processor and electromagnetic wave detector There is provided an electromagnetic wave signal processor configured to process an input pulse signal corresponding to an electromagnetic wave, comprising a signal processing unit including: a peak detecting circuit to detect peak values of each amplitude of the input pulse signal; an AD converter to convert the peak values into digital signals; a memory device comprising memory cells each having an address assigned in accordance with each of values capable of being taken by the digital signals of the peak values, and being able to have any one of a plurality of internal states representing detection frequencies of the peak values; and a writing circuit to change the internal state in the memory cell that has the address corresponding to the value of each digital signal converted by the AD converter, so as to increment the detection frequency represented by the internal state.
US09257154B2	Methods and apparatuses for compensating for source voltage Apparatuses and methods for compensating for source voltage is described. An example apparatus includes a source coupled to a memory cell and a read-write circuit coupled to the memory cell. The apparatus further includes a sense current generator coupled to a node of the source and to the read-write circuit, the sense current generator configured to control provision of a sense current by the read-write circuit responsive to a voltage of the node of the source.
US09257153B2	Current monitoring circuit for memory wakeup time A microcontroller system is determining to exit a power saving mode and, in response, enable a reference current source to begin providing a reference current for a memory module. The microcontroller system determines that the reference current has reached a substantial fraction of a target reference current, and, in response to determining that the reference current has reached a substantial fraction of the target reference current, enables the memory module to begin performing one or more memory operations.
US09257147B2	Image processing apparatus and image processing method, and recording medium storing image processing program A novel image processing apparatus that provides effective digitized audio while ensuring audio clarity and outputs image data adding the digitized audio is provided. The image processing apparatus includes an audio recording unit that stores audio data based on input audio in an audio storage device, a data editing unit that adds the audio data to image data, control circuitry that instructs the recording unit to record when a predetermined recording condition is satisfied, and a data output unit to output the image data in an appropriate format. For example, the control circuitry considers a condition that the scanner scans the document set on a platen as the recording condition.
US09257145B1	Disk drive measuring down-track spacing of read sensors A disk drive is disclosed comprising a disk comprising a track, wherein the track comprises a sync mark. The disk drive further comprises a head comprising a plurality of read sensors including a first read sensor, and a second read sensor separated from the first read sensor by a down-track spacing. A first time-stamp (TS1) is generated after detecting the sync mark using the first read sensor as the disk rotates, and a second time-stamp (TS2) is generated after detecting the sync mark using the second read sensor as the disk rotates. A calibration value representing the down-track spacing is generated based on the TS1 and the TS2.
US09257143B1	Precautionary measures for data storage device environmental conditions In preparing to send a write command to store data in at least one Data Storage Device (DSD), a request is sent to the at least one DSD to request environmental information indicating an environmental condition of the at least one DSD. The environmental information is received from the at least one DSD and it is determined whether the environmental information is within a threshold. The write command is sent to the at least one DSD if the environmental information is within the threshold and a precautionary measure is performed if the environmental information is not within the threshold.
US09257142B2	Heat-reactive resist material, layered product for thermal lithography using the material, and method of manufacturing a mold using the material and layered product A heat-reactive resist material of the invention is characterized in that the boiling point of the fluoride of the element is 200° C. or more. By this means, it is possible to achieve the heat-reactive resist material having high resistance to dry etching using fluorocarbons to form a pattern with the deep groove depth.
US09257139B2	Co-located gimbal-based dual stage actuation disk drive suspensions with motor stiffeners Various embodiments concern a gimbaled flexure having a dual stage actuation structure. The flexure comprises a gimbal which includes a pair of spring arms, a pair of struts, and a tongue between the spring arms. A motor is mounted on the gimbal. The motor comprises a top side and a bottom side opposite the top side. The bottom side of the motor faces the flexure. A stiffener is mounted on the top side of the motor. At least one layer of adhesive is located between the stiffener and the motor and bonded to the stiffener and the motor. The gimbaled flexure includes a slider mounting for attaching a slider, such as to the tongue. The motor bends the struts to move the slider mounting about a tracking axis while the stiffener limits the degree of bending of the motor.
US09257134B1	Allowing fast data zone switches on data storage devices Some embodiments described herein are directed to reducing or eliminating latency caused by data zone switches in a rotating magnetic storage device. More specifically, some embodiments described herein are directed to storing parameters associated with different zones in a parameter register in response to one or more received commands.
US09257132B2	Dominant speech extraction in the presence of diffused and directional noise sources A method of dominant speech extraction is provided that includes acquiring a primary audio signal from a microphone and at least one additional audio signal from at least one additional microphone, wherein the acquired audio signals include speech and noise, decomposing each acquired audio signal into a low frequency sub-band signal and a high frequency sub-band signal, applying speech suppression beamforming to the low frequency sub-band signals to generate a reference channel having an estimate of noise in the low frequency sub-band signals, applying noise cancellation to the low frequency sub-band signal of the primary audio signal using the reference channel to generate a first signal having a low frequency estimate of the speech, applying noise suppression beamforming to the high frequency sub-band signals to generate a second signal having a high frequency estimate of the speech, and combining the first and second signals to generate a full-band audio signal.
US09257129B2	Orthogonal transform apparatus, orthogonal transform method, orthogonal transform computer program, and audio decoding apparatus An orthogonal transform apparatus computes either one of the real and imaginary components of the quadrature mirror filter coefficient contained in a first subinterval of a plurality of subintervals among which a coefficient sequence containing a plurality of quadrature mirror filter coefficients is divided so that the values of basis functions are symmetrically placed, by computing a sum of products of the plurality of modified discrete cosine transform coefficients and the basis functions corresponding to the subinterval, computes the other one of the real and imaginary components of the quadrature mirror filter coefficient contained in the first subinterval and the real and imaginary components of the quadrature mirror filter coefficient contained in another subintervals by performing a butterfly operation using a computed value produced as a result of the sum of products and computes each quadrature mirror filter coefficient by combining the real component and imaginary component thereof.
US09257126B2	Method and system for lossless value-location encoding A method of encoding samples in a digital signal is provided that includes receiving a frame of N samples of the digital signal, determining L possible distinct data values in the N samples, determining a reference data value in the L possible distinct data values and a coding order of L−1 remaining possible distinct data values, wherein each of the L−1 remaining possible distinct data values is mapped to a position in the coding order, decomposing the N samples into L−1 coding vectors based on the coding order, wherein each coding vector identifies the locations of one of the L−1 remaining possible distinct data values in the N samples, and encoding the L−1 coding vectors.
US09257119B2	Telephony system with a background recapitulation feature A telephony system comprising means to establish an initial telephone call (1) between at least two initial telephone terminals (2, 3) characterized in that it further comprises: a call recording server (5) designed to record said initial telephone call (1), a speech to text engine (6) able to make a text transcription (9) of said initial telephone call (1), a providing mean (7) able to provide said text transcription (9) to a third telephone terminal (4).
US09257114B2	Electronic device, information processing apparatus,and method for controlling the same The present invention provides a technology for enabling a natural voice reproduction in which, depending on a gazed character position, a position of a voice output character follows but not excessively reacts with the gazed character position. Therefore, in an electronic device provided with a display unit for displaying text on a screen, a voice outputting unit for outputting the text as voice, and a sight-line detection unit for detecting a sight-line direction of a user, a control unit changes a starting position at which a voice outputting unit starts voice output if a distance between the position of the current output character and the position of the current gazed character is a preset threshold or more.
US09257113B2	Method and system for active noise cancellation From at least a first microphone, first microphone signals are received that represent first sound waves. From at least a second microphone, second microphone signals are received that represent second sound waves. In response to the first microphone signals, first noise in the first sound waves is estimated, and first cancellation signals are output for causing a speaker array to generate first additional sound waves via at least a first acoustic beam for cancelling at least some of the first noise. In response to the second microphone signals, second noise in the second sound waves is estimated, and second cancellation signals are output for causing the speaker array to generate second additional sound waves via at least a second acoustic beam for cancelling at least some of the second noise.
US09257111B2	Music analysis apparatus A music analysis apparatus calculates a similarity index based on an edit distance between a designated sequence of notes designated by a user and a reference sequence of notes of a reference piece of music. The edit distance is calculated by setting a substitution cost between a first note in the designated sequence of notes and a second note in the reference sequence of notes to a first value when one of the first note and the second note corresponds to any of a plurality of notes contained in a tolerance interval containing the other of the first note and the second note, and by setting the substitution cost to a second value different from the first value when one of the first note and the second note does not correspond to any of the plurality of notes contained in the tolerance interval.
US09257110B1	Torque suppressor Disclosed is a torque suppressor for bodies having a forward assembly comprising an extension having a rear-portion, a mid-portion, and a fore-portion, wherein the fore-portion is configured to attach to the forward assembly, the rear-portion is configured to attach to the body at a forward point of attachment, and the mid-portion is configured to attach to a first end of a shoulder strap, the shoulder strap having a second end configured to attach to a rear point of attachment of the body. The device is effective in eliminating neck dive.
US09257109B2	Eyebolt bracket assembly Eyebolt mounting devices are disclosed. In an aspect, the present disclosure provides an eyebolt bracket assembly for mounting a musical instrument to a rod. The assembly has a bracket having a first side having a first opening, a second side having a second opening, and a top side having a third opening. The bracket houses an eyebolt member having a threaded portion and an eye opening portion. The eye opening portion has an eye opening, an outer surface, and inner surface. A spring is disposed on the threaded portion and to apply a variable tension force to the eyebolt member. The threaded portion passes through the third opening and receives a washer and a fastener. The eyebolt member is held to the bracket by the fastener and is movable within the bracket.
US09257107B1	Musical drumhead with tonal modification A musical drum comprised of a drumshell and a drumhead, which includes a composite of tonal modifiers acting synergistically for dampening drum sounds by eliminating high frequencies and overtones. The tonal modifiers include a first tonal modifier comprised of synthetic material, a second tonal modifier bonded to the synthetic material in overlaying relation, a third tonal modifier positioned upon the second tonal modifier in overlaying relation, and a fourth tonal modifier bonded to the central portion of the third tonal modifier in overlaying relation, the combination of which cooperate to break down the various levels of harmonics to their purest form resulting in a unique sound and vibrational experience provided in a therapeutic context for the well-being of a person.
US09257105B1	C# mechanism for flutes and piccolos A wind-blown instrument tone hole configuration is provided. Further, a key mechanism to operate the instrument is provided to allow various opening and closing of the instrument tone holes.
US09257103B2	Guitar back plate A back plate attachable to the back of a guitar is provided. The plate includes screw holes and tremolo plate holes. The screw holes of the plate align with the screw holes on a guitar, and the tremolo plate holes of the plate align with the tremolo claw holes of a tremolo claw. The plate may be bolted or screwed to the back of the guitar via the screw holes and tremolo claw holes.
US09257094B2	Projection display device, projection display method, and computer program A projection display device according to the invention includes a separating unit that assigns X separation information for identifying a type of an image to each pixel by using a characteristic amount of the input image, a luminance detecting unit that detects a luminance of a screen, a first determining unit that determines a first target region indicating a region on which halftone processing of converting the number of gradations is performed on the input image by using the X separation information, and a halftone processing unit that executes the halftone processing that varies depending on the luminance on the first target region.
US09257093B2	Image display apparatus and image adjusting method An image display apparatus includes: an image signal processing unit which adjusts an input grayscale values included in an input image signal according to a predetermined grayscale characteristic; a display unit which displays an image based on an image signal included in an output grayscale value adjusted by the image signal processing unit; and a grayscale characteristic changing unit which changes a correlation between the input and output grayscale values defined based on the grayscale characteristic.
US09257084B2	Shift register unit and gate driver circuit Provided are a shift register unit and a gate driver circuit, which are configured to suppress output errors caused by the drifts in the threshold voltages and the interval existed in the operation of pulling the output terminal, and thus to enhance stability of the shift register unit. The shift register unit comprises: an input module, a first output module, a pull-down driving module, a pull-down module and a first output discharging unit. The pull-down driving module is connected to the first clock signal input terminal and the second clock signal input terminal, and configured to provide the first clock signal to a first pull-down node in response to the first clock signal, provide the second clock signal to a second pull-down node in response to the second clock signal, provide a first low voltage signal to the first pull-down node and the second pull-down node in response to the voltage signal at the pull-up node, provide the first low voltage signal to the second pull-down node in response to a voltage signal at the first pull-down node, and provide the first low voltage signal to the first pull-down node in response to a voltage signal at the second pull-down node.
US09257083B2	Self-healing gate driving circuit having two pull-down holding circuits connected via a bridge circuit The claimed invention is related to a self-healing gate driving circuit. The self-healing gate driving circuit includes a plurality of GOA units connected in cascade. The N-th level GOA unit includes a pull-up control circuit 100, a pull-up circuit 200, a transfer-down circuit 300, a pull-down circuit 400, a boast capacitor 500, a first pull-down holding circuit 600, a second pull-down holding circuit 700 and a bridge circuit 500. The bridge circuit 800 includes the first TFT T55, and the gate of the TFT T55 connects to the gate signal point Q(N), and the drain and the source of the TFT T55 respectively connects to the first circuit point K(N) and the second circuit point P(N). During the operation, the first circuit point K(N) and the second circuit point P(N) are alternatively configured to be at a high potential. The self-healing gate driving circuit of the claimed invention can decrease the failure risk of the pull-down holding circuit due to the manufacture process or a long term operation of GOA circuit, and perform the function of the circuit self-healing.
US09257082B2	Display device and electronic device A display device including a pixel having a memory. The pixel includes at least a display element, a capacitor, an inverter, and a switch. The switch is controlled with a signal held in the capacitor and a signal output from the inverter so that voltage is supplied to the display element. The inverter and the switch can be constituted by transistors with the same polarity. A semiconductor layer included in the pixel may be formed using a light-transmitting material. Moreover, a gate electrode, a drain electrode, and a capacitor electrode may be formed using a light-transmitting conductive layer. The pixel is formed using a light-transmitting material in such a manner, whereby the display device can be a transmissive display device while including a pixel having a memory.
US09257080B2	Display panel driving circuit and display device A scanning line driving circuit includes an arithmetic circuit for generating an operation result for specifying a unit register for outputting an output signal by means of an arithmetic process on an output number control signal for specifying the number of signals to be outputted. An input stage of each unit register is provided with a signal control circuit for controlling whether to allow the unit register to output an output signal based on the operation result.
US09257076B2	Pixel driving method and liquid crystal display implementing the same A pixel driving method is adapted for a liquid crystal display. Each pixel includes a first sub-pixel and a second sub-pixel, in which the first sub-pixel and the second sub-pixel each includes a first display region and a second display region. The pixel driving method includes providing a first voltage to the first displaying region of the first sub-pixel and the second sub-pixel; providing a second voltage to the second displaying region of the first sub-pixel and a third voltage to the second displaying region of the second sub-pixel; and when the provided first voltage is larger than a predetermined voltage, providing the second voltage so that the provided second voltage is smaller than the provided third voltage.
US09257075B2	Liquid crystal display apparatus and method for controlling the same The light sources are controlled by dividing a display period of one frame into such a first subframe period that blue transmitted light is obtained from the blue subpixel and red transmitted light is obtained from the red subpixel by turning ON the light sources of the blue color and the red color and such a second subframe period that green transmitted light is obtained from the green subpixel by turning ON a light source of a green color and at least any one of a procedure in which cyan transmitted light is obtained from the blue subpixel and a procedure in which yellow transmitted light is obtained from the red subpixel is performed.
US09257072B2	Power control device and method for a display device Disclosed is a power control device for a display device, including: a current scaling factor calculation unit calculating a current scaling factor according to an input data signal and a load of the input data signal; a data scaling unit generating a data scaling factor based on the current scaling factor and scaling a data signal corresponding to light emitting gradation of a pixel; and a gamma scaling unit generating a gamma scaling factor based on the current scaling factor and scaling a gamma value for gamma correction of a data signal.
US09257069B2	Organic light emitting diode display and method of driving the same A controller for a display panel may include a first supply circuit to output first and second driving voltages to a sub-pixel of a first color; and a second supply circuit to output third and fourth driving voltages to a sub-pixel of a second color. The first driving voltage may be greater than the second driving voltage, and the third driving voltage may be greater than the fourth driving voltage. Also, at least three of the first, second, third, and fourth driving voltages may be different from one another.
US09257068B2	Organic light emitting display device including a redundant element for a test gate line An organic light emitting display device according to example embodiments includes a display unit, a test data line to which a test data voltage is applied during a sheet unit test, a test gate line to which a first voltage is applied during the sheet unit test and to which a second voltage is applied during a normal operation of the organic light emitting display device, a plurality of test transistors configured to selectively couple the test data line to a plurality of data lines in the display unit in accordance with a voltage provided by the test gate line, and at least one redundant element configured to maintain the test gate line at the second voltage during the normal operation even if the test gate line is damaged.
US09257065B2	Liquid crystal display apparatus comprising first and second grounding routes and manufacturing method of the liquid crystal display apparatus A liquid crystal display apparatus includes: a display device a first substrate having a pixel electrode and a reference electrode, a second substrate facing the first substrate; a flexible substrate; a housing that accommodates the display device; a transparent conductive film that is formed on a surface of the second substrate; a first conductive member and a second conductive member, wherein one end portion of the first conductive member and one end portion of the second conductive member are connected to the transparent conductive film; a first grounding route, which is configured by at least the first conductive member that is connected to a grounding wiring formed at the peripheral part of the first substrate and the flexible substrate; and a second grounding route, which is configured by at least the second conductive member that is connected to the housing.
US09257059B2	Dynamic appearance-changing optical devices (DACOD) printed in a shaped magnetic field including printable fresnel structures A device includes a substrate and at least 1,000 flakes resting upon the substrate, each flake including a magnetic layer. The plurality of flakes are aligned so as to form a plurality of rings or curves, wherein within each ring or curve, flakes are tilted at a same angle with respect to the substrate and planes extending from surfaces of said flakes intersect with one another. The device provides a visible image of a single ring or curve when illuminated with a single light source, and three rings or curves are visible when three light sources illuminate the device. The device may be used as a printed light detector.
US09257057B2	Bedding product with age indicator A mattress age indicating device (10) includes an enclosure (20) and an indicating assembly (30) contained within the enclosure (20). The age indicating device (10) may be configured to present an indication related to the mattress's age and may be coupled to the mattress (2) or other bedding or seating product.
US09257056B2	Proactive user-based content correction and enrichment for geo data A system and method determines ambiguous or missing information about map features, generates questions to address the ambiguity or the missing information and determines users from whom to request feedback to clarify the ambiguity or supply the missing information.
US09257055B2	Small intestine endoscope training simulator It is possible to provide a small intestine endoscope training simulator (11) which allows to obtain a feeling similar to that of inserting an endoscope (38) into the small intestine (34) of the living body (30) and learn the actual operation of the endoscope (38). This training simulator (11) includes a plurality of longitudinal elastic members (32) for applying an elastic force to each of a plurality of portions of a simulated small intestine (13). One end portion sides of the plurality of longitudinal elastic members (32) are respectively attached to the first attachment portions (27) on the simulated small intestine (13) side. The other end portion sides of the plurality of longitudinal elastic members (32) are respectively attached to the second attachment portions (33, 57) on the case (12) side.
US09257049B2	Method for management of air traffic control center database used for air traffic control center logon An avionics system includes a human-machine interface (HMI), wherein the HMI includes a display device that displays information to an operator and an input device that receives input from an operator; a storage device that stores master air traffic control (ATC) center data; a memory device that stores separately loaded ATC center data and hard-coded ATC center data, and a processing device communicatively coupled to the HMI, the storage device and the memory device. The processing device compares the separately loaded ATC center data with the hard-coded ATC center data; requests operator validation of changes between the separately loaded ATC center data and the hard-coded ATC center data using the HMI; and updates the master ATC center data when the operator validates the changes between the separately loaded ATC center data and the hard-coded ATC center data.
US09257046B2	Method and device for cooperatively based navigation A method for navigation by road users in the area of a traffic congestion, includes the steps of determining a group of road users in the area of the traffic congestion, who are users of a predetermined service, the capturing of travel data of the members of the group, the determining of driving maneuvers for the members of the group based on the captured driving data and the outputting the driving maneuvers to the associated members of the group. The driving maneuvers are coordinated with one another, in order to reduce the effects of the traffic congestion for the members of the group.
US09257045B2	Method for detecting a traffic lane by means of a camera A method of detecting a roadway edge and/or a traffic lane on a roadway includes: acquiring at least one image of surroundings of a vehicle with a camera; detecting a driving corridor from the at least one image; and performing a structure detection on the at least one image while taking the determined driving corridor into consideration in order to determine a course of a roadway edge from the at least one image.
US09257044B2	Navigation device and method A navigation device is disclosed including a processor; and a store containing map data. In at least one embodiment, the map data includes a temporally-variable feature and the processor is arranged, in a route planning process, to determine a status of the temporally-variable feature according to temporal information.
US09257033B2	Emergency response system and method An improved emergency response system and method includes at least one zone display structured to present a plurality of zones that convey certain information to bystanders, dispatchers, and/or emergency responders. Each zone corresponds to a different portion of the local premises, such that the zones are collectively configured to convey at least directional information pertaining to the local premises. The zone display is further configured to present at least one universal directional indicator associated with each zone. Accordingly, the information associated with the zones and directional indicators is utilized to facilitate an emergency response. The presenting of the zones can include depicting at least a portion of the premises via mapping overlay display. Further, the zone displays can depict threat level indicators corresponding to perceived circumstances of one or more zones.
US09257022B2	Haptic effect conversion system using granular synthesis A system is provided that converts an input, such as audio data, into one or more haptic effects. The system applies a granular synthesis algorithm to the input in order to generate a haptic signal. The system subsequently outputs the one or more haptic effects based on the generated haptic signal. The system can also shift a frequency of the input, and also filter the input, before the system applies the granular synthesis algorithm to the input.
US09257021B2	Systems and methods for optically induced cutaneous sensation The present disclosure relates to systems and methods for inducing a cutaneous sensation in a user of an electronic device. Such systems and methods may include a stimulation system configured to generate an output operable to excite neural tissue. An interface component may be configured to direct the output of the stimulation system onto a target area of skin of the user, and a controller may be configured to generate a control signal to cause the stimulation system to modify one or more characteristics of the output of the stimulation system in order to induce a cutaneous sensation. The cutaneous sensation may be based on a tactile application executable on the electronic device that is configured to generate a representation of a simulated object. Further, a stimulation profile may represent at least one present stimulation area and at least one prior stimulation area.
US09257020B2	Notification of access control request and explanation indicative of the access control request on a communication device A communication device includes a display screen upon which information is displayed. A microprocessor configured to execute at least one notification program is provided that displays a notification descriptive of an access control request on the display screen. The at least one notification program is programmed to receive data indicative of an access control request and to receive data descriptive of the access control request. Additionally, the at least one notification program is further programmed to display a notification indicative of the access control request and comprising an explanation of the access control request based on the received descriptive data.
US09257019B2	Method and apparatus for generating an audio notification file A method and apparatus for generating an audio notification file for a computing device are provided. A first audio file associated with a first mental state is selected as a first section of the audio notification file. The audio notification file enabled for storage in a memory. The audio notification file is further enabled for processing by a processing unit to control a speaker. A final state of the audio notification file is determined, the final state designated as a final section of the audio notification file, the final state associated with a second mental state. At least one intermediate section of the audio notification file is generated, between the first section and the second section, by morphing the first audio file to the final state by processing the first audio file using a digital signal processor.
US09257017B2	Gaming system and method for providing a multiple dimension cascading symbols game A gaming system including a cascading symbol game which utilizes a plurality of adjacent symbol display position grids arranged at different depths. The multiple symbol display position grids at different depths provides that one or more of the symbols of at least a first symbol display position grid at a first depth are displayed to a player while one or more of the symbols of at least a second symbol display position grid at a second depth are not displayed to the player. When one or more symbols are removed from the first symbol display position grid at the first depth, before and/or after shifting the remaining displayed symbols from the first symbol display position grid into created empty symbol display positions of the first symbol display position grid, one or more symbols from the second symbol display position grid at the second depth become exposed.
US09257014B1	Events for selected wagering game machines in a wagering game establishment A computerized method includes creating an event associated with a number of wagering game machines in a wagering game establishment, wherein the event is configured to provide an award comprising at least one of better pay tables, a number of free spins, unlocked content, and a jackpot award. The method also includes identifying persons to notify about the event prior to a time of the event. The method includes creating an event notification to notify the persons of the event. The method also includes outputting the event notification to the persons through a network communication using at least one of a social networking website, a micro-blogging website, text messaging, and an email.
US09257013B2	Facilitation of gaming event re-creation For facilitating re-experience of an event of a gaming device with a player, data is sampled from the gaming device by a gaming system having supervisory hierarchical control over the gaming device, the data provided by the gaming system to a data processing device in communication with the gaming system, that is external to the gaming device. The sampled data is processed to create a facsimile animation recreation of the event at a subsequent time.
US09257012B2	Gaming system and method enabling player participation in selection of seed for random number generator A gaming system which utilizes a random number generator where the process of selecting one or more seeds for the random number generator includes participation of a player. In one embodiment, the player picks one of a plurality of displayed selections at a gaming device. Each selection is associated with a different external steeling source of data not controlled by the gaming system. A gaming system gathers, the data torn the external seeding sources associated with the different seeds. The gaming system uses the data gathered from the seeding source associated with the player's picked selection to determine one or more seeds. The determined seeds are used to initialize a random number generator, which generates one or more numbers and at least in part determine the outcome of the game.
US09257010B2	Gaming system and method for enabling a player to accept or reject a progressive award A gaming system which enables a player to exchange progressive awards of corresponding progressive award levels of different multi-level progressive award (“MLP”) configurations. Following the gaming system determining a progressive award of a specific progressive award level of a specific MLP configuration, the gaming system enables the player to accept that determined progressive award or forfeit that determined progressive award for another progressive award of a corresponding progressive award level of a different MLP configuration. The gaming system thus enables a player to swap or replace one progressive award of one progressive award level of one MLP configuration for a different progressive award of a corresponding progressive award level of a different MLP configuration. Such a configuration provides an increased level of excitement and enjoyment for certain players because the player's individual decisions regarding which progressive award offers to accept or reject determine which progressive award the player is ultimately provided.
US09257006B2	Dynamic updating of content based on gaming-application context A wagering game system and its operations are described herein. In some embodiments, the operations can include receiving first application data from a first application, where the first application data describes a first characteristic of first content from the first application. The first application presents the first content during a wagering game session. The operations can further include determining a relationship between the first characteristic and a second characteristic of second content of a second application that presents the second content during the wagering game session while the first application presents the first content. The operations can further include modifying the second content dynamically based on the relationship between the first characteristic and the second characteristic.
US09257005B2	Input/output overlays for facilitation of gaming event re-creation For facilitating re-experience of an event of a gaming device with a player, upon a triggering mechanism associated with an event, an input/output (I/O) mechanism is overlaid on the gaming device using a system device in communication with the gaming device. Through use of the I/O mechanism, input is received from the player and output is returned to the player. The I/O mechanism overlaying the gaming device is then removed.
US09257000B2	Method and system for varying the take-out or rake rate on wagers placed in a wagering pool In a method of wagering, one or more primary bettors place wagers having an applicable base take-out or rake rate, and thus yielding a base payout for winning wagers. One or more secondary bettors may place wagers having an applicable modified take-out or rake rate (preferably lower than the base take-out or rake rate), thus yielding a higher payout for winning wagers than the base payout. The wagering may occur relative to card games such as poker, or other types of games or events, including sports betting. Bets may be placed with a host, such as a casino or track, or an off-track entity.
US09256996B2	Method and system for training users related to a physical access control system A system and method for training users of an access control system. In particular, the system and method allow for the imposition of “penalties” for improper behavior so as to balance the training of the user with the burden placed on the operators of the system reacting to violations, while allowing the users to accomplish their tasks. The system can also track the location of users or items, determine if a request to pass through a control point is proper based on various factors, and if appropriate, administer a “penalty” based on several contributing factors.
US09256995B2	Apparatus for diagnosing driving behavior, method for diagnosing driving behavior, and program thereof An apparatus for diagnosing driving behavior includes a storage unit that stores ideal running information defining a relationship between a vehicle speed and a vehicle position corresponding to a road situation, a generation unit that generates actual running information expressing a relationship between an actual vehicle speed and an actual position when a vehicle passes through a road, a condition identification unit that identifies a matching condition where the degree of correlation of the actual running information with the ideal running information exceeds a predetermined value, and a diagnosis unit that diagnoses a driving behavior of a driver of the vehicle, based on a degree of similarity between the ideal running information and the actual running information under the matching condition identified in the condition identification unit.
US09256991B2	Automobile monitoring for operation analysis An automobile monitoring arrangement tracks and records automobile operation for post-use automobile operation analysis and in a manner with default-operation modes that facilitate use by automobile owners/supervisors and by those supervised by the automobile owners/supervisors. In one specific embodiment, sounds from the vehicle are monitored while the vehicle is in operation. A sound type is identified as corresponding to the sounds, and a sound level of the sound types are determined. The sound level is compared to a threshold for the sound type, and a vehicle supervisor is notified when the sound level exceeds the sound level threshold for the sound type.
US09256990B2	Apparatus for detecting inadequate maintenance of a system Apparatus 10 for detecting inadequate maintenance of a system 12 of an aircraft or other vehicle is provided. The apparatus comprises: computer readable medium or media 14 configured to store data 18 relating to operation or non-operation of the system 12 over a period of time; and a data processing unit 16 configured to evaluate the data to identify at least one event indicative of the inadequate maintenance of the system.
US09256989B2	Information provision device for use in vehicle A first driving instability determining unit estimates driving instability based on a difference value between plural traveling state distributions of different time ranges on the basis of the traveling state data. A second driving instability determining unit estimates driving instability by a process different from the process used in the first driving instability determining unit. A learning completion determining unit determines that the learning is completed when a predetermined learning time elapses from the start of collection of the traveling state data, depending on a degree of learning at which the traveling state distribution calculated by a first traveling state distribution calculating unit is matched with the driving characteristic of a driver. An instability selecting unit selects the instability estimated by the first driving instability determining unit when the learning is completed and selects the instability estimated by the second driving instability determining unit when the learning is not completed.
US09256988B2	System and method for identifying a power tool A system for identifying a type of a power tool, the system comprising: a power tool having an electric motor; and a usage attachment configured to couple to the power tool, the usage attachment having a vibration sensor that generates vibration data when the power tool vibrates, a memory that stores the vibration data generated by the vibration sensor, and an identification subsystem that receives the vibration data from the memory, and identifies the type of the power tool by comparing the received vibration data to predetermined vibration data of a known type of power tool.
US09256981B2	Method and device for processing geological information A method and a device for processing geological information is disclosed. The method for processing the geological information includes acquiring multiple geological image graphs, determining the relation between the image coordinate and the ground coordinate of each of the multiple geological image graphs by an imaging mode of geological images, and joining the multiple geological image graphs together according to the relation between the image coordinate and the ground coordinate of each of the multiple geological image graphs. Accordingly, large-scale ground images can be acquired by processing the geological images.
US09256976B2	Techniques for extracting and displaying partially processed graphics information Various embodiments are generally directed to an apparatus, method and other techniques receiving graphics information in a graphics processing stream and applying vertex processing and topology processing to the graphics information in the graphics processing stream to generate vertex information and topology processing information. The vertex information associated with the graphics processing stream may be identified based on one or more identifiers and sent from the graphics processing stream to a buffer for a display controller.
US09256975B2	Graphics processing systems An “accumulation buffer” process in a graphics processing system is carried out not by rendering each sub-frame making up the accumulated frame in its entirety in turn, but by subjecting each individual tile 2, 3, 4 and 5 making up the accumulated frame to the sequence of different rendering passes individually. Thus, for each individual tile making up the accumulated frame, several sub-tiles (e.g. 2′, 2″, 2′″ and 2″″) are generated in turn and accumulated together to provide a final accumulation tile (2ACC) that is output as the accumulated version of the tile in question. This is then repeated for each of the remaining individual tiles 3, 4 and 5 making up the accumulated frame 1, and the individual accumulated tiles 2ACC, 3ACC, 4ACC and 5ACC are combined together to provide the output accumulated frame 6.
US09256971B1	Methods and apparatus for data visualization of hierarchical data structures Methods and apparatuses for creating an output graphic using a processing device may include receiving one or more elements of a hierarchical data structure, wherein each of the one or more elements includes a value. In addition, the methods and apparatuses may include calculating a total value for the hierarchical data structure by adding the value from the one or more elements and creating relationships that associate the one more elements with the total value. The methods and apparatuses may also include generating a diagram to illustrate the total value and the relationships among the one or more elements and the total value and transmitting the diagram for presentation on a display.
US09256966B2	Multiparametric non-linear dimension reduction methods and systems related thereto Featured are methods and systems to multiparametric non-linear dimension reduction (NLDR) methods for segmentation and classification of radiological images. Such methods for segmentation and classification of radiological images, includes pre-processing of acquired image data; and reconstructing the acquired image data using a non-linear dimension reduction technique so as to yield an embedded image representing all of the acquired, where the acquired image data comprises a plurality of different sets of image data of the same region of interest. Such NLDR methods and systems are particularly suitable for the ability to combine multiple input images into a single unit for increased specificity of diagnosis.
US09256965B2	Method and apparatus for generating a derived image using images of different types Disclosed herein are techniques for translating a first image of a first type to a derived image of a second type. For example, a plurality of similarity indicators can be computed as between a plurality of patches of first image and a plurality of patches of a first atlas image, the first atlas image being of the first type. Weight factors can then be computed based on the computed similarity indicators. These weight factors can be applied to a plurality of data points of a second atlas image to compute a plurality of data points for the derived image such that each of at least a plurality of the data points for the derived image is a function of a plurality of the data points of the second atlas image. Such a technique can be used for pseudo-CT generation from an MR image.
US09256964B2	Electronically documenting locate operations for underground utilities A technician performs a locate operation of an underground utility in a dig area of proposed excavation by applying one or more physical colored markers (e.g., paint, flags, other colored markers) to ground, pavement or other surface to indicate a presence or an absence of the underground utility in the dig area. A digital image of a geographic area comprising the dig area is displayed on a display device, and one or more electronic colored markers corresponding to the physical colored marker(s) are added to the displayed digital image so as to generate a marked-up image. Information relating to the marked-up image is electronically transmitted and/or electronically stored so as to document the locate operation.
US09256962B2	Personalizing medical conditions with augmented reality Augmented reality is used to simulate the impact of medical conditions on body parts and other objects within images taken of the objects. The simulations enable a user to see how a medical condition can affect the user by dynamically simulating the impact of the medical condition on captured images of body parts associated with the user in real-time. A user can select different medical conditions that are associated with different body parts. These objects are then identified within images containing the body parts using image recognition algorithms and/or user input. Thereafter, the images are modified so as to render the body parts as though the body parts were being impacted by the medical condition. The modifications are made by blending image data of the captured image with condition image data available to the processing system.
US09256958B2	Active attentional sampling method for accelerating background subtraction An active attentional sampling technology for accelerating background subtraction from input videos, more specifically, an active attentional sampling technology for accelerating background subtraction by removing background region from the input video and then applying foreground probability map and sampling mask according to temporal property, spatial property and frequency property of the input video in favor of the pixel-wise background subtraction algorithm is provided. The background subtraction is accomplished by generating active attentional sampling mask for input video and then processing each frame of the input video only for regions corresponding to the sampling mask, which renders the background subtraction be much accelerated. That is, the present invention successfully speeds up pixel-wise background subtraction methods approximately 6.6 times without deteriorating detection performance. Therefore, according to the present invention, real-time detection with full-HD video is successfully achieved through various conventional background subtraction algorithms.
US09256957B1	Method for moving-object detection tracking identification cueing of videos A system and method for tracking a spherical ball is presented. A system includes grayscale conversion logic configured to convert an input image into a grayscale image. Motion detection logic detects motion of the ball in the grayscale image and generates a motion likelihood image output. Template matching logic template matches the input image and generates a template likelihood image output indicating where the ball is in the grayscale image. Color matching logic color matches the ball to the input image and generates a color space likelihood image. Fusion logic produces a final fused likelihood image output based on the motion likelihood image output, template likelihood image output and color space likelihood image output. Ball localization logic generates a ball location value and a confidence based on finding an optimal value in the final fused likelihood image output.
US09256955B2	System and method for processing visual information for event detection A system and method processes visual information including at least one object in motion. The visual information is processed by locating at least one spatial edge of the object, generating a plurality of spatio-temporal gradients for the at least one spatial edge over N frames, and then generating motion blur images from the spatio-temporal gradients. A regression analysis is performed on the motion blur images to determine direction of motion information of the object, and scene activity vectors are then generated for the N frames based on the direction of motion information. An event is detected in the visual information based on the scene activity vectors.
US09256954B2	Image analysis apparatus to analyze state of predetermined object in image An image-capture device 1 includes: an image acquisition unit 111 that acquires a plurality of images that are successively captured; an identification unit 112 that identifies a golf ball B as a predetermined object in each of the plurality of images; a rotation calculation unit 113 that calculates the number of rotations of the predetermined object; a movement amount calculation unit 114 that calculates a total movement amount that the golf ball B has moved; and a slippage amount calculation unit 115 that calculates a slippage amount based on the number of rotations as well as the total movement amount.
US09256949B2	Region growing apparatus and method using multi-core A region growing apparatus using multi-core includes a plurality of cores, each core including an operation controller configured to perform an operation for region growing of a 2D pixel region or 3D pixel region and an inner memory configured to store a queue associated with a seed pixel as a target of the operation; and a shared memory connected to the plurality of cores over a network and shared by the plurality of cores.
US09256944B2	Integration of optical area monitoring with industrial machine control An industrial safety system is provided that integrates optical safety monitoring with machine control. The safety system includes an imaging sensor device supporting pixel array processing functions that allow time-of-flight (TOF) analysis to be performed on selected portions of the pixel array, while two-dimensional imaging analysis is performed on the remaining portions of the array, reducing processing load and response time relative to performing TOF analysis for all pixels of the array. The portion of the pixel array designated for TOF analysis can be pre-defined through configuration of the imaging sensor device, or can be dynamically selected based on object detection and classification by the two-dimensional imaging analysis. The imaging sensor device can also implement a number of safety and redundancy functions to achieve a high degree of safety integrity.
US09256941B2	Microcalcification detection and classification in radiographic images An analysis of a digitized image is provided. The digitized image is repeatedly convolved to form first convolved images, which first convolved images are convolved a second time to form second convolved images. Each first convolved image and the respective second convolved image representing a stage, and each stage represents a different scale or size of anomaly. As an example, the first convolution may utilize a Gaussian convolver, and the second convolution may utilize a Laplacian convolver, but other convolvers may be used. The second convolved image from a current stage and the first convolved image from a previous stage are used with a neighborhood median determined from the second convolved image from the current stage by a peak detector to detect peaks, or possible anomalies for that particular scale.
US09256940B2	Vascular outlining with ostia visualization An apparatus and a related method of processing a 2D projection image (110a-b) taken of a tubular structure comprising two or more tubes. One of the tubes branches off from the other at a sidewall opening. The apparatus is configured to estimate a position of the sidewall opening. The estimation is based on a segmentation of the one or more projection images. A marker for the estimated position of the sidewall opening can be displayed overlaid on the projection image.
US09256937B2	Assessing peripheral vascular disease from a thermal image What is disclosed is a system and method for assessing peripheral vascular disease from a thermal image captured using a thermal imaging system. In one embodiment the present method involves the following. First, a thermal image is received of a region of exposed skin of a peripheral body part of a subject being monitored for PVD. The thermal image was acquired by a thermal imaging system. Pixels in the thermal image each have a corresponding temperature value. The thermal image is analyzed to stratify the peripheral body part into a plurality of skin surface regions. A skin surface temperature for each respective skin surface region is identified based on pixels in the thermal image associated with those regions. The temperatures are then extracted such that a progression of temperatures can be ascertained. A method for forecasting the progression for future times is also disclosed.
US09256933B2	System for determining flow properties of a blood vessel The invention relates to a method for providing quantitative measures of the flow property of a blood vessel. The method is based on analyzing cross-sectional images of a vessel by estimating the area of the lumen of the vessel. The method comprises steps of determining a point contained within the walls of the vessel, determining a closed path which approximates the inner circumference of the wall of the vessel, and determining the area of the closed path when the vessel is most expanding in order to get a measurement of the maximum lumen. This method may enable the clinical personnel to quickly evaluate the flow property e.g. of an inserted bypass vessel and, thereby, conclude if the surgical intervention is successful or if adjustments are required.
US09256914B2	Graphic card for collaborative computing through wireless technologies A graphics card is provided. The graphics card comprises: a Graphics Processing Units (GPU) for data computing; and a wireless controller for wirelessly receiving data from other graphic cards or sending data to the other graphics cards, and communicating with the GPU by bus. The graphic card able provided by the present invention can provide a low-cost solution with more powerful computing capabilities to meet the demands for computing complex problems in the fields of commerce, industry, and science.
US09256913B2	Information processing apparatus, control method thereof, and program An information processing apparatus which causes a printing apparatus to print an image to which information is added, includes a causing unit for causing, when a setting is specified for adding information to an image and the information cannot be acquired from a router, the printing apparatus not to print the image, and for causing, when a setting is specified for adding information to an image and the information can be acquired from a router, the printing apparatus to print an image to which the acquired information is added.
US09256909B2	Scientific information management method A scientific information management system is provided. It comprises a server, and at least one content server connected to the registration server to provide networking services to a plurality of users through a network, said at least one content server comprising data comprising scientific information of experimental research projects, wherein said system comprises: —a plurality of user interfaces, at least one of them comprising means for submitting data comprising first scientific information together with a status identifying the degree of accomplishment of said project; —a data processor connected to said plurality of user interfaces, said data processor being capable of processing said data retrieved from said at least one content server to generate at least one representation of the relative position of said first scientific information compared to others scientific information and the status of said first scientific information and display said representation on the user interface.
US09256907B2	Multiple field boundary data sets in an automated crop recordkeeping system A method includes defining a plurality of crop field boundaries such that an area of land falls within each of the plurality of field boundaries. The method further includes maintaining the plurality of crop field boundaries within the crop recordkeeping system, using a first of the crop field boundaries in performing a first function of the crop recordkeeping system executing on a computer, and using a second of the crop field boundaries in performing a second function of the crop recordkeeping system executing on the computer.
US09256906B2	Systems and methods for sensor-enhanced activity evaluation Systems and methods are discussed for providing sensor enhanced safety, recovery, and activity evaluation systems. Sensors that monitor user activity and behavior are worn by a user and/or placed in the user environment. Data from the sensors are processed to obtain a safety, recovery, and/or activity evaluation. Based on the evaluation, recommendations or adjustments to the terms of an insurance policy covering the user, the user's employer, or a facility providing health care to the user to accurately reflect the risks associated with the user, employer, and/or facility.
US09256904B1	Multi-bureau credit file freeze and unfreeze The systems and methods described herein allow consumers to lock or unlock their credit files at multiple credit bureaus in real-time or near real-time. The service may allow a consumer to provide identifying information, such as a personal identifier to lock or unlock credit files at a plurality of credit bureaus over a network. Upon receiving the personal identifier, the system may use the personal identifier to translate the identifier into a plurality of access codes for respective credit bureaus, for example by accessing a data structure, such as a database or table, that stores a personal identifier and access codes that are associated with a consumer. The system may then use the access codes to automatically initiate locking or unlocking of credit files for the consumer at the respective credit bureaus.
US09256903B2	Server system, product recommendation method, product recommendation program and recording medium having computer program recorded thereon A search is performed for information of other products associated with a question about a specific product.A server system 10 searches for information of other products associated with a question about a specific product, in accordance with the following procedure. [1] The server system inputs a product ID and a question text (text) related to a question (S405). [2] The server system extracts a product name corresponding to the product ID from product basic information (FIG. 2(b-1)) in an auction DB 12 (S410). [3] The server system analyzes each of the product name and the question text to specify one or more keywords (S415). [4] The server system sets a search condition for a search for products associated with each specified keyword (S420) and extracts necessary items out of the product information satisfying the search condition, from the product basic information, display information, and product price information (FIGS. 2(b-1) to (b-3)) in the auction DB 12 (S425). [5] The server system outputs the extracted necessary items out of the product information (S430).
US09256902B2	Non-transitory computer-readable media for presenting product recommendations Product recommendations are presented to a consumer by presenting to the consumer a plurality of thumbnail images that correspond to a plurality of products. The plurality of thumbnail images are presented to the consumer in a plurality of tier groupings and each of the plurality of tier groupings is indicative of a relative ranking of products within a trend that is being tracked. In response to a user interacting with a one or more of the plurality of presented thumbnail images, the consumer is further presented with at least one of a zoomed-in version of the one or more of the plurality of presented thumbnail images interacted with by the consumer and a product detail page for a product corresponding to the one or more of the plurality of presented thumbnail images interacted with by the consumer.
US09256901B2	Methods and system for enabling communication of identity information during online transaction Methods and system for enabling communication of identity information for an online transaction includes detecting a request to enter the identity information. In response, a first and a second image with a detectable trait are identified for displaying on a receiver device. A first and second delta-based analyzers are executed to monitor changes of the first and the second images. The changes of the images are combined. The changes of the images are adjustable to respective first and second display settings. The combined changes of the images are transmitted to a receiver device for display. A query regarding the detectable trait is transmitted to the receiver device and a response from a user is received. User input of the identity information is enabled at the receiver device when the response to the query is determined to be successful.
US09256900B2	Managing service demand load relative to infrastructure capacity in a networked computing environment Embodiments of the present invention provide an approach for implementing service level agreements (SLAs) having variable service delivery requirements and pricing in a networked (e.g. cloud) computing environment. Under embodiments of the present invention, a plurality of SLAs, each having a different price level, is made available to a consumer. The consumer may select one or more of the plurality of SLAs that reflects the consumer's service delivery requirements in a cloud computing environment. A consumer having relatively inflexible service delivery requirements may select one of the SLAs having a relatively higher price, whereas a consumer having relatively flexible service delivery requirements may select one of the SLAs having a relatively lower price. In one embodiment, the SLAs may dynamically provide for relatively lower variable pricing in response to the consumer receiving deferred or a relatively lower level of service during a peak service demand load. In another embodiment, the SLAs may dynamically provide for relatively higher variable pricing in response to consumer service requests that are fulfilled during a relatively higher overall service demand load. In yet another embodiment, the SLAs may dynamically provide for relatively lower variable pricing in response to consumer service requests that occur during a relatively lower overall service demand load.
US09256899B2	System and method for separation of software purchase from fulfillment A system, method, and computer-readable medium are disclosed for separating the purchase of digital assets from their fulfillment. Information associated with the purchase of a system and digital assets to be processed by the system is received, including the system's unique system identifier. The unique system identifier is associated with the digital assets to generate digital assets entitlement data. A personalization agent installed on the system determines the system's unique system identifier and automatically downloads the purchased digital assets and their associated digital assets entitlement data. Once downloaded, the personalization agent uses the digital assets entitlement data to install the purchased digital assets on the system, thereby entitling the system to process the installed digital assets.
US09256897B2	Authentication and pairing of a mobile device to an external power source A mobile device communicates with an authenticator affiliated with a recharging facility, to identify itself. To confirm that the mobile device is connected to the correct facility, the authenticator instructs the mobile device to draw electrical charge according to an identifiable pattern. Upon detecting a charge being drawn according to that pattern, the authenticator has confirmation that the identified device is connected to the facility, and permits the charging to proceed. The amount of electricity drawn during the charging procedure can be metered, and then billed to a party associated with the identified mobile device.
US09256896B2	Virtual universe rendering based on prioritized metadata terms After a change of location of an avatar in a virtual universe, an avatar is encouraged to remain at that location and avoid an immediate further or return change of location (e.g. by teleportation) by prioritizing rendering of objects such that objects most likely to be of interest to the avatar is performed prior to rendering of objects less likely to be of interest. Prioritization is performed by comparing metadata concerning objective(s) of the avatar and metadata of preferences of the avatar and objects in the avatar's inventory and/or implied from the avatar's activity history with metadata corresponding to objects at the location to which the avatar moves. Preferably, the metadata corresponding to the avatar is ranked in order of the number of occurrences of metadata terms and synonyms in metadata of the avatar.
US09256895B2	Specially programmed computer processors and methods of use thereof In some embodiments, the instant invention provides an improved computer system programmed for searching which includes at least the following components: a specialized computer machine, at least one processor for executing a particular program code stored in a memory, where the particular program code is configured to perform the following operations upon the execution: obtaining business information regarding a plurality of businesses and a plurality of offerings offered by the plurality of businesses; generating a rating score for each business based on consumer ratings; associating each business with the rating score; and concurrently conducting a plurality of searches of the business information based on: business identifying search parameter(s) obtained from each consumer, a geographic indication, a plurality of ranked filtering criteria, a rating score filtering parameter.
US09256894B2	Method and apparatus for providing predefined feedback A method and apparatus utilized in operating a feedback forum in an online auction environment is described. Instead of allowing users of the system to enter freeform comments for and about other users, a number of predefined feedback comments are provided that relate to an auction transaction. Users leaving feedback for other users are permitted to select a comment they desire to leave for or about another user relative to a transaction. The predefined feedback comments selected by the users are associated with the users whom the comment is about, and at some time thereafter, the predefined feedback comment is displayed for viewing by other users of the system.
US09256893B2	System and method for providing customer service help Systems, methods, and computer-readable storage media for providing customer service help. The system first receives, from a user device, contact information associated with the user device, wherein the contact information is received via a customer service terminal having a user interface configured to wirelessly receive data from the user device when the user device is within a distance of the customer service terminal. In response to receiving the contact information, the system then identifies a customer service representative associated with the customer service terminal. The system then sends the contact information to a remote device associated with the customer service representative. The customer service representative can then initiate a customer service communication between the user device and the remote device in order to provide customer service help to the user associated with the user device.
US09256891B2	Following content providers in a social context In general, a method for providing content to a user includes providing a content item to a user responsive to a received request. The content item is displayed to the user in a slot associated with a third party content site. The content item includes a first annotation providing information for or about re-publishing the content item. A request is received from the user to follow a content provider associated with the content item. The user is designated as being interested in updated content from the content provider. Designating the user includes presenting information about the user to one or more of the content provider or a social application that includes a content provider presence so as to allow for updates associated with the content provider to be followed by the user.
US09256889B1	Automatic quote generation Automatic quotes or references are generated based on a user's interaction with one or more pieces of content. A passage for quotation may be determined based at least in part on usage data including information about interaction with one or more pieces of content. A user may begin to type a quotation and a corresponding passage is inserted. The user may vary the scope of the passage, such as adding sentences or paragraphs. User annotation of the passage while the content is presented may also generate an automatically inserted quotation. A citation descriptive of the quoted passage may also be inserted. The automatically inserted quotation may be configured with a link or script, allowing additional functions or access to source content.
US09256887B2	Providing offers for sales of combinations of virtual items at discounted prices A method of providing offers for sales of combinations of virtual items at discounted prices is disclosed. An offer is generated for a sale of a combination of virtual items at a discounted price. The offer for the sale of the combination of virtual items at the discounted price is presented to a user. The presenting suggests to the user that the combination of virtual items is randomly selected from a set of virtual items and the discounted price is randomly selected from a set of discounted prices, the presenting of the offer being performed by a processor. However, in actuality, the combination of virtual items or the discounted price may not be selected randomly.
US09256886B2	Content recommendation system and method A system and method of recommending and rating content and/or for generating a determined affinity between content consumers and reviewers. The method includes determining a rating for one or more user-surveyed content items and determining a rating for one or more reviewer-surveyed content items for each of a plurality of content reviewers. Comparisons are then performed between user ratings and reviewer ratings for commonly surveyed content items. As a result, affinities between user(s) and content reviewers are established and the user is provided with reviews and ratings produced by high-affinity content reviewers.
US09256885B1	Method for linking an electronic media work to perform an action A computer-implemented method including the steps of: receiving, by a computer system including at least one computer, a media work uploaded from a first electronic device; receiving, by the computer system from a second electronic device, a tag associated with the media work having a media work identifier; storing, by the computer system, the media work identifier and the associated tag; obtaining, by the computer system from a third electronic device, a query related to the associated tag; correlating, by the computer system, the query with associated information related to an action to be performed; and providing, from the computer system to the third electronic device, the associated information to be used in performing the action.
US09256883B2	Method and apparatus for planning a schedule of multimedia advertisements in a broadcasting channel Various embodiments of the invention comprise a method and apparatus for planning a schedule of a multimedia advertisement across one or more broadcasting channels is disclosed. In one embodiment, the method includes accessing user data, processing survey data using the user data, generating a file having a list of one or more broadcasting channels using analyzed survey data, and scheduling a multimedia advertisement across the one or more broadcasting channels. Additionally, the file includes one or more inventory spots associated with the one or more broadcasting channels. The method further includes assigning the multimedia advertisement to the one or more inventory spots associated with the one or more broadcasting channels.
US09256880B2	System and method for downloading a safety inspection item In a safety operation for LP gas, a safety inspector selects an inspection slip and determines whether an inspection item is necessary depending on the facility. Therefore, mistakes and omissions in the inspection content occur, and problems occur, such as visiting the actual site again to perform re-inspection. Furthermore, inspection slips that were manually filled are taken back to his or her office to input into a PC. Therefore, problems occur such as increases in workload due to erroneous entry of data and data re-entry, and time lags until inspection results are reflected in the safety management system. By reading a two-dimensional code attached to the main body of LP gas supply facility and consumption facility, the inspection slip (inspection items) related to each safety operation is downloaded to a mobile terminal in real-time at the operating sites, and inspection results are aggregated on a server by data communication.
US09256879B1	Method and apparatus of providing live support service in a notification system A method and apparatus of providing notifications to a customer is disclosed. One example method of operation may include identifying a notification event associated with a customer via a customer management module and retrieving a customer preference record and determining a notification device preference for a customer Internet protocol (IP) device included in the customer preference record. The method may also include transmitting the notification event to the customer's IP device based on the notification device preference, the notification event may include a live agent support option which may be accessed in the event that the automated support options fail to satisfy the customer's questions and concerns.
US09256875B2	Processing transactions of different payment devices of the same issuer account Each portable payment device associated with a single account within a payment processing system is distinguished using track data. The track data from the portable payment device is read at each of a plurality of merchant point of sale terminals (POS). Rather than relying on the PAN alone, a merchant may utilizes the track data, or a proxy thereof, as the unique identifier for the portable payment device. The merchant may then process transactions involving the portable payment device based on the unique identifier. For example, in the transit environment the transit fare for each rider with different portable payment devices but the same account can be calculated using the unique identifier, such as the full track data read from both tracks of the corresponding portable payment devices.
US09256870B1	Methods and systems for updating expiry information of an account A method for updating expiry information of an account is provided. Additionally, a prediction computing device for updating expiry information of an account is provided. Further, a computer-readable storage medium having computer-executable instructions embodied thereon for updating expiry information of an account is provided.
US09256868B2	Switching functions for mobile payments system A data processing center (DPC) computer receives billing information, including a mobile telephone number, and a bill issuance notification request from an acquirer computer. The DPC computer then determines, based on the mobile telephone number, a mobile payment platform (MPP) computer having an account holder as a customer, transmits the billing information to the MPP computer for relaying a billing issuance notification to a mobile device of the account holder, and then receives information indicating that the account holder has been authenticated and has elected to pay the bill associated with the billing issuance notification. The DPC computer then determines a payment card account number of the account holder, and transmits it to the acquirer computer for bill payment processing.
US09256867B2	Delivery of value identifiers using short message service (SMS) A system and method for adding value to a customer account are provided. An identifier associated with a value is distributed to a customer. The identifier is usable to add the value to an account. A request to add the value to a customer account is received via short message service (SMS). The request comprises the identifier and account identification information associated with the customer account. In some embodiments, the identifier may be entered into the device using text auto-completion software. The request is received from a user communication device as an SMS message. The value associated with the identifier and the customer account associated with the account identification number are identified based on the request. The value is caused to be added to the customer account. A confirmation that the value was added to the customer account is passed to the user communication device.
US09256865B2	Mobile point-of-sale A mobile point-of-sale system includes a cart frame and a battery housed in the cart frame. The cart frame includes a front having a bottom, a back having a bottom edge and a bottom. The bottom includes a pair of upper flanges and a lower housing. The pair of upper flanges have components for receiving wheels for supporting the cart frame and the lower housing includes at least one aperture for venting heat from the battery that is supported by the lower housing. At least a portion of the lower housing and the battery are located below the pair of upper flanges and are located below the bottom edges of the front and the back.
US09256864B2	Unloading checks from an automated banking machine A banking system controlled by data bearing records utilizes metrics in acquiring and processing event data related to financial transaction activity at a plurality of automated banking machines. The system uses machine sensors to detect event data during a transaction. For each machine, the system can obtain, analyze, and store event data. The event data can include transaction data related to transaction type, time analysis data related to transaction duration, and operational data related to machine components used during the transaction. Statistical machine averages can be determined and compared by the system in real time. The system can produce statistics related to component performance, such as check reader performance in reading check data from generated check images. The system can also be used to detect and then alleviate potential problems, such as by causing a machine to perform an early sending of check images.
US09256863B2	Receiving malfunctioning mobile phone and a dispensing functioning cellular telephone console The present invention relates to a user-friendly and a user-interactive cellular mobile phone console, allowing a user to interactively replace a malfunctioning cellular mobile phone with a functioning mobile phone, whiles enabling the user to track said malfunctioning cellular mobile through its delivery cycle.
US09256858B2	Method and apparatus for associating context information with content A method and apparatus are provided to facilitate sharing of content including, but not limited to, the sharing of content between people who are co-located. In the context of a method, an indication is received of the content to be shared with a recipient and context information indicative of an intended use of the content by the recipient is associated with the content. The method also causes a representation of the content and the associated context information to be shared with the recipient. The method may also generate the context information based on at least one of the location of the content, a recent action performed on the content or a change made to the content.
US09256857B2	Scheduling start-up and shut-down of mainframe applications using topographical relationships The illustrative embodiments provide for a computer-implemented method for representing actions in a data processing system. A table is generated. The table comprises a plurality of rows and columns. Ones of the columns represent corresponding ones of computer applications that can start or stop in parallel with each other in a data processing system. Ones of the rows represent corresponding ones of sequences of actions within a corresponding column. Additionally, the table represents a definition of relationships among memory address spaces, wherein the table represents when each particular address space is started or stopped during one of a start-up process, a recovery process, and a shut-down process. The resulting table is stored.
US09256856B1	System and method for implementing multiple and simultaneous functions across multiple applications Systems and methods are disclosed herein which enable simultaneous manipulation of user-interface objects by a plurality of users across a network of a plurality of nodes using multiple independent data paths, wherein on each node, an input device activates a plurality of user-interface elements, and such activations are replicated across each node. Only user-interface change data is transmitted, thereby enabling real-time, simultaneous collaboration without transmitting an image of the user interface.
US09256854B2	Audible presentation and verbal interaction of HTML-like form constructs A method of synchronizing an audio and visual presentation in a multi-modal browser. A form is transmitted over a network having at least one field requiring user supplied information to a multi-modal browser. Blank fields within the form are filled in by user who provides either verbal or tactile interaction, or a combination of verbal and tactile interaction. The browser moves to the next field requiring user provided input. Finally, the form exits after the user has supplied input for all required fields. The method also provides a synchronized verbal and visual presentation by said browser by having the headings for the fields to be filled out and typing in what the user says.
US09256840B2	Establishing business networks using a shared platform The present disclosure describes methods, systems, and computer program products for establishing business networks based on shared usage of a common platform. One process includes receiving a set of registry data associated with a collaboration system from a first network participant executing a first application based on a first application platform. A request from a second network participant executing a second application on a compatible platform to the first application platform to access the set of registry data from the first network participant is received. Access is provided to the second network participant of a subset of data shared by the first network participant for collaboration. In some instances, providing access to the second network participant can include identifying a user associated with the second network participant to provide data access with the first network participant and assigning corresponding access authorizations to development entity instances associated with the identified user.
US09256838B2	Scalable online hierarchical meta-learning A method of meta-learning includes receiving a prediction objective, extracting a plurality of subsets of data from a distributed dataset, generating a plurality of local predictions, wherein each local prediction is based on a different subset of the plurality of subsets of data and the prediction objective, combining the plurality of local predictions, and generating a final prediction based on the combined local predictions.

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