最新美国发明专利
Document Document Title
US09231240B2 Battery unit and battery module using the same
A battery unit includes a case accommodating an electrode assembly, the case having an opening and a cap plate for covering the opening, the cap plate having a terminal insertion portion. The battery unit further includes a terminal member inserted into the case through the terminal insertion portion from an outside of the case and coupled to the electrode assembly, the terminal member including a current collector electrically coupled to the electrode assembly; a terminal portion extending parallel to an upper surface of the cap plate to an outside of the cap plate; and a connection portion electrically coupled to the current collector and to the terminal portion. The battery unit further includes a fixing member in the terminal insertion portion and fixing the terminal member to the cap plate, the fixing member including injection-molded plastic resin in the terminal insertion portion and surrounding the terminal member.
US09231238B2 Electric storage device
In an electric storage device, lithium electrodes are disposed on respective outermost portions of an electrode laminated unit in which a positive electrode and a negative electrode are laminated alternately via positive/negative electrode separators. The lithium electrode includes lithium metal serving as a lithium ion supply source, and a lithium electrode separator (a non-woven fabric separator) constituted by a non-woven fabric that satisfies the following conditions: (a) an average fiber diameter of 0.1 μm to 10 μm; and (b) a thickness of 5 μm to 500 μm is provided. By forming the lithium electrode separator that contacts the lithium electrode including the lithium ion supply source from a non-woven fabric in this manner, a dramatic improvement can be achieved in the cycle characteristic of the electric storage device.
US09231237B2 Cell module
Batteries 100 are accommodated in a case 20, wherein the batteries 100 each include an opening portion 8a for releasing gas produced in an associated one of the batteries to outside the battery, the case 20 is partitioned into an accommodation section 50 configured to accommodate the batteries 100 and an exhaust passage 60 configured to expel the gas released from at least one of the opening portions 8a of the batteries 100 to outside the case 20, the opening portions 8a of the batteries 100 are allowed to communicate with the exhaust passage 60 through sealed connection passages 40, and a one-way open valve 70 which is configured to open only along a direction from the opening portion 8a of the battery 100 to the exhaust passage 60 is provided in an intermediate portion or at an end of each of the connection passages 40.
US09231236B2 Battery pack
A battery pack including an external case having improved strength to protect a bare cell is provided. The battery pack includes a bare cell, a cover plate attached to one of long side surfaces that are widest planes of the bare cell, and an external case including a resin portion and a reinforcement plate and accommodating both the bare cell and the cover plate, wherein the resin portion surrounds sides of the reinforcement plate.
US09231230B2 Organic light emitting diode display and method of manufacturing the same
An organic light emitting diode display includes a display substrate including a display region having an organic light emitting diode; an encapsulation substrate facing the display substrate and covering the display region; a first sealing material between the display substrate and the encapsulation substrate, the first sealing material sealing the display region; a second sealing material in contact with an external exposed surface of the first sealing material and sealing the first sealing material; and a molding portion surrounding a lateral surface and an external corner of each of the display substrate and the encapsulation substrate and surrounding an external exposed surface of the second sealing material.
US09231225B2 Organic light-emitting device
An organic light-emitting device may include a substrate; an anode on the substrate; a hole transport region on the anode; an emission layer on the hole transport region; an electron transport region on the emission layer; and a cathode on the electron transport region. The electron transport region may include an electron injection layer including a first component which is a salt chloride and a second component which is at least one metal selected from ytterbium (Yb), scandium (Sc), vanadium (V), yttrium (Y), indium (In), cerium (Ce), samarium (Sm), europium (Eu), and terbium (Tb). In addition, the cathode may contacts the electron injection layer and may include an alloy of a first cathode metal including at least one of Ag, Au, Pt, Cu, Mn, Ti, Co, Ni, and W, and a second cathode metal including least one of Yb, Sc, V, Y, In, Ce, Sm, Eu, and Tb.
US09231224B2 Organic light emitting diode display
An organic light emitting diode (OLED) display is provided. An OLED display in accordance with an exemplary embodiment may include a substrate including a first subpixel, a second subpixel, and a third subpixel, a first electrode disposed on each of the first subpixel, the second subpixel, and the third subpixel, a second electrode facing the first electrode, a first common layer disposed on the first subpixel and the second subpixel, a first emission layer and a second emission layer disposed on the first common layer, a second common layer disposed on the third subpixel, and a third emission layer disposed on the second common layer. The first common layer may include a first doping layer and a second doping layer disposed on the first doping layer. Each of the doping layers may including a p-type dopant, and the second common layer may be formed as a single layer.
US09231220B2 Substituted tetraarylbenzenes
The present invention relates to electronic devices comprising at least one compound of the formula (1) where X is N and Y is CR1, and to the use thereof.
US09231218B2 Phosphorescent emitters containing dibenzo[1,4]azaborinine structure
A dibenzo[1,4]azaborine comprising compound, and devices and formulations including the same are described. The compound includes a ligand L1 including wherein E1 is N; E2 is B; and R3 and R4 represent mono, di, tri, tetra substitutions or no substitution; wherein R1, R2, R3 and R4 are each independently selected from the group consisting of hydrogen, deuterium, halide, alkyl, cycloalkyl, heteroalkyl, arylalkyl, alkoxy, aryloxy, amino, silyl, alkenyl, cycloalkenyl, heteroalkenyl, alkynyl, aryl, heteroaryl, acyl, carbonyl, carboxylic acids, ester, nitrile, isonitrile, sulfanyl, sulfinyl, sulfonyl, phosphino, and combinations thereof; wherein any two adjacent R1, R2, R3, and R4 are optionally joined to form a ring, which may be further substituted; wherein L1 is coordinated to a metal M, provided that the metal M does not form bond with E1 and E2; and wherein L1 may be linked with other ligands to comprise a bidentate, tridentate, tetradentate, pentadentate or hexadentate ligand.
US09231217B2 Synthesis method of organometallic complex, synthesis method of pyrazine derivative, 5,6-diaryl-2-pyrazyl triflate, light-emitting element, light-emitting device, electronic device, and lighting device
Provided is a 5,6-diaryl-2-pyrazyl triflate, its synthetic method, and a method for synthesizing an organometallic complex having a triarylpyrazine ligand from the 5,6-diaryl-2-pyrazyl triflate. The triflate is readily obtained from the corresponding 5,6-diarylpyrazin-2-ol, and the palladium-catalyzed coupling of the 5,6-diaryl-2-pyrazyl triflate with an arylboronic acid derivative leads to a high yield of a triarylpyrazine derivative having high purity. The use of the triarylpyrazine derivative in the reaction with a metal compound such as a metal chloride results in an ortho-metallated organometallic complex with high purity. The high purity of the organometallic complex contributes to the extremely high durability of a light-emitting element.
US09231216B2 Carborane compound, organic light-emitting diode including the same and flat display device including organic light-emitting diode
A compound represented by Formula 1 below: (R1)a—CB—[Ar]n—CB—(R2)b   wherein CB denotes carborane, Ar is a substituted or unsubstituted phenylene group, and a detailed description of R1, R2, a, b, and n is provided in the detailed description. An organic light-emitting diode including an organic layer including the compound has high luminous efficiency.
US09231214B2 Photovoltaic devices including self-assembling fullerene derivatives for improved efficiencies
Described herein are photovoltaic devices including self-assembling fullerene derivatives. In one embodiment, a photovoltaic device includes a first electrode layer, a second electrode layer, and an active layer disposed between the first electrode layer and the second electrode layer. The active layer is configured to absorb incident light to produce a first type of charge carrier that is transported to the first electrode layer and a second type of charge carrier that is transported to the second electrode layer. The active layer includes self-assembled molecules of a fullerene derivative to provide a conductive path through at least a portion of the active layer.
US09231213B2 Methods for integrating and forming optically transparent devices on surfaces
An apparatus, system, and/or method are described to enable optically transparent reconfigurable integrated electrical components, such as antennas and RF circuits to be integrated into an optically transparent host platform, such as glass. In one embodiment, an Ag NW film may be configured as a transparent conductor for antennas and/or as interconnects for passive circuit components, such as capacitors or resistors. Ag NW may also be used as transmission lines and/or interconnect overlays for devices. A graphene film may also be configured as active channel material for making active RF devices, such as amplifiers and switches.
US09231206B2 Methods of forming a ferroelectric memory cell
A method of forming a ferroelectric memory cell. The method comprises forming an electrode material exhibiting a desired dominant crystallographic orientation. A hafnium-based material is formed over the electrode material and the hafnium-based material is crystallized to induce formation of a ferroelectric material having a desired crystallographic orientation. Additional methods are also described, as are semiconductor device structures including the ferroelectric material.
US09231204B2 Low voltage embedded memory having conductive oxide and electrode stacks
Embodiments include low voltage embedded memory having conductive oxide and electrode stacks. A material layer stack for a memory element includes a first conductive electrode. A conductive oxide layer is disposed on the first conductive electrode. The conductive oxide layer has a plurality of oxygen vacancies therein. A second electrode is disposed on the conductive oxide layer.
US09231203B1 Doped narrow band gap nitrides for embedded resistors of resistive random access memory cells
Provided are memory cells, such as resistive random access memory (ReRAM) cells, and methods of fabricating such cells. A cell includes an embedded resistor and resistive switching layer connected in series within the embedded resistor. The embedded resistor prevents excessive electrical currents through the resistive switching layer, especially when the resistive switching layer is switched into its low resistive state. The embedded resistor includes a stoichiometric nitride that has a bandgap of less than 2 eV. The embedded resistor is configured to maintain a substantially constant resistance throughout fabrication and operation of the cell, such as annealing the cell and subjecting the cell to forming and switching signals. The stoichiometric nitride may be one of hafnium nitride, zirconium nitride, or titanium nitride. The embedded resistor may also include a dopant, such as tantalum, niobium, vanadium, tungsten, molybdenum, or chromium.
US09231201B2 Electric device with a layer of conductive material contacted by nanowires
The electric device (100) according to the invention comprises a layer (107) of a memory material which has an electrical resistivity switchable between a first value and a second value. The memory material may be a phase change material. The electric device (100) further comprises a set of nanowires (NW) electrically connecting a first terminal (172) of the electric device and the layer (107) of memory material thereby enabling conduction of an electric current from the first terminal via the nanowires (NW) and the layer (107) of memory material to a second terminal (272) of the electric device. Each nanowire (NW) electrically contacts the layer (107) of memory material in a respective contact area. All contact areas are substantially identical. The method according to the invention is suited to manufacture the electric device (100) according to the invention.
US09231200B2 Memory element and memory device
A memory element includes: a memory layer disposed between a first electrode and a second electrode. The memory layer includes: an ion source layer containing one or more metallic elements, and one or more chalcogen elements of tellurium (Te), sulfur (S), and selenium (Se); and a resistance change layer disposed between the ion source layer and the first electrode, the resistance change layer including a layer which includes tellurium and nitrogen (N) and is in contact with the ion source layer.
US09231195B2 Magnetic memory and method of manufacturing the same
According to one embodiment, a magnetic memory comprises an electrode, a memory layer which is formed on the electrode and has magnetic anisotropy perpendicular to a film plane, and in which a magnetization direction is variable, a tunnel barrier layer formed on the memory layer, and a reference layer which is formed on the tunnel barrier layer and has magnetic anisotropy perpendicular to the film plane, and in which a magnetization direction is invariable. The memory layer has a positive magnetostriction constant on a side of the electrode, and a negative magnetostriction constant on a side of the tunnel barrier layer.
US09231192B2 Semiconductor memory device and method for manufacturing the same
According to one embodiment, a memory device with magnetroresistive effect element is disclosed. The element includes first metal magnetic film (MMF) with nonmagnetic element and axis of easy magnetization perpendicular (EMP), first insulating film, first intermediate magnetic film between the first MMF and the first insulating film, second MMF on the first insulating film and including nonmagnetic elements, the second MMF having axis of EMP, second intermediate magnetic film between the first insulating film and the second MMF, and diffusion preventing film including metal nitride having barrier property against diffusion of the nonmagnetic elements between the first MMF and the first intermediate magnetic film.
US09231191B2 Magnetic tunnel junction device and method of making same
A magnetic tunnel junction (MTJ) device includes a reference layer having a surface, a tunnel insulating layer formed over the surface of the reference layer, a free layer formed over the tunnel insulating layer, and a magnetic field providing layer formed over the free layer. A magnetization direction in each of the reference layer and the free layer is substantially perpendicular to the surface. The magnetic field providing layer is configured to provide a lateral magnetic field in the free layer, the lateral magnetic field being substantially parallel to the surface.
US09231190B2 Method for manufacturing an ultrasonic transducer, biological sensor
A method for manufacturing an ultrasonic transducer includes: forming a piezoelectric element by laminating a lower electrode, a piezoelectric body, and an upper electrode on a first face of a support film; affixing a reinforcing substrate that covers the piezoelectric element to the first face of the support film; forming a photosensitive resin substrate to a second face of the support film that is on an opposite side from the first face; forming an opening in the resin substrate by irradiating the resin substrate with light; and removing the reinforcing substrate.
US09231179B2 Method for producing optoelectronic semiconductor components, lead frame composite, and optoelectronic semiconductor component
A method for producing a packaged component is disclosed. In one embodiment, a lead frame composite has first lead frame parts, second lead frame parts and test contacts, electrically connecting via first electrical connections the first lead frame parts to the other first lead frame parts. A potting body is formed on the lead frame composite thereby mechanically connecting the first lead frame parts to the second lead frame parts and encapsulating the first electrical connections. First semiconductor components are placed on the first lead frame parts after forming the potting body. The first semiconductor components are electrically connected to the second lead frame parts via second electrical connections. The first semiconductor components are electrically tested at the test contacts prior to singulating the lead frame composite and the potting body. The lead frame composite and the potting body are singulated thereby forming the packaged semiconductor components.
US09231173B2 Phosphor sheet, light-emitting device having the phosphor sheet and method of manufacturing the same
Disclosed herein is a light emitting device including: a substrate; a light emitting diode (LED) chip disposed on the substrate; and a phosphor sheet disposed on an upper portion of the LED chip and including alignment members formed on a lower surface thereof. The alignment members contact the LED chip, such that the phosphor sheet is aligned with the LED chip.
US09231172B2 Screen printing method of LED module with phosphor
A screen printing method of LED module with phosphor includes: board preparation providing an LED module board with a substrate and a plurality of LED sources fixed on the substrate. The LED sources are flip chip structural and the metal electrodes thereof are fixed to the bonding pads of the substrate. A screen board is provided with meshes corresponding to the shiny sides of the LED sources of the substrate one by one. A projection of each mesh to the shiny side of the corresponding LED source has similar shape with the shiny side of the LED source. The top of the screen board is printed with allocated colloidal phosphor until each mesh is coated fully. The printed substrates are baked to solidify the phosphor. The periphery of the shiny side is fully coated.
US09231171B2 Flexible LED assemblies and LED light bulbs
LED assemblies and related LED light bulbs. An LED assembly has a flexible, transparent substrate, an LED chip on the first surface and electrically connected to two adjacent conductive sections, a first wavelength conversion layer, formed on the first surface to substantially cover the LED chip, and a second wavelength conversion layer formed on the second surface. The flexible, transparent substrate has first and second surfaces opposite to each other, and several conductive sections, which are separately formed on the first surface.
US09231170B2 Phosphor LED
A phosphor LED for emitting light emitting diode light may include an LED designed for emitting blue primary light; and an LED phosphor designed and arranged such that it is excited by the primary light during operation and emits secondary light as a consequence, said secondary light forming at least a portion of the LED light. The LED phosphor may include a green phosphor and a red phosphor. The green phosphor and the red phosphor may be provided in a ratio such that the light emitting diode light in the CIE standard chromaticity system has a color locus in the green which is spaced apart from the Planckian locus, to be precise by at least 0.01 in terms of absolute value.
US09231167B2 Insulation structure for high temperature conditions and manufacturing method thereof
An insulation structure for high temperature conditions and a manufacturing method thereof. In the insulation structure, a substrate has a conductive pattern formed on at least one surface thereof for electrical connection of a device. A metal oxide layer pattern is formed on a predetermined portion of the conductive pattern by anodization, the metal oxide layer pattern made of one selected from a group consisting of Al, Ti and Mg.
US09231163B2 Semiconductor light emitting apparatus
A semiconductor light emitting apparatus includes semiconductor lamination of n-type layer, active layer, and p-type layer; recess penetrating the lamination from the p-type layer and exposing the n-type layer; n-side electrode formed on the n-type layer at the bottom of the recess and extending upward above the p-type layer; a p-side electrode formed on the p-type layer and having an opening surrounding the recess in plan view, the n-side electrode extending from inside to above the recess; and an insulating layer disposed between the p-side and the n-side electrodes on the p-type layer, the p-side electrode constituting a reflective electrode reflecting light incident from the active layer, the n-side electrode including a reflective electrode layer covering the opening in plan view and reflects light incident from the emission layer side, the reflective electrode layer having peripheral portion overlapping peripheral portion of the p-side electrode in plan view.
US09231160B1 Semiconductor light emitting element
A semiconductor light emitting element includes a metal layer, a first semiconductor layer of a first conductivity type, a light emitting layer, a second semiconductor layer of a second conductivity type, a first electrode, a second electrode, and an insulating layer. The first semiconductor layer is separated from the metal layer in a first direction. The first semiconductor layer includes a first region, a second region, and a third region. The light emitting layer has a first side surface intersecting a second direction. The second semiconductor layer has a second side surface intersecting the second direction. The first electrode is electrically connected to the first region and the metal layer. The second electrode includes a first portion, and a second portion being continuous with the first portion. The insulating layer includes a first insulating portion and a second insulating portion.
US09231159B2 Method of manufacturing nitride semiconductor light emitting element having thick metal bump
A method of manufacturing a flip-chip nitride semiconductor light emitting element includes steps of providing a nitride semiconductor light emitting element structure; forming an insulating protective layer on the nitride semiconductor light emitting element structure; forming a resist pattern having openings above an n-side electrode connecting surface and a p-side electrode connecting surface; etching the protective layer to expose the n-side electrode connecting surface and the p-side electrode connecting surface using the resist pattern as a mask; forming a first metal layer that becomes an n-side electrode and a p-side electrode, the first metal layer being formed as a continuous layer disposed on the n-side electrode connecting surface, the p-side electrode connecting surface and the resist pattern; forming a second metal layer that becomes metal bumps by electrolytic plating using the first metal layer as an electrode for the electrolytic plating; and removing the resist pattern.
US09231157B2 Light emitting diode
A light emitting diode includes a first semiconductor layer, an active layer, a second semiconductor layer, an upper electrode, and a lower electrode. The active layer is sandwiched between the first semiconductor layer and the second semiconductor layer. The lower electrode is electrically connected with the first semiconductor layer, and the upper electrode is electrically connected with the second semiconductor layer. A surface of the second semiconductor layer away from the active layer is used as the light extraction surface. A surface of the first semiconductor layer connected with the lower electrode is a patterned surface including a number of grooves.
US09231155B2 Composite substrates, a method of producing the same, a method of producing functional layers made of nitrides of group 13 elements, and functional devices
A composite substrate 10 includes a sapphire body 1A, a seed crystal film 4 composed of gallium nitride crystal and provided on a surface of the sapphire body, and a gallium nitride crystal layer 7 grown on the seed crystal film 4 and having a thickness of 200 μm or smaller. Voids 5 are provided along an interface between the sapphire body 1A and the seed crystal film 4 in a void ratio of 4.5 to 12.5 percent.
US09231153B2 Micro-light-emitting diode
A micro-light-emitting diode (micro-LED) includes a first type semiconductor layer, a second type semiconductor, a first current controlling layer, a first electrode, and a second electrode. The second type semiconductor layer and the first current controlling layer are joined with the first type semiconductor layer. The first current controlling layer has at least one opening therein. The first electrode is electrically coupled with the first type semiconductor layer through the opening. The second electrode is electrically coupled with the second type semiconductor layer. At least one of the first electrode and the second electrode has a light-permeable part. A vertical projection of the first current controlling layer on said one of the first electrode and the second electrode overlaps with the light-permeable part. The light-permeable part is transparent or semi-transparent.
US09231150B2 Phosphor for light emitting device and method for manufacturing the same, and light emitting device using the same
A phosphor for light emitting device of an embodiment includes: a phosphor particle composed of at least one selected from an alkaline earth silicate phosphor, a lanthanum oxysulfide phosphor, and a zinc sulfide phosphor; and a surface treatment agent, provided to cover a surface of the phosphor particle, of at least one selected from a silane coupling agent and an acrylic emulsion. A luminance maintenance ratio of the phosphor represented by a formula: luminance B/luminance A×100(%), is 98% or more, wherein the luminance A is a luminance of the phosphor made to emit under a condition of temperature: 23° C., humidity: 40%, and the luminance B is a luminance of the phosphor made to emit under a condition of temperature: 23° C., humidity: 40% after leaving the phosphor under a condition of temperature: 60° C., humidity: 90% for 12 hours.
US09231149B2 Photovoltaic cell electrode and method for electrically connecting a photovoltaic cell
An electrode for electrically connecting two photovoltaic cells is provided. Each photovoltaic cell may include a plurality of lamellar electrically conductive surface regions. The electrode may include a plurality of electrically conductive wires extending adjacent to one other; and a stabilizing structure coupled to the plurality of electrically conductive wires such that the space between the electrically conductive wires to one another is defined until the plurality of electrically conductive wires has been fixed on the plurality of lamellar electrically conductive surface regions of a photovoltaic cell.
US09231148B2 Method for cleaning and passivating chalcogenide layers
A method for chemically cleaning and passivating a chalcogenide layer is provided, wherein the method comprises bringing the chalcogenide layer into contact with an ammonium sulfide containing ambient, such as an ammonium sulfide liquid solution or an ammonium sulfide containing vapor. Further, a method for fabricating photovoltaic cells with a chalcogenide absorber layer is provided, wherein the method comprises: providing a chalcogenide semiconductor layer on a substrate; bringing the chalcogenide semiconductor layer into contact with an ammonium sulfide containing ambient, thereby removing impurities and passivating the chalcogenide semiconductor layer; and afterwards providing a buffer layer on the chalcogenide semiconductor layer.
US09231147B2 Heterojunction subcells in inverted metamorphic multijunction solar cells
Inverted metamorphic multijunction solar cells having a heterojunction middle subcell and a graded interlayer, and methods of making same, are disclosed herein. The present disclosure provides a method of manufacturing a solar cell using an MOCVD process, wherein the graded interlayer is composed of (InxGa1-x)y Al1-yAs, and is formed in the MOCVD reactor so that it is compositionally graded to lattice match the middle second subcell on one side and the lower third subcell on the other side, with the values for x and y computed and the composition of the graded interlayer determined so that as the layer is grown in the MOCVD reactor, the band gap of the graded interlayer remains constant at 1.5 eV throughout the thickness of the graded interlayer.
US09231141B2 Controlling a solar tracking system
A method of tracking the sun is disclosed. A measurement of a gravity vector is obtained in a frame of reference of a solar collector rotatable with respect to an earth center of reference. A measurement of a magnetic direction vector is obtained in the frame of reference of the solar collector. The orientation of the solar collector is determined from the obtained measurement of the gravity vector and the obtained measurement of the magnetic direction. The orientation of the solar collector is altered in order to track the sun.
US09231140B2 Venting assembly for concentrating photovoltaic system module
Solar cell modules for converting solar energy into electrical energy, such as used in a concentrating photovoltaic system. The modules have a first ventilating opening in the module housing; and a ventilating subassembly mounted on the module housing and disposed over the ventilating opening in the module housing. The ventilating subassembly has a housing having a first chamber adjacent to and in communication with the first ventilating opening in the module housing; a second chamber adjacent to the first chamber, the second chamber having a second ventilating opening to the external environment; and a filter membrane separating the first chamber from the second chamber to allow air to flow between the first chamber and the second chamber through the filter membrane.
US09231133B2 Nanowires formed by employing solder nanodots
A photovoltaic device and method include depositing a metal film on a substrate layer. The metal film is annealed to form islands of the metal film on the substrate layer. The substrate layer is etched using the islands as an etch mask to form pillars in the substrate layer.
US09231127B2 Light receiving and emitting element and sensor device using same
A light receiving and emitting element includes a substrate; a light emitting element formed on an upper face of the substrate; a light receiving element formed on an upper face side of the substrate; a light emitting element-side first electrode pad; and a metal lump joined to the light emitting element-side first electrode pad. The light emitting element-side electrode pad is disposed the upper face of the substrate through an insulating layer so that the metal lump blocks light emitted from the light emitting element and propagating toward the light receiving element.
US09231125B2 Solar cell and method for producing same
A solar cell includes a semiconductor wafer, at least one dielectric layer arranged on the semiconductor wafer, a metal layer arranged on the dielectric layer, and a contact structure arranged in the dielectric layer such that the contact structure provides an electrical connection between the metal layer and the semiconductor wafer. The contact structure has at least one first structure having a minimum dimension and at least one second structure having a maximum dimension, wherein the minimum dimension and the maximum dimension are defined along a surface of the semiconductor wafer and the minimum dimension of the first structure is greater than the maximum dimension of the second structure.
US09231124B2 Ball grid array packaged camera device soldered to a substrate
An assembly that attaches a ball grid array (BGA) packaged camera device to a printed circuit board (PCB) substrate is provided. The assembly includes a spacer between the device and the substrate. The spacer is configured to prevent excessive collapse of solder balls located between the device and the substrate during reflow of the solder balls. The spacer includes one of solder mask, tape, and/or legend ink.
US09231122B2 Schottky diode
The present disclosure generally relates to a Schottky diode that has a substrate, a drift layer provided over the substrate, and a Schottky layer provided over an active region of the drift layer. The metal for the Schottky layer and the semiconductor material for the drift layer are selected to provide a low barrier height Schottky junction between the drift layer and the Schottky layer.
US09231119B2 Sensor
A sensor includes a circuit board, a wiring connection layer, a sensor element, and a conductive post. The circuit board has a first electrode. The wiring connection layer has second and third electrodes. The second electrode is connected to the first electrode. The sensor element has a fourth electrode. The conductive post connects the third electrode electrically with the fourth electrode. This sensor can be driven efficiently.
US09231118B2 Chip package with isolated pin, isolated pad or isolated chip carrier and method of making the same
A chip package with isolated pin, isolated pad or isolated chip carrier and a method of making the same are disclosed. In one embodiment a chip package includes a chip, a package encapsulating the chip, pads or pins disposed on a first side of the package and an isolation pad or an isolation pin disposed on a second side of the package, the isolation pin or the isolation pad electrically isolated from the chip, wherein the chip comprises a magnetic field sensor configured to measure a magnetic field generated outside of the package.
US09231116B2 Nonvolatile semiconductor memory device
A nonvolatile semiconductor memory device includes a charge storage layer on a first insulating film, a second insulating film which is provided on the charge storage layer, formed of layers, and a control gate electrode on the second insulating film. The second insulating film includes a bottom layer (A) provided just above the charge storage layer, a top layer (C) provided just below the control gate electrode, and a middle layer (B) provided between the bottom layer (A) and the top layer (C). The middle layer (B) has higher barrier height and lower dielectric constant than both the bottom layer (A) and the top layer (C). The average coordination number of the middle layer (B) is smaller than both the average coordination number of the top layer (C) and the average coordination number of the bottom layer (A).
US09231113B2 Flash memory with P-type floating gate
Methods for manufacturing non-volatile memory devices including peripheral transistors with reduced and less variable gate resistance are described. In some embodiments, a NAND-type flash memory may include floating-gate transistors and peripheral transistors (or non-floating-gate transistors). The peripheral transistors may include select gate transistors (e.g., drain-side select gates and/or source-side select gates) and/or logic transistors that reside outside of a memory array region. A floating-gate transistor may include a floating gate of a first conductivity type (e.g., n-type) and a control gate including a lower portion of a second conductivity type different from the first conductivity type (e.g., p-type). A peripheral transistor may include a gate including a first layer of the first conductivity type, a second layer of the second conductivity type, and a cutout region including one or more sidewall diffusion barriers that extends through the second layer and a portion of the first layer.
US09231111B2 Semiconductor device
An object is to provide a semiconductor device that includes an oxide semiconductor and is suitable for a power device. An object is to provide a semiconductor device in which large current can flow. An object is to provide a highly reliable semiconductor device. A semiconductor device includes an oxide stack in which a first oxide layer, a first oxide semiconductor layer, a second oxide semiconductor layer, and a second oxide layer are stacked and has a structure in which a region that contains an element imparting conductivity and is provided in the first oxide semiconductor layer overlaps an electrode functioning as a source electrode and does not overlap an electrode functioning as a drain electrode.
US09231110B2 Semiconductor device and method for manufacturing the same
It is an object to provide a highly reliable semiconductor device including a thin film transistor whose electric characteristics are stable. In addition, it is another object to manufacture a highly reliable semiconductor device at low cost with high productivity. In a semiconductor device including a thin film transistor, a semiconductor layer of the thin film transistor is formed with an oxide semiconductor layer to which a metal element is added. As the metal element, at least one of metal elements of iron, nickel, cobalt, copper, gold, manganese, molybdenum, tungsten, niobium, and tantalum is used. In addition, the oxide semiconductor layer contains indium, gallium, and zinc.
US09231109B2 Electro-optical device and electronic apparatus
An electro-optical device includes a first light shielding film; a transistor element formed on the first light shielding film to overlap the first light shielding film; a second light shielding film formed on the transistor element to overlap the transistor element and electrically connected to an input terminal of the transistor element; a transparent conductive film extended toward an upper layer side of the second light shielding film in an opening region, through which light penetrates, of the display region; a dielectric film formed on the transparent conductive film in the opening region; and a transparent pixel electrode formed on the dielectric film in the opening region, constituting a storage capacitor together with the transparent conductive film and the dielectric film, and having a transparent pixel electrode which is electrically connected to the transistor element.
US09231107B2 Thin film transistor, method for manufacturing the same, and display device comprising the same
A thin film transistor, a method of manufacturing the thin film transistor, and a display device including the thin film transistor are provided. The thin film transistor comprises an oxide semiconductor layer, a gate electrode, a source electrode and a drain electrode formed on a substrate in a coplanar configuration. A first conductive member is in direct contact with the oxide semiconductor layer and in direct contact with the source electrode. A second conductive member is in direct contact with the oxide semiconductor layer and in direct contact with the drain electrode. The first conductive member and the second conductive member are arranged to decrease resistance between a channel region of the oxide semiconductor layer and the source and drain electrodes.
US09231105B2 Semiconductor device with group-III nitride compound semiconductor layer on substrate for transistor
To realize a transistor of normally-off type having a high mobility and a high breakdown voltage. A compound semiconductor layer is formed over a substrate, has both a concentration of p-type impurities and a concentration of n-type impurities less than 1×1016/cm3, and includes a group III nitride compound. A well is a p-type impurity layer and formed in the compound semiconductor layer. A source region is formed within the well and is an n-type impurity layer. A low-concentration n-type region is formed in the compound semiconductor layer and is linked to the well. A drain region is formed in the compound semiconductor layer and is located on a side opposite to the well via the low-concentration n-type region. The drain region is an n-type impurity layer.
US09231104B2 Semiconductor devices including bit line contact plug and peripheral transistor
A semiconductor device having a cell area and a peripheral area includes a semiconductor substrate, a cell insulating isolation region delimiting a cell active region of the semiconductor substrate in the cell area, a word line disposed within the semiconductor substrate in the cell area, a bit line contact plug disposed on the cell active region, a bit line disposed on the bit line contact plug, a peripheral insulating isolation region delimiting a peripheral active region of the semiconductor substrate in the peripheral area, and a peripheral transistor including a peripheral transistor lower electrode and a peripheral transistor upper electrode. The bit line contact plug is formed at the same level in the semiconductor device as the peripheral transistor lower electrode, and the bit line electrode is formed at the same level in the semiconductor device as the peripheral transistor upper electrode.
US09231103B2 Vertical MOSFET transistor, in particular operating as a selector in nonvolatile memory devices
A vertical MOSFET transistor is formed in a body of semiconductor material having a surface. The transistor includes a buried conductive region of a first conductivity type; a channel region of a second conductivity type, arranged on top of the buried conductive region; a surface conductive region of the first conductivity type, arranged on top of the channel region and the buried conductive region; a gate insulation region, extending at the sides of and contiguous to the channel region; and a gate region extending at the sides of and contiguous to the gate insulation region.
US09231102B2 Asymmetric semiconductor device
A semiconductor device includes a first type region including a first conductivity type. The semiconductor device includes a second type region including a second conductivity type. The semiconductor device includes a third type region including a third conductivity type that is opposite the first conductivity type, the third type region covering the first type region. The semiconductor device includes a fourth type region including a fourth conductivity type that is opposite the second conductivity type, the fourth type region covering the second type region. The semiconductor device includes a channel region extending between the third type region and the fourth type region.
US09231098B2 Mechanism for forming metal gate structure
Embodiments of mechanisms for forming a semiconductor device are provided. The semiconductor device includes a semiconductor substrate. A source region and a drain region are formed in the semiconductor substrate, and metal silicide regions are formed in the source region and the drain region, respectively. The semiconductor device further includes a metal gate stack formed over the semiconductor substrate and between the source region and the drain region. The semiconductor device also includes an insulating layer formed over the semiconductor substrate and surrounding the metal gate stack, wherein the insulating layer has contact openings exposing the metal silicide regions, respectively. The semiconductor device includes a dielectric spacer liner layer formed over inner walls of the contact openings, wherein the whole of the dielectric spacer liner layer is right above the metal silicide regions. The semiconductor device includes contact plugs formed in the contact openings.
US09231090B2 Trench-gate-type insulated gate bipolar transistor
In a trench-gate-type insulated gate bipolar transistor, a current will not flow down to a lower portion of a trench, a high electrical field at the lower portion of the trench is suppressed even if a high voltage is applied, such as at a time of turning off, an increase in on-state resistance and a decrease in breakdown resistance and withstand voltage are suppressed. In the semiconductor device, a plurality of trenches is disposed to reach a rear surface of a drift layer, and a collector layer is disposed at a tip end side in an extended direction of the trenches in a surface layer portion of the drift layer. When a gate electrode is applied with a predetermined voltage, a channel region is formed in a portion of the base layer contacting the trenches, and an electric current flows in the predetermined direction along the trenches.
US09231089B2 Formation of an asymmetric trench in a semiconductor substrate and a bipolar semiconductor device having an asymmetric trench isolation region
Disclosed is a trench formation technique wherein an opening having a first sidewall with planar contour and a second sidewall with a saw-tooth contour is etched through a semiconductor layer and into a semiconductor substrate. Then, a crystallographic wet etch process expands the portion of the opening within the semiconductor substrate to form a trench. Due to the different contours of the sidewalls and, thereby the different crystal orientations, one sidewall etches faster than the other, resulting in an asymmetric trench. Also disclosed is a bipolar semiconductor device formation method that incorporates the above-mentioned trench formation technique when forming a trench isolation region that undercuts an extrinsic base region and surrounds a collector pedestal. The asymmetry of the trench ensures that the trench isolation region has a relatively narrow width and, thereby ensures that both collector-to-base capacitance Ccb and collector resistance Rc are minimized within the resulting bipolar semiconductor device.
US09231088B2 Emitter contact epitaxial structure and ohmic contact formation for heterojunction bipolar transistor
Embodiments of the present disclosure describe apparatuses, methods, and systems of an integrated circuit (IC) device. The IC device includes a diffusion control layer as part of an emitter epitaxial structure. The IC device may utilize a common metallization scheme to simultaneously form an emitter contact and a base contact. Other embodiments may also be described and/or claimed.
US09231087B2 Bipolar junction transistors with self-aligned terminals
Device structures, design structures, and fabrication methods for a bipolar junction transistor. A first layer comprised of a first semiconductor material and a second layer comprised of a second semiconductor material are disposed on a substrate containing a first terminal of the bipolar junction transistor. The second layer is disposed on the first layer and a patterned etch mask is formed on the second layer. A trench extends through the pattern hardmask layer, the first layer, and the second layer and into the substrate. The trench defines a section of the first layer stacked with a section of the second layer. A selective etching process is used to narrow the section of the second layer relative to the section of the first layer to define a second terminal and to widen a portion of the trench in the substrate to undercut the section of the first layer.
US09231084B2 Method of forming laterally diffused metal oxide semiconductor transistor with partially unsilicided source/drain
A method of forming a semiconductor device comprises forming a gate over a substrate. The method also comprises forming a source and a drain on opposite sides of the gate. The source and the drain are formed such that the source and the drain are separated by a channel region beneath the gate. The source and the drain are positioned such that the channel region has a channel width with respect to a surface of the substrate greater than a width of the gate with respect to the surface of the substrate. The method further comprises forming a first silicide over a portion of the source. The method additionally comprises forming a second silicide over a portion of the drain such that the drain has an unsilicided region adjacent to the gate configured to provide a resistive region configured to sustain a voltage load in a high voltage laterally diffused metal oxide semiconductor (LDMOS) application.
US09231077B2 Method of making a logic transistor and non-volatile memory (NVM) cell
A method of forming a semiconductor device includes forming a first gate layer over a substrate in the NVM region and the logic region; forming an opening in the first gate layer in the NVM region; forming a charge storage layer in the opening; forming a control gate over the charge storage layer in the opening; patterning the first gate layer to form a first patterned gate layer portion over the substrate in the logic region and to form a second patterned gate layer portion over the substrate in the NVM region, wherein the second patterned gate layer portion is adjacent the control gate; forming a dielectric layer over the substrate around the first patterned gate layer portion and around the second patterned gate layer portion and the control gate, and replacing the first patterned gate layer portion with a logic gate comprising metal.
US09231075B2 Semiconductor device including gate electrode provided over active region in p-type nitride semiconductor layer and method of manufacturing the same, and power supply apparatus
A semiconductor device includes a nitride semiconductor stacked structure including a carrier transit layer and a carrier supply layer; a p-type nitride semiconductor layer provided over the nitride semiconductor stacked structure and including an active region and an inactive region; an n-type nitride semiconductor layer provided on the inactive region in the p-type nitride semiconductor layer; and a gate electrode provided over the active region in the p-type nitride semiconductor layer.
US09231074B2 Bipolar junction transistors with an air gap in the shallow trench isolation
Device structures, fabrication methods, and design structures for a bipolar junction transistor. A trench isolation region is formed in a substrate. The trench isolation region is coextensive with a collector in the substrate. A base layer is formed on the collector and on a first portion of the trench isolation region. A dielectric layer is formed on the base layer and on a second portion of the trench isolation region peripheral to the base layer. After the dielectric layer is formed, the trench isolation region is at least partially removed to define an air gap beneath the dielectric layer and the base layer.
US09231073B2 Diode-based devices and methods for making the same
In accordance with an embodiment, a diode comprises a substrate, a dielectric material including an opening that exposes a portion of the substrate, the opening having an aspect ratio of at least 1, a bottom diode material including a lower region disposed at least partly in the opening and an upper region extending above the opening, the bottom diode material comprising a semiconductor material that is lattice mismatched to the substrate, a top diode material proximate the upper region of the bottom diode material, and an active diode region between the top and bottom diode materials, the active diode region including a surface extending away from the top surface of the substrate.
US09231072B2 Multi-composition gate dielectric field effect transistors
A first gate structure and a second gate structure are formed over a semiconductor material layer. The first gate structure includes a planar silicon-based gate dielectric, a planar high-k gate dielectric, a metallic nitride portion, and a first semiconductor material portion, and the second gate structure includes a silicon-based dielectric material portion and a second semiconductor material portion. After formation of gate spacers and a planarization dielectric layer, the second gate structure is replaced with a transient gate structure including a chemical oxide portion and a second high-k gate dielectric. A work-function metal layer and a conductive material portion can be formed in each gate electrode by replacement of semiconductor material portions. A gate electrode includes the planar silicon-based gate dielectric, the planar high-k gate dielectric, and a U-shaped high-k gate dielectric, and another gate electrode includes the chemical oxide portion and another U-shaped high-k gate dielectric.
US09231068B2 Methods of stress balancing in gallium arsenide wafer processing
Systems, apparatuses, and methods related to the design, fabrication, and manufacture of gallium arsenide (GaAs) integrated circuits are disclosed. Copper can be used as the contact material for a GaAs integrated circuit. Metallization of the wafer and through-wafer vias can be achieved through copper plating processes disclosed herein. To avoid warpage, the tensile stress of a conductive layer deposited onto a GaAs substrate can be offset by depositing a compensating layer having negative stress over the GaAs substrate. GaAs integrated circuits can be singulated, packaged, and incorporated into various electronic devices.
US09231065B2 Semiconductor device and method for forming the same
A semiconductor device in which a gettering layer is formed in a semiconductor substrate, and a method for forming the same are disclosed, resulting in increased reliability of the semiconductor substrate including the gettering layer. The semiconductor device includes a semiconductor substrate; a gettering layer formed of a first-type impurity and a second-type impurity in the semiconductor substrate so as to perform gettering of metal ion; and a deep-well region formed over the gettering layer in the semiconductor substrate.
US09231062B2 Method for treating the surface of a silicon substrate
The present invention relates to a method for chemically treating the surface condition of a silicon substrate for the roughness contrast characterized in that it comprises at least two successive treatment cycles, with each treatment cycle comprising a first step including placing in contact the silicon substrate with a first solution containing water diluted hydrofluoric (HF) acid and then a second step carried out at a temperature of less than 40° C., comprising placing in contact the silicon layer with a second solution containing water (H2O) diluted ammonium hydroxide (NH4OH) and hydrogen peroxide (H2O2), in order to obtain a roughness of less than 0.100 nanometer on a 1 μm×1 μm area upon completion of the treatment cycles.The invention will be applied in the field of microelectronics for the production of transistors, of surfaces for photovoltaic panels or for direct molecular bonding.
US09231055B2 Semiconductor device having fin gate, resistive memory device including the same, and method of manufacturing the same
A semiconductor device having a fin gate that improves an operation current, and a method of manufacturing the same. The semiconductor device includes an active pillar formed on a semiconductor substrate, the active pillar including an inner region and an outer region surrounding the inner region, and a fin gate overlapping an upper surface and a lateral surface of the active pillar. The inner portion of the active pillar includes a first semiconductor layer having a first lattice constant, and the outer region of the active pillar includes a second semiconductor layer having a second lattice constant smaller than the first lattice constant.
US09231046B2 Capacitor using barrier layer metallurgy
A metal-insulator-metal (MIM) capacitor using barrier layer metallurgy and methods of manufacture are disclosed. The method includes forming a bottom plate of a metal-insulator-metal (MIM) capacitor and a bonding pad using a single masking process. The method further includes forming a MIM dielectric on the bottom plate. The method further includes forming a top plate of the MIM capacitor on the MIM dielectric. The method further includes forming a solder connection on the bonding pad.
US09231045B2 Methods for fabricating integrated circuits with polycrystalline silicon resistor structures using a replacment gate process flow, and the integrated circuits fabricated thereby
Integrated circuits and methods for fabricating integrated circuits are provided. In an embodiment, an integrated circuit includes a first transistor structure that includes an etch-stop material layer, a first workfunction material layer disposed over the etch-stop material layer, a second workfunction material layer disposed over the first workfunction material layer, and a metal fill material disposed over the second workfunction material layer. The integrated circuit further includes a second transistor structure that includes a layer of the etch-stop material, a layer of the second workfunction material disposed over the etch-stop material layer, and a layer of the metal fill material disposed over the second workfunction material layer. Still further, the integrated circuit includes a resistor structure that includes a layer of the etch-stop material, a layer of the metal fill material disposed over the etch-stop material layer, and a silicon material layer disposed over the metal fill material layer.
US09231044B2 Light emitting device and method of manufacturing the same
There is provided a light emitting device in which low power consumption can be realized even in the case of a large screen. The surface of a source signal line or a power supply line in a pixel portion is plated to reduce a resistance of a wiring. The source signal line in the pixel portion is manufactured by a step different from a source signal line in a driver circuit portion. The power supply line in the pixel portion is manufactured by a step different from a power supply line led on a substrate. A terminal is similarly plated to made the resistance reduction. It is desirable that a wiring before plating is made of the same material as a gate electrode and the surface of the wiring is plated to form the source signal line or the power supply line.
US09231041B2 Organic light emitting diode display device and method of manufacturing the same
Disclosed is an OLED display device. The OLED display device includes a metal line and a thin film transistor that are formed on a substrate, a first insulating layer formed on the metal line and the thin film transistor, a storage electrode formed on the first insulating layer, and connected to the metal line, a second insulating layer formed on the storage electrode, and an anode electrode formed on the second insulating layer to be connected to the thin film transistor and overlapping the storage electrode with the second insulating layer therebetween.
US09231038B2 Thin film transistor array and EL display employing thereof
EL display has a luminescence unit having a luminescence layer being disposed between a pair of electrodes and a thin film transistor array unit controlling luminescence of the luminescence unit. An interlayer insulation film is disposed between the luminescence unit and the transistor array unit. An anode of the luminescence unit is connected electrically to the thin film transistor array via a contact hole of the interlayer insulation film. The thin film transistor array further has a current supplying relaying electrode that is connected to the anode of the luminescence unit via the contact hole of the interlayer insulation film. A diffusion prevention film is formed on the boundary face of the anode of the luminescence unit and the relaying electrode.
US09231036B2 Organic electroluminescence display device
Provided is an organic electroluminescence display device. The organic electroluminescence display device includes a bank that is provided so as to surround a central portion of a pixel electrode, an organic electroluminescence layer that is provided on the pixel electrode, a common electrode that is formed so as to extend from the organic electroluminescence layer to the bank, a color filter layer that overlaps the organic electroluminescence layer, a black matrix layer that overlaps the bank, a spacer that is provided on the black matrix layer, and a wiring that is provided on the black matrix layer so as to be placed on the spacer. The black matrix layer is disposed on the bank through the spacer. A convex portion is formed by the wiring being placed on the spacer, and the convex portion is electrically connected to the common electrode above the bank.
US09231034B1 Organic light-emitting diode displays
An electronic device may include a display having an array of organic light-emitting diode display pixels. Color filter elements may be used to allow the display to present color images. A blue subpixel may be formed using part of an emissive layer and red and green subpixels may share a separate second part of the emissive layer. In four-subpixel designs, a white or yellow subpixel may also share the emissive layer with the red and green subpixels. Tandem diode configurations may be used in which a blue subpixel has two blue diodes connected in series and other subpixels are formed from respective pairs of series-connected diodes. A pixel definition layer may be formed from a light-absorbing material to suppress ambient light reflections.
US09231026B2 Magnetoresistive sensor module with a structured metal sheet for illumination and method for manufacturing the same
In the method of manufacturing a magnetoresistive sensor module, at first a composite arrangement out of a semiconductor substrate and a metal-insulator arrangement is provided, wherein a semiconductor circuit arrangement is integrated adjacent to a main surface of the semiconductor substrate into the same, wherein the metal-insulator arrangement is arranged on the main surface of the semiconductor substrate and comprises a structured metal sheet and insulation material at least partially surrounding the structured metal sheet, wherein the structured metal sheet is electrically connected to the semiconductor circuit arrangement. Then, a magnetoresistive sensor structure is applied onto a surface of the insulation material of the composite arrangement, and finally an electrical connection between the magnetoresistive sensor structure and the structured metal sheet is established, so that the magnetoresistive sensor structure is connected to the integrated circuit arrangement.
US09231025B2 CMOS-based thermoelectric device with reduced electrical resistance
An integrated circuit containing CMOS transistors and an embedded thermoelectric device may be formed by forming field oxide in isolation trenches to isolate the CMOS transistors and thermoelectric elements of the embedded thermoelectric device. N-type dopants are implanted into the substrate to provide at least 1×1018 cm−3 n-type dopants in n-type thermoelectric elements and the substrate under the field oxide between the n-type thermoelectric elements. P-type dopants are implanted into the substrate to provide at least 1×1018 cm−3 p-type dopants in p-type thermoelectric elements and the substrate under the field oxide between the p-type thermoelectric elements. The n-type dopants and p-type dopants may be implanted before the field oxide are formed, after the isolation trenches for the field oxide are formed and before dielectric material is formed in the isolation trenches, and/or after the field oxide is formed.
US09231023B2 Light-emitting device having a plurality of concentric light transmitting areas
The light-emitting device of the present invention includes LED chips provided on a ceramic substrate and a sealing material in which the LED chips are embedded. The sealing material contains a fluorescent substance and divided into a first fluorescent-substance-containing resin layer and a second fluorescent-substance-containing resin layer by a first resin ring and a second resin ring.
US09231022B2 Imaging device and imaging system
An object of the present invention is to prevent a sensitivity difference between pixels. There are disposed plural unit cells each including plural photodiodes with plural transfer MOSFETs arranged respectively corresponding to the plural photodiodes, and a common MOSFET that amplifies and outputs signals read from the plural photodiodes. The unit cell includes reset and selecting MOSFETs. Within the unit cell, each pair of photodiode and corresponding transfer MOSFET has translational symmetry with respect to one another.
US09231021B2 Image pickup apparatus, image pickup system, and image pickup apparatus manufacturing method
An image pickup apparatus includes a semiconductor substrate, and multiple pixels. Each of the multiple pixels includes a photoelectric-conversion unit disposed in the semiconductor substrate, a first conductive first semiconductor region disposed in the semiconductor substrate, which holds charge generated by the photoelectric-conversion unit at a place different from the photoelectric-conversion unit, a first transfer unit which transfers charge to the first semiconductor region, and a second transfer unit which transfers charge held at the first semiconductor region. The first semiconductor region includes a first portion, a second portion, and a third portion. At the depth where the third portion is disposed, the first portion is disposed between the third portion and first transfer unit, and the second portion is disposed between the third portion and second transfer unit. Impurity concentration of the third portion is lower than that of the first and second portions.
US09231020B2 Device and method of gettering on silicon on insulator (SOI) substrate
Some demonstrative embodiments include devices and/or methods of gettering on silicon on insulator (SOI) substrate. For example, a complementary metal-oxide-semiconductor (CMOS) integrated circuit (IC) may include a plurality of pixels arranged on a wafer, a pixel of the pixels including: a silicon active area; at least one non-silicided leakage-sensitive component formed on the active area, the leakage-sensitive component is sensitive to metal contaminants; a non-leakage-sensitive area formed on the active area, the non-leakage-sensitive area surrounding the leakage-sensitive component; and at least one silicided gettering region formed on the non-leakage-sensitive area to trap the metal contaminants.
US09231017B2 Manufacturing method of semiconductor device
An optical component is fixed precisely on a sensor chip. After a sensor chip including a front surface having a sensor plane with a plurality of light receiving elements is mounted face-up over a wiring substrate, an adhesive is disposed on the front surface of the sensor chip at a plurality of positions, and a plurality of spacers having adherence is formed by curing this adhesive. Then, an adhesive paste is disposed on the front surface of the sensor chip. Then, an optical component held by a bonding tool is disposed on the front surface via the spacer and the adhesive. After that, the bonding tool is separated from the optical component and the optical component is fixed by curing the adhesive in a state in which a load is not applied to the optical component.
US09231015B2 Backside-illuminated photosensor array with white, yellow and red-sensitive elements
A monolithic backside-sensor-illumination (BSI) image sensor has a sensor array is tiled with a multiple-pixel cells having a first pixel sensor primarily sensitive to red light, a second pixel sensor primarily sensitive to red and green light, and a third pixel sensor having panchromatic sensitivity, the pixel sensors laterally adjacent each other. The image sensor determines a red, a green, and a blue signal comprising by reading the red-sensitive pixel sensor of each multiple-pixel cell to determine the red signal, reading the sensor primarily sensitive to red and green light to determine a yellow signal and subtracting the red signal to determine a green signal. The image sensor reads the panchromatic-sensitive pixel sensor to determine a white signal and subtracts the yellow signal to provide the blue signal.
US09231014B2 Back side illumination photodiode of high quantum efficiency
A back side illumination photodiode includes a light-receiving back side surface of a semiconductor material substrate. An area of the light-receiving back side surface includes a recess. The recess is filled with a material having an optical index that is lower than an optical index of the semiconductor material substrate. Both the substrate and the filling material are transparent to an operating wavelength of the photodiode. The recess may be formed to have a ring shape.
US09231013B2 Resonance enhanced absorptive color filters having resonance cavities
Resonance enhanced color filter arrays are provided for image sensors. Resonance cavities formed with color filter materials that enhance the color filtering capabilities of the color filter materials. Resonance enhanced color filter arrays may be provided for back side illumination image sensors and front side illumination image sensors. A layer of high refractive index material or metamaterial may be provided between a microlens and a color filter material to serve as a first partially reflecting interface for the resonance cavity. An optional layer of high refractive index material or metamaterial may be provided between color filter material and a substrate. In front side illumination image sensors, color filter material may be provided in a light guide structure that extends through interlayer dielectric. The color filter material in the light guide structure may form at least part of a resonance cavity for a resonance enhanced color filter array.
US09231011B2 Stacked-chip imaging systems
Imaging systems may be provided with stacked-chip image sensors. A stacked-chip image sensor may include a vertical chip stack that includes an array of image pixels, analog control circuitry and storage and processing circuitry. The array of image pixels, the analog control circuitry, and the storage and processing circuitry may be formed on separate, stacked semiconductor substrates or may be formed in a vertical stack on a common semiconductor substrate. The image pixel array may be coupled to the control circuitry using vertical metal interconnects. The control circuitry may route pixel control signals and readout image data signals over the vertical metal interconnects. The control circuitry may provide digital image data to the storage and processing circuitry over additional vertical conductive interconnects coupled between the control circuitry and the storage and processing circuitry. The storage and processing circuitry may be configured to store and/or process the digital image data.
US09231009B2 Image sensor and imaging device
In an image sensor, if a pixel for focusing has a structure having a light-shielding layer for performing pupil division, between the micro lens and the photoelectric conversion unit, the pixel may be configured such that the focal position of the micro lens is positioned further on the micro lens side than the light-shielding layer, and the distance from the focal position of the micro lens to the light-shielding layer is greater than 0 and less than nFΔ, where n is the refractive index at the focal position of the micro lens, F is the aperture value of the micro lens, and Δ is the diffraction limit of the micro lens. This enables variation in the pupil intensity distribution of the pixel for focusing due to positional production tolerance of components to be suppressed.
US09231003B2 Solid-state imaging device, method for manufacturing solid-state imaging device, and imaging apparatus
A solid-state imaging device includes a first electrode, a second electrode disposed opposing to the first electrode, and a photoelectric conversion layer, which is disposed between the first electrode and the second electrode and in which narrow gap semiconductor quantum dots are dispersed in a conductive layer, wherein one electrode of the first electrode and the second electrode is formed from a transparent electrode and the other electrode is formed from a metal electrode or a transparent electrode.
US09231002B2 Display device and electronic device
To provide a display device including a capacitor whose charge capacity is increased while improving the aperture ratio, provide a display device including a capacitor whose charge capacity can be increased while improving the transmittance of a pixel portion, and provide a display device which consumes low power, the display device includes a transistor including a first oxide semiconductor film in a channel formation region, a second oxide semiconductor film formed over a surface over which the first oxide semiconductor film is formed, a pixel electrode electrically connected to the transistor, and a light-transmitting capacitor in which a dielectric film is provided between two electrodes of a pair. One electrode corresponds to the second oxide semiconductor film, and the other electrode corresponds to the pixel electrode. The second oxide semiconductor film has a smaller thickness than the first oxide semiconductor film.
US09231001B2 Display device
The inventors found out that in the case of performing a low gray scale display in which a very small amount of current is supplied to a light emitting element, variations in threshold voltages of driving transistors become notable since the gate-source voltage is low. In view of this, the invention provides a display device in which variations in the threshold voltages of the driving transistors are reduced even in the low gray scale display, and a driving method thereof. According to the invention, a gate-source voltage of the driving transistor is set higher in the low gray scale display than that in the high gray scale display. As one mode to achieve this, different power source lines are provided for the low gray scale display and the high gray scale display and their potentials are set to be different.
US09231000B2 Thin film transistor array substrate and organic light-emitting display apparatus including the same
A thin film transistor array substrate includes a plurality of pixels, each of the pixels including a capacitor comprising a first electrode, and a second electrode located above the first electrode, a data line extending in a first direction, configured to provide a data signal, located above the capacitor, and overlapping a part of the capacitor, and a driving voltage line configured to supply a driving voltage, located between the capacitor and the data line, and comprising a first line extending in the first direction, and a second line extending in a second direction substantially perpendicular to the first direction.
US09230997B2 Display panel
The present invention provides a display panel including a novel structure that is suitable for preventing a short circuit between terminals. The present invention relates to a display panel including: an active matrix substrate; a counter substrate; and a sealing material, the active matrix substrate including a plurality of terminals outside the display region; and a plurality of insulating films respectively formed from inside to outside the display region, wherein lower portions of the plurality of terminals are formed of a same material as the gate wiring or the source wiring, upper portions of the plurality of terminals are formed of a same material as the pixel electrode, and the plurality of insulating films includes an inorganic insulating film and an organic insulating film thicker than the inorganic insulating film, the inorganic insulating film and the organic insulating film being arranged between the gate wiring or the source wiring and the pixel electrode, the organic insulating film including an end portion arranged on an outer side of a region where the sealing material is provided and at a position distant from a region where the terminals are provided, the inorganic insulating film including an end portion arranged on a boundary between the plurality of wirings and the plurality of terminals.
US09230995B2 Array substrate, manufacturing method thereof and display device
Embodiments of the present application relate to an array substrate, the manufacturing method thereof and a display device. The array substrate comprises: a substrate, of gate lines and of data lines, a plurality of pixel units, defined by the gate lines and the data lines, each of the pixel units comprising a thin film transistor and a pixel electrode, wherein the thin film transistor comprises a source electrode, a drain electrode, an active layer, a gate insulating layer and a gate electrode, and the source electrode and the drain electrode are provided on the substrate opposing to each other with a channel of the thin film transistor provided therebetween, and the pixel electrode is positioned in a region outside the thin film transistor within the pixel unit, and is extended to a position above the drain electrode to be partly lapped over and directly connected to the drain electrode.
US09230994B2 Liquid crystal display device
An object of the present invention is to provide a liquid crystal display device which allows a desirable storage capacitor to be ensured in a pixel without decreasing the aperture ratio in response to changes in frame frequency. In a liquid crystal display device including a pixel transistor and two capacitive elements using an oxide semiconductor material in each pixel, one of the capacitive elements comprises a light-transmitting material to improve the aperture ratio of the pixel. Furthermore, through the use of characteristics of the light-transmitting capacitive element, the size of the storage capacitor in the pixel is varied by adjusting the voltage value of a capacitance value in response to the frame frequency varied depending on images displayed.
US09230993B2 Display apparatus and manufacturing method of the same
Provided are a display apparatus and a manufacturing method of the same. The display apparatus includes: a counter substrate, and an active matrix substrate including a pixel area. The active matrix substrate includes, in a non-transmissive region of each pixel, a transparent substrate, a polycrystalline silicon film, a gate insulating film, a gate electrode, an interlayer insulating film, and a drain layer including patterned conductive films, and includes, in a transparent region of each pixel, the transparent substrate, the gate insulating film and the interlayer insulating film. The interlayer insulating film includes zones where the interlayer insulating film is thinner than a part of the interlayer insulating film at the middle of each transmissive region. The zones are each located so as to extend between the neighboring patterned conductive films and are further located so as not to overlap with the transmissive regions and regions laid over LDD portions of the polycrystalline silicon film.
US09230992B2 Semiconductor device including gate channel having adjusted threshold voltage
A semiconductor device includes at least one first semiconductor fin formed on an nFET region of a semiconductor device and at least one second semiconductor fin formed on a pFET region. The at least one first semiconductor fin has an nFET channel region interposed between a pair of nFET source/drain regions. The at least one second semiconductor fin has a pFET channel region interposed between a pair of pFET source/drain regions. The an epitaxial liner is formed on only the pFET channel region of the at least one second semiconductor fin such that a first threshold voltage of the nFET channel region is different than a second threshold voltage of the pFET channel.
US09230988B2 Mechanisms for forming radio frequency (RF) area of integrated circuit structure
Embodiments of mechanisms of forming a radio frequency area of an integrated circuit are provided. The radio frequency area of an integrated circuit structure includes a substrate, a buried oxide layer formed over the substrate, and an interface layer formed between the substrate and the buried oxide layer. The radio frequency area of an integrated circuit structure also includes a silicon layer formed over the buried oxide layer and an interlayer dielectric layer formed in a deep trench. The radio frequency area of an integrated circuit structure further includes the interlayer dielectric layer extending through the silicon layer, the buried oxide layer and the interface layer. The radio frequency area of an integrated circuit structure includes an implant region formed below the interlayer dielectric layer in the deep trench and a polysilicon layer formed below the implant region.
US09230985B1 Vertical TFT with tunnel barrier
A vertically oriented thin film transistor (TFT) having a tunnel barrier is disclosed. The tunnel barrier may be formed from a dielectric such as silicon oxide or hafnium oxide. The vertically oriented TFT selection device with tunnel barrier may serve as a selection device in a 3D memory array. The vertically oriented TFT may be used to connect/disconnect a global bit line to/from a vertical bit line in a 3D memory array. The vertically oriented TFT may be used to connect/disconnect a source line to/from a channel of a vertical NAND string in a 3D memory array. A vertical TFT with tunnel barrier has a high breakdown voltage, low leakage current, and high on current. The tunnel barrier can be at the top junction or bottom junction of the TFT.
US09230978B2 Semiconductor constructions and NAND unit cells
Some embodiments include methods of forming semiconductor constructions. Alternating layers of n-type doped material and p-type doped material may be formed. The alternating layers may be patterned into a plurality of vertical columns that are spaced from one another by openings. The openings may be lined with tunnel dielectric, charge-storage material and blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed within the lined openings. Some embodiments include methods of forming NAND unit cells. Columns of alternating n-type material and p-type material may be formed. The columns may be lined with a layer of tunnel dielectric, a layer of charge-storage material, and a layer of blocking dielectric. Alternating layers of insulative material and conductive control gate material may be formed between the lined columns. Some embodiments include semiconductor constructions, and some embodiments include NAND unit cells.
US09230974B1 Methods of selective removal of blocking dielectric in NAND memory strings
Methods of making a monolithic three dimensional NAND string may enable selective removal of a blocking dielectric material, such as aluminum oxide, without otherwise damaging the device. Blocking dielectric may be selectively removed from the back side (e.g., slit trench) and/or front side (e.g., memory opening) of the NAND string. Also disclosed are NAND strings made in accordance with the embodiment methods.
US09230971B2 NAND string containing self-aligned control gate sidewall cladding
A method of making a NAND string includes forming a tunnel dielectric over a semiconductor channel, forming a charge storage layer over the tunnel dielectric, forming a blocking dielectric over the charge storage layer, and forming a control gate layer over the blocking dielectric. The method also includes patterning the control gate layer to form a plurality of control gates separated by trenches, and reacting a first material with exposed sidewalls of the plurality of control gates to form self aligned metal-first material compound sidewall spacers on the exposed sidewalls of the plurality of control gates.
US09230968B2 Methods of forming memory arrays and semiconductor constructions
Some embodiments include methods of forming semiconductor constructions. A heavily-doped region is formed within a first semiconductor material, and a second semiconductor material is epitaxially grown over the first semiconductor material. The second semiconductor material is patterned to form circuit components, and the heavily-doped region is patterned to form spaced-apart buried lines electrically coupling pluralities of the circuit components to one another. At least some of the patterning of the heavily-doped region occurs simultaneously with at least some of the patterning of the second semiconductor material.
US09230967B2 Method for forming self-aligned isolation trenches in semiconductor substrate and semiconductor device
The instant disclosure relates to a method for forming self-aligned isolation trenches in semiconductor substrate, comprising the following steps. The first step is providing a semiconductor substrate defined a plurality of active areas thereon. The next step is forming at least two buried bit lines in each of the active areas and an insulating structure disposed above and opposite to the at least two buried bit lines. The next step is forming a self-aligned spacer on the sidewalls of each of the insulating structures. The last step is selectively removing the semiconductor substrate with the self-aligned spacers as masks to form a plurality of isolation trenches.
US09230966B2 Capacitor and method of manufacturing the same
A capacitor includes a substrate, a multilayer over the substrate, a plurality of container-shaped storage node structures on the semiconductor substrate and surrounded by the multilayer, the storage node structure has a sidewall extending upwardly from the base to the top, where the sidewall includes an upper segment and a lower segment thinner than the upper segment, a capacitor dielectric material along a surface of each storage node structure, and a capacitor electrode material over the capacitor dielectric material.
US09230964B2 Stacked three dimensional semiconductor device with in-circuit antenna
A semiconductor device includes: a first semiconductor chip having a first antenna that is formed in a first hole provided in the first semiconductor chip, has an inclined surface inclined with respect to a central line of the first hole, and transmits and receives a radio wave; and a second semiconductor chip stacked over the first semiconductor chip, the second semiconductor chip having a second antenna that is formed in a second hole provided in the second semiconductor chip, has an inclined surface inclined with respect to a central line of the second hole, and transmits and receives a radio wave, wherein the first antenna and the second antenna are disposed so that the inclined surface of the first antenna and the inclined surface of the second antenna face each other.
US09230963B2 Semiconductor device with dual work function gate stacks and method for fabricating the same
A method for fabricating a semiconductor device includes forming a gate dielectric layer over a substrate; forming a metal containing layer, containing an effective work function adjust species, over the gate dielectric layer; forming an anti-reaction layer over the metal containing layer; increasing an amount of the effective work function adjust species contained in the metal containing layer; and forming, on the substrate, a gate stack by etching the anti-reaction layer, the metal containing layer, and the gate dielectric layer.
US09230960B1 Combined tap cell and spare cell for logic circuit
Embodiments of the present disclosure provide an apparatus for providing a combined tap cell and spare cell in a logic design. An integrated circuit contains a plurality of logic cells that are arranged in a series of columns and rows and that include one or more transistors. A first cell includes a logic portion including one or more transistors, and a tap portion. The tap portion provides tap connectivity to the one or more transistors of the subset of the plurality of logic cells, and to the one or more transistors of the logic portion.
US09230956B2 Junction field effect transistors and associated fabrication methods
A JFET having a semiconductor substrate of a first doping type, an epitaxial layer of the first doping type located on the semiconductor substrate, a body region of a second doping type located in the epitaxial layer, a source region of the first doping type located in the epitaxial layer, a gate region of the second doping type located in the body region, and a shielding layer of the second doping type located in the epitaxial layer, wherein the semiconductor substrate is configured as a drain region, the shielding layer is in a conductive path formed between the source region and the drain region.
US09230950B2 Method for producing an electronic device by assembling semi-conducting blocks and corresponding device
At least three electrically conducting blocks are disposed within an isolating region; and at least two of them are mutually separated and capacitively coupled by a part of the isolating region. At least two of them, being semiconductor, have opposite types of conductivity or identical types of conductivity, but with different concentrations of dopants, and these are in mutual contact by one of their sides. The mutual arrangement of these blocks within the isolating region, their type of conductivity and their concentration of dopants form at least one electronic module. Some of the blocks define input and output blocks.
US09230945B2 Light-emitting device
A light-emitting device is provided. The light-emitting device comprises a substrate and a light-emitting element. The substrate comprises a first variable resistor, a second variable resistor, an insulation portion and a carrier. The insulation portion is located between the first variable resistor and the second variable resistor. The carrier is surrounded by the insulation portion, and the light-emitting element is disposed on the carrier. The first variable resistor, the second variable resistor and the insulation portion respectively penetrate the substrate.
US09230944B1 Techniques and configurations associated with a capductor assembly
Embodiments of the present disclosure are directed toward techniques and configurations associated with a capductor assembly. In one embodiment, a capductor assembly may include a semiconductor wafer and a plurality of inductors disposed on a first side of the semiconductor wafer. The plurality of inductors may be embedded in electrically insulative material having a plurality of interconnect structures disposed thereon. The plurality of interconnect structures may be configured to electrically couple the plurality of inductors to a die. The IC assembly may further include a plurality of capacitors disposed on a second side of the wafer disposed opposite the first side of the wafer. The plurality of capacitors may be electrically coupled with a second plurality of interconnect structures that may be configured to electrically couple the plurality of capacitors with the die. Other embodiments may be described and/or claimed.
US09230943B2 Solid state illumination device
A solid state illumination device includes a semiconductor light emitter mounted on a base and surrounded by sidewalls, e.g., in a circular, elliptical, triangular, rectangular or other appropriate arrangement, to define a chamber. A top element, which may be reflective, may be coupled to the sidewalls to further define the chamber. The light produced by the semiconductor light emitter is emitted through the sidewalls of the chamber. The sidewalls and/or top element may include wavelength converting material, for example, as a plurality of dots on the surfaces. An adjustable wavelength converting element may be used within the chamber, with the adjustable wavelength converting element being configured to adjust the surface area that is exposed to the light emitted by the semiconductor light emitter in the chamber to alter an optical property of the chamber.
US09230942B2 Semiconductor device including alternating stepped semiconductor die stacks
A semiconductor device including alternating stepped semiconductor die stacks to allow for large numbers of semiconductor die to be provided within a semiconductor device using short wire bonds.
US09230941B2 Bonding structure for stacked semiconductor devices
A semiconductor device, and a method of fabrication, is introduced. In an embodiment, one or more passivation layers are formed over a first substrate. Recesses are formed in the passivation layers and a first bonding pad, a second bonding pad, and a first via are formed in the recesses. In some embodiment, the first via may have electrical contact with the first bonding pad and may provide an electrical pathway to a first plurality of metallization layers. The first bonding pad and the second bonding pad in the first substrate are aligned to a third bonding pad and the fourth bonding pad in a second substrate and may be bonded using a direct bonding method. A bond between the first bonding pad and the third bonding pad may provide an electrical pathway between devices on the first substrate and devices on the second substrate.
US09230933B2 Semiconductor device and method of forming conductive protrusion over conductive pillars or bond pads as fixed offset vertical interconnect structure
A semiconductor device has a semiconductor die mounted to a substrate. A plurality of conductive pillars is formed over a semiconductor die. A plurality of conductive protrusions is formed over the conductive pillars. Bumps are formed over the conductive protrusions and conductive pillars. Alternatively, the conductive protrusions are formed over the substrate. A conductive layer is formed over the substrate. The semiconductor die is mounted to the substrate by reflowing the bumps at a temperature that is less than a melting point of the conductive pillars and conductive protrusions to metallurgically and electrically connect the bumps to the conductive layer while maintaining a fixed offset between the semiconductor die and substrate. The fixed offset between the semiconductor die and substrate is determined by a height of the conductive pillars and a height of the conductive protrusions. A mold underfill material is deposited between the semiconductor die and substrate.
US09230932B2 Interconnect crack arrestor structure and methods
A system and method for preventing cracks is provided. An embodiment comprises placing crack stoppers into a connection between a semiconductor die and a substrate. The crack stoppers may be in the shape of hollow or solid cylinders and may be placed so as to prevent any cracks from propagating through the crack stoppers.
US09230915B2 Semiconductor packages including through electrodes and methods of manufacturing the same
A semiconductor package includes a substrate and a plurality of semiconductor chips stacked on the substrate. Each of the semiconductor chips has a front surface, a rear surface opposite to the front surface, a sidewall surface connecting the front surface to the rear surface, a vertical through electrode extending from the front surface toward the rear surface with a predetermined depth, and a horizontal through electrode laterally extending from the sidewall surface to be connected to the vertical through electrode. At least one connection member is disposed on the sidewall surfaces of the semiconductor chips to connect the horizontal through electrodes of the semiconductor chips to each other. Related methods are also provided.
US09230913B1 Metallization layers configured for reduced parasitic capacitance
Structures and methods to minimize parasitic capacitance in a circuit structure are provided. The structure may include a substrate supporting one or more circuits and one or more metallization layers above the substrate. The metallization layer includes a conductive pattern defined by an array of conductive fill elements, where the conductive fill elements of the array are discrete, electrically isolated elements sized to satisfy, at least in part, a pre-defined minimum area-occupation ratio for a chemical-mechanical polishing of the metallization layer, and to minimize parasitic capacitance within the metallization layer, as well as minimize parasitic capacitance between the metallization layer and the circuit, and if multiple metallization layers are present, between the layers.
US09230910B2 Oversized contacts and vias in layout defined by linearly constrained topology
A rectangular-shaped interlevel connection layout structure is defined to electrically connect a first layout structure in a first chip level with a second layout structure in a second chip level. The rectangular-shaped interlevel connection layout structure is defined by an as-drawn cross-section having at least one dimension larger than a corresponding dimension of either the first layout structure, the second layout structure, or both the first and second layout structures. A dimension of the rectangular-shaped interlevel connection layout structure can exceed a normal maximum size in one direction in exchange for a reduced size in another direction. The rectangular-shaped interlevel connection layout structure can be placed in accordance with a gridpoint of a virtual grid defined by two perpendicular sets of virtual lines. Also, the first and/or second layout structures can be spatially oriented and/or placed in accordance with one or both of the two perpendicular sets of virtual lines.
US09230904B2 Methods of forming a stack of electrodes and three-dimensional semiconductor devices fabricated thereby
Provided are methods of forming a stack of electrodes and three-dimensional semiconductor devices fabricated thereby. The device may include electrodes sequentially stacked on a substrate to constitute an electrode structure. each of the electrodes may include a connection portion protruding horizontally and outward from a sidewall of one of the electrodes located thereon and an aligned portion having a sidewall coplanar with that of one of the electrodes located thereon or thereunder. Here, at least two of the electrodes provided vertically adjacent to each other may be provided in such a way that the aligned portions thereof have sidewalls that are substantially aligned to be coplanar with each other.
US09230903B2 Multi-die, high current wafer level package
Wafer-level package semiconductor devices for high-current applications are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar. The wafer-level package device also includes an integrated circuit chip device (e.g., small die) configured upon the integrated circuit chip (e.g., large die). In the wafer-level package device, the height of the integrated circuit chip device is less than the height of the pillar and/or less than the combined height of the pillar and the one or more solder contacts.
US09230898B2 Integrated circuit packaging system with package-on-package and method of manufacture thereof
A method of manufacture of an integrated circuit packaging system includes: providing a substrate; mounting a component over a side of the substrate; forming an interface module having a module via in any location for connectivity to the substrate; and mounting the entirety of the interface module over a portion of the side of the substrate next to the component.
US09230896B2 Semiconductor device and method of reflow soldering for conductive column structure in flip chip package
A semiconductor device comprises a substrate and a semiconductor die. Bumps are formed over the substrate or a first surface of the semiconductor die. Conductive columns devoid of solder are formed over the substrate or the first surface of the semiconductor die. The semiconductor die is disposed over the substrate. A collet including a first cavity and a second cavity formed in a surface of the first cavity is mounted over the semiconductor die with a second surface of the semiconductor die opposite the first surface disposed within the first cavity. The bumps are reflowed. A force is applied to the collet to hold the bumps to the conductive columns while reflowing the bumps to make electrical connection to the conductive columns. The collet is removed. An underfill material is deposited between the semiconductor die and substrate. An encapsulant is deposited over the semiconductor die and substrate.
US09230888B2 Wafer back side coating as dicing tape adhesive
A semiconductor assembly comprises a semiconductor wafer, an adhesive coating disposed on the back side of the wafer, and a bare dicing tape, preferably UV radiation transparent. The assembly is prepared by the method comprising (a) providing a semiconductor wafer, (b) disposing a wafer back side coating on the semiconductor wafer, (c) partially curing the wafer back side coating to the extent that it adheres to the back side of the wafer and remains tacky, and (d) contacting the bare dicing tape to the partially cured and tacky wafer back side coating, optionally with heat and pressure.
US09230886B2 Method for forming through silicon via with wafer backside protection
Semiconductor devices with through silicon vias (TSVs) are formed without copper contamination. Embodiments include exposing a passivation layer surrounding a bottom portion of a TSV in a silicon substrate, forming a silicon composite layer over the exposed passivation layer and over a bottom surface of the silicon substrate, forming a hardmask layer over the silicon composite layer and over the bottom surface of the silicon substrate, removing a section of the silicon composite layer around the bottom portion of the TSV using the hardmask layer as a mask, re-exposing the passivation layer, and removing the hardmask layer and the re-exposed passivation layer to expose a contact for the bottom portion of the TSV.
US09230883B1 Trace stacking structure and method
A substrate includes a stacked trace formed from a trace and a first buildup trace stacked on the trace. The first buildup trace contacts and is electrically connected to the trace along the entire length of the trace. The current carrying cross-sectional area of the stacked trace is greater than the current carrying cross-sectional area of the trace. Accordingly, a plurality of the stacked traces can be formed with a small width and thus small pitch yet with a large current carrying cross-sectional area.
US09230882B2 Signal transmission device
Thermal connection between a plurality of communication modules and a heatsink placed on these communication modules is securely achieved and maintained. In a signal transmission device in which a common heatsink is arranged on a plurality of communication modules equipped on a board, the signal transmission device has a coil spring provided between the board and the communication modules, and the communication modules are biased toward the heatsink by the coil spring so that an upper surface of the communication module is pressed against a bottom surface of the heatsink.
US09230880B2 Electronic device and method for fabricating an electronic device
An electronic device includes a semiconductor chip including an electrode, a substrate element and a contact element connecting the electrode to the substrate element. The electronic device further includes an encapsulant configured to leave the contact element at least partially exposed such that a heatsink may be connected to the contact element.
US09230877B2 Methods of forming serpentine thermal interface material and structures formed thereby
Methods of forming a microelectronic packaging structure and associated structures formed thereby are described. Those methods may include forming a thermal interface material comprising a thermally conductive serpentine foil located between a first and a second interface material. The serpentine foil may be in a parallel position or a rotated position, in embodiments.
US09230876B2 Stack type semiconductor package
A stack type semiconductor package includes: a lower semiconductor package including a lower package substrate, and a lower semiconductor chip which is mounted on the lower package substrate and includes a first surface facing a top surface of the lower package substrate and a second surface opposite to the first surface; an upper semiconductor package including an upper package substrate and an upper semiconductor chip which is mounted on the upper package substrate; an inter-package connection unit which connects the lower package substrate and the upper package substrate; a heat dissipation member which is formed on the second surface of the lower semiconductor chip; and an interconnection unit which is formed on a bottom surface of the upper package substrate, and is adhered to the heat dissipation member to connect the lower semiconductor chip and the upper package substrate.
US09230874B1 Integrated circuit package with a heat conductor
An integrated circuit (IC) package with a heat conductor is disclosed. The IC package has an IC disposed on a surface of a package substrate. A molding compound injected into the IC package surrounds the IC package and covers the perimeter of the top surface of the IC, exposing the center portion of the top surface of the IC. A heat conductor is disposed onto the top surface of the IC that is not covered by the molding compound. The heat conductor is placed such that the heat conductor lies adjacent to the center portion of the top surface of the IC and the edges of the heat conductor are surrounded by the molding compound.
US09230873B2 Semiconductor package resin composition and usage method thereof
A semiconductor package resin composition of the present invention includes an epoxy resin, a curing agent, inorganic particles, nano-particles surface treated with a silane that contains a photopolymerizable functional group, and a photopolymerization initiator.
US09230868B2 Warp correction device and warp correction method for semiconductor element substrate
A warp correction apparatus includes an injection mechanism including a nozzle that performs injection treatment, an adsorption table that holds the semiconductor element substrate by adsorption at a principal surface side or a film surface side, a moving mechanism that moves the adsorption table so that the semiconductor element substrate relatively moves with respect to an injection area of an injection particle by the nozzle, an injection treatment chamber that houses the semiconductor element substrate held on the adsorption table and in the interior of which injection treatment is performed, a measurement mechanism that measures a warp of the semiconductor element substrate, and a control device that, based on a difference between a target warp amount and a warp amount measured by the measurement mechanism, performs at least either one of a setting processing of an injection treatment condition of the injection mechanism and an accept/reject determination of the semiconductor element substrate for which injection treatment has been performed.
US09230865B2 Semiconductor device and manufacturing method thereof
A semiconductor device is provided which includes an N-type semiconductor layer and a P-type semiconductor layer coexisting in the same wiring layer without influences on the properties of a semiconductor layer. The semiconductor device includes a first wiring layer with a first wiring, a second wiring layer with a second wiring, and first and second transistors provided in the first and second wiring layers. The first transistor includes a first gate electrode, a first gate insulating film, a first oxide semiconductor layer, a first hard mask layer, and first insulating sidewall films covering the sides of the first oxide semiconductor layer. The second transistor includes a second gate electrode, a second gate insulating film, a second oxide semiconductor layer, and a second hard mask layer.
US09230864B1 Method of forming a semiconductor device having a metal gate
A method of forming a semiconductor device having a metal gate includes the following steps. First of all, a first gate trench is formed in a dielectric layer. Next, a first work function layer is formed, covering the first gate trench. Then, a protection layer is formed in the first gate trench, also on the first work function layer. Then, a patterned sacrificial mask layer is formed in the first gate trench to expose a portion of the protection layer. After that, the exposed protection layer is removed, to form a U-shaped protection layer in the first gate trench. As following, a portion of the first work function layer under the exposed protection layer is removed, to form a U-shaped first work function layer in the first gate trench. Finally, the patterned sacrificial mask layer and the U-shaped protection layer are completely removed.
US09230863B2 Method for producing integrated circuit with smaller grains of tungsten
Integrated circuits with tungsten components having a smooth surface and methods for producing such integrated circuits are provided. A method of producing the integrated circuits includes forming a nucleation layer overlying a substrate and within a cavity, where the nucleation layer includes tungsten. A nucleation layer thickness is reduced, and a fill layer if formed overlying the nucleation layer.
US09230858B2 Semiconductor device and method for manufacturing the same
A semiconductor device is manufactured by etching a semiconductor substrate including an active region, forming a bit line contact hole from which the active region is protruded, forming a first spacer exposing a top of the active region at each of an inner wall and a bottom of the bit line contact hole, forming a bit line contact plug and a bit line over the exposed active region, and forming a second spacer over the semiconductor substrate including not only the bit line contact plug but also the bit line.
US09230854B2 Semiconductor device and method
A system and method for a semiconductor device are provided. An embodiment comprises a dielectric layer, a hard mask layer over the dielectric layer, and a capping layer over the hard mask layer. A multi-patterning process is performed to form an interconnect using the capping layer as a mask to form an opening for the interconnect.
US09230850B2 Method for manufacturing a multilayer structure on a substrate
The invention relates to a method for manufacturing a multilayer structure on a first substrate made of a material having a first Young's modulus. The method includes: providing a second substrate covered with the multilayer structure, the multilayer structure having a planar surface opposite the second substrate, the second substrate being made of a material having a second Young's modulus; applying first deformations to said surface; molecularly boding the first substrate to said surface, the molecular bonding resulting in the appearance of second deformation in said surface in the absence of the first deformations, the first deformations being opposite the second deformations; and removing the second substrate, the resulting deformations in said surface being less than 5 ppm.
US09230841B2 Substrate processing apparatus
A substrate processing apparatus including a frame, a first SCARA arm connected to the frame, including an end effector, configured to extend and retract along a first radial axis; a second SCARA arm connected to the frame, including an end effector, configured to extend and retract along a second radial axis, the SCARA arms having a common shoulder axis of rotation; and a drive section coupled to the SCARA arms is configured to independently extend each SCARA arm along a respective radial axis and rotate each SCARA arm about the common shoulder axis of rotation where the first radial axis is angled relative to the second radial axis and the end effector of a respective arm is aligned with a respective radial axis, wherein each end effector is configured to hold at least one substrate and the end effectors are located on a common transfer plane.
US09230836B2 Substrate treatment method
A substrate treatment method that includes circulating a treatment liquid from a treatment vessel through a circulation path extending through a filter and a temperature controller, spouting the treatment liquid toward a substrate accommodated in the treatment vessel to recover the treatment liquid in the treatment vessel, and controlling the liquid surface level of the treatment liquid retained in the treatment vessel below the substrate held at a substrate treatment position.
US09230835B2 Integrated platform for fabricating n-type metal oxide semiconductor (NMOS) devices
Embodiments of an integrated platform for fabricating n-type metal oxide semiconductor (NMOS) devices are provided herein. In some embodiments, an integrated platform for fabricating n-type metal oxide semiconductor (NMOS) devices may include a first deposition chamber configured to deposit a first layer atop the substrate, the first layer comprising titanium oxide (TiO2) or selenium (Se); a second deposition chamber configured to deposit a second layer atop the first layer, the second layer comprising titanium; a third deposition chamber configured to deposit a third layer atop the second layer, the third layer comprising one of titanium nitride (TiN) or tungsten nitride (WN).
US09230833B2 Methods to prevent filler entrapment in microelectronic device to microelectronic substrate interconnection structures
Embodiments of the present description include methods for attaching a microelectronic device to a microelectronic substrate with interconnection structures after disposing of an underfill material on the microelectronic device, wherein filler particless within the underfill material may be repelled away from the interconnection structures prior to connecting the microelectronic device to the microelectronic structure. These methods may include inducing a charge on the interconnection structures and may include placing the interconnection structures between opposing plates and producing a bias between the opposing plates after depositing the underfill material on the interconnection structures.
US09230830B2 Bridging arrangement and method for manufacturing a bridging arrangement
A bridging arrangement for coupling a first terminal to a second terminal includes a plurality of particles of a first type forming at least one path between the first terminal and the second terminal, wherein the particles of the first type are attached to each other; a plurality of particles of a second type arranged in a vicinity of a contact region between a first particle of the first type and a second particle of the first type, wherein at least a portion of the plurality of particles of the second type is attached to the first particle of the first type and the second particle of the first type.
US09230829B2 Adhesive compound and method for encapsulating an electronic arrangement
The invention relates to a method for encapsulating an electronic arrangement against permeants, wherein an electronic arrangement is made available on a substrate, wherein, in a vacuum, that area of the substrate which embraces that region of the electronic arrangement which is to be encapsulated, preferably said area and that region of the electronic arrangement which is to be encapsulated, is brought into contact with a sheet material comprising at least one adhesive compound and a composite is produced therefrom. The invention also relates to an apparatus for implementing the method and to an encapsulated electronic arrangement produced thereby.
US09230827B2 Method for forming a resist under layer film and patterning process
The present invention provides a method for forming a resist under layer film used in a lithography process, comprising: a process for applying a composition for forming a resist under layer film containing an organic compound having an aromatic unit on a substrate; and a process for heat-treating the resist under layer film applied in an atmosphere whose oxygen concentration is 10% or more at 150° C. to 600° C. for 10 to 600 seconds after heat-treating the same in an atmosphere whose oxygen concentration is less than 10% at 50 to 350° C. There can be provided a method for forming a resist under layer film having excellent filling/flattening properties so that unevenness on a substrate can be flattened even in complex processes such as multi-layer resist method and double patterning.
US09230822B1 Uniform gate height for mixed-type non-planar semiconductor devices
A semiconductor structure with mixed n-type and p-type non-planar transistors includes a residual overlapping mask bump on one or more of the dummy gates. A dielectric layer is created over the structure having a top surface above the residual bump, for example, using a blanket deposition and chemical-mechanical underpolish (i.e., stopping before exposing the gate cap). The residual bump is then transformed into a same material as the dielectric, either in its entirety and then removing the combined dielectric, or by removing the dielectric first and partly removing the residual bump, the remainder of which is then transformed and the dielectric removed. In either case, the structure is planarized for further processing.
US09230816B1 Method for fabricating semiconductor device
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having a gate structure thereon and an interlayer dielectric (ILD) layer around the gate structure; forming a dielectric layer on the gate structure and the ILD layer; forming a patterned hard mask on the dielectric layer; forming an opening in the dielectric layer and the ILD layer; performing a silicide process for forming a silicide layer in the opening; removing the patterned hard mask and un-reacted metal after the silicide process; and forming a contact plug in the opening.
US09230815B2 Methods for depositing fluorine/carbon-free conformal tungsten
Provided are atomic layer deposition methods to deposit a tungsten film or tungsten-containing film using a tungsten-containing reactive gas comprising one or more of tungsten pentachloride, a compound with the empirical formula WCl5 or WCl6.
US09230813B2 One-time programmable memory and method for making the same
A one time programmable nonvolatile memory formed from metal-insulator-semiconductor cells. The cells are at the crosspoints of conductive gate lines and intersecting doped semiconductor lines formed in a semiconductor substrate.
US09230811B2 Active layer ion implantation method and active layer ion implantation method for thin-film transistor
Disclosed are an active layer ion implantation method and an active layer ion implantation method for thin-film transistor. The active layer ion implantation method comprises: applying a photoresist on the active layer; and implanting ions into the active layer through the photoresist.
US09230803B2 Method for growing III-V epitaxial layers
Disclosed are methods of growing III-V epitaxial layers on a substrate, semiconductor structures thus obtained, and devices comprising such semiconductor structures. An example semiconductor substrate includes a substrate and a buffer layer on top of the substrate, where a conductive path is present between the substrate and buffer layer. A conductive path may be present in the conductive interface, and the conductive path may be interrupted by one or more local electrical isolations. The local electrical isolation(s) may be positioned with the device such that at least one of the local electrical isolation(s) is located between a high voltage terminal and a low voltage terminal of the device.
US09230801B2 Graphene structure and method of fabricating the same
A graphene structure and a method of forming the same may include a graphene formed in a three-dimensional (3D) shape, e.g., a column shape, a stacking structure, and a three-dimensionally connected structure. The graphene structure can be formed by using Ge.
US09230800B2 Plasma activated conformal film deposition
Methods of depositing a film on a substrate surface include surface mediated reactions in which a film is grown over one or more cycles of reactant adsorption and reaction. In one aspect, the method is characterized by the following operations: (a) exposing the substrate surface to a first reactant in vapor phase under conditions allowing the first reactant to adsorb onto the substrate surface; (b) exposing the substrate surface to a second reactant in vapor phase while the first reactant is adsorbed on the substrate surface; and (c) exposing the substrate surface to plasma to drive a reaction between the first and second reactants adsorbed on the substrate surface to form the film.
US09230799B2 Method for fabricating semiconductor device and the semiconductor device
A method for fabricating a semiconductor device including GaN (gallium nitride) that composes a semiconductor layer and includes forming a gate insulating film, in which at least one film selected from the group of a SiO2 film and an Al2O3 film is formed on a nitride layer containing GaN by using microwave plasma and the formed film is used as at least a part of the gate insulating film.
US09230792B2 Ion generation using modified wetted porous materials
The invention generally relates to ion generation using modified wetted porous materials. In certain aspects, the invention generally relates to systems and methods for ion generation using a wetted porous substrate that substantially prevents diffusion of sample into the substrate. In other aspects, the invention generally relate to ion generation using a wetted porous material and a drying agent. In other aspects, the invention generally relates to ion generation using a modified wetted porous substrate in which at least a portion of the porous substrate includes a material that modifies an interaction between a sample and the substrate.
US09230790B2 DC ion funnels
Systems and related methods are disclosed herein that generally involve focusing dispersed ions using one or more DC ion funnels. In some embodiments, a DC ion funnel is provided that includes a plurality of ring-shaped electrodes, each having an aperture formed therein such that the funnel defines an interior volume extending between an ion inlet and an ion outlet. A controller applies a DC potential to each of the electrodes without applying an RF potential to any of the electrodes, such that ions entering the funnel are substantially confined within said volume. The interior volume can have any of a variety of shapes, such as cylindrical, frusto-conical, and curved frusto-conical. In addition, any of a variety of DC potentials can be applied to the plurality of electrodes.
US09230786B1 Off-axis channel in electrospray ionization for removal of particulate matter
The present invention relates to electrospray ionization (ESI) at atmospheric pressure coupled with a mass spectrometer, in particular to a special kind of micro-electrospray with liquid flows in the range of 0.1 to 100 microliters per minute. The invention describes the use of an off-axis pre-entrance channel in an ESI ion source to prevent particulate matter with higher inertia than the (charged) gas molecules, such as droplets, from entering the mass spectrometer. The elimination of the particulate matter improves the quantitative precision of an LC/MS bioassay, minimizes the contamination of the mass spectrometer and improves the robustness for high throughput assays.
US09230781B2 Capacitive-coupled plasma processing apparatus and method for processing substrate
The present invention relates to a capacitive-coupled plasma processing apparatus, wherein an electric field regulating element, i.e., an “electric field lens”, is arranged in the reaction chamber to generate a regenerated electric field in a direction opposite to that of the original radio frequency electric field in the reaction chamber, so that the non-uniformity of etching rate on the surface of the substrate of the plasma incurred by the original radio frequency electric field is decreased; and the electric field regulating element, i.e., the “electric field lens”, further decreases the equivalent quality factor Q value of the reaction chamber, expands the radio frequency band, and prevents high-voltage electric arcing. The present invention further provides a method for processing the substrate using the processing apparatus.
US09230779B2 Methods and apparatus for correcting for non-uniformity in a plasma processing system
A plasma processing system having a plasma processing chamber comprising at least one of a chamber wall and a chamber liner is disclosed. The plasma processing system includes a plurality of ground straps disposed around a circumference of a chamber surface, the chamber surface being one of the chamber walls and the chamber liner of the plasma processing chamber. The plasma processing system further includes at least a first impedance device coupled to at least a first ground strap of the plurality of ground straps, wherein a second ground strap of the plurality of ground straps is not provided with a second impedance device having the same impedance value as the first impedance device.
US09230772B2 Device and method for ion generation
Illustrative embodiments of the present invention are directed to devices and methods for ion generation. One such device includes a substrate. The substrate is disposed within a housing that is configured to contain a gas. The substrate includes an interior surface that at least partially defines an interior volume. The substrate also includes a number of channels with walls. Nano-tips are disposed on the walls of the channels.
US09230767B2 Blocking element for an electrical switch
A blocking element is disclosed for blocking the movement of a handle or a switching lever of an electrical switch. In at least one embodiment, the blocking element is switchable between at least two positions. In the first position, the blocking element can block the movement of the handle or of the switching lever and, in the second position, the blocking element cannot block the movement of the handle or of the switching lever.
US09230765B2 Modular overload relay assembly with mechanically isolated connector
A mating connector assembly for electrically coupling modular electrical devices. A first stationary connector is coupled to a first rigid circuit board positioned within a first housing of a first modular electrical device. The first floating connector is coupled to a flexible circuit element positioned within a second housing of a second modular electrical device, the flexible circuit element coupled to a circuit board positioned within a second housing of a second modular electrical device. The second housing includes a first latch plate adjustable between an unlatched position and a latched position, the first latch plate including a biasing member, such that, when the first modular electronic device is pressed together with the second modular electronic device, the biasing member applies a force to the first floating connector during a latch plate transition position to ensure that the first floating connector has fully mated with the first stationary connector.
US09230759B2 Gas circuit breaker
A gas circuit breaker includes: a pair of electrodes provided so as to be able to come in contact with and separate from each other; and an insulating material that is placed so as to generate a decomposition gas in response to a direct or indirect action from an arc occurring between the pair of electrodes when a current is broken, wherein the decomposition gas generated from the insulating material when the current is broken is configured to be utilized for extinguishing the arc, and wherein an ablative material that does not include hydrogen atoms but has a carbon-oxygen bond in a main chain or ring part is used as the insulating material.
US09230755B2 Switch assembly for a mobile device
A switch assembly for an electronic device comprises a switch mount and a keycap. The switch mount has a slide switch with a slide switch base and a slide switch actuator. The keycap is positionable for slidable movement relative to the switch mount and is coupleable to the slide switch actuator. The keycap has an exposed portion slidable by a user between at least a first position and a second position to execute a first control function. The keycap is depressible in at least one of the first and second positions to execute a second control function.
US09230754B2 Pointing stick cursor key and illuminated keyboard therewith
The illuminated keyboard includes a base plate, a backlight module, a plurality of input keys and a mask layer. The backlight module and the plurality of input keys are disposed on opposite sides of the base plate. The mask layer is disposed between the base plate and the backlight module. A pointing stick cursor key includes a holding structure, an opening and a masking portion. The holding structure with a hole is disposed on the base plate. The opening is formed on the mask layer in a position corresponding to the holding structure. The holding structure is extended into the backlight module via the opening. The at least one masking portion is connected to a periphery of the opening for bendably attaching against the holding structure for covering the hole when the holding structure is extended into the backlight module via the opening.
US09230752B2 Seat switch assembly
A seat switch assembly can maintain a reliable switching operation due to enhanced durability. A pressing plate has guides which are fastened to guide holes of a base. A seat switch housing is fastened to an assembly hole of the base. An actuation rod is received inside a through-hole of the seat switch housing, and moves in the top-bottom direction in response to a pressure from the pressing plate. A V-shaped contact pin is fixed to a fixing guide of the actuation rod. One portion of a terminal pin is buried inside the seat switch housing, and the other portion of the terminal pin is exposed to the outside. A return spring is received in the lower portion of the actuation rod. A cover closes the lower portion of the through-hole. The inner surfaces of the through-hole and the terminal pin are coplanar without a stepped portion.
US09230750B2 Gas circuit breaker
An outer peripheral wall surrounds a heating chamber that communicates with an arc chamber through an opening that separates fixed contacts from each other in a circumferential direction. The outer peripheral wall includes a heat-resistive cylindrical heat-flow receiving wall portion that is arranged at a position opposed to the opening in a radial direction, and a cylindrical wall portion that is connected to the heat-flow receiving wall portion in a direction of a center axis and also connected to a fixed-side energizing member at its one end on the opposite side to where the wall portion is connected to the heat-flow receiving wall portion, and is made of an insulating material. With this configuration, the outer peripheral wall surrounding the heating chamber can be protected from damage and heat deterioration due to the influence of hot gas.
US09230746B2 Nonaqueous electrolytic solution and electrochemical device using the same
The object of the present invention is to provide a nonaqueous electrolytic solution that can improve the electrochemical properties in a broad temperature range and an electrochemical device using the same. A nonaqueous electrolytic solution prepared by dissolving an electrolyte salt in a nonaqueous solvent, wherein the nonaqueous solvent includes 0.1 to 30% by volume of a fluorine atom-containing cyclic carbonate, and further the nonaqueous electrolytic solution includes 0.001 to 5% by mass of a branched dinitrile compound in which the main chain of an alkylene chain linking the two nitrile groups has 2 or more and 4 or less of the carbon number.
US09230743B2 Gravure printing plate and manufacturing method thereof, gravure printing machine, and manufacturing method for laminated ceramic electronic component
Banks, as well as a plurality of substantially recess-shaped cells defined by the banks, are provided in an image section formed in a gravure printing plate. Each of edge cells located along an outer edge of the image section is provided with a projecting portion that projects from a part of a base surface of that edge cell, and each projecting portion is distanced from the banks and located closer to the outer edge than the center of the corresponding edge cell. Preferably, the projecting portions and the banks that face the outer edge are positioned at a predetermined interval from the outer edge, and substantially frame-shaped recess portions that extend continuously along the outer edge are provided in the image section.
US09230740B2 Multilayer ceramic electronic part to be embedded in board and printed circuit board having multilayer ceramic electronic part embedded therein
There is provided a multilayer ceramic electronic part to be embedded in a board, including: a ceramic body including dielectric layers and having first and second main surfaces facing each other, first and second side surfaces facing each other, and first and second end surfaces facing each other; first and second internal electrodes; and first and second external electrodes formed on both end portions of the ceramic body, wherein the first external electrode includes a first base electrode and a first terminal electrode formed on a portion of the first base electrode formed on at least one of the first and second main surfaces of the ceramic body, the second external electrode includes a second base electrode and a second terminal electrode formed on a portion of the second base electrode formed on at least one of the first and second main surfaces of the ceramic body.
US09230732B2 Wireless power transfer
A wireless power transmitter can include a transmitting coil configured to wirelessly transmit power to a receiving coil. The wireless power transmitter can include a shield residing on a given side of a substrate spaced apart from the transmitting coil. The shield can be configured to filter an electric field induced by the transmitting coil.
US09230731B2 Fault current limiter with saturated core
A three-phase current limiter (30) for an alternating current system includes an AC magnetic circuit having at least one AC coil (35R1, 35S1, 35T1) for each phase of a 3-phase AC supply wound on a saturable ferromagnetic core and configured to subject respective AC coils for each phase to a common magnetic flux, and a DC magnetic circuit (34a, 34b) for biasing the AC magnetic circuit into saturation at normal conditions. In use the AC coils are connected in series with a load and during alternate half cycles of the AC supply at least one of the AC coils produces a magnetic field that opposes a magnetic field of the DC magnetic circuit. The AC coils (35R, 35S, 35T) for each phase are configured so that at least one of the AC coils exhibits unbalanced magnetic impedance relative to remaining ones of the AC coils for each phase.
US09230730B2 Bi-toroidal topology transformer
The present invention relates to electrical transformers and, in particular, to improvements to efficiency in energy conversion in electrical transformers. The improved transformer has a bi-toroidal circuit topology in which the magnetic flux passing through the primary and secondary coils are different. The turns ratio displays an “effective magnification” like an impedance transformed by a feedback loop. The result is a transformer which displays virtually no primary input current increase from no-load to on-load and an on-load power factor of zero for a purely resistive load.
US09230724B2 Cooling system and superconducting magnet apparatus employing the same
A cooling system and a superconducting magnet apparatus employing the same. The cooling system includes: a thermal shield unit for thermally shielding a superconducting coil; a recondensing unit for recondensing an extremely low temperature refrigerant that cools down the superconducting coil. A cryocooler includes a body and an end portion extending from the body and inserted into the recondensing unit in order to directly contact the extremely low temperature refrigerant. A refrigerator chamber penetrates through the thermal shield unit and to which the cryocooler is attachably and detachably provided. A sealing member is disposed between the cryocooler and the refrigerator chamber to seal the recondensing unit.
US09230719B2 Method for producing an electrical component, and electrical component
A method for producing an electrical component, comprises providing a ceramic semiconducting base body (10) having a surface (O10) and a first side area (S10a) lying opposite the surface (O10), wherein a metallic layer (40) is contained within the base body. After at least two further metallic layers (210) have been arranged separately from one another on the side area (S10a) of the base body, the arrangement is sintered. An electrically insulating layer (30) is arranged between the at least two further metallic layers (210). A respective contact layer (220) is arranged on the metallic layers (210) by means of a chemical process. In this case, the material of the base body (10) is removed proceeding from the surface (O10) of the base body (10) at most as far as the metallic layer (40) arranged within the base body.
US09230715B2 Flat cable
A flat cable includes at least two conductors offset from and in parallel with one another, and an insulating covering disposed over a periphery of the conductors. The insulating covering includes a vinyl chloride-based resin composition with a brittle temperature from −40° Celsius to −25° Celsius, a hardness D from 35 to 55, and heating deformation of 10% or below. The vinyl chloride-based resin composition substantially contains only vinyl chloride homopolymer as the resin component.
US09230712B2 Flexible plastic hose and method for its manufacture
Flexible plastic hose comprising a flexible wall made out of a plurality of laterally connected windings of a helically wound profile, wherein the windings of the profile are attached to each other by means of a weld, wherein the profile comprises a web part with predetermined properties for providing flexibility to the hose, and wherein the profile ends on both sides in an upright part. The weld is located between the upright part of the adjacent windings and together with these upright parts forms a helical reinforcement rib on the flexible wall of the hose with predetermined properties for providing hub strength to the hose.
US09230704B2 Hard coat film, and radiation image conversion panel using the same
A hard coat film includes: a transparent base material; and a hard coat layer formed on the transparent base material, wherein the hard coat layer includes a cured product obtained by curing a composition including: an ultraviolet curable acrylate resin including one or more types of multifunctional acrylate; first microparticles having an average particle diameter of 5 nm or more and 100 nm or less; and a thermoplastic polyester resin.
US09230702B2 System and method for reducing grid line image artifacts
An imaging system includes a detector configured to detect X-rays from an X-ray source. The detector includes multiple photodetector elements. The imaging system also includes an anti-scatter grid disposed over the detector, wherein the anti-scatter grid includes multiple radiation absorbing elements. At least a portion of one or more of the radiation absorbing elements of the multiple radiation absorbing elements is disposed on each photodetector element, and a total area of each respective portion of the one or more radiation absorbing elements disposed on each photodetector element is substantially equal.
US09230701B2 Collimator and CT equipment comprising the same
An X-ray collimator has a collimation plate, and a shielding box made of a tungsten plastic composite, the shielding box having an opening on the top and the bottom thereof respectively, and a support part for supporting the shielding box. The collimation plate is disposed on the shielding box or the support part. Compared to the use of the shielding box alone, the collimator reduces the volume of the collimator without reducing its shielding performance.
US09230696B2 Control rod for a nuclear power light water reactor
The invention concerns a control rod configured for a nuclear power light water reactor of the BWR or PWR kind. The control rod contains absorber material. At least 50%, with respect to weight, of the absorber material that is in the control rod is in the form of hafnium hydride. The invention also concerns the use of such a control rod during operation in a nuclear power light water reactor of the BWR or PWR kind.
US09230690B2 Register file write ring oscillator
Embodiments of a register file test circuit are disclosed that may allow for determining write performance at low power supply voltages. The register file test circuit may include a decoder, a multiplexer, a frequency divider, and a control circuit. The decoder may be operable to select a register cell within a register file, and the control circuit may be operable to controllably activate the read and write paths through the selected register cell, allowing data read to be inverted and re-written back into the selected register cell.
US09230687B2 Implementing ECC redundancy using reconfigurable logic blocks
A method, system and computer program product are provided for implementing ECC (Error Correction Codes) redundancy using reconfigurable logic blocks in a computer system. When a fail is detected when reading from memory, it is determined if the incorrect data is in the data or the ECC component of the data. When incorrect data is found in the ECC component of the data, and an actionable threshold is not reached, a predetermined Reliability, Availability, and Serviceability (RAS) action is taken. When the actionable threshold is reached with incorrect data identified in the ECC component of the data, an analysis process is performed to determine if the ECC logic is faulty. When a fail in the ECC logic is detected, the identified ECC failed logic is replaced with a spare block of logic.
US09230686B2 Semiconductor device having roll call circuit
Disclosed herein is an apparatus that includes: a plurality of memory banks each including a plurality of memory cells; a plurality of redundant circuits each allocated to an associated one of the plurality of memory banks to replace a defective memory cell among the plurality of memory cells included in the associated memory bank; a plurality of roll call circuits allocated to an associated one of the plurality of memory banks to generate a roll call data when an address corresponding to the defective memory cell is supplied; and a plurality of data buses commonly allocated to the plurality of memory banks. The roll call circuits output the roll call data to the plurality of data buses in parallel.
US09230683B2 Semiconductor device and driving method thereof
An error of stored data is detected with high accuracy. Data (e.g., a remainder in a CRC) used for detecting an error is stored in a memory in which an error is unlikely to occur. Specifically, the following semiconductor device is used: a memory element including a plurality of transistors, a capacitor, and a data storage portion is provided in a matrix; the data storage portion includes one of a source and a drain of one of the plurality of transistors, a gate of another one of the plurality of transistors, and one electrode of the capacitor; a semiconductor layer including a channel of the transistor, the one of the source and the drain of which is connected to the data storage portion, has a band gap of 2.8 eV or more, or 3.2 eV or more; and the data storage portion stores data for detecting an error.
US09230682B2 Method and system for automated device testing
Embodiments described herein provide enhanced testing of devices. For example, in an embodiment, an interposer for testing devices is provided. The interposer includes a substrate, a first plurality of connection elements located on a surface of the substrate, and a memory device electrically coupled to the first plurality of connection elements through the substrate. The first plurality of connection elements are configured to mate with a second plurality of connection elements located on a device under test. The memory device is configured to store information received from the device under test and to output stored information to the device under test.
US09230677B2 NAND array hiarchical BL structures for multiple-WL and all-BL simultaneous erase, erase-verify, program, program-verify, and read operations
Several 2D and 3D HiNAND flash memory arrays with 1-level or 2-level broken BL-hierarchical structures are provided for Multiple Whole-WL and All-BL simultaneous operations in Dispersed Blocks. The global bit line (GBL) is divided to multiple 1(top)-level broken metal2 GBLs plus optional lower-level broken metal1 local bit lines (LBLs). A preferred Vinhibit supply higher than Vdd can be selectively supplied via horizontal metal0 power line LBLps to charge selected broken GBLs/LBLs which can also be selectively discharged via a String source line. Charge-sharing technique for precharging and discharging of broken GBL/LBL capacitors for NAND cell data sensing is used in Read and Verify operations with reduced power consumption and latency. Recall technique to restore the desired Program Data stored in the broken GBL/LBL capacitors is used for Multiple-WL and All-BL Program and Program-Verify operation with reduced program current for highest program yield superior P/E cycles.
US09230675B2 Semiconductor memory device using a current mirror
A semiconductor memory device is disclosed. The semiconductor memory device includes a current mirror configured to include a current mirror section for current of a first line to a second line and transistors coupled in parallel, a detector configured to control a voltage of the first line based on voltages of sensing nodes, a fail bit set section configured to control a voltage of the second line, and a comparator configured to compare the voltage of the first line with the voltage of the second line and generate a pass and fail check signal based on the comparing result.
US09230673B2 Method and apparatus for reading data stored in flash memory by referring to binary digit distribution characteristics of bit sequences read from flash memory
A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from the memory cells by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences.
US09230672B2 High-resolution readout of analog memory cells
A method includes storing data in an analog memory cell by writing an analog value into the memory cell. After storing the data, the data stored in the memory cell is read by discharging electrical current to flow through the memory cell, during a predefined time interval, while applying a variable voltage to a gate of the memory cell. A fraction of the predefined time interval, during which the variable voltage allows the electrical current to flow through the memory cell, is estimated. The stored data is estimated based on the estimated fraction.
US09230670B2 Semiconductor device, memory system and operating method thereof
There are a semiconductor device including: a plurality of memory blocks including a plurality of pages; peripheral circuits configured to perform a least significant bit read operation and a most significant bit read operation of a selected page included in a selected block; and a control circuit including a least significant bit read-retry table and a most significant bit read-retry table which have a plurality of indexes, and configured to control the peripheral circuits to store an index used when error correction is possible among the least significant bit read-retry table in the least significant bit read operation and perform the most significant bit read operation by first selecting the stored index among the most significant bit read-retry table.
US09230668B2 Semiconductor memory apparatus
A semiconductor memory apparatus including a latch unit configured to be driven in response to activation of a reset selection signal and resetting a first node and a second node; and an auxiliary driving unit configured to support a driving force of the latch unit in response to the reset selection signal and a voltage logic level of the first node or the second node, wherein the first node and the second node have substantially opposite voltage logic levels.
US09230666B2 Drain select gate voltage management
Some embodiments include apparatus, systems, and methods that operate to apply a first value of a drain select gate voltage during a first portion of a programming time period associated with programming a plurality of memory cells, and to apply a second value of the drain select gate voltage different from the first value during a second, subsequent portion of the programming time period. The drain select gate voltage may be changed between groups of programming pulses in a single programming cycle. The first and second portions may be determined according to the number of applied programming pulses, the number of memory cells that have been completely programmed, and/or other conditions. Additional apparatus, systems, and methods are disclosed.
US09230662B2 Eprom cell
The present invention relates to a register cell comprising one output node, at least two power supply nodes, and a first flash transistor and a second flash transistor, wherein the register cell is configured so that the output node can be driven by at least one of the power supply nodes as a function of the value stored in at least one of the flash transistors. The invention further relates to an FPGA comprising the register cell.
US09230661B2 Determining soft data for combinations of memory cells
The present disclosure includes apparatuses and methods for determining soft data for combinations of memory cells. A number of embodiments include an array of memory cells, wherein the array includes a first memory cell and a second memory cell, wherein the first and second memory cells are each programmable to one of a number of program states, and wherein a combination of the program states of the first and second memory cells corresponds to one of a number of data states. A number of embodiments also include a buffer and/or a controller coupled to the array and configured to determine soft data associated with the program states of the first and second memory cells and determine soft data associated with the data state that corresponds to the combination of the program states of the first and second memory cells based, at least in part, on the soft data associated with the program state of the first memory cell and the soft data associated with the program state of the second memory cell.
US09230656B2 System for maintaining back gate threshold voltage in three dimensional NAND memory
In a nonvolatile memory array in which a NAND string includes a back gate that has a charge storage element, the threshold voltage of the back gate is monitored, and if the threshold voltage deviates from a desired threshold voltage range, charge is added to, or removed from the charge storage element to return the threshold voltage to the desired threshold voltage range.
US09230655B2 Data storage management in analog memory cells using a non-integer number of bits per cell
A method for data storage includes, in a first programming phase, storing first data in a group of memory cells by programming the memory cells in the group to a set of initial programming levels. In a subsequent second programming phase, second data is stored in the group by identifying the memory cells in the group that were programmed in the first programming phase to respective levels in a predefined partial subset of the initial programming levels, and programming only the identified memory cells with the second data, so as to set at least some of the identified memory cells to one or more additional programming levels that are different from the initial programming levels. The memory cells to which the second data was programmed are recognized by reading only a partial subset of the first data. The second data is read from the recognized memory cells.
US09230654B2 Method and system for accessing a flash memory device
An apparatus, system, and computer-implemented method for controlling data transfer between a plurality of serial data link interfaces and a plurality of memory banks in a semiconductor memory is disclosed. In one example, a flash memory device with multiple links and memory banks, where the links are independent of the banks, is disclosed. The flash memory devices may be cascaded in a daisy-chain configuration using echo signal lines to serially communicate between memory devices. In addition, a virtual multiple link configuration is described wherein a single link is used to emulate multiple links.
US09230652B2 Flash memories using minimum push up, multi-cell and multi-permutation schemes for data storage
Rank modulation has been recently proposed as a scheme for storing information in flash memories. Three improved aspects are disclosed. In one aspect the minimum push-up scheme, for storing data in flash memories is provided. It aims at minimizing the cost of changing the state of the memory. In another aspect, multi-cells, used for storing data in flash memories is provided. Each transistor is replaced with a multi-cell of mm transistors connected in parallel. In yet another aspect, multi-permutations, are provided. The paradigm of representing information with permutations is generalized to the case where the number of cells in each level is a constant greater than one.
US09230643B2 Verify or read pulse for phase change memory and switch
Embodiments disclosed herein may relate to applying verify or read pulses for phase change memory and switch (PCMS) devices. The read pulses may be applied at a first voltage for a first period of time. A threshold event for the phase change memory cell may be detected during a sense window. The sense window may close after the expiration of the first period of time for which the read pulses are applied.
US09230642B2 Variable resistance memory device and a variable resistance memory system including the same
A variable resistance memory system includes a variable resistance memory device including a memory cell array including first and second areas; and a memory controller configured to control the variable resistance memory device. The first area includes first variable resistance memory cells including a first variable resistance material layer and the second area includes second variable resistance memory cells including a second variable resistance material layer having a metallic doping concentration higher than a metallic doping concentration of the first variable resistance material layer. The first variable resistance memory cells are used as storage and the second variable resistance memory cells are used as a buffer memory.
US09230638B1 Semiconductor memory device including plurality of memory cells and method of operating the same
A method includes performing a pre-reading on memory cells selected from a plurality of memory cells according to a pre-read voltage and determining whether the selected memory cells each are read as a first logical value or a second logical value, comparing a number of memory cells read as the first logical value among the selected memory cells with a predetermined number, and when the number of selected memory cells read as the first logical value is smaller than the predetermined number, performing a first main reading of the selected memory cells, the first main reading adapted to read a memory cell that stores multiple bits.
US09230637B1 SRAM circuit with increased write margin
Transistors are connected to ground outside of an SRAM array column. One transistor is connected from VSS to ground on the Q side of an SRAM cell. Another transistor is connected from VSS to ground on the Q′ (Q complement) side of an SRAM cell. Each transistor is gated by is complementary bit line. The Q side transistor is gated by the BL′ (bit line complement, or “BLC”) line, and the Q′ side is gated by the BL line. The ground of the complement side is disconnected during a write operation to increase the performance of a state change during a write operation where a logical one is written to the Q node, thus improving write margin.
US09230633B2 Memory device with timing overlap mode
In some examples, a memory device is configured to receive a precharge command and an activate command. The memory device performs a first series of events related to the precharge command in response to receiving the precharge command and a second series of events related to the activate command in response to receiving the activate command. The memory device delays the start of the second series of events until the first series of events completes.
US09230631B2 Differential current sensing scheme for magnetic random access memory
A circuit includes a cell segment, first and second reference cells, and a current sense amplifier. The first and second reference cells are configured to store opposite logic values, respectively. The current sense amplifier is configured with a first node and a second node for currents therethrough to be compared with each other. The current sense amplifier includes a multiplexer configured to couple the first reference cell or the second reference cell to the first node of the current sense amplifier, and couple the second reference cell or the first reference cell to the second node of the current sense amplifier in a first mode, and couple a cell of the cell segment to the first node of the current sense amplifier, and couple the first and second reference cells to the second node of the current sense amplifier in a second mode.
US09230622B2 Simultaneous two/dual port access on 6T SRAM
A method includes generating a first and a second internal clock signal from a clock signal, wherein a first internal clock signal edge of the first internal clock signal and a second internal clock signal edge of the second internal clock signal are generated from a same edge of the clock signal. A first one of the first and the second internal clock edges is used to trigger a first operation on a six-transistor (6T) Static Random Access Memory (SRAM) cell of a SRAM array. A second one of the first and the second internal clock edges is used to trigger a second operation on the 6T SRAM cell. The first and the second operations are performed on different ports of the 6T SRAM. The first and the second operations are performed within a same clock cycle of the clock signal.
US09230607B2 Hard drive mounting and shock system
A mounting system can be used in a storage device or other electrical device to mount a component, such as a drive, while also providing at least some shock absorption. The mounting system can include a deflection arm, a protrusion and a hole. The protrusion and hole can be configured to engage one another. One of either the hole or the protrusion can be on the deflection arm and the other can be on the component being mounted. The mounting system can also include a locking tab configured to move to a position behind the deflection arm. The locking tab can decrease the amount of deflection that can be experienced by the deflection arm to prevent the component from becoming prematurely dislodged from the mounting system.
US09230606B2 Mounting apparatus assembly
A mounting apparatus includes a bracket and a pivoting member. A first sliding slot, a second sliding slot, a first guiding slot and a locating hole are defined in the bracket. A pivoting hole, a first guiding portion, a second guiding portion and a resisting wall are located on the pivoting member. A locating block is positioned on the resisting wall. A fastening member and a pivoting portion are configured to be positioned on a hard disc drive. The pivoting portion is passed through the pivoting hole, the first guiding portion is slid in a second guiding slot in the hard disc drive, the fastening member is slid in the first sliding slot. The pivoting portion is slid in the second sliding slot, the second guiding portion is slid in the first guiding slot, the resisting wall is rotated until the locating block is locked in the locating hole.
US09230604B2 Video indexing method, video indexing apparatus and computer readable medium
A video indexing method, a video indexing apparatus, and a computer readable medium are disclosed. The video indexing apparatus comprises a generation module, a calculation module and a construction module. The generation module generates a frame movement analysis graphics according to a plurality of analysis points corresponding to a plurality of video frames of a video record. The calculation module calculates a plurality of frame movement velocities corresponding to the video frames according to the frame movement analysis graphics. The construction module constructs an indexing graphics of the video record according to the frame movement velocities.
US09230603B2 Display device for having a function of searching a divided screen, and the method for controlling the same
Disclosed herein are a video apparatus including a screen-division searching function and a method of controlling the same, which are capable of solving problems caused in a process of reproducing and checking a recorded broadcasting program at a high speed. The method of controlling the video apparatus includes selecting specific video data stored in a memory, and dividing a full screen into a plurality of partial screens, dividing the selected specific video data into a plurality of portions, and respectively displaying the portions of the selected specific video data on the plurality of partial screens. Accordingly, it is possible check the whole contents of a specific broadcasting to—accurately program or a material recorded by a closed circuit television (CCTV) camera at a high speed.
US09230601B2 Media markup system for content alteration in derivative works
A classification method and system for possible content alteration of a media work may include criteria regarding content that is feasible for alteration. Such criteria may be maintained in records that are accessible to an interested party. Some embodiments may include a record of primary authorization rights applicable to a possible content alteration. A further embodiment feature may include a record of secondary authorization rights applicable to substitute altered content incorporated in a derivative version. Various exemplary identifier markup schemes indicative of a location or category of an alterable media content component may be implemented for audio, visual, and audio/video alterable content.
US09230600B2 Data recording method for storing first data and second data into a tape medium
Provided is a method for recording data to a tape medium in such a manner as to achieve the easy management of mutually related multiple data pieces. First data and second data continuously received as a file from a higher level apparatus are accumulated in multiple buffer segments in the form of multiple successive data sets. A data structure is determined for each of the accumulated data sets. Management information indicating a result of the determination is added to the data sets, and the data sets and the management information thereof are stored into the tape medium.
US09230593B1 Data storage device optimizing spindle motor power when transitioning into a power failure mode
A data storage device is disclosed comprising a spindle motor configured to rotate a disk, wherein the spindle motor comprises a plurality of windings. The windings are commutated based on a commutation sequence while applying a driving voltage to each winding, wherein the driving voltage comprises an operating amplitude during normal operation. When a supply voltage falls below a threshold, the spindle motor is configured into a power generator by at least reducing the amplitude of the driving voltage to substantially zero and then incrementally increasing the amplitude of the driving voltage by at least two steps toward the operating amplitude.
US09230591B2 Optical disc library and storage apparatus including disc changer functionality
In an optical disc library apparatus having a cartridge storing discs; a drive carrying out recording and playback with respect to the discs; and a robot carrying out disc movements between the aforementioned cartridge and the aforementioned drive; wherein: the periphery of a disc is point restrained in three places during disc movement.
US09230588B2 Magnetic recording medium and magnetic storage apparatus
A magnetic recording medium includes a substrate, a magnetic layer including an alloy having an L10 type crystal structure as a main component thereof, a plurality of underlayers arranged between the substrate and the magnetic layer, and a barrier layer made of a material having an NaCl structure. The plurality of underlayers include at least one crystalline underlayer including Mo as a main component thereof, and at least one of Si and C in a range of 1 mol % to 20 mol % and an oxide in a range of 1 vol % to 50 vol %. The barrier layer is provided between the magnetic layer and the at least one crystalline underlayer including Mo.
US09230587B1 Air bearing surface design with extreme particle trapping holes for improving HDD particle robustnes
Embodiments disclosed herein generally relate to a head slider within disk drive data storage devices. A head slider comprises a head body having a leading portion on a leading edge and a trailing portion on a trailing edge. The leading portion includes a first leading pad disposed at the MFS and a second leading pad disposed between the first leading pad and the leading edge. The second leading pad is recessed a first vertical distance from the MFS. One or more particle trapping holes are disposed between the first leading pad and the second leading pad. The one or more particle trapping holes are recessed a second vertical distance from the MFS, the second vertical distance being greater than the first vertical distance. Particles encountered by the leading portion may be suctioned into the one or more particle trapping holes, preventing the particles from building-up onto the MFS.
US09230585B1 Per wedge preheat DFH to improve data storage device performance
A disk drive is disclosed including a disk having a plurality of tracks, wherein each track comprises a plurality of data sectors and a plurality of servo sectors. The disk drive further comprises a spindle motor for rotating the disk, and a head actuated radially over the disk, wherein the head comprises a dynamic fly height (DFH) heater. Control circuitry within the disk drive is operable to position the head over one of the tracks; determine a number of servo sectors to pass under the head before a target location over the track is reached, apply an initial amount of power to the DFH heater that is dependent at least in part on the determined number of servo sectors, and decrease the initially-applied amount of power applied to the DFH heater until a predetermined target power is reached.
US09230584B1 Position demodulation apparatus and position demodulation method
According to one embodiment, a position demodulation apparatus is provided which demodulates a first demodulated signal and a second demodulated signal, based on a servo-pattern read signal read out by a head from a medium, acquires a plurality of sets of a vector length and phase angle of vectors on a phase plane denoting the first and second demodulated signals, detects a phase angle for which the vector length is greatest based on the sets acquired, and executes rotational correction using the difference between the detected phase angle and a particular reference angle as a correction amount.
US09230579B1 Comb gripper for use with a shipping comb and a ramp in the assembly of a disk drive
A comb gripper is disclosed for use in the assembly of a disk drive. The comb gripper may be used to push a comb tower of a shipping comb such that a head stack assembly (HSA) of the disk drive is rotated and a head gimbal assembly (HGA) of the disk drive is coupled to a ramp of the disk drive. The comb gripper may comprise: a first gripper finger that includes a protruding portion; a second gripper finger; and an actuator. The actuator may be configured to move the first and second gripper fingers, wherein the actuator is configured to move the protruding portion of the first gripper finger to contact the comb tower and to push the comb tower and the shipping comb such that the HSA is rotated and the HGA is coupled to the ramp.
US09230576B1 Scissor reader with side shield decoupled from bias material
Embodiments disclosed herein generally relate to a magnetic head having a sensor stack and a bias material that is aligned in a direction perpendicular to a media facing surface. The sensor stack and a first portion of the bias material are laterally bookended by synthetic antiferromagnetic (SAF) structures, and a second portion of the bias material is laterally bookended by a dielectric material. In this configuration, the SAF structures are decoupled from the bias material, which minimizes the disturbance to the bias material.
US09230573B1 Magnetic recording head with non-magnetic bump structure formed on spin torque oscillator
A magnetic write head having a write pole with a tapered trailing edge and a magnetic oscillator formed on the trailing edge of the write pole. The magnetic oscillator is sandwiched between the magnetic write pole and a trailing magnetic shield. The write head also includes a non-magnetic, electrically conductive bump structure located over a back portion of the magnetic oscillator between the magnetic oscillator and the trailing magnetic shield. The presence of the non-magnetic, electrically conductive bump structure causes electrons to properly flow through the magnetic oscillator in a direction that is generally perpendicular to the plane of the magnetic oscillator, even when the magnetic oscillator is formed on an inclined plane on the tapered trailing edge of the write pole. This thereby ensures optimal performance of the magnetic oscillator.
US09230572B2 Noble metal surrounded magnetic lip and heat sink for heat assisted magnetic recording head
The embodiments of the present invention generally relate to a magnetic head having a magnetic lip. The vertical sides and the bottom of the magnetic lip are covered by one or more conductive layers. In one embodiment, the bottom of the magnetic lip is covered by a first conductive layer and the vertical sides of the magnetic lip are covered by a second conductive layer. The conductive layers are made of a material that would not react with oxygen, thus no oxide films are formed on the vertical sides and the bottom of the magnetic lip during the manufacturing of the magnetic head.
US09230568B1 Magnetic head for perpendicular magnetic recording including a coil having an inclined front end face
A magnetic head includes a coil, a main pole, a trailing shield, a gap section, a return path section, and a coil underlayer. The main pole has a top surface including a first inclined portion and a flat portion. The coil includes a specific coil element. The specific coil element has a bottom surface facing toward the top surface of the main pole, and a front end face inclined with respect to a medium facing surface. The coil underlayer lies under the specific coil element, and has a front end face. The trailing shield includes a portion interposed between the front end face of the coil underlayer and the medium facing surface. The bottom surface of the specific coil element includes a second inclined portion.
US09230567B1 Spin torque oscillator, microwave-assisted magnetic recording head, magnetic recording head assembly, and magnetic recording and resuming device
According to one embodiment, a microwave-assisted magnetic recording head includes a SIL formed either in an area outside a FGL in a track width direction or in an area outside a FGL in a depth direction perpendicular to an air bearing surface of the FGL. An area between the SIL and the FGL can be enlarged, and an intermediate layer can be formed therebetween such that an area in which the intermediate layer contacts the FGL can be enlarged as well.
US09230564B2 Methods for fabricating magnetic transducers using post-deposition tilting
In one general embodiment, a method is provided for fabricating magnetic structures using post-deposition tilting. A thin film magnetic transducer structure is formed on a substantially planar portion of a substrate such that a plane of deposition of the thin film transducer structure is substantially parallel to a plane of the substrate. Additionally, the thin film transducer structure is caused to tilt at an angle relative to the plane of the substrate. The thin film transducer is fixed at the angle after being tilted.
US09230559B2 Server and method of controlling the same
A server which interacts with a display apparatus is provided. The server includes a storage unit configured to store conversation patterns for each service domain, a communication unit configured to receive a user's voice from the display apparatus, and a control unit configured to determine a service domain including the user's voice, generate response information corresponding to the user's voice based on a conversation pattern of the determined service domain, and to control the communication unit to transmit the response information to the display apparatus. When it is determined that a currently received user's voice is included in another service domain which is different from a service domain including a previously received user's voice, the control unit generates the response information corresponding to the currently received user's voice based on a conversation pattern of the other service domain.
US09230556B2 Voice instructions during navigation
A method of providing navigation on an electronic device when the display screen is locked. The method receives a verbal request to start navigation while the display is locked. The method identifies a route from a current location to a destination based on the received verbal request. While the display screen is locked, the method provides navigational directions on the electronic device from the current location of the electronic device to the destination. Some embodiments provide a method for processing a verbal search request. The method receives a navigation-related verbal search request and prepares a sequential list of the search results based on the received request. The method then provides audible information to present a search result from the sequential list. The method presents the search results in a batch form until the user selects a search result, the user terminates the search, or the search items are exhausted.
US09230553B2 Fixed codebook searching by closed-loop search using multiplexed loop
A pulse location search device (400) is equipped with: a first search unit (401) that obtains a first location where a first pulse is located by conducting a first preliminary selection with respect to a first candidate group, and conducting a first search; a second search unit (402) that obtains a second location where a second pulse is located by using the first location and conducting a second search with respect to all of the location candidates of a second candidate group of locations where the second pulse is located; and a third search unit (403) that obtains a third location where the first pulse is located by using the second location and conducting a second preliminary selection with respect to the first candidate group, and conducting a third search with respect to the result of the second preliminary selection.
US09230552B2 Advanced encoding of music files
A system for the playback of content files includes a memory storing a content file including a plurality of stems, each stem encoding a portion of the audio of a sound recording, multiple stems in the plurality of stems representing different portions of the sound recording for the same time period, the content file also including a set of instructions controlling playback of the stems. A decoder is configured to decode the stems according to the set of instructions to create an audio output signal.
US09230549B1 Multi-modal communications (MMC)
A multi-modal communications system integrates multiple different communications channels and modalities into a single user interface that enables operators to monitor and respond to multiple audio and text communications.
US09230548B2 Hybrid hashing scheme for active HMMS
Embodiments of the present invention include a data storage device and a method for storing data in a hash table. The data storage device can include a first memory device, a second memory device, and a processing device. The first memory device is configured to store one or more data elements. The second memory device is configured to store one or more status bits at one or more respective table indices. In addition, each of the table indices is mapped to a corresponding table index in the first memory device. The processing device is configured to calculate one or more hash values based on the one or more data elements.
US09230544B2 Spoken dialog system based on dual dialog management using hierarchical dialog task library
The present invention relates to a spoken dialog system and method based on dual dialog management using a hierarchical dialog task library that may increase reutilization of dialog knowledge by constructing and packaging the dialog knowledge based on a task unit having a hierarchical structure, and may construct and process the dialog knowledge using a dialog plan scheme about relationship therebetween by classifying the dialog knowledge based on a task unit to make design of a dialog service convenient, which is different from an existing spoken dialog system in which it is difficult to reuse dialog knowledge since a large amount of construction costs and time is required.
US09230537B2 Voice synthesis apparatus using a plurality of phonetic piece data
A voice signal is synthesized using a plurality of phonetic piece data each indicating a phonetic piece containing at least two phoneme sections corresponding to different phonemes. In the apparatus, a phonetic piece adjustor forms a target section from first and second phonetic pieces so as to connect the first and second phonetic pieces to each other such that the target section includes a rear phoneme section of the first piece and a front phoneme section of the second piece, and expands the target section by a target time length to form an adjustment section such that a central part is expanded at an expansion rate higher than that of front and rear parts of the target section, to thereby create synthesized phonetic piece data having the target time length. A voice synthesizer creates a voice signal from the synthesized phonetic piece data.
US09230536B2 Voice synthesizer
A candidate voice segment sequence generator 1 generates candidate voice segment sequences 102 for an input language information sequence 101 by using DB voice segments 105 in a voice segment database 4. An output voice segment sequence determinator 2 calculates a degree of match between the input language information sequence 101 and each of the candidate voice segment sequences 102 by using a parameter 107 showing a value according to a cooccurrence criterion 106 for cooccurrence between the input language information sequence 101 and a sound parameter showing the attribute of each of a plurality of candidate voice segments in each of the candidate voice segment sequences 102, and determines an output voice segment sequence 103 on the basis of the degree of match.
US09230526B1 Computer keyboard instrument and improved system for learning music
A computerized system for enabling a user to compose a song comprises displaying a compose song screen to the user on a video display, the compose song screen including a play bar associated with the current time position of the song; enabling the user to create a first track of the song, wherein the track is associated with an instrument selected by the user, wherein notes of the instrument are assigned to respective keys on a computer keyboard, and wherein the user chooses a tempo for the song, wherein, upon initiating of recording of the track, keys pressed by the user on the keyboard (i) are translated into visual notes on the screen that move, at the tempo, across the play bar and (ii) generate audio output that corresponds to notes from the selected instrument. Multiple tracks, for different instruments, can be created and combined to create a multi-track song.
US09230524B2 Secure guitar stands and racks therefor
A stand for securely and gently cradling a stringed instrument such as a guitar. The stand includes a pair of cradling arms and at least one support member both mounted for movement relative to a base member. A user places the guitar on the generally horizontally oriented support member depressing it downward which causes movement of the cradling arms from an outward open position to an inward closed position latterly supporting the body of the stringed instrument. Movement of the two cradling arms is coordinated by providing a single support member or by attaching to support members to a common yoke mounted for vertical movement on the base member. Each stand can be mounted on a separate stabilizing platform, or a plurality of stands can be mounted to adapters along a storage rack.
US09230520B2 Piccolo
A piccolo having a flute body (25) with tone holes; a head piece (10) having a mouth hole (12) and a head piece body; at least one tube piece formed, respectively, on the flute body (25) and head piece (10). The flute body (25) and the head piece (10) are connectable to one another via said at least one tube piece, wherein said at least one tube piece slidingly engage in one another. The flute body (25) and head piece (10) are displaceable relative to one another based on said slidingly arranged at least one tube piece. An axial pin tube (14) is formed on an end of the head piece (10) to be connected with the flute body (25) and projects from the head piece body. An annular adapter socket (16) is slidingly and interchangeably positioned onto the pin tube (14) and secured to the pin tube (14).
US09230515B2 Hand-held electronic device and display method
A hand-held electronic device and a display method are described. The hand-held electronic device of the invention includes an image processing unit configured to provide a first image; a first display unit configured to display the first image; a first optical system configured to receive light emitted from the first display unit and conduct a light path conversion on it to form a first magnified virtual image, wherein a length of a light path between the first optical system and the first display unit is less than a focal distance of first optical system; and a first window disposed on a first external surface of the hand-held electronic device to allow a viewer to watch the first magnified virtual image through the first optical system when the viewer is close to the first external surface.
US09230514B1 Simulating variances in human writing with digital typography
Methods and systems for rendering text to simulate human penmanship are described. A text rendering engine converts a text string into an image that can be displayed on a string using one or more seed numbers to influence the rendering and appearance of the text. The text rendering engine may render each character of the text string using a size, weight, slope, or Bezier curve control point selected based on the seed numbers.
US09230509B2 Luminance changing image processing with color constraints
To be able to do good color mapping between color encodings for gamuts with considerably different luminance dynamic range while not introducing significant color errors, we describe an image color processing apparatus (201) arranged to transform an input color (L,x,y) of a pixel specified in a color representation corresponding to a first luminance dynamic range into an output color (L*,x,y) of a pixel specified in a color representation corresponding to a second luminance dynamic range, which first and second dynamic ranges differ in extent by at least a multiplicative factor 1.5, comprising a tone mapping deformation unit (203) arranged to determine on the basis of an input tone mapping (301) and a quantity linearly related to the luminance (L) of the input color, an adjusted output luminance (L*, 309), wherein the determining is arranged so that the adjusted output luminance (L*, 309) obtained by applying the input tone mapping to the input luminance (L) of all possible input luminances in its extent of valid values [0,1] giving the highest output (L*,L_HDR), is not higher than a maximum luminance Lmax(x,y) which for the chromatic coordinates (x,y) of the input color is maximally achievable in the gamut corresponding to the second luminance dynamic range for those chromatic coordinates (x,y).
US09230500B2 Expanded 3D stereoscopic display system
An expanded three-dimensional (3D) stereoscopic image display system is provided. The expanded 3D stereoscopic image display system according to an embodiment of the present invention provides a display platform that presents integrated services by fusing homogeneous and heterogeneous display devices in a single space, and an operation technique of the display platform.
US09230497B2 Display device having each pixel divided into sub pixels for improved view angle characteristic
In a liquid crystal display device having a configuration in which one pixel is divided into a plurality of sub pixels, low power consumption is realized by reducing an amplitude of a video signal. In each pixel formation portion, an amplification circuit unit including a second-capacitor is provided between a dark display pixel electrode and a bright display pixel electrode. A selection period consists of a precharge period and an amplification period. In the precharge period, a potential of a control wiring is applied to the dark display pixel electrode, and a potential of a video signal line is applied to the bright display pixel electrode. In the amplification period, a potential of the video signal line is applied to the dark display pixel electrode in the state where the bright display pixel electrode is placed in a floating state.
US09230496B2 Display device and method of driving the same
This display device has a demultiplexer (501) formed on a liquid crystal panel, the demultiplexer including three switching elements SW1 to SW3 for time-division drive, which are connected to video signal lines SL1 to SL3. Here, the number of switching control signal lines for transmitting switching control signals GS1 to GS6 to be provided to switching elements coupled to the video signal lines is six, which is twice the number of time divisions, and switching control signals (e.g., GS1 and GS4) with the same timing are individually transmitted by two switching control signal lines, so that the number of switching elements to be coupled to the switching control signal lines as loads can be halved, resulting in reduced waveform rounding of the control signals.
US09230495B2 Self-detection charge sharing module
A self-detection charge sharing module for a liquid crystal display device is disclosed. The self-detection charge sharing module includes at least one detecting unit, for detecting a plurality of input voltages of a plurality of operational amplifiers driving a plurality of data line sand a plurality of output voltage of the plurality of data line, to generate at least one detecting result, and at least one charge sharing unit, for conducting connection between at least one first data line and at least one second data line among the plurality of data line when the at least one detecting result indicates at least one corresponding first input voltage and at least one corresponding second input voltage among the plurality of input voltage have opposite voltage variation direction and vary toward each other. The at least one first input voltage and the at least one second input voltage maintain respective polarities.
US09230489B2 Liquid crystal display device and method for driving liquid crystal display device
An object of the invention is to suppress degradation in image quality of a liquid crystal display device which performs display by field sequential method and to reduce power consumption of a backlight. The highest brightness of a first color light in a pixel region is detected. Gamma correction is performed so that transmittance of a pixel of the region displaying the highest brightness of the first color light is set to maximum and transmittance of other pixel of the region is decreased in accordance with lowering of the first color light intensity, and the region is irradiated with the highest brightness of the first color light. Similarly, a second color light is irradiated in another region concurrently with irradiation of the first color, whereby input of an image signal and lighting of the backlight are performed simultaneously in every region of the pixel portion.
US09230487B2 Display device and television receiver
A display device that can adjust brightness of each of a plurality of regions of an image by performing local dimming executes local dimming in a case of displaying a multi-color image (color image), and does not execute local dimming in a case of displaying a grayscale image. Moreover, in a case of displaying a mixed image of a multi-color image and a grayscale image, the display device does not execute local dimming in regions including a grayscale image among a plurality of regions of an image. Displaying a multi-color image at high contrast and displaying a grayscale image at high tone reproduction are both achieved.
US09230484B2 Adaptive backlight control and contrast enhancement
A transform function represented by at least n points that define n−1 regions is determined based at least in part on a first set of values associated with a display frame and a maximum average contrast function. The n points can be determined in response to a change in an average contrast of the display frame compared to an average contrast of a previous display frame exceeding a predetermined threshold. The first set of values is converted to a corresponding second set of values based on the transform function. A backlight control signal is generated based on an average contrast of the second set of values, whereby the backlight control signal is configured to control an intensity of a backlight of a display. Further, a video signal is generated based on the second set of values, whereby the video signal configured to drive the display.
US09230483B2 Pixel circuit and driving method and display device thereof
A pixel circuit includes an OLED, a driving transistor, first and second transistors, a storage capacitor and a coupling capacitor. The OLED includes an anode and a cathode connected to a first voltage source. The driving transistor includes a first node connected to a second voltage source, a second node, and a third node connected to the anode. The first transistor includes first, second and third terminals connected to a data driving line, a first control signal source, and the second node, respectively. The second transistor includes a first terminal, a second terminal connected to a second control signal source, and a third terminal connected to the anode and the third node. The storage capacitor includes first and second terminals connected to a third voltage source and the second transistor, respectively. The coupling capacitor includes first and second terminals connected to the second transistor and the second node, respectively.
US09230482B2 Shift register and method of driving the same
A shift register for flat panel display devices includes a start signal unit configured to control a start of an output signal, an end signal unit configured to control an end of the output signal, and a plurality of stages configured to increase the output signal to a high-level driving voltage according to a signal supplied from a first node connected to the start signal unit, and decrease the output signal to a low-level driving voltage according to a signal supplied from a second node connected to the end signal unit. Each of the plurality of stages generates multi signals for diving a pixel circuit of a display device.
US09230478B2 Organic light emitting display device and method for driving the same
Disclosed is an organic light emitting display device that displays images with uniform luminance by compensating degradation of organic light emitting diode, and a method for driving the same. The device comprises a display panel with sub-pixels, each sub-pixel having an organic light emitting diode for emitting light; a memory which stores accumulated data of each sub-pixel; and a panel driver which calculates an individual compensation gain value for each sub-pixel and a global compensation gain value for all the sub-pixels in common based on the accumulated data of sub-pixel, modulates input data for each sub-pixel through the individual compensation gain value and global compensation gain value, converts the modulated data into a data voltage, and accumulates the modulated data on the accumulated data of the corresponding sub-pixel and stores the obtained data in the memory.
US09230476B2 Method and electronic device for reducing power consumption of display
A method for reducing power consumption of an electronic device. The method includes setting a luminance of a display to a minimum, and reducing a data amount sent to the display.
US09230475B2 Display device and electronic apparatus
There is provided a display device including pixel circuits which are arranged and each of which includes a driving transistor to drive an electro-optical element and a capacitor connected between a gate electrode and one source/drain electrode of the driving transistor. The driving transistor is configured by stacking the gate electrode and the source/drain electrode and a peripheral portion of the gate electrode is covered by the source/drain electrode.
US09230473B2 Dual duty cycle OLED to enable dynamic control for reduced motion blur control with constant brightness in augmented reality experiences
A head-mounted display (HMD) device is provided with reduced motion blur by reducing row duty cycle for an organic light-emitting diode (LED) panel as a function of a detected movement of a user's head. Further, a panel duty cycle of the panel is increased in concert with the decrease in the row duty cycle to maintain a constant brightness. The technique is applicable, e.g., to scenarios in which an augmented reality image is displayed in a specific location in world coordinates. A sensor such as an accelerometer or gyroscope can be used to obtain an angular velocity of a user's head. The angular velocity indicates a number of pixels subtended in a frame period according to an angular resolution of the LED panel. The duty cycles can be set, e.g., once per frame, based on the angular velocity or the number of pixels subtended in a frame period.
US09230470B2 Data driver and a display apparatus including the same
A data driver includes a data storage unit configured to store a data signal therein, a level shifting block configured to shift a level of the data signal and output a level shifted data signal based on the result of the level shifting, a waveform conversion block configured to convert a waveform of the level shifted data signal and generate a conversion data signal (e.g., based on the waveform conversion), and a digital-analog conversion unit configured to output an analog signal based on the conversion data signal, wherein the conversion data signal has a rising time and a descending time that are different from each other.
US09230468B2 Display device
A display device includes: a flexible display panel including a recognition pattern; a housing for holding the flexible display panel, wherein varying amounts of a display area of the flexible display panel are exposable to the outside to display an image; and a sensor in the housing for sensing an amount of the exposed display area corresponding to the recognition pattern.
US09230463B2 Message in a bottle
Embodiments of the invention relate to a container with one or more secondary objects housed in the container and configured with indicia to communicate a message. One or more secondary objects in communication with a weight are housed in the container. A combination of the weight and buoyancy characteristics of the secondary object(s) supports floating of the secondary object in the fluid.
US09230462B2 Image display device
To provide an image display device in which reflection of an image on one display surface onto another display surface is suppressed. In an image display device where an image is displayed on a screen combining the display surfaces of two or more image display elements, a polarizing plate is arranged on the display surface on conditions that extinction takes place between the display surfaces of the image display elements. The extinction conditions are set such that the light entering from a display surface to which the polarizing plate is fixed is passed through and the light entering from other than the above display surface is absorbed by intersecting the polarization directions of the polarizing plates perpendicularly.
US09230460B2 Illuminated ATM surround
A low profile illuminated ATM surround is provided. The surround is used with ATMs which are mounted through a wall. The surround is attached to the wall, providing a broad illuminated advertising area around the ATM while maintaining a very low profile, allowing the surround to be used in locations where minimal space is available.
US09230457B2 Adjustable large-sized advertisement curtain wind-resistant module
The present invention relates to an adjustable large-sized advertisement curtain wind-resistant module, which includes a base, the slidable board, a coupler, a transmission device, and a transmission rod. The base has a screw rod. The slidable board has a surface slidably mounted to the base and coupled with the screw rod and an opposite surface to which the coupler is mounted for coupling with the frame. The transmission device is arranged in the base and coupled to the screw rod. The transmission rod drives the transmission device and the transmission device in turn drives the screw rod, so that the screw rod may drive the slidable board to do linear displacement on the base. The linear displacement of the slidable board in opposite directions carries the frame to be moved in unison therewith to achieve adjustment of distance between two frames for stretching flat an advertisement curtain between the frames.
US09230452B2 Device and method for generating a virtual anatomic environment
This invention relates to a method for generating a virtual anatomic environment for use in minimally invasive surgery simulation, comprising the steps of: incorporating a main virtual anatomic environment (1); selecting a local anatomic environment (2) from a predefined library (3) comprising a set of two or more simulated local anatomic environments (2); including the selected local anatomic environment (2) in said main anatomic environment (1) to form a total virtual anatomic environment (4). The invention also relates to a device for generating a virtual anatomic environment for use in minimally invasive surgery simulation, as well as a computer-based minimal-invasive surgery simulation system comprising such a device.
US09230451B2 Tactile display device
Actuators are disposed between a lower wiring substrate and an upper wiring substrate. The actuators, the lower wiring substrate, and the upper wiring substrate are interposed between a lower frame and an upper frame. The end of each actuator is held between pushing parts of the lower frame and upper frame. The free ends of the actuators move projections upward that are displayed in a tactile display.
US09230450B1 Systems and methods for distributed adaptive simulator training
Simulation equipment can be integrated into courseware presented to a student using technology which, based on the native output of a system running the courseware, can generate control signals for the simulation equipment. Such signals could then be sent to the simulation equipment without requiring the designer of the courseware to create low level programming code to communicate directly with the simulation equipment itself.
US09230449B2 Welding training system
A system for training welders that includes a data generating component, a data capturing component and a data processing and visualization component. The data generating component operates in real time and derives data from an actual manually-executed weld and further includes a weld process-specific jig, a calibration block positioned on the jig, wherein the geometric configuration of the calibration block is specific to a particular type of weld joint, a weld coupon positioned on the welding process-specific jig adjacent to the calibration block, a welding gun for use by a trainee, wherein the welding gun is operative to form the weld; and at least one target mounted on the welding gun that is recognized by the data processing and visualization component for providing multidimensional position and orientation feedback to the trainee.
US09230443B2 Method and system for predictive vehicle systems performance selection for enhanced maneuverability
A predictive enhanced maneuverability system providing enhanced timely delivery of vehicle performance selection of chassis, and steering modes for potential predicted safety collisions is disclosed. The primary inputs of the disclosed invention include a determination of the proximity to a preceding vehicle, the density of the surrounding traffic, a forward collision warning alert, and the predictive enhanced maneuverability decision sub-system for vehicle mode selection. The system of the disclosed invention provides a customized vehicle dynamics chassis and steering dynamic mode output, based on a predicted decision about vehicle potential for collision, for improved driver maneuverability and safety. In addition, the disclosed invention provides an improved system and method for incorporating the time dependent headway, forward collision warning alert, and the traffic density for chassis collision-mode embedded decision-making. The predictive enhanced maneuverability decision-module allows vehicle dynamics mode selection to be tailored based on proximity to a potential collision.
US09230437B2 Method and apparatus to encode fuel use data with GPS data and to analyze such data
System and method for analyzing position data and fuel injector data from a vehicle equipped with a geographical position system (GPS) and fuel injector sensors to enable fuel use patterns of the vehicle to be analyzed. Data defining a flow of fuel through the vehicle's fuel injectors is combined with temporal data and GPS data to produce fuel use encoded GPS data that is transmitted to a remote computer. The fuel use encoded GPS data can be analyzed to determine how much fuel was used by the vehicle during off road use to enable proper fuel tax computations to be performed. The data can also be used to evaluate the mechanical condition of a vehicle. By monitoring fuel use for a trip repeated numerous times, a decrease in fuel efficiency may indicate a mechanical problem (dirty injectors, fouled spark plugs, etc).
US09230434B2 Road traffic information server and road traffic information system
Provided are a server and a system that are capable of generating road traffic information on traffic congestion in a more appropriate manner, considering actual road traffic conditions. If a vehicle speed V falls below a first reference speed V1 and then exceeds a second reference speed V2 (>V1), then a traffic congestion situation is estimated based on an inference that the vehicle is highly likely to have escaped from traffic congestion. To estimate a traffic congestion situation, it is required that a situation in which the vehicle speed V exceeds the second reference speed V2 continue for a second specified distance or more or for a second specified time T2 or more.
US09230431B2 Method and apparatus for determining traffic conditions
A system includes a vehicle processor configured to detect one or more brake presses. The processor is also configured to detect one or more accelerator presses. Further, the processor is configured to add values related to the brake presses and accelerator presses to aggregate an index value based on detected brake and acceleration presses. The processor is additionally configured to enact a safety and convenience related measure based on the index value passing at least a first predetermined threshold.
US09230426B2 Universal remote controller and remote control method thereof
A universal remote controller and a remote control method thereof are provided. The universal remote controller includes a communication module which communicates with a plurality of devices; an input unit through which a user command is input; and a controlling unit which determines a pointed device, among the plurality of devices, that the universal remote controller is pointing towards, and controls the communication module to transmit the user command to the pointed device to control the pointed device.
US09230425B2 Vehicle controller
A vehicle controller includes a communicator communicating with an information processor located outside the vehicle by transmitting and receiving information, a controller controlling the vehicle controller based on control information transmitted from the information processor, and a position-information-obtaining-part obtaining position information of the vehicle, wherein the position-information-obtaining-part obtains position information at a time of parking start upon parking start of the vehicle, and obtains position information at a time of reception of the control information when the controller receives the control information from the information processor while being in a sleep mode, and when the position-information-obtaining-part obtains the position information at the time of reception of the control information, the communicator transmits a more accurate one of the position information at the time of parking start and the position information at the time of reception of the control information.
US09230421B2 System for monitoring caregivers and equipment
A hospital monitoring system for monitoring hospital personnel, a plurality of patient locations for patients, and associated devices is configured to control the associated devices based on the presence of hospital personnel or alarms.
US09230419B2 Methods and apparatus to detect and warn proximate entities of interest
Systems and methods to detect and warn proximate entities of interest are described herein. An example signal generation system for a vehicle capable of different modes of movement includes a detector to determine at least one property of vehicle movement and an output representative of that at least one property and a selectively variable signal generator includes an input to receive the at least one output representative of the at least one property of vehicle movement and, responsively, generates a selected signal based on the received output. In some examples, a detector on a pedestrian detects the selected signal from the signal generator and, responsively, provides an output indicative of a vehicle in proximity to the pedestrian. In some examples, a trajectory vector is generated for at least two entities of interest based on at least one characteristic of movement of each entity. Each entity's trajectory vector is expanded and each entity's expanded trajectory vector is analyzed for overlap with the other entity's expanded trajectory vector to assess the possibility of a collision between them.
US09230415B2 Time analysis of a banking system
A banking system that utilizes metrics in acquiring and processing event data related to financial transaction activity at a plurality of automated banking machines. Automated banking machine include sensors able to detect event data during a transaction. The event data can include transaction data related to the type of transaction, time analysis data related to duration of the transaction, and operational data related to machine components used in carrying out the transaction. The event data for automated banking machines can be obtained, analyzed, and stored. Statistical averages associated with the banking system machines can be determined in real time. The averages allow a respective machine to be compared to other machines with respect to operational efficiency. An alert can be issued concerning a statistical anomaly regarding the respective machine.
US09230412B2 Gaming machine and control method thereof
In a gaming machine, a symbol display device variably displays a plurality of symbols, and an input device inputs an instruction related to a game. A controller executes a normal game in which the symbol display device variably displays and then stop-displays symbols, triggers a bonus game when a plurality of specific symbols are stop-displayed in the normal game, selects any one of a plurality of options by an operation of the input device by a user in the bonus game, and awards a benefit according to the selected option. Further, when the selected option selected in the processing is a specific option, the controller selects another one of the plurality of options by the operation of the input device by the user, and awards a benefit according to the selected another option.
US09230406B2 Draw poker with option to wager for additional replacement cards
The player makes a wager to not only play the game but also to determine the total number of possible replacement cards that will be dealt. After dealing of the original cards, the player selects cards in the hand to hold and discard. The player is then dealt replacement cards and the number of cards dealt corresponds to the amount of the wager. If the player wagers more, then the player receives more cards, which in turn results in the player having more cards per card position. The player has the option of using any one of the one or more replacement cards dealt to each card position, to form a best hand from all the possible combinations of the cards such that replacement cards dealt to a particular card position can only be used in the card position to which the card was dealt.
US09230400B2 Display mechanism for volatility-alteration features
A gaming system includes an input device, a display device, a processor, and a memory device. The memory device stores instructions that, when executed by the processor, cause the gaming system to receive a wager for playing a wagering game having an overall volatility. A plurality of volatility components are displayed on the display device, the volatility components having respective component ratings. Each component rating contributes to a total rating of the overall volatility. The wagering game is selected from a plurality of wagering games, each of the plurality of wagering games having (a) the same total rating and (b) at least one different component rating.
US09230397B2 Slot machine game with bonus game having selectable modifier elements
A slot game includes a secondary game which upon being triggered displays an initial set of selectable symbols arranged on a touchscreen display at the gaming device, the player being provided ability to make selections from the selectable symbols until all selectable symbols have been selected, each selectable symbol corresponding to an associated benefit which is one of an award, an award enhancer, or one or more additional selectable symbols. If an option is picked revealing additional selectable symbols, the game adds more picks having associated benefit like those of the initial set and the player keeps selecting. The game may also have a “game pick” in which it removes one or more of the remaining unselected choices without awarding an associated benefit.
US09230395B2 Control of wager-based game using gesture recognition
Various techniques are described for controlling a wager-based game played at a gaming system. In one embodiment the gaming system may include a gesture input interface device operable to detect movements gestures associated with one or more persons, and a gesture interpretation component operable to identify selected movements or gestures detected by the gesture input interface device. In one embodiment, the gesture interpretation component may also be operable to generate gesture interpretation information relating to interpretation of the selected movements or gestures. In one embodiment, the gaming system may be operable to automatically detect a gesture by a player participating in a game session at the gaming system; interpret the gesture with respect to a set of criteria; generate gesture interpretation information relating to the interpretation of the gesture; and advance a state of the game session using at least a portion of the gesture interpretation information.
US09230390B2 Vehicle battery point of sale system and method
A point of sale battery distribution system includes a cabinet in which batteries may be stored, a user interface for facilitating selection and purchase of batteries, and doors which may be secured and freed to be opened based upon purchase transactions. Batteries stored in the cabinet may be charged by a charging system until purchase. The charging system may provide one or more charging voltages and regimes, and output of the charging system may be disabled by a control system when a door is open or freed to be open. An inventory management system may detect batteries stored in the cabinet and convey inventory information to remote systems for replenishment of the cabinet based upon purchases.
US09230389B2 Automated card customization machine
A memory card includes a non-volatile memory, a connector configured to enable the memory card to be operatively coupled to a host computer, and a housing enclosing the non-volatile memory. The housing has a customized physical contour that is determined according to a user-selected value.
US09230385B1 Coin acceptor with anti-fraud feature
A method and apparatus for preventing the fraudulent receipt of credit for the goods or services provided by a coin-operated device is disclosed. A coin acceptor with an anti-fraud feature comprises a coin-accept channel comprising a lip to block the introduction of a non-coin object to a coin sensor and a coin-guiding surface to guide a coin downstream the lip to the coin sensor. The coin-accept channel may further comprise a blocking area, a deflection surface, and a protrusion to prevent the upstream movement of a tethered coin-like object, thereby preventing a single tethered coin-like object from receiving multiple credits for the goods or services provided by a coin-operated device.
US09230384B2 Device for inserting bank notes into a bill acceptor
A device for inserting bank notes into a bank note processing device. The bank note processing device has a main body, a support surface for supporting a bank note to be inserted on a flat side, and at least one lateral positioning edge for laterally positioning the slot on the bank note processing device and/or for connecting the slot to the bank processing device in an accurately fitting manner. The device for inserting bank notes into a bank note processing device is characterized by a setting mechanism for variably setting the position of the positioning edge transversely to the insertion direction of the bank note through the slot.
US09230382B2 Document image capturing and processing
The present invention relates to the automated processing of documents and, more specifically, to methods and systems for aligning, capturing and processing document images using mobile and desktop devices. In accordance with various embodiments, methods and systems for document image alignment, capture, transmission, and verification are provided such that accurate data capture is optimized. These methods and systems may comprise capturing an image on a mobile or stationary device, analyzing images using iterative and weighting procedures, locating the edges or corners of the document, providing geometric correction of document images, converting the color image into a black and white image, transmitting images to a server, and testing the accuracy of the images captured and transmitted.
US09230381B2 Coin counting and sorting machines
Systems, apparatuses, and associated methods for counting and sorting coins are described herein. In one embodiment, a coin processing machine can include a coin input region, a coin counting portion, and a coin sorting portion. The coin counting portion can include a first hopper that receives coins from the coin input region, and a coin discriminator that receives the coins from the first hopper and discriminates the coins to determine their value. The coin sorting portion can include a second coin hopper that receives the coins from the coin discriminator, and a coin sorter that receives the coins from the second hopper and sorts the coins into individual denominations.
US09230374B1 Access management and reporting technology
An access management and reporting system includes a keysafe that is located outside of a building and a communication system that is located within the building. The communication system is configured to perform, over a short-range wireless communication protocol, two-way communication with a communication module of the keysafe. The system also includes a server that is located remote from the building and the keysafe. The server is configured to perform, over a long-range communication protocol, two-way communication with the communication system located within the building, is configured to manage access to the keysafe, and is configured to handle reporting related to access of the keysafe.
US09230373B2 System and method to aggregate control of multiple devices via multicast messages and automatic set up of connections
A method and apparatus are provided wherein the method includes the steps of a downstream controller of a security system advertising a service type of the downstream controller on a sub-network, a gateway controller of the security system detecting the advertisement and authenticating the downstream controller as being part of a group that also includes the gateway controller, the gateway controller sending a connection request to the downstream controller, the gateway and downstream controllers establishing an L4 connection based upon the connection request, and the gateway and downstream controllers establishing a L5 session channel through the L4 connection.
US09230364B2 Zebra lights
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for rendering zebra stripes on a three dimensional (3D) object. In one aspect, a method includes rendering an image of an object from the perspective of a camera For each pixel of a plurality of pixels of the image, a point on the surface of the object corresponding to the pixel is determined. An angle between a surface normal at the point and a line between the point and the light source is determined. A zebra light color for the pixel is determined using a stripe function and the angle, the stripe function specifying alternating high and low intensities for various angles. A blended pixel color for the pixel is determined by blending a material color for the point with the zebra light color.
US09230358B2 Visual connectivity of widgets using event propagation
A method, system and computer program product receive a set of objects for connection, create a moving object within the set of objects, display visual connection cues on objects in the set of objects, adjust the visual connection cues of the moving object and a target object in the set of objects, identify event propagation precedence, and connect the moving object with the target object.
US09230353B2 Method and apparatus for encoding/decoding image data
The invention relates to a method and an apparatus for encoding images, more particularly to an encoding unit in conjunction with a library of pictorial entities and image qualifiers. The method and apparatus provide encoding an image by using a code factor table in conjunction with a set of element codes. The resulting image code allows the set pictorial elements of an image and their associated image, qualifiers to be represented by a compact code uniquely representing a given configuration of pictorial elements. The use of the resulting image code facilitates the transmission and storage of images requiring only the code to be sent or stored. The invention further provides a computer readable medium comprising a program element that direct a computer to implement the encoding process.
US09230352B2 Information processing apparatus, information processing method, and computer program product
An information processing apparatus, method and computer program product cooperate to provide graphical trends of posts regarding a posting subject and additional information. The apparatus includes a collector that collects posts regarding a posting subject that proceeds over time. A counting unit is included that counts a number of collected posts for each of different classes of posts. A display controller causes graphs to be displayed along a time-axis illustrating time-wise trends in the posts for each class together with additional information. The additional information is information that includes at least one of posts at respective times and information regarding the posting subject.
US09230351B2 Data binding graph for interactive chart
Implementing multi-view visualizations in a computing environment. A method includes accessing a directed acyclic graph defining a data flow. The directed acyclic graph includes one or more data source nodes. The acyclic graph has a first visualization node connected to one of the data source nodes of the directed acyclic graph. The acyclic graph has a second visualization node connected to one of the data source nodes of the directed acyclic graph. The method further includes detecting user interaction with a visualization element of the first visualization node. The method further includes propagating the user interaction with the visualization element to the data source node to which the first visualization node is connected. The method further includes propagating the user interaction with the visualization element from the data source node to which the first visualization node is connected to the second visualization node.
US09230348B2 Imaging system for imaging a region of interest
The noise of a detection value acquired by an imaging system (30) can depend on the contributions of different components within a region of interest to be imaged, which has been traversed by radiation (4) causing the respective acquired detection value. This dependence is considered while iteratively reconstructing an image of the region of interest, wherein first component attenuation values, which correspond to elements of a first component within the region of interest, and second component attenuation values, which correspond to elements of a first component within the region of interest, are determined, wherein noise values are determined from the first component attenuation values and the second component attenuation values and wherein the noise values are used for updating the image. This consideration of the dependence of the noise of an acquired detection value on the different components improves the quality of the iteratively reconstructed image.
US09230344B2 Software, system, and method of changing colors in a video
A method of changing colors in a video comprises providing a paint map image video comprising multidimensional location information of spatial points of an animated object, providing a rendered replacement image video comprising visual colors, each visual color comprising a transparency and shades of multiple linearly independent colors, identifying a first replacement image location on the animated object in a frame of the replacement image video, the first replacement image location having a first visual color, identifying a first paint map image location corresponding to the first replacement image location in a corresponding frame of the paint map image video, the first paint map image location represented by a first spatial color, creating a color mapping function that maps the first spatial color to a different visual color, and providing an altered rendered replacement image video that has been rendered according to the color mapping function.
US09230343B2 Image processing apparatus and storage medium
An image processing apparatus including: a processor; and a memory storing instructions that, when executed by the processor, cause the apparatus to perform: acquiring target image data and template image data; specifying a partial image in a target image based on a result of detecting a face area; and compositing the specified partial image in a specific area in a template image, wherein, when a single face area is detected, a first partial image including the single face area and having a size determined based on a size of the single face area is specified, and, when a plurality of face areas are detected, a second partial image including at least one of the face areas, having a shape homothetic to the specific area and having a maximum size within the target image is specified.
US09230341B2 Compressed domain system and method for compression gains in encoded data
A system and method for compressed domain compression are provided for improving compression gains in an encoded image, such as a Joint Photographic Experts Group (JPEG)-encoded images, or encoded video, such as Motion Joint Photographic Experts Group (Motion JPEG)-encoded video, without fully decoding and re-encoding the compressed images or video.
US09230334B2 X-ray CT apparatus and image processing method
An X-ray CT apparatus according to an exemplary embodiment includes: a specifying unit that specifies the position of a lesion and the position of a surrounding site positioned in a surrounding of the lesion, from pieces of image data of the inside of the patient corresponding to the mutually-different temporal phases; a movement information calculating unit that calculates movement information related to movements of the lesion and the surrounding site, based on the positions of the lesion and the surrounding site specified by the specifying unit; and a relative relationship calculating unit that calculates a relative relationship between the movement information of the lesion and the movement information of the surrounding site calculated by the movement information calculating unit.
US09230333B2 Method and apparatus for image processing
In accordance with various aspects of the disclosure, a system, a method, and computer readable medium having instructions for processing images is disclosed. For example, the method includes receiving, at an image processor, a set of images corresponding to a scene changing with time, decomposing, at the image processor, the set of images to detect static objects, leaner objects, and mover objects in the scene, the mover objects being objects that change spatial orientation in the scene with time, and compressing, using the image processor, the mover objects in the scene separately at a rate different from that of the static objects and the leaner objects for storage and/or transmission.
US09230331B2 Systems and methods for registration of ultrasound and CT images
A computerized method for model-less segmentation and registration of ultrasound (US) with computed tomography (CT) images of an organ with a fluid filled chamber. The method is based on correlating between the US image(s) and the CT image(s) by processing the US image(s) by iteratively expanding the CT image segment so that the expanded CT image segment is correlated with the visual boundaries of the US image segment; transforming the CT image(s) according to an estimated US transducer position and estimated US beam direction related to the US image(s) so that at least one of shape and volume of the organ in the CT image is adapted with at least one of shape and volume of the organ of the US image, to form a CT image representation which is correlated with US image(s).
US09230325B2 Three-dimensional model acquisition using planar mirrors
3-D model acquisition of an object is performed using two planar mirrors and a camera. According to some embodiments, 3-D reconstruction is achieved by recovering the scene geometry, including the equations of the mirrors, the camera parameters and the position of the markers, which give the location and orientation of the subjects. After establishing the geometry, a volume intersection algorithm is applied to build a 3-D model of the subject. Camera parameters and spatial constraints of the mirrors may be initially unknown. Camera parameters may be solved with reference to the object and references in the object. Further, distance from the camera to at least one point on the object may be determined once camera parameters are solved. Markers having fixed relative positions may be provided on the object for reference.
US09230323B2 X-ray diagnostic apparatus and X-ray diagnostic method
According to one embodiment, an X-ray diagnostic apparatus includes processing circuitry. The processing circuitry generates a plurality of contrast images sequentially based on X-rays after administration of a contrast medium to the object, determines a monitoring region in the plurality of contrast images, monitors change in signal strength of each of pixels included in the monitoring region, and determines whether or not the signal strength of each of the pixels included in the monitoring region satisfies a specified condition. The processing circuitry controls an X-ray generator based on a result of the determination so as to reduce an X-ray dose or turn off irradiation. The processing circuitry generates a parametric image based on a feature amount determined by change in signal strength of each of pixels of a part of the plurality of contrast images sequentially generated before the X-ray generator is controlled based on the result of the determination.
US09230321B2 Computer aided diagnostic system incorporating 3D shape analysis of the brain for identifying developmental brain disorders
A computer aided diagnostic system and automated method classify a brain through modeling and analyzing the shape of a brain cortex, e.g., to detect a brain cortex that is indicative of a developmental disorder such as ADHD, autism or dyslexia. A model used in such analysis describes the shape of brain cortices in terms of spherical harmonics required to delineate a unit sphere corresponding to the brain cortex to a model of the brain cortex.
US09230320B2 Computer aided diagnostic system incorporating shape analysis for diagnosing malignant lung nodules
A computer aided diagnostic system and automated method diagnose lung cancer through modeling and analyzing the shape of pulmonary nodules. A model used in such analysis describes the shape of pulmonary nodules in terms of spherical harmonics required to delineate a unit sphere corresponding to the pulmonary nodule to a model of the pulmonary nodule.
US09230319B2 Method of reconstructing a biological tissue image, and method and apparatus for acquiring a biological tissue image
Provided are a method of reconstructing a biological tissue image, and a method and apparatus for acquiring a biological tissue image, which allow a biological tissue to be identified with higher accuracy than ever before. The reconstruction of the biological tissue image is performed by measuring spectra having a two-dimensional distribution correlated with a biological tissue section, and acquiring a biological tissue image from the two-dimensional measured spectra through utilization of the measured spectra and an classifier.
US09230318B2 Analysis of the digital image of the external surface of a tyre and processing of false measurement points
A method for processing an image of a surface of a tire to be inspected is described. A three-dimensional digital image is captured of the surface, and each pixel of a plane of the image is assigned an item of information relating to an elevation of the pixel with respect to the surface. By utilizing of a morphological operator that uses a structuring element, a first transformation of the image of the surface is performed with aid of an opening and then of a closing, so as to tailor a grey level of pixels situated abnormally above or below the surface.
US09230317B2 Inspection method and inspection apparatus
An inspection method and inspection apparatus comprising, acquiring an optical image of a pattern formed in a sample, generating a reference image corresponding to the optical image, comparing the optical image and the reference image using a die-to-database method to detect a defect in the optical image and storing information on the defect; regenerating a reference image by reflecting a dimension distribution of a pattern in the surface of the sample on the reference image, and re-comparing an optical image in which a defect is detected by the comparison using the die-to-database method and the regenerated reference image which corresponds to the optical image using the die-to-database method to detect the defect in the optical image in which the defect has been detected, storing information on the defect when the defect is redetected, and determining that the optical image has no defect.
US09230316B2 Defect inspection device for display panel and method for the same
The present invention provides a defect inspection method and device for a display panel. The defect inspection method comprises: A) obtaining an edge image of the display panel and obtaining a grayscale value of each pixel of the edge image; B) selecting a specific area in the edge image and obtaining a grayscale value of each pixel in the specific area; C) obtaining an average grayscale value of all pixels in the specific area; D) executing binarization for the grayscale value of each pixel in the specific area to obtain some boundary lines based on the average grayscale value, wherein the grayscale values of pixels on the boundary lines are different from grayscale values of the other pixels which are not on the boundary lines; E) filtering horizontal and vertical lines of the boundary lines to obtain some remaining boundary lines; and F) fitting a defect specification line for the remaining boundary lines, wherein, if widths of the remaining boundary lines are not smaller than a width of the defect specification line, confirming that the remaining boundary lines are defect lines.
US09230311B2 High dynamic range mammography using a restricted dynamic range full field digital mammogram
Methods of imaging a breast comprising acquiring a sequence of image data sets having differing exposure parameters; and combining the image data sets into a mammography image having greater dynamic range than the dynamic range of any single component image data set. Disclosed methods may further comprise determining an exposure parameter of one or more component image data sets prior to acquiring the sequence of image data sets. The step of determining an exposure parameter of one or more component image data sets may comprise determining exposure duration or an exposure irradiation level. Also disclosed are mammography apparatus and systems to obtain images according to the disclosed methods.
US09230300B2 Method for creating a mosaic image using masks
Photographic images recorded with mobile mapping vehicles (20) in real life situations usually contain cars or other moving objects (34) that cover visual information on the road surface (24). According to the techniques of this invention, moving objects (34) are detected by grayscale differencing in overlapping pixels or sections of two or more orthorectified image tiles. Based on moving object identification, masks are generated for each orthorectified tile. The masks are then compared and priorities established based on grayscale values associated with the masks. Mosaics of a large surface of interest such as the Earth can be assembled from a plurality of overlapping photographic images with moving objects (34) largely removed from the resulting mosaic.
US09230299B2 Video camera
Embodiments provide a video camera configured to capture, compress, and store video image data in a memory of the video camera at a rate of at least about twenty three frames per second. The video image data can be mosaiced image data, and the compressed, mosaiced image data may remain substantially visually lossless upon decompression and demosaicing.
US09230297B2 Systems, methods, and computer program products for compound image demosaicing and warping
Methods, systems, and computer program products to obtain a color image from a color filter array, such as, for example, a color filter array comprising a Bayer pattern. A method of image processing includes, for each pixel location (i,j) and for each color channel in a color image, determining a warped location (i′,j′) in a color filter array, and determining a color value of the color channel at location (i′,j′) in the color filter array. The method may further include storing the determined color value. The determining of the color value may include interpolating the color value of the color channel at location (i′,j′) in the color filter array. In this manner, a single interpolation operation set may be needed and an intermediate image may be avoided, saving memory, reducing processing time, minimizing artifacts, and reducing cost.
US09230296B2 Spatial and temporal pulse width modulation method for image display
A method of controlling micromirrors of reset groups of a spatial light modulator (SLM) digital micromirror array is disclosed. In a first reset operation, the positions of a first subgroup of micromirrors of a reset group are set based on a first portion of a first bitplane and the positions of a second subgroup of micromirrors of the same reset group are set based on a first portion of a second bitplane. Then, in a second reset operation, the positions of the first subgroup are set based on a second portion of the second bitplane and the positions of the second subgroup are set based on a second portion of a first bitplane. In one example, subsets of alternating rows of micromirrors of the same reset group are successively set according to alternating data corresponding to different ones of first and second bitplanes.
US09230293B2 Display controlling program and display controlling apparatus
An information processing apparatus includes a computer. The computer subsequently images a user, makes an evaluation of first image data indicating an image obtained by subsequently imaging, and displays the evaluation result on an LCD by subsequently updating the same.
US09230290B2 Power meter consumption system and method to verify data stored in a register by comparing an address of the register with request for data of the register
Communicating with verified data includes receiving a request with a first device where the request is addressed to a register within the first device and sending a response with the first device to a second device where the response includes an address of the register.
US09230287B2 Real-time notifications and sharing of photos among users of a social network
A system and method for sending a notification to a user in a social network is disclosed. A controller receives a first photo from a first user. The first user is associated with a social network. A identification module determines a first location of the first photo. The identification module determines a second location of a second user. The second user has a connection with the first user in the social network. The identification module determines that the first location matches the second location. A notification module sends a first notification to the second user. The first notification identifies the first photo. The controller receives a second photo taken at the second location. A determining engine determines to share the second photo with the first user.
US09230286B2 Methods and systems for associating users through network societies
A method is provided for associating a first user using a first device and a second user using a second device. The method may include receiving an invitation request from the first user; verifying, by a verification server, the invitation request; sending an invitation to the second user after verifying the invitation request; and receiving an acknowledgement from the second user to acknowledge an association between the first user and the second user. The invitation request may be identified as directed to the second user and may include at least a device token associated with at least one of the first and second devices and an identification associated with at least one of the second device and the second user.
US09230280B1 Clustering data based on indications of financial malfeasance
In various embodiments, systems, methods, and techniques are disclosed for generating a collection of clusters of related data from a seed to assist in detection of financial malfeasance. Seeds may be generated based on seed generation strategies or rules. Clusters may be generated by, for example, retrieving a seed, adding the seed to a first cluster, retrieving a clustering strategy or rules, and adding related data (such as trades, emails or chat messages) and/or data entities to the cluster based on the clustering strategy. Various cluster scores may be generated based on attributes of data in a given cluster, and the clusters may be displayed and ranked based on their scores. Various embodiments may enable an analyst to review clusters of trades, emails and/or chat messages that are the most likely to reveal financial malfeasance.
US09230273B2 Creation and use of constraint templates
The new creation and use of entitlement constraint templates methods and systems can be linked to software offerings in a software catalog. Allowing software catalog experts to link contractual entitlement data with software product offerings via constraint templates on such a varying list of constraint types, establishes a highly robust software catalog knowledge base. The result is significant cost savings in terms of time spent inputting entitlement constraint data by contract analysts as well as minimizing errors by those analysts who would otherwise be required to have a very high level of expertise in the software offerings while potentially inputting the same constraint data repeated times.
US09230272B1 Smart line routing using wireless beacons
There are provided systems and methods for smart line routing using wireless beacons. A merchant may set up a wireless beacon throughout a storefront or retail location for the merchant. The beacons may connect to a user's device and provide check-in services to the user. Based on the connections between the user's device and the wireless beacons, information about the user's behavior in the merchant location may be determined. The information may correspond to items/services the user may purchase and an amount of items/services the user may purchase. Using this information and a payment instrument the user utilizes to complete a transaction for the items/services, and expected time for the user to complete a checkout and payment to the merchant may be determined. The expected time can be used to direct the user to a checkout line that minimizes a wait time for each line.
US09230271B2 Queue management
Disclosed are methods and devices for queue management that allow a person waiting in the queue to choose to receive at least one warning communication, for example on a wireless communication device such as a cellular telephone. In some embodiments, the person agrees to “buy” the warnings and concomitant free time by agreeing to pay for at least one warning communication and/or by agreeing to accept advertisements.
US09230268B2 Financial transaction processing with digital artifacts and a default payment method using a POS
A method and system for conducting an online payment transaction through a point of sale device. The method includes receiving input from a user selecting an item for purchase through the point of sale device; calculating a total purchase amount for the item in response to a request from the user to purchase the item; and sending payment authorization for the total purchase amount from the point of sale device to a payment entity, in which the payment authorization is sent to the payment entity via a mobile communication device of the user. The method further includes receiving a result of the payment authorization from the payment entity through the mobile communication device; and completing the payment transaction based on the result of the payment authorization.
US09230267B2 Cell-allocation in location-selective information provision systems
Systems and methods for allocating cells within a virtual grid to content providers according to various priority and selection schemes are used to target content delivery to information playback devices in a geographically and/or application selective manner. The priority schemes, geographical selectivity, and application selectivity of the system and methods of the invention allow a content provider to specifically target a desired demographic with high cost efficiency and flexibility.
US09230266B2 Systems and methods for generating customized advertisements
Systems and methods for generating customized electronic advertisements are disclosed. A request for an advertisement is received. Viewer data is received and analyzed to determine current viewer features, characteristics, attributes, and/or interest(s). Product data can be extracted from publicly accessible electronic data generated by an ad source organization. The product data can be compared to the current viewer interest(s) to determine which product of the plurality of products most closely aligns with the current interests of the viewer to select a product to be advertised. A customized advertisement can be generated specifically for the viewer using at least a portion of the extracted product data for the product to be advertised.
US09230265B2 Managing targeting of advertisements based on user associations with social networking objects
An entity provides a competitive block list for one or more of its objects in a social networking system. The competitive block list identifies advertisers or other entities prevented from targeting advertisements based on connections between users and objects of the entity. If a later received advertisement is targeted based on a connection between a user and an object of the entity, the social networking system determines whether the advertiser associated with the advertisement is included on the competitive block list. If the competitive block list includes the advertiser, the advertisement is determined not to be valid, and not presented to users. Otherwise, the advertisement is determined to be valid, and may be presented to users thereafter.
US09230262B2 Smoothed visualization having rings containing pixels representing unevenly spaced data
Unevenly spaced data records are received over time. A smoothed graphical visualization has a plurality of discrete rings to allow for detection of periodical patterns in the data records, where the discrete rings correspond to plural time periods and contain pixels representing values of an attribute of the data records. Visual indicators are assigned to the corresponding pixels, where a first of a visual indicators for a first time interval that is missing a data record is based on aggregating values of the attribute of neighboring data records, and where a second of the visual indicators for a second time interval having multiple data records is based on aggregating values of the attribute of the multiple data records.
US09230261B2 Systems and methods for scanning a user environment and evaluating data of interest
According to various embodiments, a mobile device continuously and/or automatically scans a user environment for containing non-human-readable data. The mobile device may continuously and/or automatically scan the environment for tags without being specifically directed at a particular tag. The mobile device may be adapted to scan for audio tags, radio frequency tags, and/or image tags. The mobile device may be configured to scan for and identify tags within the user environment that satisfy a user preference. The mobile device may perform an action in response to identifying a tag that satisfies a user preference. The mobile device may be configured to scan for a wide variety of tags, including tags in the form of quick response codes, steganographic content, audio watermarks, audio outside of a human audible range, radio frequency identification tags, long wavelength identification tags, near field communication tags, and/or a Memory Spot device.
US09230259B1 Systems and methods for mobile ordering and payment
Computer implemented methods and systems for fulfilling a customer request for a requested item purchased from a merchant is provided. The method may be performed by a tangibly embodied processing machine disposed in a customer device. The method may include (1) observing, through the input of information, an observed event that is associated with a customer; (2) associating the observed event with a corresponding order record; (3) retrieving order information from the corresponding order record, the order information including at least customer financial entity account information; (4) generating a merchant request based at least in part on the order information in the corresponding order record, the merchant request including at least customer identification information and customer financial entity account information; and (5) outputting the merchant request to the designated merchant, so as to provide the designated merchant with information to fulfill the customer request.
US09230258B2 Space and time for entity resolution
Provided are techniques for receiving a record, wherein the received record has a space-time feature, selecting candidate entities using the space time feature, performing space time analysis to determine whether the received record should be conjoined with a candidate entity from the candidate entities, and, in response to determining that the received record should be conjoined with the candidate entity, making an entity resolution assertion by conjoining the received record and the candidate entity to form a newly conjoined entity.
US09230257B2 Systems and methods for customer relationship management
According to various embodiments, a social media message posted on a social media system is accessed. One or more similar messages determined to be similar to the social media message may be selected from a database of previously posted messages, based on, for example, an author, product, problem, keyword, etc., identified in the social media message. The similar messages may be displayed in a similar message recommendation list of a user interface. One or more relevant knowledgebase articles determined to be relevant to the social media message may be selected from a knowledgebase repository, based on, for example, a product, problem, keyword, etc., identified in the social media message. The relevant knowledgebase articles may be displayed in a knowledgebase article list of a user interface.
US09230256B2 System and method for electronically creating a customized catalog
Catalog pages on which appear identified products and catalog pages on which appear products purchased-with the identified products are selected and aggregated to form a customized, electronic catalog.
US09230255B1 Payment card having light-emitting diode indicators coordinated with stored payment applications
In an IC (integrated circuit) card, a selection signal is received from a user-actuatable switch to select between two different payment card accounts, each represented by a respective account indicator number stored in the IC component of the card. In response to the selection signal, a light-emitting diode indicator on the IC card is illuminated to indicate selection of a corresponding one of the payment card accounts.
US09230253B2 Methods and systems for managing transaction card accounts enabled for use with particular categories of providers and/or goods/services
A computer-implemented method and system for managing transaction card accounts involves enabling a transaction card account by a card issuer for use with pre-defined categories of providers of goods/services and goods/services sold and issuing a transaction card and establishing an associated pre-qualified category card account. Upon receiving data for a transaction with the transaction card at a transaction terminal by a processing platform of the card issuer via a card association processing network, the category of the provider and goods/services is interrogated to determine whether or not the transaction can be posted on the pre-qualified category card account of the cardholder, and the transaction is approved and posted to the pre-qualified category card account if the transaction falls within the pre-qualified category of the cardholder.
US09230247B2 Card activated cash dispensing automated banking machine system and method
An automated banking machine system operates to cause financial transfers responsive to data read from data bearing records. The system is operative to read a financial card bearing account indicia with a card reader. A user is enabled to perform at least one banking operation responsive to account indicia read from the card. Such banking operations may include dispensing cash and accessing financial accounts. A user is also enabled to perform at least one banking operation responsive to financial account data communicated to the automated banking machine from a mobile phone.
US09230246B1 Systems and methods for electronic document delivery, execution, and return
To expedite electronic delivery and return of a document, the document is sent to an electronic mail system and stored in an electronic form thereat. The recipient is informed that the document is available thereto at any of a plurality of merchants where the document may be retrieved. The recipient visits one of the plurality of merchants and at the visited merchant retrieves the document in the electronic form from the mail system to a computing device at the visited merchant. The recipient then reviews and executes the document at the visited merchant, and sends the executed document in an electronic form to the organization by way of the visited merchant and the computing device thereat.
US09230245B1 Deliverability-based e-mail sending
Methods and systems for deliverability-based e-mail sending are disclosed. A plurality of e-mail addresses for a user are acquired. For each of the e-mail addresses, a connection between a sending computer system and a receiving computer system is opened. A likelihood of successful e-mail delivery is determined for each of the connections. The connection having the highest likelihood of delivery is automatically selected. An e-mail is sent using the selected connection, and the other connections are closed without sending an e-mail.
US09230238B2 Favorites list sharing
Techniques are described to share items from a favorites list. In an implementation, a list entry for a favorites list may be associated with content from a third party source by a first user. The favorites list may be presented in a webpage to display the list entry and the associated content to another user. A control operable to share the list entry with the other user may be exposed with the list entry. Responsive to operation of the control, the content and/or related data may be obtained from the third party source and data may be stored to associate the list entry including the obtained content with the other user. In at least some embodiments, the control is operable by a single-click to cause the sharing of the list entry.
US09230234B2 Method and system for an inventory aggregator
A system and method for aggregating and listing inventory. The system may include a database for storing data in a plurality of record classes. The record classes may include data pertaining at least to a plurality of inventory and may include any variety of identifying data for each inventory record. The database may be a relational database, and the records may be grouped in a plurality of classes, which may be interrelated. The system may further include a search engine for searching the database so as to find and return a list of inventory based on desired criteria.
US09230223B2 Consistent presentation of content and passive relevance determination of content relationship in an on-line commerce system
A platform allows experts, for example home improvement professionals, to upload their portfolios, i.e. content such as photos, videos, text, and sound, to a publicly available resource, such as a Web browser accessible, network based commerce system. Users may then browse the content, for example by room, style, and metro area. The content is arranged in collections that are in part passively sorted, based upon user relevance. Tags are shown on objects, for example within photos, for which there is more information. In the case of a movable display device, the tags can simulate the physics of real tags, for example they can move back and forth when the device is shaken. In another embodiment, a snap point is set to impart either a scrolling transition or a step transition between display pages, based upon user scroll activity.
US09230216B2 Scalable spatiotemporal clustering of heterogeneous events
One embodiment of the present invention provides a system for clustering heterogeneous events. During operation, the system finds a partition of events into clusters such that each cluster includes a set of events. In addition, the system estimates probability distributions for various properties of events associated with each cluster. The system obtains heterogeneous event data, and analyzes the heterogeneous event data to determine the distribution of event properties associated with clusters and to assign events to clusters.
US09230214B1 Personalizing auto-completion results based on user intent
Some embodiments provide a system that facilitates use of an auto-completion system. During operation, the system receives an input text string entered by a user. The system determines a set of text strings, wherein each of the text strings in the set can replace the input text string entered by the user. Next, the system calculates a commercial intent score for each text string in the set. Following this, the system selects a replacement text string from the set of text strings based on commercial intent scores computed for each text string in the set. Finally, the system displays the selected replacement text string in the place of the input text string to the user.
US09230212B2 Content based recommendation system
A media control system enables a device-agnostic and source-agnostic entertainment experience through use of an internet-enabled user device. The user device includes a client application for navigating through media or entertainment content, controlling media devices according to a type of media content selected by the user, and sharing media experiences via social networks. The user device includes smartphones, tablet computers, and other internet-enabled processor-based devices. The media control system leverages the internet access of the user device to enable search and discovery of all available media content. A recommendation engine coupled to the client application learns media preferences from user behavior, generates from numerous disparate media sources recommended media choices corresponding to the media preferences, and presents the recommended media choices on the user device.
US09230210B2 Information processing apparatus and method for obtaining a knowledge item based on relation information and an attribute of the relation
There is provided an information processing apparatus for presenting knowledge information that is similar to inputted knowledge information, by using a knowledge system including relation information between a plurality of knowledge information items, the apparatus comprising: an input unit configured to receive first knowledge information, and second knowledge information that is associated with the first knowledge information; a relation acquisition unit configured to acquire first relation information indicating a relation that the first knowledge information has with respect to the second knowledge information, from the knowledge system; a knowledge acquisition unit configured to acquire knowledge information that has the relation indicated by the first relation information with respect to the second knowledge information, from the knowledge system; and an output unit configured to output the knowledge information acquired by the knowledge acquisition unit as knowledge information similar to the first knowledge information.
US09230208B2 Haptic-based artificial neural network training
In a method for training an artificial neural network based algorithm designed to monitor a first device, a processor receives a first data. A processor determines a first service action recommendation for a first device using the received first data and an artificial neural network (ANN) algorithm. A processor causes a second device to provide haptic feedback using the received first data. A processor receives a second service action recommendation for the first device based on the haptic feedback. A processor adjusts at least one parameter of the ANN algorithm such that the ANN algorithm determines a third service action recommendation for the first device using the received first data, wherein the third service action recommendation is equivalent to the second service action recommendation.
US09230206B2 Image forming with save mode for reducing color material cost
An image forming apparatus includes an image forming unit, a save mode setting unit, a reference cost obtaining unit, a minimum monetary-sum extraction unit, and a usage volume setting unit. The minimum monetary-sum extraction unit is configured to extract a minimum monetary sum for each tone from reference costs for a plurality of image forming modes. The usage volume setting unit is configured to: obtain a post-reduction cost where a reduced monetary sum by the save mode is subtracted from the minimum monetary sum; and set reference usage volume as usage volumes for the dark color material and the light color material in the save mode, the reference usage volume being obtained based on the reference costs for the image forming modes corresponding to the post-reduction cost.
US09230199B2 Printing system and printing method
A printing system includes a storage unit that associates and stores print job data and post processing job data; a printing unit that prints a code regarding the association on media when an image is printed on the media based on the print job data; a code reading unit that reads the code that is printed on the media; and a post processing unit that selects the post processing job data that is associated from the storage unit based on the read code and performs the post processing with respect to the media based on the selected post processing job data.
US09230197B2 Recording medium and label production processing method
A non-transitory computer readable recording medium storing a label production processing program for executing steps on an arithmetic device of an operation terminal, to operate a label producing apparatus is disclosed. The steps include an identification information acquiring step that acquires identification information of the label producing apparatus from at least one of a plurality of label producing apparatuses configured to transmit and receive information, a medium information acquiring step that acquires medium information on the attached print-receiving medium from the label producing apparatus from which the identification information has been acquired, and a displaying step that displays on the display device menu screens in which the identification information and the medium information corresponding to the identification information are displayed as a list, to set alternatively the label producing apparatus which is a print output destination from among the at least one of the label producing apparatuses.
US09230190B2 Image recognition to support shelf auditing for consumer research
Image recognition methods, apparatus and articles or manufacture to support shelf auditing for consumer research are disclosed herein. Example methods disclosed herein include comparing a first image signature associated with an input image with a plurality of reference signatures associated with a plurality of reference images to identify a first reference image matching the input image. Such disclosed example methods also include identifying a first group of items depicted in the input image as corresponding to a first group of reference items registered with the first reference image. Such disclosed example methods further include determining a first region of the input image that differs from a corresponding first region of the first reference image, and processing the first region of the input image based on a template to identify a second item depicted in the input image.
US09230185B1 Analysis of electrophoretic bands in a substrate
A method and system to enhance analysis of electrophoretic bands by overlaying only the pixels of interest. The overlaid pixels are superimposed as a layer above, i.e., in the foreground of, the overlaid image, i.e., in the background. A user employs the superimposed pixels for molecular weight determination and is still able to generate densitometry analysis of the remaining pixels in the overlaid image.
US09230178B2 Vision support apparatus for vehicle
A vision support apparatus of the invention includes a first obstacle detecting part configured to detect an obstacle near a vehicle with a visible light image; a second obstacle detecting part configured to detect the obstacle using an infrared light image, a detection status determining part configured to determine whether it is difficult or impossible for the first obstacle detecting part to detect the obstacle; and an obstacle information providing part configured to provide a driver of the vehicle with information about the obstacle detected by the second obstacle detecting part, if it is determined by the detection status determining part that it is difficult or impossible for the first obstacle detecting part to detect the obstacle, thereby informing the driver of the existence of the obstacle when it is difficult for the driver to visually perceive the obstacle because of insufficient reflection of the visible light from the obstacle.
US09230176B2 Method of detecting camera tampering and system thereof
A method of detecting camera tempering and a system therefor are provided. The method includes: performing at least one of following operations: (i) detecting a size of a foreground in an image, and determining whether a first condition, that the size exceeds a first reference value, is satisfied, (ii) detecting change of a sum of the largest pixel value differences among pixel value differences between adjacent pixels in selected horizontal lines of the image, according to time, and determining whether a second condition, that the change lasts for a predetermined time period, is satisfied, and (iii) adding up a plurality of global motion vectors with respect to a plurality of images, and determining whether a third condition, that a sum of the global motion vectors exceeds a second reference value, is satisfied; and determining occurrence of camera tempering if at least one of the corresponding conditions is satisfied.
US09230170B2 Plant species identification apparatus and method
A plant species identification apparatus for identifying plant species is disclosed. A reference data storage part stores reference spectral data which indicate a reflectance spectral feature classified by area segments including a sunlit portion and a shaded portion in addition to the plant species. A data input part acquires hyperspectral data to be a target. A determination part specifies the reflectance spectral feature of a pixel for each of pixels of the hyperspectral data from the reference data storage part and to determine the plant species of the pixels based on a classification of the reference spectral data.
US09230169B2 Generation of high resolution population density data sets through exploitation of high resolution overhead imagery data and low resolution population density data sets
Utilities (e.g., systems, methods, etc.) for automatically generating high resolution population density estimation data sets through manipulation of low resolution population density estimation data sets with high resolution overhead imagery data (e.g., such as overhead imagery data acquired by satellites, aircrafts, etc. of celestial bodies). Stated differently, the present utilities make use of high resolution overhead imagery data to determine how to distribute the population density of a large, low resolution cell (e.g., 1000 m) among a plurality of smaller, high resolution cells (e.g., 100 m) within the larger cell.
US09230168B2 Automatic generation of built-up layers from high resolution satellite image data
A system for automatically extracting interesting structures or areas (e.g., built-up structures such as buildings, tents, etc.) from HR/VHR satellite imagery data using corresponding LR satellite imagery data. The system breaks down HR/VHR input satellite images into a plurality of components (e.g., groups of pixels), organizes the components into a first hierarchical data structure (e.g., a Max-Tree), generates a second hierarchical data structure (e.g., a KD-Tree) from feature elements (e.g., spectral and shape characteristics) of the components, uses LR satellite imagery data to categorize components as being of interest or not, uses the feature elements of the categorized components to train the second data structure to be able to classify all components of the first data structure as being of interest or not, classifies the components of the first data structure with the trained second data structure, and then maps components classified as being of interest into a resultant image.
US09230163B2 Cascade analysis for intestinal contraction detection
A method and system cascade analysis for intestinal contraction detection is provided by extracting from image frames captured in-vivo. The method and system also relate to the detection of turbid liquids in intestinal tracts, to automatic detection of video image frames taken in the gastrointestinal tract including a field of view obstructed by turbid media, and more particularly to extraction of image data obstructed by turbid media.
US09230161B2 Multiple layer block matching method and system for image denoising
This disclosure provides a method, system and computer program product for denoising an image by extending a Block Matching and 3D Filtering algorithm to include decomposition of high contrast image blocks into multiple layers that are collaboratively filtered. According to an exemplary method, the high contrast image blocks are decomposed into a top layer, a bottom layer and a mask layer.
US09230159B1 Action recognition and detection on videos
This disclosure generally relates to systems and methods that facilitate employing exemplar Histogram of Oriented Gradients Linear Discriminant Analysis (HOG-LDA) models along with Localizer Hidden Markov Models (HMM) to train a classification model to classify actions in videos by learning poses and transitions between the poses associated with the actions in a view of a continuous state represented by bounding boxes corresponding to where the action is located in frames of the video.
US09230158B1 Fraud detection for facial recognition systems
Approaches are described which enable a computing device (e.g., mobile phone, tablet computer) to utilize one or more facial recognition techniques to control access to the device and to detect when artificial representations of a user, such as a picture or photograph, are being used in an attempt to gain access to the device. Evidence indicative of artificial representations may include lack of changes in facial skin color between multiple images captured by a camera, ability to track one or more features of the human face while the camera is rotated or moved, presence of secular reflections caused by an illumination device, absence of shadows in the image, and others.
US09230157B2 System and method for face capture and matching
According to an example, a face capture and matching system may include a memory storing machine readable instructions to receive captured images of an area monitored by an image capture device, and detect one or more faces in the captured images. The memory may further store machine readable instructions to track movement of the one or more detected faces in the area monitored by the image capture device, and based on the one or more tracked detected faces, select one or more images from the captured images to be used for identifying the one or more tracked detected faces. The memory may further store machine readable instructions to select one or more fusion techniques to identify the one or more tracked detected faces using the one or more selected images. The face capture and matching system may further include a processor to implement the machine readable instructions.
US09230156B2 Data processor, data processing system, and computer-readable recording medium
A data processor includes an obtainment part that obtains an image of a person's face, a creation part that creates a face direction map in which face images of the person facing respective directions are arranged, based on the image of the person's face obtained by the obtainment part, and a determination part that determines movement of the person's face, based on the face direction map and a moving image of the person's face obtained by the obtainment part.
US09230155B2 Extraction of keyframes at regular intervals by finding nearby high-quality frames
An image processing apparatus according to the present invention can specify, among a plurality of frames, a plurality of frame groups having at least one frame included between the plurality of frame groups that are extraction target candidates in an array of the plurality of frames in the moving image according to a predetermined frame interval, analyze each of the plurality of specified frame groups, and extract a frame to be output from each of the plurality of frame groups based on a result of the analysis.
US09230154B2 Information processing apparatus, method, and storage medium for assisting with a diagnosis based on a tissue sample
This invention relates to an information processing apparatus which assists diagnosis based on a tissue sample image obtained by staining and capturing a tissue. The information processing apparatus receives and analyzes lower magnification image data among a plurality of image data obtained at different magnifications for an area image selected in the tissue sample image. Based on the analysis result, the information processing apparatus determines whether analysis based on higher magnification image data is necessary. When analysis based on the higher magnification image data is necessary, the information processing apparatus notifies a request of transmitting the higher magnification image data for the area image, receives and analyzes the higher magnification image data transmitted in response to the transmission request, and transmits the analysis result. This arrangement can quickly provide high-accuracy diagnosis assistance for a tissue sample image from a pathologist regardless of the restriction of the transmission capacity.
US09230152B2 Electronic device for processing composite finger matching biometric data and related methods
A device may include a finger biometric sensor and a processor coupled thereto. The processor may acquire first and second finger matching biometric data based upon first and second finger placements adjacent the sensor. The processor may also perform a matching between the first and second finger matching data to generate composite finger matching data having an associated composite match score, perform another matching between the composite matching data and finger enrollment data when the composite match score exceeds a match threshold to generate an enrollment match score, and update the finger enrollment data with the composite matching data when the enrollment match score exceeds an enrollment threshold. In other embodiments, where the second finger matching data is acquired based upon a removal and replacement of the finger from adjacent the finger sensor, instead of or in addition to updating the finger enrollment data, a device function may be performed.
US09230151B2 Method, apparatus, and system for searching for image and image-related information using a fingerprint of a captured image
An apparatus, method, and system for searching for images and image-related information are described in which the image information search system includes: an image reproducing apparatus reproducing or capturing an image; and an image/information search server searching for image/information associated with the captured image. In the image and image-information search apparatus and method, a user can easily acquire his or her desired image file or image-related information while he or she is watching images, even when he or she does not know any detailed identification information associated with his or her desired image.
US09230146B1 System, device and method employing machine-readable symbol reader and shield
Machine-readable symbol reader systems including one or more shields are provided. One example machine-readable symbol reader system includes a conveyor system to convey objects bearing one or more machine-readable symbols past a first region that is transmissive to light. The system includes a machine-readable symbol reader having a housing, a window formed in the housing, and at least one optical sensor received in the housing and having a field of view that extends outward of the window, at least the window of the machine-readable symbol reader positioned relatively below the conveyor system with the field of view aligned with the first region of the conveyor system. The system can further include a shield having a frame with a plurality of apertures that are transmissive to light, the shield positioned relatively below the first region and positioned relatively above the window of the machine-readable symbol reader.
US09230145B2 Apparatus and method pertaining to conveying information via an RFID transceiver
An RFID transceiver and RFID-tag reader cooperate to convey information from one to the other and further accommodate the RFID-tag reader transmitting information to the RFID transceiver that causes a modification of information presented via the RFID transceiver. By one approach an RFID-tag reader detects a circumstance that evidences a particular status as pertains to a particular item of such information in a given RFID transceivers. An RFID-tag reader can then serve to modify the information at the corresponding RFID transceiver. By one approach, the aforementioned information comprises a to-do list. The aforementioned modification can comprise modifying at least one to-do item in that to-do list. The aforementioned detection of a circumstance can comprise detecting a physical location of the given RFID transceiver. That location information can be compared to locations that correspond to specific to-do items in the list to identify correlations that evidence completion of specific to-do items.
US09230144B2 Communication device and working vehicle provided with the same
A reader writer (a communication device) executes at least one of reading identification information of an IC tag (an identification component) and writing the identification information to the IC tag. The reader writer includes a CPU board (a control board) that includes CPU (a controller) and a wireless control circuit to output radio waves by a command from the CPU, an antenna that is spaced from the CPU board, and a connection cable that electrically connects the CPU board to the antenna. The CPU board includes a disconnection detector that detects a disconnection of the connection cable, and a transmission controller that interrupts an output from the wireless control circuit to the antenna when the disconnection detector judges that the connection cable is disconnected.
US09230138B2 Information processing method and apparatus for securely sharing personalized information
There is disclosed an apparatus capable of suitably deleting information of, e.g., an operation environment that is personalized in a given apparatus and handled in another apparatus and remains in it, thereby improving the operability and security. An information processing apparatus receives personalized information set in another information processing apparatus and stores the personalized information. A user who requests access to the stored personalized information is authenticated. A user who has passed authentication can obtain an operation environment based on the personalized information. Upon logout of the user or after the elapse of a predetermined time after access, the stored personalized information is erased.
US09230137B2 Secure original equipment manufacturer (OEM) identifier for OEM devices
An authorized information handling system (IHS) generates unique identifier codes for an OEM (programmable) device designed as a component for an IHS. An identifier generation and validation (IGV) controller in the authorized IHS generates a unique encrypted sequence by encrypting identification (ID) data read from the OEM device. The IGV controller generates a unique OEM identifier code by further encrypting the encrypted sequence using a first OEM proprietary code. The IGV controller writes the first identifier code to a pre-specified storage location of the OEM device. According to one embodiment, the IGV controller generates the unique OEM identifier code using a second reversible encryption-decryption component that comprises an Exclusive-OR (XOR) scrambler engine and generates the unique encrypted sequence using a first reversible encryption-decryption component that comprises an LFSR based scrambler, which utilizes polynomial coefficients that are securely generated and maintained.
US09230135B2 Secure access for sensitive digital information
Sensitive pieces of information stored on an individual's device can be protected using a device identification system that applies, for each sensitive piece of information, a function that integrates an identifier of the individual with a respective sensitive piece of information to create a respective identity element. Each identity element can be signed with a signature to create a trust group. The identity element and signature can be uploaded to the individual's device using an application that is configured to provide a subset of the sensitive pieces of information in response to a query.
US09230133B2 Secure access for sensitive digital information
Sensitive pieces of information stored on an individual's device can be protected using a device identification system that applies, for each sensitive piece of information, a function that integrates an identifier of the individual with a respective sensitive piece of information to create a respective identity element. Each identity element can be signed with a signature to create a trust group. The identity element and signature can be uploaded to the individual's device using an application that is configured to provide a subset of the sensitive pieces of information in response to a query.
US09230132B2 Anonymization for data having a relational part and sequential part
A system, method and computer program product for anonymizing data. Datasets anonymized according to the method have a relational part having multiple tables of relational data, and a sequential part having tables of time-ordered data. The sequential part may include data representing a “sequences-of-sequences”. A “sequence-of-sequences” is a sequence which, itself, consists of a number of sequences. Each of these kinds of data may be anonymized using k-anonymization techniques and offers privacy protection to individuals or entities from attackers whose knowledge spans the two (or more) kinds of attribute data.
US09230130B2 System and method for rules-based control of custody of electronic signature transactions
Techniques for electronic signature processes are described. Some embodiments provide an electronic signature service (“ESS”) configured to facilitate the creation, storage, and management of electronic signature documents. In one embodiment, an electronic signature document may be associated with custody transfer rules that facilitate transfers of custody of an electronic signature document from one user or party to another. A custody transfer may results in a transfer of rights or capabilities to operate upon (e.g., modify, view, send, delete) an electronic signature document and/or its associated data. A custody transfer rule may be trigged by the occurrence of a particular event, such as the receipt of an electronic signature.
US09230129B1 Software trusted computing base
A software trusted platform module (sTPM) operates in a hypervisor, receives trust assurances from specialized hardware, and extends this trust such that the hypervisor performs trust attestation. The hypervisor receives a startup sequence validation from a TPM, or Trusted Platform Module. The TPM performs bus monitoring during a boot sequence of the computer system, records the startup sequence from the bus, and performs a hash on the sequence. The TPM performs an authentication exchange with the hypervisor such that the hypervisor authenticates the attestation of the computer system from the TPM, and the hypervisor, now delegated with trust assurances from the TPM, provides assurances to users via an authentication chain. The ATCB then performs the attestation of the computer system according to the attestation protocol much faster than the TPM. In this manner, the hypervisor operates as a software delegate of the TPM for providing user assurances of trust.
US09230128B2 Assignment of security contexts to define access permissions for file system objects
A system and method are provided for restricting various operations in a file system based on security contexts. An object security context including permissible roles and defining a set of access permissions associated with each of the permissible roles is assigned to a file system object. A user security context is assigned to a user based on authentication information from the user, and the user security context identifies a user role for the user. An executable security context is assigned to an executable program. When the user has launched the executable program, a process is created and assigned the user security context and the executable security context. Responsive to the process attempting to access the file system object, at least one of the user security context and executable security context is verified against the object security context to determine if the attempted access should be allowed.
US09230127B2 Methods and systems for increasing the security of electronic messages
A method for accessing e-mail messages from a control system includes requesting access to e-mail message contents of a user stored in the control system, determining whether the user is enrolled in and activated by the control system, and authenticating the user when the user is enrolled in and activated by the control system. Moreover, the method includes permitting the user to view a list of e-mail messages when the user is successfully authenticated. The e-mail messages included in the list are associated with the user. Furthermore, the method includes permitting the user to access the contents of e-mail messages in the list having a security level equal to or less than a security level associated with the successful authentication.
US09230125B2 Image forming apparatus, printing method, and storage medium
An image forming apparatus, for use in a printing system including a print client, a printer server, and an authentication server, enables a secure print setting according to received policy information specifying that printing is to be performed using a secure print protocol employing a certificate.
US09230123B2 Apparatus for tamper protection of application code based on self modification and method thereof
Disclosed is an apparatus for tamper protection of an application which includes: an input unit that receives codes to be used for an application; a code separator that separates the inputted codes into sensitive codes requiring application tamper protection and general codes including sensitive method calling routine for calling the sensitive codes by analyzing the input codes; an encoder that encrypts the sensitive codes and inserts the address of an sensitive code connector storing the address information of the sensitive codes; a controller that converts the sensitive method calling routine to be able to call dummy codes by inserting the dummy codes to the general codes, inserts vector table generator, to the sensitive codes, and insert a sensitive method calling routine converter, to the sensitive codes; and a code combiner that creates the application by combining the general codes and the sensitive codes.
US09230122B2 System and method for validating program execution at run-time using control flow signatures
A processor comprising: an instruction processing pipeline, configured to receive a sequence of instructions for execution, said sequence comprising at least one instruction including a flow control instruction which terminates the sequence; a hash generator, configured to generate a hash associated with execution of the sequence of instructions; a memory configured to securely receive a reference signature corresponding to a hash of a verified corresponding sequence of instructions; verification logic configured to determine a correspondence between the hash and the reference signature; and authorization logic configured to selectively produce a signal, in dependence on a degree of correspondence of the hash with the reference signature.
US09230121B1 Techniques for persistently toggling a FIPS-140 cryptographic mode of a clustered storage system
Improved clustered storage systems make use of a software toggle switch stored in a shared persistent configuration database, which allows a peer node to be rebooted into a FIPS 140 mode defined by the switch and then to take over as master while the original master node reboots into the new FIPS 140 mode as defined by the switch. Advantageously, system availability is maintained as the nodes are rebooted sequentially while a master is always available. The persistent switch allows for synchronization, while also allowing persistence of state even in the event of a system crash.
US09230120B2 Architecture and instruction set for implementing advanced encryption standard (AES)
A flexible aes instruction for a general purpose processor is provided that performs aes encryption or decryption using n rounds, where n includes the standard aes set of rounds {10, 12, 14}. A parameter is provided to allow the type of aes round to be selected, that is, whether it is a “last round”. In addition to standard aes, the flexible aes instruction allows an AES-like cipher with 20 rounds to be specified or a “one round” pass.
US09230115B1 Educating computer users concerning security threats
Attacks are simulated to a user, by performing the steps of the attacks without actually performing any malicious activity. Educational security information is displayed to the user, based on the user's response to simulated attacks. If the user responds to a simulated attack in a manner indicating that the user is vulnerable, educational security information can be displayed that educates the user as to how to avoid being victimized. One or more security settings for protecting the user's computer from malware can be adjusted, based on the user's response to the simulating of attacks. Additionally, other factors can be adjusted based on the user's response to the simulating of attacks, such as a security hygiene rating and/or a level of monitoring activity concerning the user.
US09230114B1 Remote verification of file protections for cloud data storage
A client device or other processing device comprises a file processing module, with the file processing module being operative to provide a file to a file system for encoding, to receive from the file system a proof of correct encoding of the file, and to verify the proof of correct encoding. The file system may comprise one or more servers associated with a cloud storage provider. Advantageously, one or more illustrative embodiments allow a client device to verify that its files are stored by a cloud storage provider in encrypted form or with other appropriate protections.
US09230111B1 Systems and methods for protecting document files from macro threats
A computer-implemented method for protecting document files from macro threats may include (1) identifying a document file that contains an embedded macro, (2) locating an event-driven programming language module that stores the embedded macro for the document file, and (3) cleaning the event-driven programming language module by removing procedures for the embedded macro within the event-driven programming language module and retaining variable definitions within the event-driven programming language module. Various other methods, systems, and computer-readable media are also disclosed.
US09230110B2 Accessing privileged objects in a server environment
Accessing privileged objects in a server environment. A privileged object is associated with an application comprising at least one process resource and a corresponding semi-privileged instruction. The association is filed in an entity of an operating system kernel. A central processing unit (CPU) performs an authorization check if the semi-privileged instruction is issued and attempts to access the privileged object. The CPU executes the semi-privileged instruction and grants access to the privileged object if the operating system kernel has issued the semi-privileged instruction; or accesses the entity if a process resource of the application has issued the semi-privileged instruction to determine authorization of the process resource to access the privileged object. Upon positive authorization the CPU executes the semi-privileged instruction and grants access to the privileged object, and upon authorization failure denies execution of the semi-privileged instruction and performs a corresponding authorization check failure handling.
US09230108B2 Contextual alert of an invasion of a computer system
Methods, systems, and computer-readable media for providing contextual feedback to a user of a computer system upon detection of an invasion of the computer system are provided herein. An invasion of the computer system is detected and a contextually appropriate alert is selected from a set of alerts. The alert is played immediately upon detection of the invasion so that the user is alerted to the invasion within close temporal proximity to the user's action that resulted in the invasion of the computer system. In addition, details of the invasion are logged to a diagnostic log file for later use by support personnel in repairing the computer system.
US09230107B2 Security devices and methods for detection of malware by detecting data modification
Disclosed is a portable security device and method for detection and treatment of computer malware. An example method includes performing a malware detection experiment by the security device on the computer by simulating a connection to the computer of a simulated data storage device containing a predefined set of data. The method further includes determining if there are any modifications in the set of data contained in the simulated data storage device after termination of the malware detection experiment. The method further includes, based on whether there are any modifications in the set of data, determining whether to perform one or more subsequent malware detection experiments by the security device on the computer. In one example aspect, each of the one or more subsequent malware detection experiments are configured to simulate a different connection to the computer of a different simulated data storage device containing the predefined set of data.
US09230106B2 System and method for detecting malicious software using malware trigger scenarios in a modified computer environment
Disclosed system and methods for malware testing of software programs. An example method includes storing a plurality of malware trigger scenarios specifying different sets of malware trigger events known to trigger malicious behavior in software programs; in response to obtaining a software program, modifying a computer environment for operating the software program by creating malware trigger events associated with a selected one of the plurality of malware trigger scenarios; analyzing an execution of the software program in the modified computer environment in response to the malware trigger events; upon detecting that the software program exhibits malicious behavior, performing remedial actions on the software program; and upon detecting that the software program exhibits no malicious behavior, selecting a different malware trigger scenario from the plurality of malware trigger scenarios for malware testing of the software program.
US09230097B2 Method and system for detecting data modification within computing device
A method and apparatus for detecting data modification in a layered operating system is disclosed. Outbound content indicators at different layers are compared to detect potential outbound data modifications. Likewise, inbound content indicators at different layers are compared to detect potential inbound data modifications. Content indicators include checksum, cryptographic hash, signature, and fingerprint indicators. Embodiments of the present invention enable detection of data modifications across an operating system's kernel and user mode spaces, prevention of modified outbound data from reaching a network, prevention of modified input data from reaching a user application, and detection of malware and faults within an operating system.
US09230096B2 System and method for data loss prevention in a virtualized environment
A data loss prevention (DLP) manager running on a security virtual machine manages DLP policies for a plurality of guest virtual machines. The DLP manager identifies a startup event of a guest virtual machine, and installs a DLP component in the guest virtual machine. The DLP component communicates with the DLP manager operating within the security virtual machine. The DLP manager also receives file system events from the DLP component, and enforces a response rule associated with the guest virtual machine if the file system event violates a DLP policy.
US09230094B2 Managing password strength
A method for managing password strength including receiving a password on a data processing system for a user, filtering for personal information about the user from multiple independent data sources accessible across a computer network, computing the password strength by the data processing system using an algorithm which compares the password to the filtered personal information about the user, and presenting feedback to the user through a user interface on a data processing system display regarding the computed password strength.
US09230090B2 Storage device, and authentication method and authentication device of storage device
An authentication method of a storage device includes an authentication device requesting an EID (Encoded IDentifer) from the storage device for authenticating the storage device, the authentication device receiving the EID and restoring original ID information by decoding the received EID, and finally the authentication device verifying, by using ID authentication information received from the storage device, individual ID information corresponding to use of the storage device included in ID information, wherein the ID information includes multiple pieces of individual ID information corresponding to the use of the storage device.
US09230086B2 System and method for dynamically unlocking mobile device
A system and a method for dynamically unlocking a mobile device are provided. The method includes displaying various lock images, where at least one of the parts is altered, when an attempt is made to unlock the mobile device, determining whether a lock image, detected according to a user input, matches a preset image, and unlocking the mobile device according to the result of matching between the detected lock image and the preset image. The system and method increases the level of security when an unlock attempt is made in a public place.
US09230080B2 Method of starting a computer using a biometric authentication device
A computer is made usable in a short time using a fingerprint authentication device. When a fingerprint authentication device performs authentication successfully, the fingerprint authentication device sends a startup signal to a power controller via a line. The power controller controls a DC/DC converter to supply power to devices. The fingerprint authentication device sets whether normal boot or fast boot that is completed in a shorter time than the normal boot is successful, in a register via a line. In the fast boot, initialization of a USB interface of a line and password input by a user are skipped, and a BIOS accesses a system by single sign-on using a password stored in a secure area.
US09230079B2 Apparatus and method for configuring password and for releasing lock
Methods of configuring a different authority for a plurality of users to use at least one application in an electronic device. User inputs are received to set passwords for respective user levels, where each user level is associated with a different authority to access applications. The passwords are registered for the respective user levels. At least one application is associated with one of the user levels.
US09230061B2 System and method for text extraction and contextual decision support
A contextual analysis system that extracts data elements from an unstructured text input; determines whether the extracted data elements are relevant to a predetermined context; and determines, for the extracted elements deemed as relevant, whether the information contained in the relevant data elements complies with a guideline.
US09230060B2 Associating records in healthcare databases with individuals
At least one attribute type associated with an individual in a first record of a first database and one or more similar attribute types in record(s) of other second database(s) are located. The attribute types compared. Based on the comparison, a first weighted score for the first record and another weighted score for each other records are computed. The weighted score indicates a likelihood the particular attribute type is associated with a same individual as other attribute type(s) located in other record(s) and further accounts for a time delta between measurements of the attribute types. Confidence score outputs for the records are also computed. The confidence score output of a record is based on all weighted scores of that record and indicates a likelihood that record is associated with the same individual. At least one database is updated based on at least one of the confidence score outputs.
US09230058B2 Image processing device, image processing method and program
An image processing device includes: a first feature amount extraction unit configured to extract a first feature amount from an image; a position detection unit configured to detect observation positions from the image based on a position detection dictionary, and the first feature amount extracted from the image; a second feature amount extraction unit configured to extract a second feature amount from the observation position; an observation-order determining unit configured to determine the order of observing the observation positions based on an order generation dictionary, and respective second feature amounts of the observation positions; and an image generation unit configured to generate observation images for displaying the observation positions in the observation order based on the image, the detected observation positions and the determined observation order.
US09230055B2 Method of optimizing film cooling performance for turbo-machinery components
A method, apparatus and program product are provided to optimize film cooling performance for turbomachinery components. A design space is defined by selecting process variables and limits. A random initial population of a plurality of designs is provided using Latin hypersquare sampling, varying the process variables across the design space. Each design of the plurality of designs is evaluated. A fitness function value is determined based on a performance of each of the evaluated designs of the plurality of designs. A half of the plurality of designs having higher fitness function values is selected. Designs of the selected half of the plurality of designs are randomly paired to generate two new designs from each random pair of designs forming a plurality of new designs.
US09230051B2 Method of generating voltage island for 3D many-core chip multiprocessor
Provided is a method of forming a voltage island for a 3D many-core chip multiprocessor, the method including setting the priority of a voltage zone based on the heat emission characteristic of the voltage zone; and forming a voltage island by using the priority.
US09230050B1 System and method for identifying electrical properties of integrate circuits
A new method for displaying electrical properties for integrated circuit (IC) layout designs provides for improved human visualization of those properties and comparison of as designed layout design parameters to as specified layout design parameters and to as manufactured layout parameters. The method starts with a circuitry as designed layout in a first digital format, extracts values for electrical properties from that circuitry as designed layout then annotates those values back into the first digital format. The annotated circuitry as designed layout is then converted from the first digital format to a second digital format that can be converted to a raster scan image of the extracted and annotated electrical property values superimposed at their corresponding physical locations onto a physical layout image of the integrated circuit, preferably color-coded to further spotlight potential defects. The visual images are compared to as specified layout design parameters and to as manufactured parameters.
US09230049B1 Arraying power grid vias by tile cells
A system for designing a power grid for an integrated circuit system forms a plurality of half pitch tiles that do not have a via violation, where each half pitch tile has a different orientation. The system generates sub tile arrays from each of the half pitch tiles. The system then forms a plurality of quarter pitch tiles that do not have a via violation, where each quarter pitch tile has a different orientation. The system generates deep sub tile cell arrays from each of the quarter pitch tiles. The system then covers a plurality of adjacent individual sub tile cells of the power grid with one of the sub tile arrays, and covers a plurality of adjacent individual deep sub tile cells of the power grid with one of the deep sub tile arrays.
US09230048B1 Integrated circuits with interconnect selection circuitry
Integrated circuits such as programmable integrated circuits may include programmable logic regions that can be configured to perform custom user functions. The programmable logic regions may produce output signals. The integrated circuit may include interconnects that route selected output signals throughout the integrated circuit. The integrated circuit may include output selection circuitry having output selection and interconnect selection stages. The output selection circuitry may be configured to select which of the output signals produced by the programmable logic regions are provided to the interconnects for routing. The interconnect selection stage may be formed using multiplexing circuits or tristate drivers. Logic design system computing equipment may be used to generate configuration data that can be used to program the output selection circuitry to reduce crosstalk by routing signals away from critical interconnects or by double-driving critical interconnects.
US09230046B2 Generating clock signals for a cycle accurate, cycle reproducible FPGA based hardware accelerator
A method, system and computer program product are disclosed for generating clock signals for a cycle accurate FPGA based hardware accelerator used to simulate operations of a device-under-test (DUT). In one embodiment, the DUT includes multiple device clocks generating multiple device clock signals at multiple frequencies and at a defined frequency ratio; and the FPG hardware accelerator includes multiple accelerator clocks generating multiple accelerator clock signals to operate the FPGA hardware accelerator to simulate the operations of the DUT. In one embodiment, operations of the DUT are mapped to the FPGA hardware accelerator, and the accelerator clock signals are generated at multiple frequencies and at the defined frequency ratio of the frequencies of the multiple device clocks, to maintain cycle accuracy between the DUT and the FPGA hardware accelerator. In an embodiment, the FPGA hardware accelerator may be used to control the frequencies of the multiple device clocks.
US09230045B2 Layer-by-layer quantification of the remodeling of the human fovea in neurodegenerative disease
A system and method for layer-by-layer quantification of the remodeling of the human fovea comprises finding a fixed reference point in inner retina, measuring the thickness of the inner retina at the fixed reference point, for a range of finely sampled distances starting from the fixed reference point, measuring the thickness, comparing the measured thickness with a normative base and obtaining a plurality of curves, evaluating area for each curve and defining a distance from the fixed reference having highest sensitivity with respect to the fixed reference point compared to the normative base, displaying a 3D re-creation of foveal architecture-based color-coded picture in accordance with the measured thickness at each finely sampled distance, entering the measured thickness into a model having parameters, obtaining numerical solutions for each parameter, and defining percent change of the parameters for the patient versus the parameters for the control.
US09230040B2 Scalable, schemaless document query model
Query models for document sets (such as XML documents or records in a relational database) typically involve a schema defining the structure of the documents. However, rigidly defined schemas often raise difficulties with document validation with even inconsequential structural variations. Additionally, queries developed against schema-constrained documents are often sensitive to structural details and variations that are not inconsequential to the query, resulting in inaccurate results and development complications, and that may break upon schema changes. Instead, query models for hierarchically structured documents that enable “twig” queries specifying only the structural details of document nodes that are relevant to the query (e.g., students in a student database having a sibling named “Lee” and a teacher named “Smith,” irrespective of unrelated structural details of the document). Such “twig” query models may enable a more natural query development, and continued accuracy of queries in the event of unrelated schema variations and changes.
US09230039B2 Adaptive data transformation engine
Information streams are integrated with context information objects and processing instruction objects. The integrated information streams are received by a solution manifold and transformed in accordance with the context information objects, the instruction objects, and logic inherent in the solution manifold. The transformed information is then viewed by a client of the solution manifold. The client may also impose different transformation rules and context information on the transformed information and return those transformation rules and context information to the solution manifold to revised the manner in which integrated data is subsequently transformed. Additionally, the solution manifold logic may be overruled by the instruction objects and/or updated by the instruction objects.
US09230038B2 Content fetching and caching on a mobile device
A device may receive application information associated with an application. The application information may include information associated with a native homepage associated with the application, and may include a single file that includes content associated with the application. The device may receive an indication associated with running the application. The device may present, for display, the native homepage. The native homepage may include information associated with accessing the content. The device may determine that the content, associated with the application, is not current content. The device may obtain the current content, associated with the application, based on determining that the content is not the current content. The device may store the current content based on obtaining the current content. The device may load the current content based on storing the current content. The current content may be loaded to prepare the current content to be displayed to a user.
US09230037B2 Identifying and resolving cache poisoning
According to some embodiments, a method and apparatus are provided to receive, at a cache entity, a refresh request associated with a resource. A determination is made, via a processor, and based on the refresh request, to reload the resource from a server. The reloaded resource is replaced at the cache entity.
US09230035B2 Pushing specific content to a predetermined webpage
A method and an apparatus for pushing specific content for a predetermined webpage, and a website server. The method for pushing specific content for text content on a predetermined webpage comprises: subjecting text content on a predetermined webpage to emotional analysis; determining a matching degree between a result of the emotional analysis and an emotion expressed by specific content to be pushed; and responding to that the matching degree determined above satisfies a predetermined condition, combining a part of the text content with the specific content to be pushed, thereby forming content to be pushed specific for users. By using the technology of the present invention, user can be avoided from feeling disgust for content to be pushed and accuracy of push can be enhanced.
US09230024B2 Method and system for ranking web pages in a search engine based on direct evidence of interest to end users
A method and system for ranking Web pages in a Web search engine is described. One illustrative embodiment receives a Web search query from a particular user, the query including at least one keyword; identifies one or more Web pages that contain the at least one keyword; determines, for each of the one or more Web pages, a raw page ranking; adjusts the raw page ranking of each of at least one Web page among the one or more Web pages based on direct evidence of how interesting that Web page is to users to produce an adjusted page ranking, the direct evidence being derived from clickstream data collected from the users; and presents, as search results, the at least one Web page to the particular user in accordance with the adjusted page rankings.
US09230021B2 Image diagnostic apparatus, image diagnostic method, medical image server and medical image storage method
An image diagnostic apparatus includes an examination information acquisition unit and an imaging unit. The examination information acquisition unit searches a medical image server based on patient information to acquire past examination information corresponding to the patient information automatically from the medical image server. The imaging unit performs imaging according to an imaging condition set by referring to the examination information. Alternatively, an image diagnostic apparatus includes an imaging condition setting unit and an imaging unit. The imaging condition setting unit automatically sets or indicates an imaging condition closest to information designating an imaging condition included in examination order information directed to an image diagnostic apparatus made by another maker or a different type of an image diagnostic apparatus made by a same maker. The imaging unit performs imaging according to the set or indicated imaging condition.
US09230019B2 Semantic information processing
A system for exchanging various forms of information between computer-executable agents. A computing device is configured to determine semantic data associated with each data object (DO) of a plurality of DOs. Each DO is associated with a location, and the semantic data describes the content of the associated DO. The computing device receives, from a first user computing device, a request for DO information and, in response to the request, provides DO information including the locations and the semantic data associated with the retrieved DOs to the user computing device by (a) transmitting the locations and the semantic data to the first user computing device, and/or (b) instructing the first user computing device to request the DO information from a second user computing device to which the locations and the semantic data were previously transmitted.
US09230016B2 User input auto-completion
Methods and computer program product relate to user input auto-completion. The methods and product are executable on a processing device in a computing system environment so as to provide an auto-completion scheme with enhanced capabilities that improve user efficiency when performing a task.
US09230009B2 Routing of questions to appropriately trained question and answer system pipelines using clustering
Mechanisms for selecting a pipeline of a question and answer (QA) system to process an input question are provided. An input question is received and analyzed to identify at least one feature of the input question. Clustering of the input question, with one or more previously generated clusters of questions, is performed based on the at least one feature of the input question. Based on results of the clustering, a matching cluster, of the one or more previously generated clusters, is identified with which the input question is associated. A QA system pipeline associated with the matching cluster is identified and the input question is processed using the identified QA system pipeline to generate one or more candidate answers for the input question. Each cluster in the one or more previously generated clusters has an associated QA system pipeline.
US09230007B2 Preserving sets of information in rollup tables
Techniques for making aggregated entries in a database table which aggregate information from other entries in tables in the database system. The techniques permit the aggregated entries to contain not only metric values aggregated from the other entries by techniques such as averaging in which the individual values are lost, but also sets of individual values from the other entries. One area of application for the techniques is the roll up tables used in the management systems for database management systems to reduce the size of historic information about events that have occurred in the database management system. Each roll up entry in a roll up table is an aggregated entry that contains information about some number of events. A roll up entry that uses the techniques contains a representation of a set whose values are the occurrence times of the events that are represented by the rollup record. Among the techniques that can be used to represent the set of occurrence times are a comma list of the occurrence times and a bit map which has a bit for each second in a day. Roll up entries that contain such representations of sets of occurrence times may be analyzed to determine whether occurrences of events are related, and if they are, the fact of the relationship can be used to design filters that can be applied in the roll up process, in error reporting, and in the analysis of the roll up tables.
US09230006B2 Remote access to tracking system contact information
In the context of tracking systems, it is difficult to ensure that an organization has a complete, accurate database of contacts stored in its tracking system. When tracking systems users are required to manage exporting and importing of contacts from their desktop mail clients and handheld devices, it is almost certain that contact information will not be kept up-to-date and that confidence in the accuracy of the contact information will not be high. By enabling a remote directory access portal in the tracking system, all users can be assured that they have available the latest contact information for the organizations' contacts. In addition to providing directory access, the tracking system can authenticate users and, based on the users' entitlements, authorize users' access to specific contacts.
US09230004B2 Data processing method, system, and computer program product
The present description refers in particular to a data processing method, a computer program product, and a data processing system for obtaining and storing data in an outsourcing environment, the method including providing a user interface on a user computer; determining an indicator which indicates whether there is synchronization data in a user database, wherein the synchronization data is for synchronization with a remote database which is located on a remote computer; obtaining user data with the user interface; and storing the user data in the user database if the indicator indicates that there is synchronization data in the user database.
US09230002B2 High performant information sharing and replication for single-publisher and multiple-subscriber configuration
A method for sharing information between a publisher and multiple subscribers is provided. The publisher uses a latch-free, single publisher, multiple subscriber shared queue to share information. Logical change records representing changes made to a database are enqueued in the shared queue as messages in a stream of messages, and subscribers read the logical change records. Subscribers may filter logical change records before sending to apply processes for processing. An identifying property of the source instance of a change encapsulated in a logical change record may be included with each message enqueued.
US09230001B2 Intelligent data propagation using performance monitoring
Exemplary methods, apparatuses, and systems that can intelligently copy data to a plurality of datastores using performance monitoring are described. In one embodiment, a shortest path tree determines the most efficient paths available for copying data from a source datastore to one or more destination datastores. During the copying of the data between a source datastore and the one or more destination datastores, a performance value of each of the datastores involved in the copying process is compared to a threshold. In response to determining that the performance value of a given source or destination datastore involved in the copying exceeds the threshold, the copying of the data to the corresponding destination datastore is suspended. An updated shortest path tree is determined to locate a more efficient path for copying data to the suspended destination datastore. Copying is resumed to the suspended destination datastore using the updated shortest path tree.
US09229999B2 Using average replication latency to influence routing query transactions
A data processing system and method of operation are disclosed. The data processing system includes a first site for processing data; a second site for processing data; and a transaction replay program configured to send a copy of data from the first site to the second site. A processor defines a maximum replication latency threshold and a reset threshold for the system, estimates a replication latency of a workload the system, switches the system to a first replication latency state when the estimated replication latency rises above the maximum replication latency and switches the system out of the first replication latency state to a second replication latency state when the estimated replication latency falls below the reset threshold.
US09229992B2 Automatic identification of digital content related to a block of text, such as a blog entry
A system for identifying digital content related to a portion of a block of text receives, automatically or via input by a user, an indication of one or more words included in the block of text. The system searches a database of digital content based on the one or more words and retrieves from the database one or more digital content items or identifiers of digital content items that are related to the one or more words. The system provides the retrieved digital content items or identifiers to the user, and receives a selection of one or more of the provided items or identifiers from the user. The system associates for display or replay the one or more selected digital content items with the one or more words in the block of text. Other embodiments of the system are also disclosed.
US09229991B2 Computer-implemented system and method for exploring and filtering an information space based on attributes via an interactive display
A computer-implemented system and method for exploring and filtering an information space based on attributes via an interactive display is provided. Entities related to an information space are retrieved. Attributes associated with the entities are identified. The entities are displayed as a list. A status representation of the entities and at least one attribute graph based on one of the attributes from the entity list are presented. A status of a user with respect to one or more of the entities is tracked. The status for the one or more entities is received from the user. The user status is applied to the status representation and the attribute graph.
US09229989B1 Using resource load times in ranking search results
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for using resource load times in ranking search results. In one aspect, a method includes receiving a search query from a particular user device; receiving, for each of a plurality of resources responsive to the search query, a respective first score; accessing load time data that specifies, for each of the plurality of resources, a load time measure for the resource; and adjusting the first score for each of the plurality of resources based on the load time measure for the resource to generate a second score for each of the plurality of resources.
US09229987B2 Mapping between tokenization domains
A tokenization environment includes a first tokenization system in a first token domain and a second tokenization system in a second token domain. A token mapper accesses a first token from the first tokenization system and maps it to a second token from the second tokenization system. The first token can be a single-use or SLT token mapped to a clear text value within a single-use token table in the first tokenization system. The token mapper can identify the clear text value, and can query a multi-use token table in the second tokenization system with the clear text value to identify a multi-use token (the second token) mapped to the same clear text value. The token mapper can store the association between the first token and the second token in a token map.
US09229983B2 System-wide query optimization
A locally optimized plan for executing a command using a sequence of steps can be determined for a single computing node. However, the locally optimized sequence of steps may not be optimized for a combined system comprising multiple computing nodes, any one of which may be tasked with executing the command. A plan that is optimized for the combined system may be determined by comparing the predicted cost of locally optimized plans for computing nodes in the combined system.
US09229978B2 Rule-based extendable query optimizer
A query is received which causes an initial data flow graph that includes a plurality of nodes that are used to execute the query is generated. Thereafter, the initial data flow graph is optimized using a model optimizer that includes an optimizer framework and an application programming interface (API). The optimizer framework provides logic to restructure the initial data flow graph and a rules engine for executing one or more optimization rules. The API allows for registration of new optimization rules to be executed by the rules engine. Execution of the query is then initiated using the optimized data flow graph. Related apparatus, systems, techniques and articles are also described.
US09229976B2 Identifying entities based on interactivity models
An interactivity system is provided that tracks interactivity between a target entity and participant entities and identifies entities whose interactions satisfy an interactivity criterion. The interactivity system maintains for the target entity interactivity models between the target entity and each participant entity, with each interactivity model modeling the interactions between the target entity and that participant entity. The interactivity system dynamically updates the interactivity models as notification of interactions are received. Upon receiving a query that specifies an interactivity criterion, the interactivity system analyzes the interactivity models to determine whether the interactivity criterion is satisfied. When an interactivity criterion is satisfied, the interactivity system sends a response to the query indicating that the interactivity criterion is satisfied along with the identity of the entity that satisfies the interactivity criterion.
US09229973B2 Apparatus and method for search and retrieval of documents
A system for the support and management of search for documents is presented. The system includes knowledge-database, query interface and communication to a database of documents to be searched. Information generated during a search session is collected by the system and is added to the knowledge-database. The information is ranked automatically according to the usage of that information by the user. During successive search session, or during search made by other users, the system uses the knowledge-database to support the users with keywords, queries and reference to documents.
US09229972B2 Systems and methods for content collection validation
Electronic data file and content capturing systems and methods enable enhanced accessibility and reduced complexity for clients managing large volumes of digital data files. According to one aspect, a system and method provided for validation and tracking of content collection tasks. According to another aspect, systems and methods are disclosed for error management through integrated interfaces that are capable of interacting with and correcting the results of content collection tasks.
US09229971B2 Matching data based on numeric difference
Systems and methods for matching data based on numeric difference are described herein. Input data elements are parsed to identify a first number and a second number. A difference between the first number and the second number is calculated based on a predefined formula. Based on the difference, a matching score between the input data elements is evaluated. The matching score is proportional to a base matching score corresponding to a threshold difference, and a maximum score corresponding to a match between the first number and the second number. A similarity between the input data elements is reported based on the evaluated matching score.
US09229970B2 Methods to minimize communication in a cluster database system
An ordering of operations in log records includes: performing update operations on a database object by a node; writing log records for the update operations into a local buffer by the node, the log records each including a local virtual timestamp; determining that a log flush to write the log records in the local buffer to a persistent storage is to be performed; in response, sending a request from the node to a log flush sequence server for a log flush sequence number; receiving the log flush sequence number by the node; inserting the log flush sequence number into the log records in the local buffer; and performing the log flush to write the log records in the local buffer to the persistent storage, where the log records written to the persistent storage comprises the local virtual timestamps and the log flush sequence number.
US09229966B2 Object modeling for exploring large data sets
Techniques are described for facilitating performing computer-implemented financial analysis. A metric that transforms one or more time series into an output object is identified. The one or more time series are determined based on one or more input objects. The metric is applied using the one or more time series, thereby generating a particular value for the output object. One of the metric and the particular value for the output object is stored in a physical storage device.
US09229958B2 Retrieving visual media
Examples of the present disclosure may include methods, systems, and computer readable media with executable instructions. An example method for retrieving visual media can include receiving a text query associated with a target content. A first group of visual media is identified based on correspondence of metadata of the visual media with the text query, and keyframes from the first group of identified visual media are selected. The method further includes detecting instances of a content type in the selected keyframes, and grouping similar instances of the content type into clusters. The target content is associated with a cluster having a greatest quantity of similar instances.
US09229955B2 Method and apparatus for recognizing objects in media content
An approach is provided for recognizing objects in media content. The capture manager determines to detect, at a device, one or more objects in a content stream. Next, the capture manager determines to capture one or more representations of the one or more objects in the content stream. Then, the capture manager associates the one or more representations with one or more instances of the content stream.
US09229954B2 Sharing item images based on a similarity score
Techniques for sharing item images based on a similarity score are described. For example, a machine receives an item listing for an item from a user device. The machine generates a similarity score for an existing image corresponding to one or more existing item listings by comparing the item listing received from the user device with the one or more existing item listings. The similarity score may indicate a degree of similarity between the item listing received from the user device and the one or more existing item listings corresponding to the existing image. The machine selects one or more existing images corresponding to the one or more existing item listings based on the one or more existing images having corresponding similarity scores that exceed a threshold value. The machine transmits a communication to the user device in response to the receiving of the item listing from the user device. The communication may include the one or more existing images.
US09229953B2 Geo-enabling of data sources
A method includes receiving data from a non-geo enabled data source, obtaining information related to location in the received data, converting the obtained information to a standardized form of geo-location data, and storing the geo-location data.
US09229951B1 Key value databases for virtual backups
A method, article of manufacture, and apparatus for protecting data. This includes identifying files from a master file table, generate a key/value database based on the identified files, wherein the key includes directory information and the value includes file metadata, and storing the key/value database in a storage device. Identifying files from a master file table includes parsing a VMDK to isolate a master file table region.
US09229950B2 Method and device for processing files of distributed file system
A method and device for processing files of distributed file system are disclosed, in which the method involves dividing the file into at least one data group according to the size of the file, and determining first mapping information from the file to the at least one data group, in which each of the at least one data group includes content blocks and verification block of file, and determining second mapping information from each of the at least one data group to data storage servers storing the each of the at least one data group (102), and providing the first mapping information and the second mapping information to a client for executing a writing operation of files (103). The technical solution can improve availability of memory space and decrease costs of constructing a distributed file system.
US09229942B1 Method and system for hard link handling for incremental file migration
Hard link handling for incremental file migration is described. A file is stored on a storage device. A determination is made whether a path associated with the file is also associated with an index node number in a hard link table. The file is deleted from the storage device if the path associated with the file is also associated with the index node number in the hard link table. The path is linked on the storage device with another file that is associated with another path that is associated with the index node number in the hard link table.
US09229940B2 Method and apparatus for improving the integration between a search engine and one or more file servers
In one aspect of the invention, a search engine parses files stored among one or more file servers in order to create and maintain index information used by the search engine to perform searches. For a given file server, the population of files presented to the search engine is reduced in size to facilitate the process of updating the index. In another aspect of the invention, the file server limits the files presented in a directory list request made by a search engine. This reduces the number of file s that need to be considered when performing an index update.
US09229937B2 Apparatus and method for managing digital contents distributed over network
A content management system entails analyzing similarity of the contents distributed among at least one network element (e.g., contents server) and managing the contents on the basis of the analysis result. The content management server analyzing similarities of content files and providing the similarities information includes a communication unit that collects content information from at least one content server stored the content files and the content information corresponding to the content files; a digital content management (DCM) control unit which analyzes similarities of the content files received from the content server; a storage which stores information on the similarities analyzed by the DCM control unit; a content information comparison unit which detects the content information in response to a similar content file request transmitted from a client on the basis of the similarities information.
US09229935B2 Simulating accesses for archived content
According to one embodiment of the present invention, a system identifies content for publication by determining a projected usage of unpublished content. The system applies one or more predefined criteria for publication to the projected usage. The content is published in response to the projected usage satisfying the criteria for publication. Embodiments of the present invention further include a method and computer program product for identifying content for publication in substantially the same manners described above.
US09229932B2 Conformed dimensional data gravity wells
A processor-implemented method, system, and/or computer program product defines multiple dimensional data gravity wells on a conformed dimensional data gravity wells membrane. Non-dimensional data objects are associated with dimension objects to define conformed dimensional objects. The conformed dimensional objects are parsed into an n-tuple that includes a pointer to one of the non-dimensional data objects, a probability that a non-dimensional data object has been associated with a correct dimension object, and a weighting factor of importance of the conformed dimensional object. A virtual mass of each parsed conformed dimensional object is calculated, in order to define a shape of multiple dimensional data gravity wells that are created when conformed dimensional objects are pulled into each of the dimensional data gravity well frameworks on a conformed dimensional data gravity wells membrane.
US09229929B2 Modular translation of learning applications in a modular learning system
A modular learning system is provided that incorporates translation of language and media metadata associated with learning applications. The author of a learning application may provide a description of a desired translating user to perform translation of the author's learning application. The modular learning system provides a set of translating users meeting the description. The author selects a translating user and the selected translating user is provided on a translation request being made. After translation by the translating user, the language and media are updated to provide the translation to users. A badge is created for display to users to indicate the translation and data about the translation.
US09229928B2 Language learning platform using relevant and contextual content
A method and system for displaying translated text for language learning having content in a first language and a translation thereof in a second language. A user can hover over the content with a mouse to display a popup box containing a content component in the second language corresponding to a content component in the first language. The content components are highlighted as the user hovers over them with the mouse to identify corresponding content components between the first language and the second language. Also provided is an electronic flashcard generated by the user from the content.
US09229922B2 Token representation of references and function arguments
A token representation of references and function arguments is disclosed. In some embodiments, an indication that a formula is being entered into a cell is received, and references and/or function arguments in the formula, if any, are represented as tokens. Each token comprises an atomic user interface object. In various embodiments, references are rendered as reference tokens and function arguments are rendered as argument tokens and/or mode tokens.
US09229921B2 Method and system for processing the input in a XML form
System and method for processing the input in an XML form. The method may include providing a template XML form to the user, receiving a modified XML form from the user, identifying the differences between the template XML form and the modified XML form and further processing the modified XML form based on the identified differences.
US09229918B2 Presenting an application change through a tile
This document describes techniques and apparatuses for presenting an application change through a tile. These techniques enable a user to see content associated with content changes to an application or other information about the application, such as a new article, new email, or a software update having become available since a user last visited the application. By so doing, the techniques enable a user to forgo visiting the application or permit the user to quickly and easily decide whether or not to visit the application.
US09229916B2 Rendering sections of content in a document
Systems, methods and articles of manufacture are disclosed for rendering a document having collapsible sections of content. In one embodiment, the document may be received and rendered for display. Rendering the document for display may include collapsing all but a first section of the collapsible sections of content. Rendering the document for display may also include collapsing all but a second section of the collapsible sections of content, upon determining that a period of time has elapsed since collapsing all but the first section of the collapsible sections of content.
US09229911B1 Detecting continuation of flow of a page
A flow of objects, such as text, on a page may be analyzed by generating an initial determination of whether a portion of an object is continued from one page to another based on a cue in an area of the object. The initial determination may be visually represented on a page. The initial determination may be corrected by an editor to create an editor determination when the initial determination is not a correct continuation status of the portion of the object. In some aspects, the initial determination may include a statistical confidence interval, a reason display, and/or a magnification of portions of the object which may be included in a continuation. In other aspects, heuristics may learn from the editor changes to improve a subsequent initial determination.
US09229902B1 Managing update deployment
Systems and methods for managing deployment of an update to computing devices, and for diagnosing issues with such deployment, are provided. An update deployment manager determines one or more initial computing devices to receive and execute an update. The update deployment manager further monitors a set of performance metrics with respect to the initial computing devices or a collection of computing devices. If a deployment issue is detected based on the monitored metrics, the update deployment manager may attempt to diagnosis the deployment issue. For example, the update deployment manager may determine that a specific characteristic of computing devices is associated with the deployment issue. Thereafter, the update deployment manager may modify future deployment based on the diagnosis (e.g., to exclude computing devices likely to experience the deployment issue).
US09229891B2 Determining a direct memory access data transfer mode
In response to receiving a request for a DMA data transfer, a DMA transfer mode may be determined based on based on the size of the requested DMA data transfer and profile data of an I/O adapter. The profile data for the I/O adapter may include a physical location of the I/O adapter or a number of clients supported by the I/O adapter. The DMA transfer mode may also be determined based on a preference of an application or an I/O device. Moreover, the DMA transfer mode may be determined based on a CPU usage metric being outside of a threshold for the CPU usage metric or on a memory usage metric being outside of a threshold for the memory usage metric.
US09229890B2 Method and a system for integrating data from a source to a destination
The embodiments herein provide a system and a method for integrating a data from a source to a destination. The method comprises generating a global-id, setting an event-id corresponding to an entity id in the global id, polling a data from a source, sorting changes of a source system based on a time of update and an entity id, creating and comparing an old as of state value and a new as of state value for each field for each update in the entity in the source and destination to detect a conflict on an entity, sending a time of update in the entity and a revision id of a change to the destination, comparing the global id with an event id for each entity at the destination to detect a presence of an entity in the destination and processing an entity at the destination based an event id.
US09229888B1 Area-efficient dynamically-configurable memory controller
Architecture, systems, and methods for developing, an area-efficient dynamically-configurable memory controller are described. The architecture, systems and methods may provide savings in terms of surface area required for implementing a dynamically configurable hardened memory controller or controllers.
US09229883B2 Extended input/output measurement word facility for obtaining measurement data in an emulated environment
An Extended Input/output (I/O) measurement word facility is provided. Provision is made for emulation of the Extended I/O measurement word facility. The facility provides for storing measurement data associated with a single I/O operation in an extended measurement word associated with an I/O response block. In a further aspect, the stored data may have a resolution of approximately one-half microsecond.
US09229877B2 Method and apparatus for optimal cache sizing and configuration for large memory systems
A method for configuring a large hybrid memory subsystem having a large cache size in a computing system where one or more performance metrics of the computing system are expressed as an explicit function of configuration parameters of the memory subsystem and workload parameters of the memory subsystem. The computing system hosts applications that utilize the memory subsystem, and the performance metrics cover the use of the memory subsystem by the applications. A performance goal containing values for the performance metric is identified for the computing system. These values for the performance metrics are used in the explicit function of performance metrics, configuration parameters and workload parameters to calculate values for the configuration parameters that achieve the identified performance goal. The calculated values of the configuration parameters are implemented in the memory subsystem.
US09229876B2 Method and system for dynamic compression of address tables in a memory
A method and system are disclosed for handling logical-to-physical mapping and increasing the amount of mapping table information that may be stored in a cache in volatile memory. The method includes the storage device storing in fast access memory, such as RAM, a copy of only a portion of the complete mapping information for non-volatile memory of the storage device using a compressed format by compressing the mapping data when a skip pattern of interleaved sequential writes to non-volatile memory are found in the mapping information. The system includes a storage device having volatile memory, non-volatile memory and a controller in communication with the volatile and non-volatile memory that is configured to carry out the method noted above.
US09229875B2 Method and system for extending virtual address space of process performed in operating system
A method of extending a virtual address space of a process executed in an operating system includes selecting a virtual address range included in a virtual address space corresponding to the process and the number of a plurality of extended virtual address ranges, extending and thereby setting the virtual address space to a multi-virtual address space based on the selected virtual address range and the selected number of the plurality of extended virtual address ranges, and providing the multi-virtual address space to the process.
US09229870B1 Managing cache systems of storage systems
A method is used in managing cache systems of storage systems. Information is gathered from a storage system to determine an estimated amount of time required to flush data of a nonvolatile cache of the storage system to storage devices. The data cached in the nonvolatile cache is associated with a set of logical objects configured to cache the data in the nonvolatile cache. Based on the information gathered from the storage system, the estimated amount of time required to flush the data of the nonvolatile cache is determined.
US09229864B1 Managing metadata synchronization for reducing host system latency in a storage system
Flushing cache memory of dirty metadata in a plurality of file systems without either letting the caches reach their maximum capacity, or using so much of the total system IO process bandwidth that host system IO process requests are unreasonably delayed, may include determining the length of an interval between sync operations for each individual one of the plurality of file system, and how to divide a system wide maximum sync process IO operation bandwidth fairly between various ones of the plurality of file systems. A computer dynamically measures overall system operation rates, and calculates an available portion of a current calculated sync operation bandwidth for each file system. The computer also measures file system operation rates and determines how long a time period should be between sync operations in each file system.
US09229863B2 Semiconductor storage device
According to the embodiments, a first storage area and a second storage area specified by a trim request is managed by a first management unit, and the second storage area specified by the trim request is managed by a second management unit. A block in which data of the first management unit are all specified by the trim request from the first or second storage areas and a block in which data of the second management unit are all specified by the trim request from the second storage area are released.
US09229859B2 Mapping non-prefetchable storage locations into memory mapped input/output space
A system including a host and a device. The device has at least one non-prefetchable storage location. The host and the device are configured to map the at least one non-prefetchable storage location into memory mapped input/output space that is addressed via greater than 32 address bits.
US09229857B2 Method for wear leveling in a nonvolatile memory
A method for writing and reading data memory cells, comprising: defining in a first memory zone erasable data pages and programmable data blocks; and, in response to write commands of data, writing data in erased blocks of the first memory zone, and writing, in a second memory zone, metadata structures associated with data pages and comprising, for each data page, a wear counter containing a value representative of the number of times that the page has been erased.
US09229853B2 Method and system for data de-duplication
An apparatus may comprise a non-volatile random access memory to store data and a processor coupled to the non-volatile random access memory. The apparatus may further include a data de-duplication module operable on the processor to read a signature of incoming data, compare the signature to first data in the non-volatile random access memory, and flag the incoming data for discard when the signature indicates a match to the first data. Other embodiments are disclosed and claimed.
US09229852B2 Flash translation layer system for maintaining data versions in solid state memory
One or more embodiments are directed to maintaining versions of data within a solid state memory. At least one request to perform an operation on at least one logical page of a solid state memory is received from a file system. A data structure associated with the at least one logical page is identified. The data structure at least identifies one or more physical pages associated with the at least one logical page, and a version of the at least one logical page represented by a dataset stored in each of the one or more physical page. The operation is performed on the at least one logical page based on the data structure that has been identified.
US09229851B2 Memory controller, semiconductor memory device and control method thereof
A memory controller includes logical-physical address conversion table, an access number storing section configured to store the number of accesses to read out data from a memory cell in association with a logical address, a storage state checking section configured to check a storage state of data stored in the memory cell at every predetermined number of accesses, and a refresh processing section configured to perform refresh processing to restore the data stored in the memory cell if the storage state of the data is in a predetermined degraded state.
US09229849B2 Dynamic reconfiguration of storage system
A storage system is dynamically reconfigured. The storage system includes storage pools that each include one or more storage disks. Storage pools to be expanded are determined as target storage pools. For the target storage pools, source storage disks to be moved into the target storage pools are determined from other storage pools than the target storage pools in the storage system. The source storage disks are migrated to the respective target storage pools.
US09229843B2 Predictively managing failover in high availability systems
A method, system, and computer usable program product for predictively managing failover in a high availability system are provided in the illustrative embodiments. A disruptive activity occurring on the HA data processing system is detected. The disruptive activity has a potential to cause an operation of the HA data processing system to perform outside a specified parameter. A determination is made of a desired response in the HA data processing system should the disruptive activity disrupting the operation. A precautionary action is initiated with respect to the HA data processing system.
US09229839B2 Implementing rate controls to limit timeout-based faults
Embodiments are directed to implementing rate controls to limit faults detected by timeout and to learning and adjusting an optimal timeout value. In one scenario, a computer system identifies cloud components that have the potential to fail within a time frame that is specified by a timeout value. The computer system establishes a number of components that are allowed to fail during the time frame specified by the timeout value and further determines that the number of component failures within the time frame specified by the timeout value has exceeded the established number of components that are allowed to fail. In response, the computer system increases the timeout value by a specified amount of time to ensure that fewer than or equal to the established number of components fail within the time frame specified by the timeout value.
US09229837B1 Sensor array evaluation tool and method
A method for evaluating a sensor array includes providing software having the sensor array topology, relating array elements to hardware components. Data from the array elements is collected and evaluated to determine operative components. Displays of the determinations are generated allowing a user to diagnose sensor array failures. Other aspects of the invention provide for automatic array failure diagnosis and improvement of sensor array directivity. An additional aspect provides a system for evaluating a sensor array incorporating a computer with a database and a display.
US09229835B2 Method and apparatus for monitoring state of online application
An online application system and a method for implementing an online application system are disclosed. A method for implementing the online application system includes a) receiving a user search request from a user browser; b) searching for a match according to the search request and obtaining an online application that matches with the search request to form a search result page; and c) presenting the online application before the user browser in a form as a canvas page which is embedded in the search result page and is directly accessible from the search result page. The present disclosure also provides an online application system. The technical solutions disclosed herein allow a user to directly search out an online application via a search engine without a need to click multi-level linkages, thereby providing a quick and convenient search process which enhances the users' experiences with networks.
US09229832B2 Time monitor
A method and system for measuring latency is provided. A monitor node is used to measure latency in a computer network or in a computing device by time stamping signal messages sent from nodes in the computer network and/or tasks in a particular node or device. The time stamps are generated using a system clock of the monitor node to reduce any discrepancies in timing. In addition, the monitor node may compensate for latencies between the monitor node and each of the one or more nodes or devices across which latency is to be measured. Signal messages may include a data message ID and/or a node ID identifying the message that is being tracked and for which latency is being measured. Latency may further be measured across multiple tasks being performed in the same or different nodes or devices by transmitting signal messages for each of the multiple tasks.
US09229831B2 Test device and method
A test device is provided for testing a device under test (DUT) having a control interface compliant with a standard selected from a plurality of standards each supporting a common set of management data input/output (MDIO) and non-MDIO control signals. The test device includes a test interface and an integrated control interface. The integrated control interface adapts to the standard with which the control interface of the DUT complies, so that the integrated control interface directly and fully controls the DUT via at least the common set of MDIO and non-MDIO control signals. The integrated control interface exchanges control signals selected from the common set of MDIO and non-MDIO control signals with the control interface of the DUT to monitor the DUT and thereby obtain status information about the DUT.
US09229826B2 Volatile memory representation of nonvolatile storage device set
The storage devices of a storage device set (e.g., a RAID array) may generate a nonvolatile representation of the configuration of the storage device set, including logical disks, spaces, storage pools, and layout and provisioning plans, on the physical media of the storage devices. A computer accessing the storage device set may also generate a volatile memory representation of the storage device set to use while accessing the storage devices; however, the nonvolatile representation may not be performant due to its different usage and characteristics. Presented herein are techniques for accessing the storage device set according to a volatile memory representation comprising a hierarchy of logical disks, slabs, and extents, and an accessory comprising a provisioning component that handles slab accesses while applying provisioning plans, and that interfaces with a lower-level layout component that translates slab accesses into storage device accesses while applying layout plans to the storage device set.
US09229823B2 Storage and retrieval of dispersed storage network access information
A method begins by a dispersed storage (DS) processing module receiving a certificate signing request (CSR) from a user device. The method continues with the DS processing module generating a set of hidden passwords based on the CSR and accessing a set of authenticating units to obtain a set of passkeys. The method continues with the DS processing module retrieving a set of encrypted shares and decrypting the set of encrypted shares to produce a set of encoded shares. The method continues with the DS processing module decoding the set of encoded shares to recapture a private key and generating a user signed certificate based on the private key. The method continues with the DS processing module discarding the private key to substantially protect the private key from the user device and outputting the user signed certificate to the user device.
US09229822B2 Data disaster recovery
A system includes a production computer machine that includes an operating system and a driver stack. The driver stack includes a file system layer, a recovery driver, a storage layer, a driver layer, a bus driver layer, and a storage device. The system also includes a backup computer processor coupled to the production computer machine via the recovery driver. The recovery driver is configured to commence a recovery of data from the backup computer processor, receive a disk access request from the file system layer, determine if the disk access request accesses data that has not yet been recovered from the backup computer processor, and initiate an on-demand recovery request from the backup computer processor when the data has not been recovered from the backup computer processor.
US09229817B2 Control method of data storage system for restarting expander
The present disclosure discloses a data storage system and a control method thereof. The data storage system includes a plurality of data storage devices, a temporary memory device and an expander. The control method includes: detecting, by the expander, if a flag is in a first status after the expander is restarted; sending, by the expander, a first command to all the data storage devices if the first status is detected. The first status indicates that all the data storage devices are ready for linking and operation.
US09229809B2 Nonvolatile media journaling of verified data sets
The storage of data sets in a storage set (e.g., data sets written to hard disk drives comprising a RAID array) may diminish the performance of the storage set through non-sequential writes, particularly if the storage devices promptly write data sets that are followed by sequentially following data sets. Additionally, storage sets may exhibit inconsistencies due to non-atomic writes of data sets and verifiers (e.g., checksums) and an intervening failure, such as an occurrence of the RAID write hole. Instead, data sets and verifiers may first be written to a stored on the nonvolatile media of a storage device before being committed to the storage set. Such writes may be sequentially written to the journal, irrespective of the locations of the data sets in the storage set; and recovery of a failure may simply involve re-committing the consistent records in the journal to correct incomplete writes to the storage set.
US09229804B2 Mitigating inter-cell coupling effects in non volatile memory (NVM) cells
A system, computer readable medium and a method of operating a non volatile memory (NVM) array that comprises multiple NVM cells, the method comprises: receiving input data to be written to the non volatile memory; performing constraint coding on the input data to provide encoded data; wherein the constraint coding prevents the encoded data from comprising forbidden combinations of values; wherein the forbidden combinations of values are defined based on expected inter-cell coupling induced errors resulting from coupling between NVM cells; and writing the encoded data to the non volatile memory.
US09229803B2 Dirty cacheline duplication
A method of managing memory includes installing a first cacheline at a first location in a cache memory and receiving a write request. In response to the write request, the first cacheline is modified in accordance with the write request and marked as dirty. Also in response to the write request, a second cacheline is installed that duplicates the first cacheline, as modified in accordance with the write request, at a second location in the cache memory.
US09229802B2 Non-systematic coded error correction
Methods are described that facilitate the detection and correction of data in memory systems or devices by encoding the data bits of a memory row or block in a non-systematic ECC code. This allows memory embodiments of the present invention to utilize reduced complexity error detection and correction hardware and/or routines to efficiently detect and correct corrupted user data in a segment of memory, such as a sector, word line row, or erase block. User data is not stored in a plaintext format in the memory array, allowing for an increased level of data security. The ECC code is distributed throughout the stored data in the memory segment, increasing the robustness of the ECC code and its resistance to damage or data corruption.
US09229801B2 Method and device for write abort protection
A data storage device includes a non-volatile memory and a controller. A method includes receiving first data and second data from a host device. A first error-correcting code (ECC) codeword associated with the first data is written to a first word line of the non-volatile memory, and a second ECC codeword associated with the second data is written to a second word line of the non-volatile memory. The first ECC codeword includes a first bit and a second bit, and the second ECC codeword includes a third bit and a fourth bit. The method further includes writing parity information to a parity storage portion of the non-volatile memory that is distinct from the first word line and from the second word line. The parity information includes a parity bit that is based on the first bit, the second bit, the third bit, and the fourth bit.
US09229794B1 Signaling service interface module
Generating a signaling service message for a message group of a sysplex coupled together using a signaling service includes executing, on a computer, a data transfer application that communicates with a respective partner data transfer application on each member of the message group, the data transfer application comprised of a plurality of interworking modules including an interface module. Generating the message also includes receiving by the interface module a request from one of the other interworking modules that is related to sending the signaling service message; and based on the request, determining by the interface module a type of message for the signaling service message. Based on the type of message, the interface module identifies a corresponding routine of an operating system executing on the computer which will generate the signaling service message; and invoking the corresponding routine which causes the operating system to generate the signaling service message.
US09229791B1 System and method for high speed multiple buffer allocation
An adapter for high speed multiple buffer allocation is provided. The adapter is configured with logic to search a data buffer availability vector corresponding to data buffer storage elements from low priority to high priority and from high priority to low priority in parallel thereby enabling multiple data buffers to be located in a single path and reducing the impact of pipelining.
US09229788B2 Performing a wait operation to wait for one or more tasks to complete
A method of performing a wait operation includes creating a first plurality of tasks and a continuation task. The continuation task represents a second plurality of tasks. The continuation task and each of the tasks in the first plurality have an associated wait handle. The wait handles for the first plurality of tasks and the continuation task are stored in an array. A wait operation is performed on the array, thereby waiting for at least one of the tasks in the first and second pluralities to complete.
US09229786B2 Provisioning aggregate computational workloads and air conditioning unit configurations to optimize utility of air conditioning units and processing resources within a data center
Methods, apparatuses, and computer program products for provisioning aggregate computational workloads and air conditioning unit configurations to optimize utility of air conditioning units and processing resources within a data center are provided. Embodiments include for each air conditioning unit within the data center, determining a thermal zone generated by the air conditioning unit; for a given aggregate computational workload, identifying a plurality of computational workload configurations, each computational workload configuration indicating spatial assignments of the aggregate computational workload among a plurality of processing resources within the data center; for each computational workload configuration, calculating a total minimum energy consumption of the air conditioning units and the processing resources; and selecting the computational workload configuration with the lowest total minimum energy consumption and the determined lowest power air conditioning unit configuration corresponding with the selected computational workload configuration.
US09229784B2 Determining resource instance placement in a networked computing environment
Embodiments of the present invention provide an approach for provisioning a virtual resource instance (e.g., a server instance, etc.) in a networked computing environment (e.g., a cloud computing environment) based upon network characteristics (e.g., physical locations, email addresses/configurations, network connection types, internet protocol (IP) addresses, etc.) of a set (at least one) of intended end users of the virtual resource instance. Specifically, in a typical embodiment, the network characteristics associated with the set of intended end users will be gathered and analyzed (e.g., to determine end user location, etc.). The analysis of the network characteristics will then be used to calculate/determine relative (e.g., network) efficiency scores for each intended end user for a set of potential data centers for the virtual resource instance. The relative efficiency scores for each potential data center will be summed/totaled to yield a total (e.g., network) efficiency score for each potential data center. Thereafter, the particular data center with the highest/best total efficiency score may be selected, and the requested resource instance may be provisioned at that data center.
US09229780B2 Identifying data communications algorithms of all other tasks in a single collective operation in a distributed processing system
Topology mapping in a distributed processing system, the distributed processing system including a plurality of compute nodes, each compute node having a plurality of tasks, each task assigned a unique rank, including: assigning each task to a geometry defining the resources available to the task; selecting, from a list of possible data communications algorithms, one or more algorithms configured for the assigned geometry; and identifying, by each task to all other tasks, the selected data communications algorithms of each task in a single collective operation.
US09229779B2 Parallelizing heterogeneous network communications in smart devices based on selection of task allocation strategy
The present disclosure relates to devices, implementations and techniques for task scheduling. Specifically, task scheduling in an electronic device that has a multi-processing environment and support network interface devices.
US09229778B2 Method and system for dynamic scaling in a cloud environment
Various exemplary embodiments relate to a method and related network node including one or more of the following: determining first server dynamics associated with a first server instance, wherein the first server dynamics are indicative of a current performance of the first server instance; determining second server dynamics associated with a second server instance, wherein the second server dynamics are indicative of a current performance of the second server instance; determining, based on the first server dynamics, a current operating mode of the first server instance; determining, based on the second server dynamics, a current operating mode of the second server instance; scaling up with respect to the first server instance based on the first current operating mode indicating that the server instance is oversaturated; and scaling down with respect to the second server instance based on the second current operating mode indicating that the server instance is undersaturated.
US09229774B1 Systems and methods for performing scheduling for a cluster
Multiple scheduler verticals can allocate tasks to resources that are shared by the scheduler verticals. Information regarding a state of each resource may be stored in memory accessible by the multiple scheduler verticals, and a processor updates the information. The scheduler verticals schedule events to be performed by any of the resources, and submit updates to reflect the scheduled events in the information. In the event of conflicting events, an update corresponding to only one of the conflicting events is committed. Moreover, disruptions may be preplanned and scheduled so as to minimize impact on scheduled tasks.
US09229773B1 Determining when to perform a maintenance operation on a computing device based on status of a currently running process or application on the computing device
A method for determining when to perform an operation on a computing device is described. The computing device receives a direction to perform an operation. A deferral configuration including at least one criterion is also received. The computing device determines whether a criterion is met and defers performance of the operation if it is met. The computing device performs the operation if a criterion is not met.
US09229767B2 Processing load with normal or fast operation mode
A data processing apparatus includes a processing unit having first and second modes of operation for processing data, including receiving data packets from a sender and sending acknowledgements to the sender the second mode of operation requires more power than the first mode, and the processing unit switches between the first and second modes of operation based on a processing load; a metric module for determining a metric indicative of the processing load; an acknowledgement module for sending one acknowledgement in respect of n received data packets; and an acknowledgement configuration module for setting n to be a value m greater than a first predetermined value if the metric lies in a predetermined range that includes a value that the metric assumes when the processing unit switches between the first mode of operation and the second mode of operation, and to the first predetermined value otherwise.
US09229766B2 Mainframe virtualization
Request data is identified that describes a request of a second program by a first program intercepted by a first exit in the first program. Response data is identified that describes a response by the second program to the request as intercepted by a second exit in the first program. A virtual service configured to model operation of the second program is instantiated based on the request data and response data. In another aspect, a request by the first program to the second program is intercepted by the first exit and the request is redirected to the virtual service. A response is received as generated by the virtual service and the response is returned to the first program using the second exit.
US09229757B2 Optimizing a file system interface in a virtualized computing environment
Systems and methods for optimizing write operations to a storage device in a virtualized computing environment comprise monitoring write operations issued by an application running on a virtual machine's (VM) operating system, wherein the VM is hosted by a hypervisor providing access to a storage device in a virtualized computing environment; and causing a virtual file system (VFS) supported by the operating system to call on a first para-virtualized file system (PVFS FE) supported by the operating system to execute a write operation, in response to determining that the write operation is to write data to the storage device, wherein data that is to be written to the storage device is first written to a VM memory area allocated to the VM and accessible to the hypervisor hosting the VM.
US09229753B2 Autonomic customization of properties of a virtual appliance in a computer system
A customizer autonomically customizes a virtual appliance by retrieving customization values for various customizable properties of a virtual machine from various providers to customize the virtual appliance in order to simplify deployment of the virtual appliance. The customization properties may include CPU properties, memory properties, storage properties, network properties and properties specific to the software in the virtual appliance. The customizer allows an end user to initiate autonomic customization of the virtual appliance at various times prior to deployment of the virtual appliance. The customizer also allows the user to provide additional customization upon execution.
US09229751B2 Apparatus and method for managing virtual memory
A virtual memory management apparatus and method to execute virtual machines in a multi-processor and multi-memory environment are provided. The virtual memory management apparatus includes a virtual system memory manager configured to allocate a virtual system memory to a virtual machine. The virtual memory management apparatus further includes a virtual swap device map storage configured to store location information of virtual swap devices that are able to be allocated to the virtual machine. The virtual memory management apparatus further includes a virtual swap device manager configured to allocate a virtual swap device to the virtual machine with reference to a virtual swap device map.
关于PatentHub
关于我们 加入我们 联系我们 帮助中心
PatentHub产品
专利百科 商标查询 专利交易 大学排行榜 行业专题库
API接口 排行榜 专利资讯 最新中国发明专利 最新美国发明专利
PatentHub联系方式
QQ：3307693423 QQ：3236401158