Modular arithmetic and logic unit专利检索-算术逻辑单元中央处理器硬件计算机系统电脑零配件专利检索查询-专利查询网

Modular arithmetic and logic unit

阅读：789发布：2021-10-27

专利汇可以提供Modular arithmetic and logic unit专利检索，专利查询，专利分析的服务。并且A modular and arithmetic logic unit (ALU) for performing logic functions of AND, OR and exclusive OR and arithmetic functions of binary and decimal subtract/add where decimal subtract/add operates with both zoned decimal and decimal data formats. A pair of registers holds the two operands. The outputs of one register feed complement circuitry and the outputs of the other register together with outputs from the complement circuitry go into a subtractor and into borrow look ahead circuitry. The subtractor feeds the borrow look ahead circuitry and function control logic. The outputs from the borrow look ahead circuitry are sent back into the subtractor and one of the outputs is borrow out. The data outputs are taken from a six correct circuit having inputs from the function control logic. Control signals appropriately control the operation of the complement circuit, subtractor, borrow look ahead circuit, function control logic and the six correct circuit.，下面是Modular arithmetic and logic unit专利的具体信息内容。

权利要求

1. An arithmetic and logic unit for selectively performing arithmetic and logical operations upon a pair of operands represented in coded form comprising control means for selectively providing predetermined control signals; complement means connected to receive one of said operands and responsive to control signals from said control means to pass said one operand in true form, one''s complement form or nine''s complement form; first subtractor means operative to subtract said one operand passed by said complement means from the other of said operands; borrow look ahead means connected to receive said one operand passed by said complement means, said other operand, control signals and results from said first subtractor means to develop in parallel low and high order groups of borrow signals; and second subtractor means connected to receive said results from said first subtractor means, a control signal and said plurality of borrow signals and operative to subtract said control signal and said borrow signals from said results of said first subtractor means.

2. The arithmetic and logic unit of claim 1 wherein said first subtractor means comprises a plurality of exclusive OR circuits.

3. The arithmetic and logic unit oF claim 1 wherein said second subtractor means comprises a plurality of exclusive OR circuits.

4. The arithmetic and logic unit of claim 1 wherein one of said control signals received by said borrow look ahead means is a borrow in signal and other control signals of said control signals direct said borrow in signal to said low and high order groups of borrow signals.

5. The arithmetic and logic unit of claim 1 wherein another of said control signals received by said borrow look ahead means selectively generates a borrow out signal from said low and high order groups of borrow signals.

6. The arithmetic and logic unit of claim 5 wherein said another control signal is a zoned decimal control signal.

7. The arithmetic and logic unit of claim 4 wherein said borrow in signal is selectively directed to said high order group of borrow signals by a sign control signal.

8. The arithmetic and logic unit of claim 4 wherein said borrow in signal is constantly directed to said low order group of borrow signals.

9. The arithmetic and logic unit of claim 5 wherein the presence of said another control signal generates said borrow out signal from said low order group of borrow signals.

10. The arithmetic and logic unit of claim 5 wherein the absence of said another control signal generates said borrow out signal from said high order group of borrow signals.

11. The arithmetic and logic unit of claim 1 further comprising functional logic control means connected to receive said one operand passed by said complement means, said other operand, results from said first and second subtractor means and control signals from said control means whereby said function control means selectively passes the results of said second subtractor means or the results of logically Anding, Oring, or Exclusive Oring said one and other operands.

12. The arithmetic and logic unit of claim 1 further comprising six correct means connected to receive the results of said second subtractor means, borrow signals from said borrow look ahead means and control signals from said control means and selectively operative under control of said control signals and said borrow signals to six correct said results of said second subtractor means.

13. The arithmetic and logic unit of claim 12 wherein said six correct means selectively six corrects a low order group of results from said second subtractor means.

14. A arithmetic and logic unit of claim 12 wherein said six correct means selectively six corrects a high order group of results from said second subtractor means.

15. The arithmetic and logic unit of claim 12 wherein said six correct means further comprises logic responsive to certain of said control signals to generate a low order group of sign signals.

16. The arithmetic and logic unit of claim 12 wherein said six correct means further comprises logic responsive to certain of said control signals to generate a high order group of sign signals.

17. The arithmetic and logic unit of claim 12 wherein said six correct means further comprises logic responsive to certain of said control signals to generate a high order group of zone signals.

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Modular arithmetic and logic unit

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