Document Document Title
US09699223B2 Routing of data including multimedia between electronic devices
Rerouting apparatus for rerouting data including multimedia data. The apparatus is for association with electronic equipment and allows for routing the data to a device regarded as the most convenie t for playing the media. The apparatus comprises an announcer device for indicating to surrounding equipment that associated equipment is available for rerouting, thereby to enable receipt of rerouted communications therefrom, and a scout device for scanning surroundings of the associated equipment to find out about compatible equipment in the vicinity, thereby to reroute communications thereto. The apparatus may be attached to any device having data processing capability, to enable rerouting of data and communications therebetween.
US09699221B2 Telecommunications network emergency-call handover
Telecommunications network components configured to manage a handover of a communication session, e.g., an emergency communication session, of user equipment are described herein. A core network device may transmit respective handover queries to a plurality of anchoring network devices following a handover request from user equipment. Each anchoring network device can provide a respective indication of whether the emergency communication session is being proxied by that anchoring network device. The core network device may transmit an invitation message to an anchoring network device in response to a positive indication from that anchoring network device. An anchoring network device may store in a memory an address of the anchoring network device in association with an address of the user equipment. The core network device may retrieve from memory the address of the anchoring network device and transmit an invitation message to the anchoring network device using the retrieved address.
US09699216B2 System and method for remotely managing security and configuration of compute devices
The present invention relates to a system that manages security of one or more computer systems and/or one or more different types of I/O channels such as USB, Ethernet, SATA, and SAS. According to certain aspects, the management system is distributed. That is, a central management system and computer subsystems are physically distributed within one or more geographical areas, and communicate with each other by passing messages through a computer network. According to certain additional aspects, the configuration and/or security functions performed by methods and apparatuses according to the invention can be logically transparent to the upstream host and to the downstream device.
US09699213B2 Cost-based configuration using a context-based cloud security assurance system
A cloud infrastructure is enhanced to provide a context-based security assurance service to enable secure application deployment. The service inspects network and cloud topologies to identify potential security capabilities and needs. Preferably, these options are then surfaced to the user with easy-to-understand, pre-configured templates representing security assurance levels. When a template (e.g., representing a pre-configured assurance level) is selected by the user, the system then applies specific capabilities and controls to translate the user-selected generalized specification (e.g., “high security”) into granular requirements for a specific set of security resources. Preferably, the identification of these security resources is based on system configuration, administration, and information associated with the pre-configured template.
US09699211B2 Scalable inline behavioral DDoS attack mitigation
Methods and systems for a scalable solution to behavioral Distributed Denial of Service (DDoS) attacks targeting a network are provided. According to one embodiment, a method to determine the scaling treatment is provided for various granular layer parameters of the Open System Interconnection (OSI) model for communication systems. A hardware-based apparatus helps identify packet rates and determine packet rate thresholds through continuous and adaptive learning with multiple DDoS attack mitigation components. The system can be scaled up by stacking multiple DDoS attack mitigation components to provide protection against large scale DDoS attacks by distributing load across these stacked components.
US09699208B1 System and method for evaluating and enhancing the security level of a network system
Examples described herein provide for a system that evaluates a security level of a network system. Additionally, examples described herein evaluate a security level of a network system in order to enable a determination of components that can be used to enhance the security level of the network system.
US09699202B2 Intrusion detection to prevent impersonation attacks in computer networks
In an embodiment, a central computer performs a data processing method. The central computer receives telemetry data from intrusion sensors. The central computer stores authentication records in a hosts database. Each authentication record is based on the telemetry data and comprises a thumbprint of a public key certificate and a host identifier of a sender computer. The central computer receives a suspect record that was sent by a first intrusion sensor. The suspect record has a first particular thumbprint of a first particular public key certificate and a first particular host identifier of a suspect sender. From the hosts database, the central computer searches for a matching record having a same host identifier as the first particular host identifier of the suspect record and a same thumbprint as the first particular thumbprint of the suspect record. The central computer generates an intrusion alert when no matching record is found.
US09699201B2 Automated response to detection of threat to cloud virtual machine
An approach for responding to a threat in a networked computing environment (e.g., a cloud computing environment) is provided. In an embodiment, a set of associations to a virtual machine (VM) instance are established, each association indicating a relationship between the VM instance and a related VM instance. Each of the associations in the set of associations is assigned a strength attribute. When a threat is detected in a VM instance, a first preventative measure is performed on a first related VM instance, the strength of which is determined based on the strength attribute that corresponds to the association between the VM instance and the first related VM instance. A second preventative measure is performed on a second related VM instance, the strength of which is based on the strength attribute that corresponds to the association between the VM instance and the second related VM instance.
US09699200B2 Inline arinc data authenticity inspection module, method and computer program product
An inline ARINC data authenticity inspection module, method and computer program product are provided. In the context of a method, ARINC data that is transmitted via an ARINC bus is received into a buffer partition. The method also includes inspecting the ARINC data from the buffer partition within an inspection partition. The method further includes determining, as a result of having inspected the ARINC data within the inspection partition, whether the ARINC data is authentic. In an instance in which the ARINC data is determined to not be authentic, the method logs receipt of the ARINC data that is determined to not be authentic. However, in an instance in which the ARINC data is determined to be authentic, the method permits data corresponding to the ARINC data to be transmitted to an intended destination.
US09699199B2 Media stream trust display
Media stream trust display techniques are described in which trust information regarding content elements is accessible on an individual element basis. In particular, composite content having various content elements is rendered via a user interface of a browser or other application that supports web-based communications. Trust data is then obtained for the content elements on an individual basis in accordance with a trust model implemented by the application that facilitates retrieval of trust assertions for individual content elements. The user interface may be configured to display trust data using separate elements to represent trust data for different content elements. The display of trust data may include previews of content elements, such as thumbnail images and/or live media tiles for media streams. Additionally, a thumbnail view of a composite page/document may be provided that has selectable representations of content elements through which a user may access corresponding trust data.
US09699198B2 System and method for parallel secure content bootstrapping in content-centric networks
One embodiment of the present invention provides a system for retrieving a content collection over a network. During operation, the system determines additional information associated with the piece of content that is needed for consumption of the content collection; generates a plurality of Interests, which includes at least one Interest for a catalog of the content collection and at least one Interest for the additional information; and forwards, concurrently, the plurality of Interests, thereby facilitating parallel retrieval of the content collection and the additional information.
US09699196B1 Providing security to an enterprise via user clustering
A computer-implemented technique provides security to an enterprise. The technique involves receiving, by processing circuitry, personal information belonging to users of the enterprise. The technique further involves providing, by the processing circuitry, lists of user identifiers based on user relationships defined by the personal information. The lists of user identifiers respectively identify clusters of users of the enterprise. The technique further involves electronically imposing, by the processing circuitry, security classes on the clusters of users of the enterprise based on the lists of user identifiers. Along these lines, such classification can be used for risk assessment (e.g., authentication), alert filtering (e.g., filtering false alarms), and permission/privilege monitoring and/or assignment, among others.
US09699190B2 Method and device for the connection to a remote service
The present invention relates to the field of the connection to a secure remote service from a terminal and notably of the establishment of a connection between the secure remote service and a security device connected to the terminal. A security device including a security element is connected to the terminal via a physical or virtual local network. When trying to access a secure remote service, a software module is automatically downloaded onto the terminal, without requiring particular rights, from the secure remote service for the discovery and the interaction with the security device. In this way, it is not necessary to install drivers or other specific software in order to enable the use of the secure element when trying to access a secure remote service.
US09699184B2 Method and device for processing data
A method for processing data is suggested, and includes (i) conveying input data from a safety component to a security component, and (ii) calculating, at the security component, a second identifier based on the input data. The method further includes (iii) conveying the second identifier to the safety component, and (iv) verifying, at the safety component, a first identifier based on the second identifier.
US09699183B2 Mutual authentication of a user and service provider
Disclosed is a process for mutual authentication of a user and service provider. The process receives, at a key generation module (KGM), a notification of an event generated at a computing device. The process transmits the notification of the event to an authentication server. A third party server receives a shared secret provided by a registered user for the event. The shared secret transmitted to the KGM by the authentication server. The KGM generates a one-time key for the event. The process appends the shared secret to the one time key to generate an appended key, which is transmitted to a registered user mobile device. The process authenticates the event in response to receiving a notification from the computing device within a predetermined time period indicating the one-time key was entered at the computing device.
US09699182B2 Electrocardiogram (ECG) biometric authentication
Electrocardiogram, better known as ECG or EKG, is a method used to measure and record the electrical potential generated by the heart on the skin. ECG data is unique to a user and can be used for authentication systems such as access or financial cards or for granting access to computing devices such as mobile devices. Electrode contact on a card or device are used to received ECG data which is processed to extract features of the ECG which are compared to a template for a user.
US09699180B2 Cloud service authentication
Providing access to a cloud service includes a system receiving an application request to access a cloud service. In response, the system sends an identity provider (IP) a token request, comprising an application identifier (ID), an operating system (OS) cloud credential associated with login credentials of a user of an OS hosting the application, and a cloud service ID of the cloud service. Based on sending the token request, and on the IP authenticating the user and verifying the application ID is valid, the system receives a token from the IP. The token, which is signed with an IP signature, comprises the cloud service ID, the application ID, and a user assigned ID associated with the cloud service. The system provides the token to the application for submission to a cloud service provider for access, and obtains cloud service access based on the cloud service provider validating the IP signature.
US09699174B2 Facilitating network login
A system and method for transmitting user credentials to another device. According to some embodiments, a method is described of receiving into a first portable electronic device a set of credentials from a user, the set of credentials to include a WLAN SSID and a network key, the set of credentials to allow the first device to connect to the WLAN. The set of credentials is used to connect the first device to the WLAN. The first device creates a message for wireless transmission, the message includes the set of credentials for accessing the WLAN and is adapted to be delivered to a second device. Finally, the first device transmits the message over the air, wherein the message is addressed to the second device. The second device receives the message and uses the credentials in the message to connect to the WLAN. Other embodiments are also described.
US09699171B1 Systems and methods for logging out of cloud-based applications managed by single sign-on services
The disclosed computer-implemented method for logging out of cloud-based applications managed by single sign-on services may include (1) identifying an attempt by a single sign-on service to log a user out of a set of cloud-based applications, (2) in response to identifying the attempt to log the user out of the set of applications, tracking a logout status of each application within the set of cloud-based applications by, for each application (a) identifying a logout request sent by the single sign-on service to the application and (b) determining whether the application has sent a logout response to the single sign-on service that verifies that the user has been successfully logged out of the application, and (3) determining that the user is still logged into at least one application managed by the single sign-on service by determining that the application did not send a logout response to the single sign-on service.
US09699162B2 Personal area network
An entity may store various levels of sensitive and personal data in a secure computing environment. The entity may create permission rules which allow the data to be shared or not shared depending on the circumstances and situation. As an entity such as a human moves through life, the entity may be in touch with numerous electronic devices that act like sensors. The entity may share a token which may allow a sensor or operator of the sensor to access various levels of the sensitive data stored in the secure computing environment.
US09699161B2 Authentication mechanism
A system and method including: receiving, from a client device, an authorization request originating from an authorization module of an application executing on the client device, where the authorization request includes an identifier identifying the client device; causing transmission, based on the identifier, of a verification message to the client device, where the verification message includes a verification code; receiving a confirmation of the verification code from the authorization module of the application executing on the client device; authenticating the application based on the receiving the confirmation of the verification code; determining that the client device identified by the identifier corresponds to a user account including secure user data associated with a user; and transmitting a unique token verifying that the application is authorized to sign into the user account, where: the unique token uniquely identifies the user account to the application, and the secure user data is not shared with the application.
US09699160B2 System and methods for exchanging identity information among independent enterprises which may include person enabled correlation
A system and method for exchanging identity information and for correlating protected data across independent data systems connected through a network is disclosed. The system contains connectors in communication with protected data systems which house the protected data. Data is correlated between the protected data systems through coincident authentication of both systems by a user. Messages are exchanged which allow the identity exchange system to correlate data based on a session identifier from an authenticated session on one of the protected data systems.
US09699159B2 Methods, apparatuses and systems for providing user authentication
The methods, apparatuses and systems described herein provide a system for authenticating users, authorization or information during secure transactions. The system may include a transaction device requiring user authentication, a personal communication device, and a wearable authentication device that communicates with both of the other devices. In one aspect, the wearable authentication device may be configured to communicate with the transaction device requiring authentication and the personal communication device through one or more wireless communication technologies, wherein the wearable authentication device may be configured to act as an intermediary between the transaction device and the personal communication device to facilitate the exchange of at least one authentication information or transaction completion information between the personal communication device and the transaction device.
US09699157B2 Method and system for media cataloging for exchange in controlled facilities
In general, in one aspect, the invention relates to a method for reviewing a posting to a secure social network (SSN). The method includes receiving a first media item from a SSN member, evaluating the first media item to identify a first media attribute, and receiving a request to access the first media item from an inmate of a controlled facility. The method further includes retrieving a set of restricted attributes corresponding to the inmate, and determining whether the inmate is allowed to access the media item based on comparing the first media attribute to the set of restricted attributes. When the inmate is allowed to access the media item, granting the inmate access to the media item based on the first determination. When the inmate is not allowed to access the media item, denying the inmate access to the media item based on the first determination.
US09699155B2 Cloud aware file system
A virtual file system is described that is implemented in a virtualization platform as a stackable file system layer that intercepts file operations between a hypervisor and a physical file system. The virtual file system encrypts (at least in part) VM files to be stored, organizes the encrypted VM files into VM sets, and then maps and stores the encrypted VM sets into storage pools. Storage and access to files within the VM sets is controlled through the use of administrator-determined policies governing storage, security, access control, authentication, and auditing. The system and method described herein allow a seamless integration between a data center (e.g., a private cloud) and computing resources served across the internet and supported by cloud service providers (e.g., public clouds) while ensuring that the security needs of customers and cloud service providers are met.
US09699152B2 Sharing content with permission control using near field communication
A sending device receives a user input indicating that the user wishes to share and open item of content with a receiving device. A near field communication link is opened between the sending device and the receiving device. Metadata for sharing the open data is gathered on the sending device and a permission setting user interface display is displayed, with the user input mechanism that allows a user to set permissions corresponding to the open item. User actuation of the permission setting user input mechanism is received, the permissions are added to the open item, and the metadata is sent to the receiving device over the near field communication link. The metadata includes a location of the open item. The open item can then be accessed by the receiving device, with the permissions applied to the open item.
US09699151B2 Manage encrypted network traffic using spoofed addresses
Methods and systems for managing encrypted network traffic using spoofed addresses. One example method includes receiving a request to resolve a domain name; determining that the domain name is included in a predetermined set of domain names; associating a spoofed address with the domain name; sending a response to the request to resolve the domain name, the response including the spoofed address; receiving a secure request for a resource, the secure request directed to the spoofed address; determining that the secure request is directed to the domain name based on the association between the spoofed address and the domain name; and selectively decrypting the secure request based at least in part on determining that the secure request is directed to the domain name.
US09699148B2 Moving a portion of a streaming application to a public cloud based on sensitive data
A streams manager determines which portions of a streaming application process sensitive data, and when performance of the streaming application needs to be increased, selects based on the sensitive data which portion(s) of the streaming application can be moved to a public cloud. The streams manager then interacts with the public cloud manager to move the selected portion(s) of the streaming application to the public cloud. This may include cloning of processing elements or operators to a public cloud, then splitting tuple attributes so tuple attributes that do not include sensitive data can be processed in the public cloud while tuple attributes that include sensitive data are processed in a secure system. The tuple attributes are then recombined into full tuples in the secure system. The streams manager thus protects the integrity of sensitive data while still taking advantage of the additional resources available in a public cloud.
US09699137B2 Naming of cloud components
Examples disclosed herein relate to naming of cloud components. The examples enable generating, for a first node of a cloud infrastructure comprising a plurality of nodes, a first node name associated with a first fixed Internet Protocol (IP) address that is assigned to the first node, the first node name identifying the cloud infrastructure and a first control plane to which the first node belongs; generating, for a second node of the cloud infrastructure, a second node name associated with a second fixed IP address that is assigned to the second node, the second node name identifying the cloud infrastructure and a second control plane to which the second node belongs; and causing information related to the cloud infrastructure to be published to the plurality of nodes of the cloud infrastructure, the information related to the cloud infrastructure comprising the first node name and the second node name.
US09699136B2 Stateless autoconfiguration of hostnames of network devices
Techniques are disclosed for dynamically determining or learning hostnames. According to embodiments described herein, a solicitation message is received at a first network device. Based on the solicitation message, a hostname is determined for a second network device that sent the solicitation message. A first network address is also determined for the second network device that sent the solicitation message. A mapping between the hostname and the first network address is stored at the first network device.
US09699128B1 Automated generation of prompts and analyses of user responses to the prompts to determine an entity for an action and perform one or more computing actions related to the action and the entity
Methods and apparatus directed to utilizing an automated messaging system to engage in a dialog with at least one user, via a computing device of the user, to determine a particular service entity for an action. In some implementations, the automated messaging system may generate a plurality of questions and/or other prompts to solicit user interface input from the user(s) for use in determining the particular service entity and/or in determining one or more criteria for the action. Some implementations are further directed to performing one or more computing actions based on the determined service entity and optionally based on one or more criteria for the action determined via user interface input of the dialog.
US09699127B2 System and method for sending, delivery and receiving of digital content
Embodiments of a content delivery system are disclosed herein. In particular, an embodiment of a content delivery system may receive content associated with a first destination identifier associated with a first delivery method, determine a second destination identifier and a second delivery method associated with the first delivery destination, and deliver the content to the second destination identifier according to the second delivery method.
US09699124B2 On-demand robot acquisition of communication features
Methods, devices, and systems are provided that determine required communications features to be used in a communication session and provide participants of the communication session with an identification of the required communications features. When a communication device used by the participant does not include one of the required communications features, the user is provided access to those features, based on compatibility. When a communication device is found to be compatible, the communication device accesses the features by running communications applications having the required communications features.
US09699118B2 System for flexible dynamic reassignment of throughput
A network switch including a set of communication ports is provided. The communication ports may have an allocated prebuffer to store data during packet switching operations. The network switch may further include a calendar associated with the set of communication ports that provides bandwidth configuration for the set of communication ports. The network switch may further include a secondary calendar that may be dynamically setup. The secondary calendar may provide an alternative bandwidth configuration strategy for the set of communication ports. The switch includes circuitry that may increase the prebuffer size and upon the successful increase of the prebuffer size reconfigure the set of communication ports from the original calendar to the secondary calendar, without a reboot. The circuitry may reset the prebuffer size after reconfiguration is complete and the switch may continue operation according to the reconfigured settings.
US09699116B2 SDN based interdomain and intradomain traffic engineering
A method is implemented by a centralized control plane device for a software defined networking (SDN) network. The method performs joint inter-domain and intra-domain traffic engineering as a single optimization process with location varying objectives. The method includes generating a joint representation of interdomain and intradomain traffic demand with spatial differentiation where each domain can have individually defined optimization objectives. The method further includes determining a set of candidate paths for each source-destination pairs (SD) in the SDN network using the joint representation, selecting a candidate path from the set of candidate paths for each SD pair in the SDN network, and programming a set of switches in the data plane of the SDN network to forward the data traffic according to the selected candidate path.
US09699115B2 Bus network having a safety gate of a substantial safety isolation type
The present invention relate to a bus network having a safety gate of a substantial safety isolation type. The bus network comprises a first region, a second region, and signal isolators. The first region has disposed therein a first bus and has distributed therein one or more first processing devices, one or more first transceivers, one or more first controllers, and one or more gateways. The second region has disposed therein a second bus and has distributed therein one or more second processing devices and one or more second transceivers. The signal isolators are disposed between the first region and the second region. An isolation device driving terminal and an output terminal on one side of the signal isolator are respectively connected to a transmitting terminal and a receiving terminal of a second controller. An output terminal and an isolation device driving terminal on the other side of the signal isolator are respectively connected to a transmitting terminal and a receiving terminal of a second transceiver.
US09699112B2 Efficient allocation of network resources
Using information for efficient allocation of network resources, such as for a communication session, is disclosed. The methods and systems can utilize one or more identifiers that can be configured to indicate the presence of one or more supported features, along with an indication of whether the supported feature is required for communication.
US09699111B2 Control of supplemental content in a data flow
Systems and methods for the control of supplemental content in a data flow are provided such that supplemental content, such as advertising content, may be handled separately from other content in the data flow. One embodiment comprises a network element of a Packet-Switched (PS) network that serves mobile User Equipment (UE). The network element receives a data flow of packets for a download of content requested by the UE, identifies in the data flow supplemental content that was not requested by the UE, makes a determination concerning transmission of the supplemental content, and transmits at least a portion of the data flow based on the determination. For example, a repetition frequency limit, a temporal limitation, or a repetition frequency limit and corresponding temporal limitation can be utilized to control transmission of the supplemental content. The supplemental content also can be charged separately from other content of the data flow.
US09699108B2 Peer-assisted deployment of resources in a network
In particular embodiments, a server computing device receives one or more inputs specifying a software module and one or more portions of a network. Each of the portions of the network includes multiple client devices. For each of the client devices in a portion of the network, the server computing device determines whether the client device meets one or more criteria. For at least one portion of the network having a client device meeting the one or more criteria, the server computing device selects the client device as a master device and provides the software module to the master device. The master device is operable to download the software module from one or more server computing devices, provide the software module to the other client devices in the portion of the network, and provide status information to the server computing device.
US09699105B2 Self-routing multicast in a software defined network fabric
Methods and systems presented herein provide for self-routing multicast. In one embodiment, a method includes receiving, using a switch controller, a multicast data stream join request from a source in a network, and creating, using the switch controller, a multipath identifier (ID) for a multicast data stream. Moreover, the method includes creating, using the switch controller, path identifiers (IDs) for intermediate switches in the network based on a local network topology database. Each path ID is associated with an output port bitmap. The method also includes transmitting, using the switch controller, the multipath ID and a path ID to a source of the multicast data stream, the path ID corresponding to the source of the multicast join request. Also, the multipath ID and the path ID are configured to allow the source of the multicast data stream to determine an output port mapping for a packet.
US09699104B2 Deterministic distributed network coding
A network and a communication method are described. The network comprises: source nodes, receiver nodes, and coding nodes. The coding nodes are connected with input links for communication of input signals to the coding nodes and output links for communication of output signals from the coding nodes. The output signals are a linear combination of the input signals. The coefficients of the linear combination are deterministically chosen based on local information available locally at the coding node.
US09699103B2 Method and system for flow controlling
Content delivery to end user devices (EUD) is controlled by transmitting content portions at a controlled flow. The time for the EUD to process the data is used to control the flow. The first portion is transmitted to the EUD and the amount of time to process the first portion is noted. Threshold values to stop and start transmissions are examined prior to the transmission of each content portion. If the amount of data remaining to be processed by the EUD is below the stop transmission threshold, transmission continues with the next portion. If the amount of data remaining to be processed by the EUD is above the stop threshold, transmission is either stopped or retarded. When it is determined that the amount of data remaining to be processed by the EUD is above the start transmission threshold, transmission is started or continued.
US09699099B2 Method of transmitting data in a communication system
A method of transmitting image data from a first node to a second node during a communication event, wherein the second node comprises a display for displaying image data at the second node, includes receiving at the first node, information indicating at least one display characteristic with which image data received at the second node will be displayed on the display; inputting image data at the first node; determining a processing step to be applied to the inputted image data to generate adapted image data, such that at least one characteristic of the adapted image data is optimized for the at least one display characteristic; applying the processing step to generate the adapted image data; and transmitting the adapted image data to the second terminal.
US09699096B2 Priority-based routing
Disclosed herein is a router configured for priority-based routing. The router is configured to receive a plurality of packets, wherein each packet is assigned a priority value. The router includes an output circuit configured to select the packet with the highest priority value. The output circuit is configured to forward the priority value of the selected packet to a second router. The output circuit is configured to transfer the selected packet to the second router when the link between the first router and the second router is available.
US09699083B2 Frame search processing apparatus and method
A frame search processing apparatus includes a frame information extraction unit (1) that extracts frame information from an input frame, a search processing unit (2) that compares the frame information with entry information, and a frame information output control unit (3) that controls output of the frame information to the search processing unit (2). The search processing unit (2) includes a plurality of comparison units that read out N pieces of entry information from a search table, and perform comparison between the entry information and the frame information at once. The frame information output control unit (3) includes a frame information buffer that accumulates the frame information, and an output processing unit that, when triggered by a predetermined accumulation count of the frame information or an elapse of a predetermined accumulation time of the frame information, distributes a plurality of pieces of frame information accumulated in the frame information buffer to the comparison units of the search processing unit (2) one by one.
US09699078B1 Multi-planed unified switching topologies
An apparatus and method for extending the scalability and improving the partitionability of networks that contain all-to-all links for transporting packet traffic from a source endpoint to a destination endpoint with low per-endpoint (per-server) cost and a small number of hops. An all-to-all wiring in the baseline topology is decomposed into smaller all-to-all components in which each smaller all-to-all connection is replaced with star topology by using global switches. Stacking multiple copies of the star topology baseline network creates a multi-planed switching topology for transporting packet traffic. Point-to-point unified stacking method using global switch wiring methods connects multiple planes of a baseline topology by using the global switches to create a large network size with a low number of hops, i.e., low network latency. Grouped unified stacking method increases the scalability (network size) of a stacked topology.
US09699077B2 Method for determining a packet forwarding path, network device, and control device
The application provides a method for determining a packet forwarding path, a network device acquires device information of the network device and interface information of the network device, so that the network device can send the device information of the network device and the interface information of the network device to a control device by using an IGP, so that the control device determines a packet forwarding path from the network device to the control device according to the device information of the network device and the interface information of the network device. Each network device that sends device information and interface information of the network device by using an IGP does not need to compute a packet forwarding path from the network device to a corresponding control device; therefore, decreasing a processing burden of the network device.
US09699075B2 Repair of failed network routing arcs using data plane protocol
A network includes routing arcs for routing network traffic to a destination. Each arc comprising nodes connected in sequence by reversible links oriented to direct network traffic to first and second edge nodes through which the network traffic exits the arc. The nodes in the arc detect a first failure. In response, the nodes exchange first management frames to reverse links in the arc so that the network traffic in the arc is directed away from the first failure toward the first edge node of the arc through which the network traffic exits the arc. The nodes detect a second failure in the arc that is spaced apart from the first failure. In response, the nodes exchange second management frames to freeze incoming edges of parent arcs to prevent network traffic in the corresponding parent arc from entering the arc.
US09699074B2 Efficient utilization of transceivers for shared restoration in flexible grid optical networks
Optical transceiver sharing methods may be based on different ROADM node architectures for shared restoration in flexible grid optical networks. A ROADM node architecture with a pool of transceivers may improve transceiver utilization for backup optical paths, compared to a conventional ROADM node architecture. Sharing of transceivers in the pool for working and backup optical paths may further improve transceiver utilization. The methods disclosed herein may be used for multiple bit rates and different modulation formats.
US09699072B2 Packet handling in information centric networking networks
A method of packet handling in an information centric networking (ICN) network is provided. The method may include receiving an interest packet at an incoming interface of a network device. The interest packet may include a pending interest table (PIT) update indicator. After a determination that the PIT update indicator signifies aggregation, the method may include adding the incoming interface to a PIT entry associated with the interest packet. The method may also include determining whether the outgoing interface is in a set of requesting interfaces of the PIT entry. After a determination that the outgoing interface is in the set of requesting interfaces, the method may include removing the outgoing interface from the PIT entry and updating the PIT update indicator based on the PIT entry.
US09699069B1 Systems and methods for optimizing application data delivery over third party networks
Aspects of the present disclosure generally relate to systems and methods for managing and optimizing end-to-end communication sessions involving the delivery of application data (e.g., audio data, audio/video data, electronic file download data, etc.) over third party networks using an optimized communication system (OCS), as described herein. Embodiments of the disclosed system enable optimal quality (e.g., reduced delay, packet loss, jitter, etc.) of communication sessions. In one example, the system provides a real-time or close to real-time evaluation of network conditions, e.g., network congestion, nodes best-suited for application data transfer, etc., and other factors associated with geographically diverse and unpredictable routing infrastructure characteristics of the Internet to enable optimized communication sessions.
US09699068B1 Distributing routing updates according to a decay mode
Techniques and solutions for distributing routing updates using timing information are described. For example, inter-device messaging protocols can support timing information (e.g., routing protocols be extended to support timing information). The timing information can indicate a time at which the routing update is to be put into effect where the time decreases the further away a given routing device is from the source of the routing update. For example, each routing device can determine a decayed update reference time when the given routing device will put the routing update into effect according to a decay mode. Routing updates can be managed between routing devices that support timing information and routing devices that do not support timing information.
US09699062B2 Performance measurement of a link of a packet-switched communication network
A method for performing a performance measurement of a link between two nodes of a communication network. Before starting a measurement, measurement mode information including start time and packet transmission rate are provided to both nodes. At the start time, a first node generates and transmits to the other node a packet flow including packets with transmission times determined by the start time and packet transmission rate. The packet flow is divided into alternating blocks transmitted during even and odd block periods. At each block period, while the packet flow is received, a variable indicative of its behavior is updated by using the measurement mode information and detected information on reception of the packet flow. Then, a parameter indicative of a performance of the packet flow during the block period is calculated using the value reached by the variable at the end of the block period.
US09699049B2 Predictive model for anomaly detection and feedback-based scheduling
In an example embodiment, clusters of nodes in a network are monitored. Then the monitored data may be stored in an open time-series database. Data from the open time-series database is collected and labeled it as training data. Then a model is built through machine learning using the training data. Additional data is retrieved from the open time-series database. The additional data is left as unlabeled. Anomalies in the unlabeled data are computed using the model, producing prediction outcomes and metrics. Finally, the prediction outcomes and the network.
US09699047B2 Communication device, control method for communication device, and program
A communication device capable of handling, even in the case where requests for provision of a service are received from a plurality of devices, the requests appropriately, is provided.A communication device which provides a service to a service utilizing device which utilizes a service, determines whether or not the communication device is executing a service requested from the service utilizing device. In the case where it is determined that the communication device is executing the service, the communication device makes a response to the request with the contents of the response changed according to whether or not the service is able to be provided to a plurality of service utilizing devices.
US09699041B2 Link cost determination for network links
A link cost determining method including computing, by a station, a new composite data rate using a set of data rates including an average data rate, a geometric mean data rate, and a minimum data rate for data samples, computing, by the station, a pair of hysteresis thresholds for a previous composite data rate, determining, by the station, whether the new composite data rate exceeds one of the pair of hysteresis thresholds, and advertising, by the station, the new composite data rate when the new composite data rate exceeds one of the pair of hysteresis thresholds.
US09699038B2 Node and method for service usage reporting and quota establishment
Example embodiments presented herein are directed towards a Packet Domain Network Gateway (PGW), and corresponding methods therein, for service usage reporting and quota management in a Policy and Charging Control (PCC) based network. Example embodiments presented herein are also directed towards an Online Charging System (OCS) for receiving service usage reporting and quota management in a PCC based network. Quota reporting and quota management is performed on a pre-rating group basis.
US09699035B1 Topology determination for an optical network
Techniques are described for determining the topology of an optical network. A computing device receives a message on a data communication network after a first device in an optical network receives an optical pulse pattern on an optical fiber in the optical network. The computing device generates topology data using the message. The topology data indicates that a second device is physically connected in the optical network to the first device when the received optical pulse pattern matches an optical pulse pattern sent by the second device.
US09699032B2 Storage area network queue depth profiler
A system for improving performance of a network includes a monitor that obtains data sets corresponding to network performance, infers characteristics from the data set and generates visualizations and recommendations. In one aspect, the network is a storage area network and the system generates a box plot showing response time based on inferred queue depth, and recommending a queue depth setting if possible.
US09699029B2 Distributed configuration management in a switch group
One embodiment of the present invention provides a switch. The switch includes a switch group module, a persistent storage module, and a distributed configuration management module. The switch group module maintains a membership in a switch group. The switch group includes a plurality of switches and operates as a single switch. The persistent storage module stores configuration information associated with the switch group in a table, which includes one or more columns for attribute values of the configuration information, in a local persistent storage. The distributed configuration management module verifies whether the configuration information is eligible for a distributed commit to the switch group. If the configuration information is eligible for the distributed commit, the distributed configuration management module commits the configuration information to the persistent storage and switch modules of the switch.
US09699025B2 System and method for managing multiple server node clusters using a hierarchical configuration data structure
A system and method are described for managing a plurality of sever nodes. In one embodiment, the sever nodes are organized into groups referred to as “instances.” Each instance includes a group of redundant sever nodes and a dispatcher for distributing service requests to each of the sever nodes. In addition, a central message passing architecture is defined which allows the various instances to communicate with one another. In one embodiment, a hierarchical configuration data object is stored within a database and is centrally accessible by all of the servers from all of the instances. The hierarchical configuration data object organizes configuration data and binary data in a logical hierarchy which simplifies sever node management in an enterprise network.
US09699024B2 Distribution of applications over a dispersed network
Disclosed are various embodiments for facilitating anticipatory distribution of applications to a network of remote hosts. A demand for each of the applications is calculated. Based on criteria within the demand and computing resources available, remote hosts are selected to receive the applications. Transmissions of the applications to the selected remote hosts are scheduled and monitored for completion according to the schedule.
US09699021B2 Ring protection state aware bandwidth adaptation
For performing link adaptation in an Ethernet ring protection system, a link management controller (180) determines a ring protection state of an Ethernet protection ring. Further, the link management controller (180) adapts bandwidth of a link (25) of the Ethernet protection ring. Depending on the adapted bandwidth and the determined ring protection state, the link management controller (180) deactivates the link of the Ethernet protection ring. In particular, if the adapted bandwidth is below a threshold value and the ring protection state indicates that there is no link failure in the Ethernet protection ring, the link management controller (180) may deactivate the link (25).
US09699019B2 Related content display associated with browsing
One or more techniques and/or systems are provided for displaying related content associated with browsing a website. For example, a user may access a website to view content provided by the website. As opposed to the user manually searching for interesting content through trial and error, related content that may be interesting to the user may be identified and surfaced to the user. For example, a user profile specifying user interests of the user may be used to identify related content assigned topics corresponding to the user interests (e.g., content provided by the website or other web source). In this way, the related content may be displayed to the user through a content recommendation reader interface. In an example, the content recommendation reader interface may be provided by a web browser so that related content may be identified and/or provided to users of any website from any device.
US09699018B2 Communication terminal, communication management system, communication management method, and recording medium storing communication management program
A communication terminal reads, from a removable memory, user-specific application information indicating one or more of the plurality of applications that are allowed for use by a specific user, and transmits a request for address information that includes application identification information of each one of one or more applications that are allowed for use by the specific user at the communication terminal to obtain address information associated with the application identification information.
US09699017B1 Dynamic utilization of bandwidth for a quorum-based distributed storage system
A storage client and a quorum-based distributed storage system may implement dynamic utilization of bandwidth for a quorum-based distributed storage system. An update at a storage client may be received, and storage nodes of a protection group may be sent a write request indicating the update. In some embodiment, storage nodes that receive the write request may determine whether other storage nodes have not received the update and send the write request to be completed at those other storage nodes. In some embodiments, if a latency threshold is exceeded other storage nodes in the protection group not previously sent the write request may be identified and sent the write request. Based on acknowledgements received from storage nodes in the distributed storage system, it may be determined whether a write quorum requirement is met for a write request.
US09699016B2 Sign-in method and system
Disclosed are a sign-in method and system. The method includes: obtaining, by using a location-based service (LBS) of a mobile terminal, geographical information of a current location of a person who signs in; binding the geographical information of the current location with identity information of the person who signs in and time information, using the geographical information of the current location, the identity information of the person who signs in, and the time information as sign-in information, and sending the sign-in information to a sign-in server; verifying, by the sign-in server, the sent sign-in information; and recording the sign-in information if the verification succeeds. The present disclosure not only can save costs of labor, material, and money, but also can enable several people to sign in simultaneously, thereby greatly improving sign-in efficiency.
US09699011B1 Continuous phase modulation signaling
A device includes a frequency offset (FO) estimation circuit and a frequency offset compensation circuit coupled with the frequency offset estimation circuit. The frequency offset compensation circuit is configured to (i) receive a continuous phase modulation (CPM) signal, (ii) receive, from the FO estimation circuit, an uncompensated frequency offset for a wth sampling window of the CPM signal, (iii) generate a frequency offset compensation value for a w+1st sampling window of the CPM signal based on the uncompensated frequency offset for the wth sampling window, (iv) adjust the CPM signal in the w+1st sampling window based on the frequency offset compensation value, and (v) provide the adjusted CPM signal to a filter.
US09699010B2 Wireless communication apparatus
A wireless communication apparatus includes a generating unit, a detecting unit, and a suppressing unit. The generating unit generates, using signals at multiple carrier frequencies that are different from each other, a replica signal for passive inter modulation distortion that occurs in a reception signal from a terminal due to the transmission of a multicarrier signal that includes the signals at the multiple carrier frequencies. The detecting unit detects the correlation value between the replica signal for the passive inter modulation distortion and the reception signal. The suppressing unit suppresses the peak of the multicarrier signal when the correlation value is equal to or more than the threshold.
US09699008B2 Method and apparatus for transmitting signal using sliding-window superposition coding in wireless network
The present disclosure relates to a pre-5th-Generation (5G) or 5G communication system for supporting higher data rates beyond 4th-Generation (4G) communication system such as Long Term Evolution (LTE). A performance of the existing sliding-window superposition coding (SWSC) is degraded when a wireless channel state is changed due to a large scale fading and a small scale fading. In addition, the performance of the existing SWSC is degraded when channel state information at a receiver is different from that of the real channel. To resolve these problems, a transmitter applies an accurate data transmission rate suitable for a channel state. Therefore, a receiver applies an adaptive SWSC and to reduce a block error rate (BLER) and a hybrid automatic repeat request (HARQ) overhead of the receiver. In addition, to resolve wireless channel state change due to large and small scale fading, the transmitter may use the adaptive transmission method.
US09699004B2 Barcode reading system including a sled reader and relay application
The present disclosure provides a relay application configured to send decoded barcode image data to an intermediary device as text via a TCP/IP connection. The relay application is executed by a processor of a mobile device that is in communication with the barcode sled reader. The barcode sled reader includes a barcode reader that generates image data of a barcode and a decoding processor that decodes the image data.
US09699002B1 Electronic receipt for purchase order
The web-enabled system provides an electronic document exchange environment where transactional information is received by the system in one format, translated to a second format, and sent. The system allows its users to bypass the costs involved in owning or accessing an EDI translator or a value-added network and generates and sends an electronic receipt for auditing purposes. In addition to the translation of information, the system creates the functional acknowledgment message (the electronic receipt), associates it with the transactional information, and sends it to the intended recipient. The functional acknowledgement message is then returned to the system by that recipient. The system may translate the functional acknowledgement to the first format or may not. Once received, the system then sends the acknowledgement to the original provider of the transactional information. This loop allows the originator to determine whether its transactional information was received.
US09699001B2 Scalable and segregated network virtualization
One embodiment of the present invention provides a switch. The switch includes a virtual network module and a forwarding module. The virtual network module includes a global virtual local area network (VLAN) tag in a packet. The global VLAN tag is mapped to an edge VLAN tag in the packet and is associated with a datacenter domain. The datacenter domain indicates a set of ports associated with a datacenter. The forwarding module identifies an egress edge port for the packet based on the global VLAN tag.
US09698999B2 Natural language control of secondary device
Natural language controlled devices may be configured to activate command recognition in response to one or more wake words. Techniques are provided to enable a voice controlled system to detect or receive an indication of a secondary device available to be controlled. The voice controlled system communicates with the secondary device to obtain information related to the secondary device. The voice controlled system may output of an audio query requesting audio input data related to controlling the secondary device from a user and generate, based on the requested audio input data, recognition data utilized to recognize of at least part of one or more commands to issue one or more controls to the secondary device.
US09698998B2 Apparatus and method for playing contents in home network system
Provided is a method and apparatus for controlling home devices forming a home network at a time by using a mobile terminal in a home network system. In particular, the present disclosure provides a method and apparatus for controlling home devices at a time, depending on a type of contents. A method for playing contents in a Home GateWay (HGW) in a home network system includes receiving from a mobile terminal a control command requesting continuous playback of contents that are currently played in the mobile terminal and controlling at least one home devices in response to the control command.
US09698997B2 Apparatus and method pertaining to the communication of information regarding appliances that utilize differing communications protocol
An end-user device can aggregate information as pertains to a variety of appliances that otherwise utilize incompatible communication protocols to present a shared opportunity to accommodate current information regarding those appliances. This information can include status information regarding such appliances as well as, or in lieu of, instructions to be acted upon by those appliances. Gateways can serve to provide a communications interface between such appliances and, for example, an internet. By one approach one or more middleware platform intermediaries can interface between one or more of those gateways and the end-user device.
US09698996B2 Information acquisition using a scalable wireless geocast protocol
Information is acquired from a geographically-distributed sensor network using a scalable wireless geocast protocol. Geographically distributed networks of unattended sensors are placed at desired locations to collect various types of information, such as, for example, environmental parameters, temperature, humidity, rainfall, heat signatures, video, audio, seismic activity, and/or wind conditions. To acquire information, a query is provided to the geographic area at which the sensors are located utilizing the geocast protocol. Delivery of the query is based on a physical location of a region in which a sensor network is located, the type of information being queried, and/or temporal conditions. Each sensor that receives a query determines if all requirements/conditions are satisfied. If so, the query is accepted and processed by the recipient sensor, and responded to accordingly. Responses to queries are provided via the geocast protocol.
US09698993B2 Hashing prefix-free values in a signature scheme
Methods, systems, and computer programs for producing hash values are disclosed. A prefix-free value is obtained based on input data. The prefix-free value can be based on an implicit certificate, a message to be signed, a message to be verified, or other suitable information. A hash value is obtained by applying a hash function to the prefix-free value. The hash value is used in a cryptographic scheme. In some instances, a public key or a private key is generated based on the hash value. In some instances, a digital signature is generated based on the hash value, or a digital signature is verified based on the hash value, as appropriate.
US09698992B2 Method for signing electronic documents with an analog-digital signature with additional verification
There is disclosed a method of signing an electronic document. The method comprises: receiving via an encrypted connection a signature generation request file; receiving the AD information (such as dynamic autographic signature of the user) associated with a user. The method further comprises generating a first control sum based on the electronic document and a second control sum based on the AD information. The method further comprises generating a single numeric sequence based on the first and second control sums and encrypting the single numeric sequence using the private key to generate a digital signature. The method further comprises generating a final signature confirmation file including a hyperlink to the electronic document to be signed and to the AD information associated with the user; and transmitting, to the electronic address associated with the user, a file containing the digital signature, only in response to a conformation response from the user.
US09698991B2 Systems, methods and apparatuses for device attestation based on speed of computation
The systems, methods and apparatuses described herein provide a computing device that is configured to attest itself to a communication partner. In one aspect, the computing device may comprise a communication port configured to receive an attestation request from the communication partner, and an application-specific integrated circuit (ASIC). The ASIC may be configured to receive the attestation request, which may include a nonce. The ASIC may be further configured to generate a verification value, capture data representing a state of computation of the ASIC when the verification value is being generated, and send the verification value and captured data to the communication port to be transmitted back to the communication partner. The verification value may be a computation result of a predefined function taking the nonce as an initial value. In another aspect, the communication partner may be configured to attest the computing device using speed of computation attestation.
US09698989B2 Feature licensing in a secure processing environment
Embodiments of an invention for feature licensing in a secure processing environment are disclosed. In one embodiment, a processor includes an instruction unit and an execution unit. The instruction unit is to receive an instruction to initialize a secure enclave. The execution unit is to execute the instruction. Execution of the instruction includes determining whether a requested feature is licensed for use in the secure enclave.
US09698987B2 Server algorithms to improve space based authentication
A system and methods for location authentication are presented. An estimated server signal is estimated based on a generated known code signal, and a client received satellite signal is received from a client device. The client received satellite signal is compared to the estimated server signal to provide a comparison result.
US09698982B2 Bluesalt security
Embodiments of the present invention disclose a method, system, and computer program product for bluesalt security. A computer receives a confidential data configuration wherein specific sensor are assigned to specific confidential information. The assigned sensors are measured for values as a system administrator enters a password corresponding to the confidential information. The measured values are converted into a salt and concatenated with the password to generate a primary key. The primary key is used to encrypt the confidential information, then the primary key is encrypted using a secondary key comprised of a second password with a second set of sensor information as the salt. The encrypted key is saved securely while the secondary key is destroyed. In order to decrypt the confidential information, a user must replicate the password and sensor values to generate the primary or secondary key.
US09698980B2 One-way key fob and vehicle pairing verification, retention, and revocation
Embodiments of the invention provide methods for key fob to control unit verification, retention, and revocation. After an initial pairing between a key fob and a control unit, the devices share a secret operation key (OpKey). For verification, the key fob sends the 8 lowest-order bits of a 128-bit counter and some bits of an AES-128, OpKey encrypted value of the counter to the control unit. For key revocation and retention, the control unit is prompted to enter an OpKey retention and revocation mode. Subsequently, each of the remaining or new key fobs is prompted by the user to send a verification message to the control unit. When the control unit is prompted to exit the OpKey retention and revocation mode, it retains the OpKeys of only the key fobs that sent a valid verification message immediately before entering and exiting the OpKey retention and revocation mode.
US09698973B2 Securing accessible systems using dynamic data mangling
Systems and techniques for securing accessible computer-executable program code and systems are provided. One or more base functions may be generated and blended with existing program code, such that it may be difficult or impossible for a potential attacker to distinguish the base functions from the existing code. The systems and code also may be protected using a variety of other blending and protection techniques, such as fractures, variable dependent coding, dynamic data mangling, and cross-linking, which may be used individually or in combination, and/or may be blended with the base functions.
US09698972B2 Voltage mode drivers and electronic apparatus having the same
Voltage mode drivers and an electronic apparatus having the same are provided. The voltage mode drivers may include a voltage regulator and a ripple compensation unit connected to an output terminal of the voltage regulator and configured to compare a current data bit of a data pattern with a previous data bit of the data pattern in synchronization with a clock signal input into the ripple compensation unit, generate a control signal when the current data bit is equal to the previous data bit, and apply a ground voltage to the output terminal in response to the control signal.
US09698971B2 Digital filter circuit, reception circuit, and semiconductor integrated circuit
A phase to digital converter determines whether a phase of an internal clock advances or delays with respect to an input serial signal and outputs a first determination code, a determination circuit outputs, for each of first periods, a second determination code based on a plurality of the first determination codes, a gain control code generator circuit generates a gain control code based on a total sum of the first determination codes during the first period, and a phase adjustment code generator circuit gives a gain in accordance with the gain control code to the second determination code, and generates and outputs a phase adjustment code so that the phase of the internal clock is adjusted to make the phase of the internal clock follow the input serial signal.
US09698963B2 Method and apparatus for scheduling user equipment on full-duplex cellular network
The present invention discloses a method for scheduling user equipment on a full-duplex cellular network, including: determining a pairing set for each piece of user equipment in a cell, where a pairing parameter of the piece of user equipment and any piece of user equipment that is in the pairing set of the piece of user equipment meets a preset threshold; and selecting, when a piece of user equipment is scheduled to perform data transmission, another piece of user equipment from a pairing set of the piece of user equipment to perform data transmission in an opposite direction. Embodiments of the present invention further provide a corresponding apparatus. According to the technical solution of the present invention, existing spectrum resources can be utilized more thoroughly and spectrum utilization efficiency of wireless access can be improved.
US09698956B2 Mobile station aggregation of acknowledgments and negative acknowledgments in wireless networks
Various example embodiments are disclosed herein. According to one example embodiment, a method may include determining, at a base station in a wireless network, an uplink channel quality for a mobile station, sending an acknowledgment/negative acknowledgment (ACK/NAK) aggregation indicator to the mobile station based on the determining, sending a plurality of data bursts to the mobile station, and receiving at least one aggregated ACK/NAK report from the mobile station.
US09698954B2 Multiplexing demodulation reference signals in wireless communications
Methods and apparatuses are provided for determining cyclic shift (CS) values and/or orthogonal cover codes (OCC) for a plurality of demodulation reference signals (DM-RS) transmitted over multiple layers in multiple-input multiple-output (MIMO) communications. A CS index can be received from a base station in downlink control information (DCI) or similar signaling. Based at least in part on the CS index, CS values for the plurality of DM-RS can be determined. In addition, OCC can be explicitly signaled or similarly determined from the CS index and/or a configured CS value received from a higher layer. In addition, controlling assignment of CS indices and/or OCC can facilitate providing orthogonality for communications from paired devices in multiuser MIMO.
US09698953B2 Method and apparatus for signal transmission in wireless communication system
Provided are a method and an apparatus for signal transmission in a wireless communication system. The apparatus comprises: an information processor for generating a first information sequence based on a first transmission symbol and a first resource index, and a second information sequence based on a second transmission symbol and a second resource index; a reference signal generator for generating a different reference signal depending upon whether a first resource block indicated by the first resource index and a second resource block indicated by the second resource index are the same; and an antenna for transmitting a signal generated based on the first information sequence, the second information sequence, and the reference signal sequence.
US09698951B2 Method and apparatus for transmitting/receiving channel state information in wireless communication system
The present invention relates to a wireless communication system. A method for user equipment transmitting channel state information (CSI) in the wireless communication system, according to the present invention, comprises the steps of: receiving information on an N number of CSI configurations for reporting the CSI; receiving information for selecting an M (2≦M≦N) number of the CSI configurations for joint CSI from the N number of the CSI configurations; calculating the M number of rank indexes (RI) based on each channel corresponding to the M number of CSI configurations; calculating a joint RI based on a synthetic channel generated by synthesizing the channels corresponding to the M number of the CSI configurations; and transmitting information on whether to report the joint CSI based on a result from comparing the M number of the RIs and the joint RI.
US09698949B2 Method of handling device-to-device signal and device-to-cellular signal and related communication device
A method of handling a device-to-device (D2D) signal and a device-to-cellular (D2C) signal for a first communication device comprises communicating with a second communication device according to a D2D communication; communicating with a network according to a D2C communication; and transmitting one of the D2D signal and the D2C signal in a subframe, wherein the D2D signal and the D2C signal are transmitted to the second communication device and the network, respectively.
US09698947B2 Transmission method
In a WLAN, a device sets a first NAV to a bandwidth used by a signal from a second device. The device selects a channel that does not correspond to the bandwidth from among a plurality of channels when a predetermined condition is satisfied. The predetermined condition includes a condition that the first NAV is set. The device transmits a first frame on the selected channel.
US09698945B2 Long-term evolution unlicensed (LTE-U) and wireless local area network (WLAN) coexistence mechanism
In some aspects, the disclosure is directed to methods and systems for protocol coexistence. Within a frequency band of a wireless local area network (WLAN), a device implemented for operation in at least a non-WLAN protocol can determine that the frequency band is quiet at a first time instance. The device can transmit a message in WLAN protocol responsive to the determination and prior to operation in the non-WLAN protocol within the frequency band. The message can have a receiver address other than an address belonging to other devices operating within the frequency band.
US09698944B2 Methods for communicating simultaneously on multiple frequencies
This disclosure describes methods for communicating simultaneously on multiple frequencies. In various implementations, if a wireless terminal receives a first set of data and a second set of data simultaneously on different frequencies, then it sends signals responsive to the first and second sets of data on different slots of a single uplink subframe and on different frequencies.
US09698942B2 Method and arrangement for retransmission using HARQ
The present invention relates to a method and device for enhancing coverage of a power-limited mobile terminal by sending information relating to a single Hybrid Automatic Repeat Request (HARQ) process from the mobile terminal to a base station using several transmission time intervals.
US09698938B2 Method and apparatus for transmitting control information to remove and suppress interference in wireless communication system
A communication method and an apparatus for transferring interference-related control information in order to enhance reception performance of a user terminal that receives downlink signals in a cellular mobile communication system based on a long term evolution-advanced (LTE-A) system are provided. The method includes receiving transmission parameters of interference, which include information on a resource by which interference data is not transmitted, performing blind detection using the information on a resource by which interference data is not transmitted, performing error correction encoding using the transmission parameters of the interference and the blind detection result, and decoding the received data.
US09698933B2 Communication device and communication method
The present disclosure provides a communication device, including: a reception section that receives information relating to a reception timing at a reception side, which is transmitted from a transmission destination after a data frame is transmitted to the transmission destination; an information storage section that stores a transmission interval and the information relating to the reception timing for previous transmissions; a mismatch correction section that, in a case in which a new data frame is transmitted, calculates a correction amount for eliminating a mismatch in a transmission timing of a wakeup frame or a mismatch in a reception timing at which the transmission destination receives the wakeup frame, based on the transmission interval and the information relating to the reception timing; and a communication control section that determines the transmission or reception timing based on the information relating to the reception timing and the correction amount.
US09698930B2 Bandwidth map update method and device
A method for bandwidth map update includes: after receiving a bandwidth report carried by a control frame, a master node newly establishing a bandwidth map, newly establishing a resource state table, and setting all resource states in the newly established resource state table to be available; adding a cross-master node transport channel drop allocation structure of the newly established bandwidth map in accordance with a cross-master node transport channel add allocation structure of a bandwidth map to be updated, and updating the resource state table; according to the bandwidth report carried by the control frame, allocating a wavelength and an optical burst timeslot one by one to a current bandwidth request, adding wavelengths and optical burst timeslots to the newly established bandwidth map, generating a new bandwidth map, and updating the resource state table; and distributing the control frame carrying the new bandwidth map to slave nodes hop by hop.
US09698923B2 Traffic information client device
The invention provides an electronic device configured to operate as a traffic information client. The traffic information client device comprises an interface adapted to receive traffic information messages, where a traffic information message comprises a location code which identifies a location of a traffic event. The traffic information client device further comprises a memory and a relational database stored in the memory, the relational database comprising at least a first set of relations including at least one relation which directly or indirectly associates location codes with location information.
US09698920B2 Radio channel data and the use thereof
An apparatus comprises a receiver receiving wireless transmission of a real radio system from at least one base station of a radio system as a function of reception direction. The transmission comprises predetermined data. The apparatus comprises also a processing unit that forms taps of a delay profile on the basis of comparison between the data that is received and corresponding predetermined data. The processing unit estimates direction for the taps of the delay profile on the basis of a reception direction of the transmission, and forms radio channel data by associating the taps of the delay profile with the estimated direction. The radio channel data is for a radio channel model of a MIMO emulation in an OTA chamber having a plurality of antennas around a test zone where a device-under-test may be placed.
US09698918B2 Distributed adaptive CCA mechanisms
A method implemented by a first network device where the method provides an adaptive clear channel assessment (CCA) by collecting a neighboring network device set for a wireless local area network (WLAN). The method detects a wireless signal from a second network device on a wireless medium. A signal quality of the wireless signal is then determined. An identity of the second network device is also determined. The second network device is then added to the neighboring network device set of the first network device, in response to determining that the second network device is a neighbor based on the signal quality of the wireless signal.
US09698914B2 Recovering data from quadrature phase shift keying modulated optical signals
Systems, devices and techniques for processing received QPSK modulated optical signals include sampling the received signal at twice the baud rate, thereby producing samples that are then processed as 9-QAM symbols using a decision directed least squares optimization method. A third stage of channel equalization is filtering performs channel equalization to mitigate linear filtering effects along the transmission link. Data bits are then recovered from the resulting symbol estimates. The received optical signal may also include dual polarized signals for increased bandwidth capacity.
US09698912B2 Methods and systems for superchannel subcarrier monitoring using frequency modulation tones
Methods and systems for superchannel subcarrier monitoring using frequency modulated (FM) tones includes frequency modulating an optical subcarrier of a superchannel with a first frequency that is unique to the optical subcarrier and is chosen to be smaller than an optical transmission frequency for carrier data modulated onto the optical subcarrier. Then, downstream detection and monitoring of the optical subcarrier may be performed based on demodulation of the first frequency. Each optical subcarrier in the superchannel may be modulated using a respectively unique FM tone.
US09698911B2 Systems, devices, and methods for photonic to radio frequency downconversion
A system, method, and device for RF upconversion. The system can include a laser, two EAMs, a photonic filter, a photonic service filter, two photodiodes, and a mixer. The first EAM can convert a received RF signal into the photonic domain by modulating an optical signal (received from the laser) based on the received RF signal to output a modulated optical signal. The photonic filter can output a filtered optical signal based on the modulated optical signal to the first photodiode which can output a filtered RF signal in the RF domain. The second EAM can output an LO modulated optical signal based on a received LO to the service filter which can output a filtered LO optical signal to the second photodiode which can output a filtered LO signal in the RF domain. The mixer can mix the filtered RF and LO signals to generate an IF signal.
US09698908B2 Sub-sampling raster lines in rolling shutter mode for light-based communication
Light-based communication (LCom) techniques are disclosed for decoding LCom signals using a sub-raster line sampling process. In accordance with an embodiment, a system is provided that is configured to sub-sample each raster line to capture data at a much faster sampling rate, which in turn allows for longer LCom messages and faster response time. The sub-sampling of the raster lines can be carried out in a rolling shutter mode. Without such sub-sampling of the raster lines, decoding the LCom signals may be effectively limited by the raster line frequency, given that the raster line sampling rate is tied to the horizontal resolution of the camera. However, by sub-sampling the raster lines as provided herein, the sampling rate can be a combination of horizontal and vertical pixels which represents a substantial improvement over standard raster line based rolling shutter modes.
US09698907B2 Handshake synchronization by adjusting status of status machine of receiving end to a state indicated by status reset signal
A handshake synchronization restoration method and system based on visible light communication are provided. The method includes: after a transmitting end in which a state machine varies with unit time is powered on again, transmitting in the form of a visible light signal, to a receive and control system, a status reset signal which varies with unit time, wherein the receive and control system comprises one or multiple receiving ends; and receiving, by the receive and control system, the visible light signal, and when it is determined that the received visible light signal is a status reset signal, adjusting status of a state machine of a receiving end to a state indicated by the status reset signal. Status synchronization with the transmitting end is restored, avoiding a case in which the transmitting end is asynchronous with the receiving end after encountering power outage and being powered on again.
US09698899B2 Slave station apparatus, master station apparatus, control device, communication system, and wavelength switching method
An ONU communicates with an OLT that can transmit optical signals having different wavelengths simultaneously and receive optical signals having different wavelengths simultaneously. The ONU includes: an optical transceiver that receives any one of the optical signals that the OLT can transmit and transmits any one of the optical signals that the OLT can receive; a communication failure detection unit that detects a communication failure between the OLT and the ONU; and a wavelength selection unit that, when the communication failure detection unit detects a communication failure, changes a setting of a downstream wavelength to be received by the optical transceiver and an upstream wavelength to be transmitted by the optical transceiver.
US09698891B2 Reduced power consumption in a wireless communication system while providing adequate directional radio coverage
There is provided an arrangement for a wireless communication system that includes a set of power amplifiers and a set of antennas based on which at least two different configurations are provided, including a first configuration of power amplifiers and antennas and a second configuration of power amplifier(s) and antennas. The arrangement also includes switching circuitry configured to switch between the configurations. The second configuration employs a smaller number of power amplifiers than the first configuration, and the second configuration has fewer power amplifiers than antennas where at least one power amplifier is connected to at least two antennas via respective antenna branches that are configured with different delays, as represented by delay elements. A difference in delay between a pair of these antenna branches is based on a measure representative of the inverse bandwidth of a signal to be transmitted through the antennas.
US09698888B2 Method and apparatus for performing effective feedback in wireless communication system supporting multiple antennas
A method for transmitting channel status information (CSI) of downlink multi-carrier transmission includes generating the CSI including at least one of a rank indicator (RI), a first precoding matrix index (PMI), a second PMI and a channel quality indicator (CQI) for one or more downlink carriers, the CQI being calculated based on precoding information determined by a combination of the first and second PMIs, determining, when two or more CSIs collide with one another in one uplink subframe of one uplink carrier, a CSI to be transmitted on the basis of priority, and transmitting the determined CSI over a uplink channel. If a CSI including an RI or a wideband first PMI collides with a CSI including a wideband CQI or a subband CQI, the CSI including a wideband CQI or a subband CQI has low priority and is dropped.
US09698886B2 Base station, communication control method, and processor
In a mobile communication system that supports downlink multi-antenna transmission, a base station managing a cell receives beamforming control information fed back from each of a plurality of beamforming target terminals connected to the cell, and null steering control information fed back from a null steering target terminal. When there exists no beamforming target terminal that feeds back the beamforming control information that coincides with the null steering control information, the base station selects, as a pair terminal, a beamforming target terminal that feeds back the beamforming control information containing a predefined rank indicator.
US09698882B2 Reconfigurable single and multi-sector cell site system
A telecommunications system is provided that is controllably operable as a sectorized antenna system and as an omnidirectional antenna system without requiring hardware reconfiguration. The telecommunications system includes a phase correlation measurement unit that can be between a sectorized antenna sub-system and a remotely located RF source site. The phase correlation measurement unit can be coupled to the RF source site over at least one feed line. The phase correlation measurement unit can output signals for controlling a phase shifter at the RF source site for phase shifting downlink signals and for causing operation of the sectorized antenna sub-system as an omnidirectional antenna sub-system. In a sectorized operation mode, the phase correlation measurement unit and the phase shifter can be inactivated.
US09698880B2 Pre-coding method and pre-coding device
Disclosed is a precoding method comprising the steps of: generating a first coded block and a second coded block with use of a predetermined error correction block coding scheme; generating a first precoded signal z1 and a second precoded signal z2 by performing a precoding process, which corresponds to a matrix selected from among the N matrices F[i], on a first baseband signal s1 generated from the first coded block and a second baseband signal s2 generated from the second coded block, respectively; the first precoded signal z1 and the second precoded signal z2 satisfying (z1, z2)T=F[i] (s1, s2)T; and changing both of or one of a power of the first precoded signal z1 and a power of the second precoded signal z2, such that an average power of the first precoded signal z1 is less than an average power of the second precoded signal z2.
US09698873B2 Power transmission device and power transmission and reception system
A power transmission device has: a plurality of power transmission units which perform wireless power transmission of strong-coupling system; a communication unit which, when the plurality of power transmission units transmit power at different timings to a power reception device, receives from the power reception device a plurality of reception power values of power each received by the power reception device and posture information of the power reception device; and a control unit which calculates a plurality of efficiencies based on power values of power transmitted by the plurality of power transmission units and the received plurality of reception power values, obtains a plurality of equal efficiency surfaces with respect to the plurality of power transmission units based on the plurality of efficiencies and the received posture information, and estimates that the power reception device is present at a position where the plurality of equal efficiency surfaces intersect.
US09698862B2 Transformed kernels for cancelling non-linear distortion
Disclosed are a method, computing device, and a non-transitory computer-readable medium storing computer-executable instructions which, when executed, cause a processor to perform operations, which may include: sending a transmit signal including non-linear elements; receiving another signal comprising at least a portion of the transmit signal through a receive chain of a computing device; simulating the transmit chain; generating, by the simulated transmit chain, a first signal associated with the transmit signal; generating a second signal by frequency shifting the first signal; generating one or more first kernels associated with the second signal; performing decimation of the one or more first kernels; transforming the one or more first kernels using a lower triangular matrix, into one or more second kernels; combining the one or more second kernels to generate an echo cancellation signal; and subtracting the echo cancellation signal from the received at least a portion of the transmit signal.
US09698861B2 RF module for wireless unit configured for self-interference cancellation
A system and methods for cancelling transmission leakage signals in a wide bandwidth Distributed Antenna System (“DAS”) having remote units is disclosed. An internal cancellation circuit within the remote unit is employed to reduce the transmitted leakage signals by generating a cancellation signal. This cancellation signal is added to the received signal to cancel the transmission leakage signal in the receiving signal path. A pilot signal generation circuit is employed to optimize the cancellation circuit operating parameters. The frequency of the pilot signal is swept over a range to determine the pilot frequency having the highest electromagnetic coupling. The amplitude and phase of the cancellation signal is then optimized to minimize the level of transmission leakage in the receiving transmission path.
US09698860B2 Systems and methods for self-interference canceller tuning
A method for tuning an analog self-interference canceller includes detecting a tuning trigger, calculating a set of tuning parameters (the tuning parameters including complex weights for a set of taps of the analog self-interference canceller) in response to the tuning trigger, and applying the set of tuning parameters based on component calibration data.
US09698858B2 Method and apparatus for radio antenna frequency tuning
A system that incorporates teachings of the present disclosure may include, for example, a non-transitory computer-readable storage medium, which can include computer instructions to determine a subset of use cases from a group of use cases stored in a memory of a communication device, and to determine a target use case from among the subset of use cases based on an operational parameter associated with a transceiver of the communication device. Additional embodiments are disclosed.
US09698856B2 Electronic device with radio function and operating method thereof
A method and a device for selecting a radio in an electronic device with a hybrid radio function. The method includes detecting an entrance to a hybrid radio function; determining a default radio mode to be executed as a default in response to a preconfigured mode determination condition; and receiving and reproducing a radio broadcast in a radio mode corresponding to the determined default radio mode. The present disclosure can be applied to various other embodiments based on the aforementioned embodiment.
US09698855B1 Performance optimization of power scaled delta sigma modulators using a reconfigurable gm-array
A cellular radio architecture that includes a receiver module having a delta-sigma modulator that includes a plurality of gm cells configured in stages, where each stage includes at least two gm cells and an LC filter circuit. The gm cells in each stage can be controlled to be active or inactive to convert, for example, the modulator from a fourth order modulator to a second order modulator to reduce power dissipation. Further, the gm cells can be controlled to optimize a dynamic range of the modulator and to redirect current from inactive cells to active cells in order to optimize power consumption.
US09698853B2 Power amplifier open loop current clamp
Various implementations include circuits, devices and/or methods that provide open loop current limiting power amplifiers and the like. In some implementations, an open loop current clamp includes a trim module to provide a control value and a limiting source having respective input and output terminals. The input terminal is coupled to the trim module to receive the control value. The output terminal coupled to a control terminal of the first transistor to provide a limiting electrical level produced in response to the control value by the limiting source. The limiting electrical level substantially setting a first mode of operation for the first transistor such that the current draw of the first transistor is substantially determined by the first mode of operation and the limiting electrical level such that a voltage at an output terminal of the first transistor exerts reduced influence on the current draw.
US09698851B2 Electronic device holder
A holder for a housing of an electronic device includes an extruded metal portion adapted to receive the housing and a securement element that is either mounted to the extruded metal portion or integral with the extruded metal portion. The securement element is adapted to secure the housing in the extruded metal portion.
US09698848B2 Protective case accessory with multi-function button for smart-phone device
A protective case accessory with integrated Multifunction button configured for attachment to a cellular smartphone device, facilitating the initiation of embedded features or software applications, or both, when attached to the Smartphone device. The invention includes a Multifunction button integrated into a protective case accessory and preferably uses a Bluetooth transceiver to connect wirelessly to a smartphone device to send and receive audio or data communication, or both.
US09698847B2 Wireless communication device grip guide
A grip guide for a hand held wireless communication device housing that guides proper hand placement on the housing. The grip guide can include a frame having an interior region sized and shaped to receive a hand held wireless communication device. An exterior surface includes first and second protrusions adjacent an antenna area of the communication device, and a gripping region between the regions. The protrusions guide a user to grip the housing at the gripping regions.
US09698844B2 Signal path processing bias error detector
The present invention detects, determines, and mitigates signal-path processing errors. An extracted and inverted reference signal is compared to the carrier signal produced by various functional components to determine the error introduced to that signal by functional components. After the signal has been processed by various signal-processing components, the signal can once again be compared to the inverted reference signal so that a signal-path processing bias can be determined. Using that determination, a signal modification can be initiated to substantially reduce or eliminate all signal-path processing error.
US09698843B2 Extracting parameters from a communications channel
A method for extracting a parameter of a communication channel from a channel estimate that characterizes the communication channel in terms of a frequency response over time. The method includes generating a set of feature identifiers that characterize features of the channel, for example energy peaks or troughs and determining the parameter, for example time delay of a multipath signal or frequency offset of a multipath signal, dependent on the feature identifiers. Methods using the parameter are also described including methods to estimate the environment.
US09698841B2 Method and apparatus for associating radio frequency identification tags with participants
Systems, methods, apparatuses, and computer readable media are disclosed for associating a radio frequency identification tag with a participant. In one embodiment, a method is provided for associating an unassociated RF location tag with a participant. The method may include determining an unassociated RF location tag to be associated with the participant, receiving sensor derived data from one or more sensors, determining an identity of the particular participant using the sensor derived data, and associating the identity of the particular participant with the unassociated RF location tag.
US09698840B2 Receiver and a method for reducing a distortion component related to a baseband transmit signal in a baseband receive signal
A receiver for reducing a distortion component related to a baseband transmit signal in a baseband receive signal is provided. The receiver includes a distortion meter including a correlation unit configured to correlate a signal that depends on the baseband receive signal and a signal that depends on the baseband transmit signal. The receiver further includes a combiner configured to provide the baseband receive signal using the received radio frequency signal and a plurality of settings based on a correlation result of the distortion meter.
US09698838B1 Real-time blocker-adaptive broadband wireless receiver for low-power operation under co-existence in 5G and beyond
A receiver system includes a blocker detector circuit configured to receive a radio frequency (RF) input signal and detect an existence of a blocker therein, and further configured to output a blocker detection signal indicative of the existence of the blocker. The receiver system further includes a configurable receiver circuit configured to receive the RF input signal and the blocker detection signal, and selectively configure the configurable receiver circuit between a first mode wherein the configurable receiver circuit exhibits first linearity characteristics, and a second mode wherein the configurable receiver circuit exhibits second, different linearity characteristics based on the blocker detection signal.
US09698837B2 Communication device and method for processing a received signal
A communication device is provided comprising a frontend component configured to receive a signal being a combination of an information signal and an interference signal; a first interference removal component configured to reconstruct the interference signal and to subtract the reconstructed interference signal from the received signal to generate a first processed received signal; a second interference removal component configured to equalize the received signal based on channel information of a channel between the device and a sender of the information signal and channel information of a channel between the device and a sender of the interference signal to generate a second processed received signal; and a processor configured to reproduce information contained in the information signal based on the one of the processed received signals or a combination of the processed received signals based a comparison of the first processed received signal and the second processed received signal.
US09698836B2 Systems and methods for mitigation of self-interference in spectrally efficient full duplex communications
Systems and methods which provide mitigation of self-interference in spectrally efficient full duplex (e.g., transmit and receive using the same frequency simultaneously) communications are described. Embodiments provide an interference mitigation structure having a multi-tap vector modulator interference cancellation circuit operable to cancel time varying multipath interference in the analog RF domain. A multi-tap vector modulator interference cancellation circuit of embodiments may comprise part of a multi-stage interference cancellation circuit, such as a multi-stage interference cancellation circuit comprising a multi-tap vector modulator interference cancellation circuit and a digital residual interference cancellation circuit. A digital residual interference cancellation circuit of embodiments provides residual interference cancellation. A multi-stage interference cancellation circuit configuration of embodiments is operable to provide cancellation of strong multipath signals as well as cancellation of residual multipath signals, including interference in the received signal associated with circulator leakage, antenna reflection and multipath.
US09698832B2 Apparatus and methods for negative voltage generation with reduced clock feed-through
Apparatus and methods for negative voltage generation with reduced clock feed-through are provided. In certain configurations, a method of negative voltage generation in a wireless device is provided. The method includes generating a regulated voltage from a battery voltage using a voltage regulator, powering a first charge pump and a second charge pump using the regulated voltage, generating a first negative voltage based on timing of a first clock phase using the first charge pump, generating a second negative voltage based on the first negative voltage and on timing of a second clock phase using the second charge pump, and generating the first clock phase and the second clock phase with different phases using a poly-phase oscillator such that the first charge pump and the second charge pump draw from the regulated voltage at different points in time.
US09698829B2 Bit interleaver for low-density parity check codeword having length of 16200 and code rate of 2/15 and 16-symbol mapping, and bit interleaving method using same
A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 16200 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 16-symbol mapping.
US09698828B2 Method of performing two-dimensional interleaving, and recording medium, and apparatus for performing the same
A two-dimensional interleaving method is provided. The two-dimensional interleaving method includes dividing a first page having N2×N2 pixels, N being a natural number, into a plurality of blocks, wherein each of the plurality of blocks includes N×N pixels, rearranging each of the plurality of the blocks of the first page into a second page, wherein each of two index located at same position in two adjacent block of the first page, respectively, is rearranged to have at least a dispersion distance D in the second page, and relocating an index pixel located at same position of each of the plurality of the blocks of the first page into a k-th block of the second page.
US09698823B2 Method and arrangement for coding transform coefficients in picture and/or video coders and decoders and a corresponding computer program and a corresponding computer-readable storage medium
The present invention describes a method and an arrangement for coding transform coefficients in picture and/or video coders and decoders and a corresponding computer program and a corresponding computer-readable storage medium, which can particularly be employed as a novel efficient method for binary-arithmetic coding transform coefficients in the field of video coding.For this, it is suggested that, for blocks of (video) pictures containing significant transform coefficients, coding of the transform coefficients takes place in such a way that, for each block in a scan process, the positions of significant transform coefficients in the block and subsequently, in a reverse scan order—starting from the last significant transform coefficient within the block—the values (levels) of the significant transform coefficients are determined and coded.
US09698820B2 Method and arrangement for coding transform coefficients in picture and/or video coders and decoders and a corresponding computer program and a corresponding computer-readable storage medium
The present invention describes a method and an arrangement for coding transform coefficients in picture and/or video coders and decoders and a corresponding computer program and a corresponding computer-readable storage medium, which can particularly be employed as a novel efficient method for binary-arithmetic coding transform coefficients in the field of video coding.For this, it is suggested that, for blocks of (video) pictures containing significant transform coefficients, coding of the transform coefficients takes place in such a way that, for each block in a scan process, the positions of significant transform coefficients in the block and subsequently, in a reverse scan order—starting from the last significant transform coefficient within the block—the values (levels) of the significant transform coefficients are determined and coded.
US09698819B1 Huffman code generation
A method for generating Huffman codewords to encode a dataset includes selecting a Huffman tree type from a plurality of different Huffman tree types. Each of the Huffman tree types specifies a different range of codeword length in a Huffman tree. A Huffman tree of the selected type is produced by: determining a number of nodes available to be allocated as leaves in each level of the Huffman tree accounting for allocation of leaves in each level of the Huffman tree; allocating nodes to be leaves such that the number of nodes allocated in a given level of the Huffman tree is constrained to be no more than the number of nodes available to be allocated in the given level; and assigning the leaves to symbols of the dataset based an assignment strategy selected from a plurality of assignment strategies to produce symbol codeword information.
US09698818B2 Entropy encoding and decoding scheme
Decomposing a value range of the respective syntax elements into a sequence of n partitions with coding the components of z laying within the respective partitions separately with at least one by VLC coding and with at least one by PIPE or entropy coding is used to greatly increase the compression efficiency at a moderate coding overhead since the coding scheme used may be better adapted to the syntax element statistics. Accordingly, syntax elements are decomposed into a respective number n of source symbols si with i=1 . . . n, the respective number n of source symbols depending on as to which of a sequence of n partitions into which a value range of the respective syntax elements is sub-divided, a value z of the respective syntax elements falls into, so that a sum of values of the respective number of source symbols si yields z, and, if n>1, for all i=1 . . . n−1, the value of si corresponds to a range of the ith partition.
US09698817B2 Apparatuses and methods for data compression and for data recovery in digital baseband transmission system
A data compression apparatus and a data recovery apparatus for a digital baseband transmission system. The data compression apparatus includes compressor A configured to generate a first compression signal through up-down sampling an input signal; and compressor B configured to generate a second compression signal through partial bit sampling whereby at least one least-significant bit is eliminated from the first compression signal.
US09698815B1 Pipelined ADC with constant charge demand
A multiplying digital to analog converter includes first and second inputs for receiving first and second differential input signals. A differential amplifier has first and second differential input nodes and first and second differential output nodes. A first capacitor is coupled in series with a first switch between the first differential input node and the first input. The first capacitor is further coupled to at least one reference voltage supply node via one or more further switches. A second capacitor is coupled between the first differential input node and the first differential output node. A third capacitor is coupled between the first differential input node and the first input.
US09698814B2 Method and apparatus for indirect conversion of voltage value to digital word
A method for indirect conversion of a voltage value to a digital word consisting in sampling an input voltage through a parallel connection of a sampling capacitor to a source of the input voltage, and next in mapping a sample value of the input voltage to a time interval, and in assignment of a corresponding value of n-bit output digital word by the use a control module characterized in that the time interval is mapped to a difference of a length of a reference time and a length of a signal time, while the reference time is generated from an instant when the beginning of the time interval is detected by the use the control module, and the signal time is generated from an instant when the end of the time interval is detected by the use the control module, whereas generation of the reference time and the signal time is terminated at the same instant.
US09698813B2 Input buffer and analog-to-digital converter
An input buffer for an ADC is provided. The input buffer includes a receiving circuit and an impedance circuit. The receiving circuit is coupled between a power supply and a sample-and-hold circuit of the ADC, and receives an analog input signal and generating an analog signal. The impedance circuit is coupled to the receiving circuit, and selectively provides a variable impedance. When the sample-and-hold circuit of the ADC is operated in a first phase, the impedance circuit provides a small impedance, and when the sample-and-hold circuit of the ADC is operated in a second phase, the impedance circuit provides a large impedance.
US09698812B2 Multiplying analog to digital converter and method
A multiplying analog to digital converter including an analog to digital converter (ADC) having a sample input and a feedback input and an ADC output configured with a feedback path configured to couple the ADC output to a digital to analog converter. A feedback attenuator is disposed in the feedback path, the feedback attenuator being configured to attenuate a feedback signal coupled to the feedback input, the feedback attenuator being configured to provide analog multiplication observed at the ADC output. A barrel shifter is configured to provide digital multiplication of the ADC output. The feedback attenuator may be configured as a divider network. The feedback attenuator may be configured to provide attenuation using only passive components. The feedback attenuator may be configured as a capacitive divider network. The feedback attenuator may be configured to provide attenuation ranging between 1 and 0.5.
US09698811B2 Successive approximation register analog-to-digital converter
Aspects of a method and apparatus for converting an analog input value to a digital output code are provided. One embodiment of the apparatus includes a digital-to-analog converter, a comparator, and control logic circuitry. The digital-to-analog converter is configured to generate an analog reference value based on a received digital reference value. The comparator is configured to compare an analog input value to the analog reference value after expiration of an allotted settling time for the digital-to-analog converter and generate a comparison result indicative a relationship between the analog input value and the analog reference value. The control logic circuitry is configured to select the allotted settling time for the digital-to-analog converter based on a bit position of a digital output code to be determined, and update the bit position of the digital output code based on the comparison result.
US09698808B1 Phase measurement and correction circuitry
A circuit provides for phase adjustment of an offset clock pair, and includes an analog stage and a digital stage. The analog stage provides for generating an adjusted offset clock pair and detecting a phase difference between the adjusted offset clock pair. The digital stage operates to quantify the phase difference and provide a command for further adjusting the phase of the adjusted offset clock pair, at the analog stage, towards a target phase offset value.
US09698799B2 Phase locked loop frequency calibration circuit and method
A phase locked loop frequency calibration circuit and a method are provided. The circuit includes a timer, a counter, a control module, a frequency divider and a voltage controlled oscillator; output of voltage controlled oscillator is connected with first input of frequency divider, output of frequency divider is connected with first input of counter, second input of frequency divider, first input of timer and second input of counter are respectively connected with first output of control module, third input of counter is connected with output of timer, output of counter is connected with first input of control module, a reference clock signal is respectively sent to second input of timer and second input of control module, the number of clocks used by frequency divider to perform frequency division on output clock signal of voltage controlled oscillator is sent to third input of control module.
US09698797B1 Hierarchical feedback-controlled oscillator techniques
Techniques are disclosed relating to feedback-controlled oscillators (e.g., phase-locked loops) arranged in two or more levels. In some embodiments, in a relatively higher-frequency mode, a first level feedback-controlled oscillator provides reference signals to one or more second level feedback-controlled oscillators that in turn generate output clock signals to clock sequential circuitry. In some embodiments, in a relatively lower-frequency mode, the first level feedback-controlled oscillator bypasses the second level feedback-controlled oscillators and provides output clock signals directly to sequential circuitry (without using any intervening feedback-controlled oscillators).
US09698795B1 Supporting pseudo open drain input/output standards in a programmable logic device
Techniques and mechanisms allow a Programmable Logic Device (PLD) to support a pseudo open drain (POD) input/output (I/O) standard used in interface protocols such as fourth generation double data rate (DDR4). An OR gate with inputs including data and an inverted output enable from a user's design may be inserted into programmable logic. The output of the OR gate may be coupled with an input of an I/O buffer.
US09698789B2 Integrated circuit
An integrated circuit is provided. The integrated circuit includes a pad, a core circuit, an impedance matching component, a first switch and a second switch. The pad is configured to transmit a communication signal. A communication terminal of the core circuit is coupled to the pad, and a power terminal of the core circuit is coupled to a system voltage rail. A first terminal of the impedance matching component is coupled to the pad. A first terminal of the first switch is coupled to the system voltage rail, and a second terminal of the first switch is coupled to a second terminal of the impedance matching component. A first terminal of the second switch is coupled to a control terminal of the first switch, and a second terminal of the second switch is coupled to the second terminal of the impedance matching component.
US09698788B2 Interface device, related method, and related open-drain device
An interface device may include a first transistor, a pull-up unit, a pull-down unit, a first power supply terminal, a ground terminal, an output signal terminal, and a bias unit. A first gate terminal of the pull-up unit is electrically connected to a source terminal of the first transistor. A drain terminal of the pull-down unit is electrically connected to a drain terminal of the first transistor. The first power supply terminal is electrically connected to a source terminal of the pull-up unit. The ground terminal is electrically connected to a source terminal of the pull-down unit. The output signal terminal is electrically connected to each of a drain terminal of the pull-up unit and the drain terminal of the pull-down unit. An output terminal of the bias unit is electrically connected, without any intervening transistor, to a gate terminal of the first transistor.
US09698786B2 Interface apparatus with leakage mitigation
Aspects of the present disclosure are directed to detecting and powering external circuits via a common port. As may be implemented in accordance with one or more embodiments, an accessory detection circuit detects a type of an external circuit based upon a pull-down resistance at an interface port (e.g., where each accessory type provides a discernable pull-down resistance). Power switching circuitry couples power between the interface port and an internal power-based circuit, and operates in an open condition when the accessory detection circuit is active. An adaptive biasing circuit sets a voltage across the power switching circuitry to about zero, based on a voltage level provided on the interface port, thereby mitigating changes in the pull-down resistance due to current leakage. Once the type of external circuit is identified, the power switching circuitry couples power between the external circuit and the internal circuit.
US09698782B1 Systems and methods to provide charge sharing at a transmit buffer circuit
A circuit includes a data input in communication with a first transistor stack; a first capacitor having a first capacitance and in communication with a power supply via a first transistor of the first transistor stack, wherein the first transistor is configured to charge the first capacitor in response to the data input receiving a signal corresponding to a first binary value; a data output node coupled between the first transistor stack and a transmission line having a second capacitance; and wherein the first capacitor is coupled between the data output node and a second transistor of the first transistor stack, further wherein the second transistor is configured to discharge the first capacitor to the data output node in response to the data input receiving a signal corresponding to a second binary value.
US09698775B2 Operating device for an electrical apparatus, in particular for a vehicle component
The operating device for an electrical apparatus or a system, in particular for a vehicle component, is provided with at least one elastically mounted operating element (12), a counter-element (14), relative to which the at least one operating element (12) is movable when actuated, thereby varying the distance, namely as seen in the movement direction, and at least one capacitor (38) which comprises a first carrier body (20) with a first capacitor electrode (34) and an elastically bendable second carrier body (22), designed as a bending bar, having a first end (26) and a second end (32) opposite said first end and having a second capacitor electrode (36) opposite the first capacitor electrode (34). Connected to the first and second capacitor electrode (34, 36) is an evaluation unit (42) for determining the capacitance and/or a change in the capacitance of the at least one capacitor (38) upon actuation of the at least one operating element (12).
US09698766B2 Apparatuses and methods for adjusting timing of signals
Apparatuses and methods for adjusting timing of signals are described herein. An example apparatus may include a first signal adjustment cell configured to receive a first clock signal and to adjust skew of rising or falling edges of the first clock signal based on a first control signal. The timing adjustment circuit may further include a second signal adjustment cell configured to adjust skew of rising or falling edges of a second clock signal based on a second control signal. The timing adjustment circuit may further include a differential adjustment cell configured to receive the first and second clock signals and to adjust skew of rising or falling edges of the first clock signal based on the first control signal and to adjust skew of rising or falling edges of the second clock signal based on the second control signal. The first and second clock signals may be complementary.
US09698764B2 Quadrature divider
Described is an apparatus of a quadrature divider. The apparatus is independent of a jam latch, and is for generating a quadrature clock. The apparatus comprises: a first selection unit controllable by a clock signal, the first selection unit to directly or indirectly generate a first phase of the quadrature clock; a third selection unit controllable by the clock signal, the third selection unit to receive the first phase of the quadrature clock, the third selection unit to directly or indirectly generate a third phase of the quadrature clock, wherein the first selection unit to receive the third phase of the quadrature clock.
US09698760B1 Continuous-time analog delay device
Systems, methods, and other embodiments associated with a continuous-time analog delay device are described. According to one embodiment, a device includes a first terminal connected to an input line to receive an input signal. The device includes a first differential pair of transistors comprising a first transistor and a second transistor, wherein a gate of the second transistor is connected to the first terminal. The device includes a second differential pair of transistors comprising a third transistor and a fourth transistor, wherein a gate of the third transistor is connected to the first terminal. The device includes a first load connected to a drain of the third transistor. The device includes a second load connected to a drain of the fourth transistor. The device includes at least one capacitor connected in parallel between the first load and the second load.
US09698753B2 Laterally coupled resonator filter having apodized shape
A laterally coupled resonator filter device includes a bottom electrode, a piezoelectric layer disposed on the bottom electrode, and a top contour electrode disposed on the piezoelectric layer. The top contour electrode includes first and second top comb electrodes. The first top comb electrode include a first top bus bar and multiple first top fingers extending in a first direction from the first top bus bar. The second top comb electrode includes a second top bus bar and multiple second top fingers extending in a second direction from the second top bus bar, the second direction being substantially opposite to the first direction such that the first and second top fingers form a top interleaving pattern providing an acoustic filter having an apodized shape.
US09698745B2 Contextual volume control for adjusting volume level of a mobile device
Adjustment of volume level of a mobile device, by the mobile device without direct or manual user-input, based on one or more contextual parameters detected by the mobile device, such as ambient noise level. A query or other techniques may be used for the adjustment to be ignored. The system may be trained over time by modifying the one or more contextual parameters due to detecting events or sequences of events, such as a user ignoring attenuation in a particular situation.
US09698732B2 Switched mode converter with low-voltage turn-around mode
A controller may be configured to sequentially apply a plurality of switch configurations of a power converter in order to operate the power converter as a differential output converter to switch a polarity of the output voltage, such that: during a charging phase of the power converter, a power inductor is coupled between one of a first terminal and a second terminal of the power source and one of a first terminal and a second terminal of the output load, during a transfer phase of the power converter, at least one of the plurality of switches is activated in order to couple the power inductor between the second terminal of the power source and one of the first terminal of the output load and the second terminal of the output load, wherein the output voltage is a differential voltage between the first terminal and the second terminal.
US09698729B2 Optimum current control CMOS cascode amplifier
A CMOS cascode amplifier comprises a cascode circuit comprising a plurality of branches in parallel, each branch comprising a first transistor and a second switchable transistor connected in series forming a cascode pair, wherein the cascode circuit is configured to amplify an input signal. The CMOS cascode amplifier further comprises a bias circuit configured to bias the cascode circuit by providing a bias signal to the first transistor in each of the plurality of the branches in the cascode circuit. In addition, the CMOS cascode amplifier comprises a switching control circuit configured to control a quiescent current in the cascode circuit based on selectively activating the plurality of branches by providing a switching control signal that switches on the second switchable transistor in the one or more activated branches.
US09698728B2 Digital isolator
Several circuits and methods for transferring an input data signal in a digital isolator are disclosed. In an embodiment, the digital isolator includes an isolation element, input circuit, and output circuit. The isolation element includes at least one input node and at least one output node, the input circuit is electronically coupled to the input node and generates modulated differential data signals based on modulating the input data signal on a carrier signal. The input circuit operates using a first supply voltage with respect to a first ground. The output circuit is electronically coupled to the output node to receive the modulated differential data signals, operates using a second supply voltage with respect to a second ground and includes a frequency-shift keying demodulator configured to generate a demodulated data signal in response to detection of presence of the carrier signal. The output circuit further generates an output data signal.
US09698727B1 Coupled inductor-based resonator
A two-walled coupled inductor includes an outer wall and an inner wall separated by a slit. The outer wall has a first width and the inner wall has a second width. The inner wall and the outer wall may be configured to be coupled to oscillator circuitry. The two-walled coupled inductor may include an electrically conductive stub coupled to the outer wall to be coupled to a power supply. A common mode current flows through the outer wall, and the stub if one is present, and a differential mode current flows through both the outer wall and the inner wall, but not the stub. The first and second widths, and dimensions of the stub, may be sized to increase an inductance of the common mode compared to an inductance of the differential mode, thereby reducing phase noise of the inductor-based resonator.
US09698719B2 Linear motor driver and method for driving same
The present disclosure discloses a linear vibration motor driver including an amplitude and temperature testing unit, a gain controller, and a coil resistance detector and an amplifier. The amplitude and temperature testing unit receives a motor drive input signal and a feedback drive signal output by the amplifier, and outputs a corresponding estimated motor amplitude and real-time temperature according to the motor drive input signal and the feedback drive signal. The amplifier adjusts magnification, amplifies the motor drive input signal according to the magnification and outputs the feedback drive signal to drive the motor. The present disclosure can adjust the magnitude of the drive signal according to current estimated amplitude and maximum amplitude and make corresponding rectification of the amplifier magnification upon too high temperature to extend the service life of the motor.
US09698717B2 Motor drive device provided with function of changing current detection mode
A motor drive device driving any of a feed shaft or spindle of a machine tool or arm of an industrial machine or industrial robot etc., comprising a current detecting part detecting a motor current, a current control part using an output from the current detecting part as the basis to output a command value to the motor, and a power converting part using a current command as the basis to supply power to the motor, the current detecting part comprising a current slope detecting part and a switching part using an output of the current slope detecting part to switch a plurality of filter characteristics to switch a mode of current detection. The switching part switches to a filter with a narrow/a broad bandwidth when the slope of the current is small/large to thereby improve the precision of current detection.
US09698716B2 Motor control device and work machine using the same
The controller estimates torque output by the motor and controls the current supplied to the motor in such a manner that a torque estimate of the motor obtained by the estimation corresponds to the torque command value. A torque estimation calculator 120 estimates the torque output by the motor. A phase error command calculator 125 calculates a command value of a phase error from the deviation between the torque estimate and a torque command value. A speed estimation calculator 130 outputs a speed estimate in such a manner that a phase error estimate corresponds to the command value of the phase error.
US09698713B2 Apparatus for correcting offset of current sensor
Disclosed are embodiments of an apparatus for correcting an offset of a current sensor. The apparatus includes an inverter, a detector, and a RMS calculator, and a controller. The RMS calculator converts the high frequency component extracted from the filter into an effective (RMS) value. The controller, if the effective (RMS) value of the d-axis or q-axis current transformed by the RMS calculator is larger than a preset reference, increases/decreases a currently-set DC offset of each of the current sensors by a certain amount, and replaces the currently-set DC offsets with a DC offset corresponding to a smallest one of the effective (RMS) values of the d-axis or q-axis transformed by the RMS calculator, thereby correcting each of the current sensors. Accordingly, a pulsation in an output torque in controlling an electric motor can be effectively prevented.
US09698703B2 Switching converter having a primary winding divided into a first partial winding and a second partial winding with a tap arranged therebetween
A switching converter includes a transformer having a primary winding to which an input voltage is supplied and formed of two primary winding halves, a tap between the winding halves, and a pair of switching elements in series connection with the winding halves. A voltage divider formed of two capacitors and across which the input voltage is supplied is connected at a center tap between the two capacitors to the primary winding tap through a damping element or network. Each switching element is connected through a respective driver to a controller that operatively effects synchronous control of the switching elements.
US09698702B1 Switching power supply and a power supply apparatus that incorporates the same
A switching power supply and a power supply apparatus that incorporates the switching power supply are provided. Advantages of the switching power supply include the following: 1. Two or more switching power supplies can be used in parallel when they have the same kind of input power and the same rated output power. 2. Two or more switching power supplies can be used in parallel when they have the same rated output power but different kinds of input power. 3. Two or more switching power supplies can be used in parallel when they have the same kind of input power but different rated output powers. 4. Two or more switching power supplies can be used in parallel when they have different kinds of input power and different rated output power. 5. When the above-described switching power supplies are connected in parallel, the respective load proportion of each of them can be adjusted at will.
US09698697B2 Power supply device, and method of controlling power supply device
A storage (80) stores a first drooping characteristic of a rated current Ioc1, and a second drooping characteristic of an allowable current value Ico2 that is greater than the rated current value Ioc1. A controller (70) is configured to select a drooping characteristic stored in the storage (80) in accordance with the current value detected by an output current detector (50) and a mask condition, and perform droop control.
US09698685B2 Methods and apparatus for a single inductor multiple output (SIMO) DC-DC converter circuit
In some embodiments, an apparatus includes a single-inductor multiple-output (SIMO) direct current (DC-DC) converter circuit, with the SIMO DC-DC converter circuit having a set of output nodes. The apparatus also includes a panoptic dynamic voltage scaling (PDVS) circuit operatively coupled to the SIMO DC-DC converter circuit, where the PDVS circuit has a set of operational blocks with each operational block from the set of operational blocks drawing power from one supply voltage rail from a set of supply voltage rails. Additionally, each output node from the set of output nodes is uniquely associated with a supply voltage rail from the set of supply voltage rails.
US09698684B2 Adaptive soft switching control for power converter
A control apparatus for use in controlling a power converter adapted to carry out power conversion between a high-voltage end and a low-voltage end includes an input configured for receiving at least one input signal conveying a sensed voltage across the high-voltage end, a sensed voltage across the low-voltage end and a sensed current through the low-voltage end; circuitry configured for determining a target switching frequency, a target dead time and a target duty cycle for the converter based at least in part on the sensed voltages, the sensed current and at least one circuit characteristic of the converter; and an output configured for releasing at least one output signal to cause the converter to carry out soft switching in accordance with the target switching frequency, the target dead time and the target duty cycle.
US09698681B2 Circuit and method for maximum duty cycle limitation in step up converters
An adaptive duty cycle limiting circuit is used with a switching DC-to-DC converter for preventing the duty cycle entering a region of operation having negative gain. The adaptive duty cycle limiting circuit includes a duty cycle ramp signal generator, a voltage source for providing a voltage having a fractional value of an input voltage source, and a comparator that compares the duty cycle ramp signal with the fractional value of the input voltage source. When the voltage level of the duty cycle ramp signal is less than the fractional value of the voltage source, a cycle limit signal is activated and communicated to a switching control circuit to adjust the duty cycle of the switching DC-to-DC converter to prevent the duty cycle entering the region of operation where the gain of the switching DC-to-DC converter becomes negative.
US09698678B2 Circuitry and method for regulating a current for diagnosing an electromechanical load utilizing multiple current measurements
A circuitry for regulating a current for an electromechanical load comprises a first connection and a second connection for the electromechanical load. The first connection can be coupled to a first supply potential thereby, and a potential of the second connection can be modified by means of a pulse width modulation. The circuitry also comprises a measurement assembly having a first measurement signal input, which is coupled to the first connection and a second measurement signal input, which is coupled to the second connection. The measurement assembly is designed thereby to determine a measurement signal that is proportional to a potential difference between the first and second connection, in order to regulate the current for the electromechanical load on the basis of the measurement signal.
US09698677B2 Brownout recovery circuit for bootstrap capacitor and switch power supply circuit
In one embodiment, a brownout recovery circuit configured for a switch power supply circuit with a first switch, can include: (i) an under-voltage detection circuit that activates a detection signal when a bootstrap capacitor is not in an under-voltage state, and deactivates the detection signal when the bootstrap capacitor is in the under-voltage state; (ii) a logic circuit that generates a first control signal according to a main control signal from the switch power supply circuit and a second switch state; (iii) a first control circuit that generates a first switch signal according to the detection signal, and controls the first switch thereby; and (iv) a second control circuit that receives the first control signal, and generates a second switch signal to control the second switch thereby.
US09698676B1 Charge pump based over-sampling with uniform step size for current detection
Techniques are presented for determining current levels based on the behavior of a charge pump system while driving a load under regulation. Rather than diving the load directly, a fixed pump output voltage is used to supply a step-down regulator, which it turn drives the load at the selected voltage. While driving the load under regulation, the number of pump clocks during a set interval is counted. This can be compared to a reference that can be obtained, for example, from the numbers of cycles needed to drive a known load current over an interval of the duration. By comparing the counts, the amount of current being drawn by the load can be determined. This technique can be applied to determining leakage from circuit elements, such as word lines in a non-volatile memory.
US09698668B2 Systems and methods for increasing output current quality, output power, and reliability of grid-interactive inverters
Various enhancements to grid-interactive inverters in accordance with embodiments of the invention are disclosed. One embodiment includes input terminals configured to receive a direct current, output terminals configured to provide an alternating output current to the utility grid, a controller, an output current sensor, and a DC-AC inverter stage comprising a plurality of switches controlled by control signals generated by the controller. In addition, the controller is configured to: generate control signals that cause the switches in the DC-AC inverter stage to switch a direct current in a bidirectional manner; measure the alternating output current; perform frequency decomposition of the output current; and generate control signals that cause the switches in the DC-AC inverter stage to switch current in a way that the magnitude of a plurality of unwanted current components is subtracted from the resulting output current.
US09698666B2 Power supply and gate driver therein
A power supply and a gate driver includes a power switching element to control current, a control circuit to output a control signal for opening or closing of the power switching element, and a gate drive circuit to open or close the power switching element in accordance with the control signal. The gate drive circuit includes a first inductive circuit connected to a supply voltage source, and a second inductive circuit connected to an input stage of the power switching element, and transfers electrical energy stored in the input stage of the power switching element, using the first and second inductive circuits. Accordingly, electrical energy supplied to the input stage of the power switching element during an ON state of the power switching element is again recovered during an OFF state of the power switching element.
US09698665B2 Digital controller for a power converter
Provided are methods and circuits for a controller for a control system, comprising first and second control loops that operate substantially independently, wherein the first control loop is an amplitude control loop and the second loop is a phase or frequency control loop. In some embodiments the amplitude control loop operates at an amplitude that is proportional to an amplitude of an input signal at a fundamental system frequency and at a selected harmonic of a fundamental system frequency; and the frequency control loop operates at a fundamental system frequency and at a selected harmonic of the fundamental system frequency. The frequency control loop may adaptable to a fundamental control system frequency or to a selected harmonic of the fundamental control system frequency. The controller may be implemented as a resonant controller and used in various ac systems, and offers high structural robustness in digital implementations.
US09698659B2 Flux-switching electrical machine
A singly-excited flux-switching electrical machine, that includes field coils and phase windings, is provided. The field coils and the phase windings are accommodated respectively in the unevenly shaped notches of a stator, such that the field coils and phase windings are radially offset.
US09698655B2 Pump, method for manufacturing pump, and refrigeration cycle device
Provided is a pump that includes an annular molded stator having a substrate mounted with a Hall element and that includes a rotor having an annular rotor unit rotatably housed in a cup-shaped partition component, with one end thereof in an axial direction facing the Hall element and the other end thereof in the axial direction provided with an impeller attachment unit. The rotor unit includes a resin magnet, a sleeve bearing, and a resin portion. The resin magnet includes a rotor-position detecting magnetic-pole portion protruding axially with a predetermined height in an annular shape having a predetermined width in a radial direction on an outer periphery of an end face opposite to the Hall element. The rotor-position detecting magnetic-pole portion includes a plurality of arc-shaped notches on the same circumference on an inner diameter side thereof.
US09698647B2 Electric machine with magnetic sensor
According to an embodiment of the invention, an electric machine is provided. The machine includes a support structure and a stator secured to the support structure. The machine also includes a rotor rotatably scoured to the support structure. The rotor defines a wall of the rotor. The machine also includes a sensor secured to the support structure and adapted to cooperate with the wall of the rotor to sense the position of the rotor relative to that of the stator.
US09698645B2 Electric machine and associated method
A member for cooperation with the stator of an electric machine and for mounting electrical connectors to the stator is provided. The member includes a body, a mounting feature and a receptacle. The mounting feature is operably associated with the body and is adapted for mounting the body onto the stator. The receptacle is operably associated with the body and is adapted for receiving at least a portion of one of the electrical connectors.
US09698638B2 Electric machine cooling system
A cooling system for an electric machine is provided. The cooling system includes an airflow diverter feature configured to provide even distribution of airflow to the electric machine. The airflow diverter feature includes a circular disk mounted to the housing of the electric machine. The disk defines a plurality of vents forming an axial air passage. A plurality of radial air passages are in fluid communication with the axial air passage. The airflow diverter feature defines at least one inlet and at least one outlet. The inlet comprises at least one interior choke and the outlet comprises at least one exhaust choke. The interior choke and the exhaust choke are sized to control a rate of air flow through the radial air passages.
US09698636B2 Brushless motor
A brushless motor includes: a rotor including a magnet; and a stator including at its center a space for placing the rotor. The rotor includes: a rotor core; and a plurality of magnets. The rotor core includes a plurality of magnet holders radially formed around a rotating shaft. The magnets are housed in the magnet holders such that the same magnetic poles of adjacent magnets face each other in a circumferential direction of the rotor core, and the stator includes a plurality of teeth formed toward the center to face the rotor. Given that a radius of curvature of an outer circumference of the rotor core is R, a width of an end of the teeth in a circumferential direction is W, and a maximum outer diameter of the rotor core is L, 0.9≦R/W≦4.2 and R
US09698635B2 Cores for electrical machines
A core for an electrical machine includes a core body. The core body extends long a rotation axis and includes two or more core segments axially stacked with one another along the rotation axis. A plurality of the core segments define notches that are axially-aligned to one another and form an axial slot. The first core segment notch has an area that is greater than an area of a second core segment notch to accommodate thermal expansion of the core.
US09698634B2 Stator core and permanent magnet motor
A stator core includes a first core sheet having a plurality of teeth that is radially protruded outward and a teeth coupling portion that couples the plurality of teeth, and at least two kinds of second core sheets having a plurality of teeth that is radially protruded outward and slot openings that are provided between the plurality of teeth. The first and second core sheets are laminated to form a stack structure, and, in the second core sheets of an identical kind, the slot openings are identical in opening angle and are evenly distributed in a circumferential direction.
US09698632B2 Wireless battery charger and charge-receiving device
A wireless charger includes a plurality of conductive coils and electronic circuitry. The coils are disposed around a perimeter and face a generally central area of the perimeter. The coils are connected to and controlled by the electronic circuitry, which includes an electric power receiving circuit and a coil controller. The electric power receiving circuit receives electrical power from an external source and conditions the power for provision to the coil controller. The coil controller controls provision of an oscillating current to select coils within the plurality of coils. A protective enclosure or portable electronic device may have receiving coils disposed at its sides for corresponding to at least two of the conductive coils of the wireless charger.
US09698631B2 Wireless power supply device
A wireless power supply device is capable of supplying constant power without fluctuation in transmission efficiency even when small-sized antennas in which the power fluctuates due to the transmission distance are used. The wireless power supply device includes a first power receiving antenna having a power receiving surface facing a power transmission surface of a first transmission antenna and a second power receiving antenna having a power receiving surface facing a power transmission surface of a second power transmission antenna, both are integrally formed and connected to a power supply target. A direction in which the power receiving surface of the first power receiving antenna faces the power transmission surface of the first power transmission antenna is parallel to a direction in which the power receiving surface of the second power receiving antenna faces the power transmission surface of the second power transmission antenna.
US09698628B2 System integration of wireless power transmission subsystem
In accordance with various aspects of the disclosure, systems, methods, and devices are disclosed that include a power source integrated with a host computing device, and configured to provide power to the host computing device, and a wireless power transmission module coupled to the host computing device. The wireless power transmission module is configured to wirelessly transmit power derived from the power source independent of whether the host computing device is in a powered-off state or not. The host computing device may be configured to stop the wireless power transmission based on a determination that at least one of one or more predetermined transmission policies has been violated or that an unrecoverable error has occurred at the host computing device.
US09698625B2 Power generation system with anticipatory operation
Systems and methods include operating a power system in a first state, and detecting an anticipated load increase. The systems and methods further include changing operation of the power system from the first state to a second state upon detection of the anticipated load increase.
US09698622B2 Energizing hydrogenerator
The invention relates to an on-board assembly for producing and storing electricity, including at least one hydrogenerator having an output line connected to at least one electrical battery having predetermined electrical load parameters. The hydrogenerator includes a load-bearing structure onto which a generator and an impeller, secured to a shaft for driving a rotor of the generator, are mounted. Said assembly is characterized in that the generator is an excitation generator, and the hydrogenerator includes a rectifier circuit, connecting the generator to the output line, and at least one circuit for exciting the generator. The excitation circuit is connected to an excitation current regulator controlled by a control unit set up so that the generator provides a load current consistent with the electrical load parameters on the basis of a resisting torque of the generator, said torque being predetermined so as to limit drag of the impeller.
US09698620B2 System and a method for charging multiple power receivers in a wireless charging environment
A wireless power charging system and a method thereof are provided. The system includes a power transmitter configured to charge one or more power receivers. The power transmitter includes a signal and control unit configured to detect the one or more power receivers present within a radio frequency range of a power transmitter, transmit a request for discovering each of the one or more power receivers, and determine whether a response is received from each of the one or more power receivers. The power transmitter further includes a regulator unit connected to the signal and control unit configured to modulate an amount of radiation to be transmitted based on the number of power receivers that provided a response and a power conversion unit connected to the regulator unit transmitting energy radiation to charge the one or more power receivers.
US09698615B2 Electric vehicle and method of controlling electric vehicle
An electric vehicle includes: a storage device configured to store power used for traveling; an auxiliary battery configured to store power supplied to an auxiliary load; a converter configured to charge the auxiliary battery by using power supplied from the storage device; and a shut-off device configured to switch between a supply condition in which power is supplied to the auxiliary load from the auxiliary battery and a shut-off condition in which power is not supplied to the auxiliary load from the auxiliary battery. During control of the electric vehicle, the converter is controlled such that an output voltage of the converter is higher when the shut-off device is in the shut-off condition than when the shut-off device is in the supply condition.
US09698610B2 Charge and discharge control method, charge and discharge control system, and charge and discharge control apparatus
A charge or discharge control method includes: receiving a power instruction value with respect to a power storage apparatus; obtaining a remaining state of charge (SOC) and a target SOC which is a target value of the SOC of the power storage apparatus; controlling charge or discharge of the power storage apparatus according to the power instruction value when the power instruction value is received; wherein, in the controlling, a delay time is determined according to a difference between the target SOC and the remaining SOC, and the power storage apparatus is controlled according to the power instruction value at a timing when the delay time passes after the power instruction value is received.
US09698602B2 Power control system and method therefor
The present invention relates to an electric power control system and method therefor, and comprises a control unit 10 and a transformer 20 connected thereto. The control unit 10 detects varying input voltage in real-time, controls switching of triac devices equipped in the transformer, and applies control signal which switches triac device among a plurality of triac devices for target voltage output to the transformer 20. The transformer 20 outputs target voltage by switching tabs of triac devices according to control signal, supplies power by switching tabs of triac devices corresponding to target voltage included in control signal, and preventing EMF induced from primary coil to secondary coil by grounding the tabs of unused triac devices with N-phase for adjustment to the target voltage.
US09698600B2 Control system for synchronous capacitor switch
Systems and methods for connecting a power source to switched capacitors are provided. A method may be used in controlling the connection of a multiple phase power source to a plurality of capacitors. Each phase of the multiple phase power source is electrically connectable to at least one of the capacitors through a switching device. The method comprises, for each phase of the multiple phase power source, determining a first voltage of a power signal for the respective phase of the power source using a first voltage divider that is electrically connected to a first terminal of the switching device for the phase. The method further comprises determining a second voltage across a capacitor that is connected to a second terminal of the switching device for the phase. The second voltage is determined using a second voltage divider that is connected to the second terminal of the switching device.
US09698598B2 Electrical vehicle charging using fuel cell system
A battery charging station receives power from two or more sources and supplies power to charge batteries of electric vehicles and devices.
US09698597B1 Adjustable power and system efficiency maximizing scheme using micro-controllers
A method performed by a circuit for managing power, the method comprising: receiving a plurality of voltages at a microcontroller, where each voltage is associated with a distinct power supply; determining one or more voltages of the plurality of voltages are being or will be adjusted by the respective power supply; in response to the determining, optimizing, using the microcontroller, one or more parameters of one or more of the power supplies to minimize power loss.
US09698592B2 Device for connecting to a power network and method for protecting such a device
A device for connecting to a power network includes a circuit board, a first input-side connection point, to which a first phase of the power network can be connected, a second input-side connection point, to which a second phase of the power network can be connected, and a first and second electrical conductor. The first conductor is connected to the first input-side connection point and the second conductor is connected to the second input-side connection point inside the device. The first conductor is routed as a conductor trace in an interior layer of the circuit board and includes a constriction. The second conductor is routed past the constriction such that electrical insulation existing between the constriction of the first conductor and the second conductor is destroyed in the case of a short-circuit current, to provide an electrically conductive connection between the first and second conductor exists.
US09698589B1 DC power distribution architectures
This specification describes direct current (DC) power distribution systems. One of the systems includes a DC power distribution bus that includes a plurality of sector distribution buses. Each sector distribution bus is coupled to a respective sector power source. A plurality of sector isolation switches are coupled between the sector distribution buses and configured to individually isolate each sector distribution bus from the DC power distribution bus. At least one load is coupled to at least two different sector distribution buses of the DC power distribution bus.
US09698586B2 Pole-attached cable relay carriage and power supply system to electric work machine
A power support system to an electric work machine includes: a cable holding unit configured to hold a cable that transmits power; a cable support pole configured to support the cable held by the cable holding unit at a position higher than a height of a vehicle that travels on a track that intersects at a position where the cable is disposed; and a travel device connected to the cable holding unit and the cable support pole and configured to perform a traveling operation so as to be able to move the cable holding unit and the cable support pole.
US09698584B2 Snap on screwless wallplate wiring devices
A wall cover plate is provided for connecting directly to an electrical wiring device without the use of the base plate or adapter plate. The wall plate can have a connector such as a hook and/or prong that engages the housing for the mounting strap of the electrical wiring device. The electrical wiring device can include a removable connector attached to the mounting strap where the connector has at least one edge or coupling member for coupling with a faceplate. The faceplate can have an inner edge with a rib or series of teeth for connecting with the mounting strap or the removable connector by an interference fit.
US09698582B2 Quick connection identification module junction box
An electrical trainline junction box formed from a housing having first and second opposing sides, an identification module positioned in the housing, and first and second receptacles positioned in each of the first and second opposing sides. The first and second receptacles have a plurality of electrical contacts arranged in a predetermined geometry so that only one possible orientation and electrical connection to trainline flanges is possible. The flanges include contact pins in inserts coupled to the flanges by sleeves. The outer surface of the inserts and the inner surface of the sleeves are keyed to allow only a single orientation of the inserts relative to the sleeves. The outer surface of the sleeves is shaped to allow only a single orientation of the sleeves relative to the flanges, thus ensuring that the proper electrical connection is made when the junction box is installed.
US09698578B1 Slotted bus bar for electrical distribution
A bus bar for electrical power distribution may be an elongated extruded metal bar having slots extending the entire length thereof. The slots may be of T-shape cross section, each with the channel opening through a face of the bar. Bolts are arranged with their heads captured in, and slidable along the length of the slots to any desired position. The bolts may have threaded stems which extend from the head through the channel of the T-slot in which its head is disposed and beyond that face of the bar through which the associated T-slot opens. Each stem is adapted to threadably receive a nut for clamping, supporting or connecting lugs to the bar. The bus bars can be mounted on insulating support members.
US09698577B2 Portable power supply unit with bus bar adapter and tool-less connection
A portable power unit is used for powering a rack-mountable equipment module, in which the equipment module includes an equipment chassis and a bus bar connector extending from the equipment chassis, and in which the bus bar connector is configured to engage a power distribution system of an equipment rack when the equipment module is mounted in the equipment rack. One aspect is directed to a portable power supply unit generally including a bus bar adapter electrically connected to a DC power supply, a mount for supporting the bus bar adapter, the mount having an end, and a tool-less connection electrically connected to the bus bar adapter and extending from the end of the mount, in which the tool-less connection is configured for engaging the bus bar connector of the equipment module.
US09698576B2 Method for manufacturing an ignition electrode for spark plugs and spark plug manufactured therewith
A method for manufacturing an ignition electrode for spark plugs for internal combustion engines. The method includes producing by powder metallurgy a green part or brown part containing the base metal or the base metal alloy, coating of a part of the surface of the green part or brown part with a mixture that contains the precious metal or the precious metal alloy in the form of a powder and a binder, removing the binder from the layer that was formed by the coating and that contains the precious metal or the precious metal alloy, and sintering the coated green part or brown part to form a composite part. The composite part is welded as an end piece to the one end of the base-metal section of the ignition electrode.
US09698575B2 Corona ignition device with gas-tight HF plug connector
This disclosure relates to a corona ignition device, comprising a center electrode, an insulator, into which the center electrode plugs, a coil, which is connected to the center electrode, and a housing, in which the coil is arranged. The housing is closed at one end by the insulator and at the other end carries an HF plug connector, which has an inner conductor connected to the coil and an outer conductor connected to the housing. In accordance with this disclosure, the HF plug connector contains a glass body, which seals an annular gap between the inner conductor and the outer conductor. This disclosure also relates to an HF plug connector suitable for such an HF ignition device.
US09698573B2 Extruded insulator for spark plug and method of making the same
A method for making an extruded insulator for a spark plug in a manner that minimizes pores, relics and/or other defects in the insulator microstructure so that the overall dielectric strength or performance of the insulator is improved. The method may be used to manufacture an extruded insulator that avoids many of the drawbacks associated with such defects, but also has a stepped internal bore for receiving a center electrode. In one embodiment, the method uses a multi-phase extrusion process to extrude a ceramic paste around an elongated arbor and form an extruded section, and then removes the arbor from the extruded section to reveal a stepped internal bore.
US09698569B2 Method for manufacturing semiconductor device and semiconductor device
To improve characteristics of a semiconductor device (semiconductor laser), an active layer waveguide (AWG) comprised of InP is formed over an exposed part of a surface of a substrate having an off angle ranging from 0.5° to 1.0° in a [1-1-1] direction from a (100) plane to extend in the [0-1-1] direction. A cover layer comprised of p-type InP is formed over the AWG with a V/III ratio of 2000 or more. Thereby, it is possible to obtain excellent multiple quantum wells (MQWs) by reducing a film thickness variation of the AWG. Moreover, the cover layer having side faces where a (0-11) plane almost perpendicular to a substrate surface mainly appears can be formed. A sectional shape of a lamination part of the cover layer and the AWG becomes an approximately rectangular shape. Therefore, an electrification region can be enlarged and it is possible to reduce a resistance of the semiconductor device.
US09698567B2 Wavelength-selectable laser device providing spatially-selectable wavelength(S)
A wavelength-selectable laser device providing spatially-selectable wavelength(s) may be used to select one or more wavelengths for lasing in a tunable transmitter or transceiver, for example, in a wavelength division multiplexed (WDM) optical system such as a WDM passive optical network (PON). The wavelength-selectable laser device uses a dispersive optical element, such as a diffraction grating, to disperse light emitted from a laser emitter and to direct different wavelengths of the light toward a reflector at different spatial positions such that the wavelengths may be selected by allowing light to be reflected from selected spatial position(s) back into the laser emitter. Thus, the reflected light with a wavelength at the selected spatial position(s) is allowed to complete the laser cavity.
US09698564B1 Hybrid integrated MCM with waveguide-fiber connector
A multi-chip module (MCM) includes: an interposer, a photonic chip, an optical gain chip, and a waveguide-fiber connector. The photonic chip, which may be electrically coupled to the interposer, may be implemented using a silicon-on-insulator (SOI) technology, and may include an optical waveguide that conveys an optical signal. Moreover, the optical gain chip, which may be electrically coupled to the interposer, may include a III-V compound semiconductor, and may include a second optical waveguide that conveys the optical signal and that is vertically aligned with the optical waveguide relative to a top surface of the interposer. Furthermore, the waveguide-fiber connector may be mechanically coupled to the interposer, and remateably mechanically coupled to an optical fiber coupler that includes the optical fiber. The waveguide-fiber connector may convey the optical signal between the optical waveguide in the photonic chip and the optical fiber.
US09698563B2 Flexible LED device and method of making
Provided is a flexible light emitting semiconductor device, such as an LED device, that includes a flexible dielectric layer having first and second major surfaces with a conductive layer on the first major surface and at least one cavity in the first major surface with a conductive layer in the cavity that supports a light emitting semiconductor device. The conductive layer in the cavity is electrically isolated from the second major surface of the dielectric layer.
US09698554B2 Female terminal fabricating method
A female terminal includes a box portion which is formed into a quadrangular prism-like shape so as for a tab of a male terminal to fit therein by bending a copper alloy plate which is obtained by being continuously and repeatedly bent before an age heat treatment is applied thereto, which has a proof stress of 700 MPa or larger and a width of 10 mm or larger and in which no crack is produced therein when bent 180 degrees about a bending axis which is at right angle to a rolling direction of the copper alloy plate. The box portion comprises notches which are formed in inner sides of bent portions produced by bending the copper alloy plate. A depth of the notch is set to be in the range from ¼ to ½ of a thickness of the copper alloy plate.
US09698550B2 Electrical power outlet housing assembly
An electrical power outlet housing assembly is provided for mounting electrical and/or data outlets in a work area or the like. The housing assembly includes at least one outlet housing portion having an interior surface that is configured to support the electrical components of an electrical and/or data outlet. The outlet housing portion cooperates with a housing enclosure portion by filling an opening of the housing enclosure, where the housing enclosure and outlet housing portions cooperate with a housing base to define an interior cavity that receives the electrical or electronic components associated with the electrical or data outlets. The electrical components may be installed without any separate mechanical fasteners, and the housing components may be assembled with minimal use of separate fasteners.
US09698549B2 Connector port arrangement in an electronic device
An arrangement of connector ports for an electronic device, specifically for a weighing platform unit (1), includes a plurality of connector sockets (22, 23, 25, 26) which are installed in one or more walls of a chassis (4) thereof. The one or more walls that carry the connector sockets are interior partitioning walls that define a connector port compartment (20) inside the chassis. Furthermore, at least one wall section of the connector port compartment is an exterior wall section of the chassis and contains a passage opening (21). Electrical cables (30) that are terminated by plugs matching the connector sockets can be introduced into the connector port compartment through this passage opening.
US09698543B2 Fuse-equipped connector
A fuse-equipped connector (1) is configured in combination of a first connector (10) and a second connector (30) which can be assembled to each other in an attachable and detachable state. The first connector (10) includes a first terminal (13) electrically connected to an external apparatus (50) and a connection portion (12a) mechanically connectable to the external apparatus (50). The second connector (30) includes a second terminal (33) electrically connected to the first terminal (13) and a fuse (35) being electrically connected to the second terminal (33). In a state where the first connector (10) and the second connector (30) are assembled with each other, the first terminal (13) and the second terminal (33) are electrically connected to each other.
US09698540B2 Cable connector assembly having internal metallic shield
A cable connector assembly includes: a printed circuit board (PCB) having a front end, a rear end, and an intermediate portion; a cable electrically connected to the rear end of the PCB; an inner metal member disposed about the intermediate portion of the PCB; an insulating member holding the inner metal member in position relative to the PCB; a metallic shield disposed around the insulating member; a front metal casing engaging the metallic shield; a rear metal casing surrounding a front of the cable and engaging the front metal casing; and an outer over-mold surrounding the front and rear metal casings.
US09698539B2 Connector, data transmitting apparatus, data receiving apparatus, and data transmitting and receiving system
To be able to further reduce deterioration in signal quality, there is provided a connector including: a signal pin (11) that is connected to a wiring pattern (15) on a mounted substrate (14) and that transmits a signal to an inside and an outside of any apparatus, the mounted substrate (14) having an end disposed in the apparatus; and a shell (13) that is formed of an electric conductor and grounded to ground potential on the mounted substrate (14), in a manner that the shell (13) covers the signal pin (11) in a region in which the signal pin (11) stretches toward the mounted substrate (14).
US09698538B2 Ribbon assembly and a communication system having a plurality of ribbon assemblies
Ribbon assembly includes first and second contact modules that each include signal and ground contacts that are configured to engage electrical contacts of a corresponding mating connector. The ribbon assembly also including a plurality of cables that are coupled to and extend between the first and second contact modules. The cables electrically couple the signal and ground contacts of the first contact module to the signal and ground contacts, respectively, of the second contact module. The cables extend parallel to one another and are coplanar at the first contact module and at the second contact module. The ribbon assembly also includes a cable organizer that is coupled to the plurality of cables at a location between and separate from the first and second contact modules. The cables extend parallel to one another and are coplanar as the cables extend through the cable organizer.
US09698537B2 Connector
A mating connector, that includes a mating ground portion, includes a holding member, a contact, a shell and a ground member. The holding member is formed of an insulating body defining a connection space, the contact has a contact point which is held by the holding member to be positioned in the connection space, the shell covers, at least in part, the holding member in a plane perpendicular to a front-rear direction, and the ground member is electrically connected with the shell and has a base portion positioned between the holding member and the shell. A ground spring extends from the base portion and a ground contact point to be connected to the mating ground portion, and has first, second and third springs. The third spring is inward of the second spring, and supports the ground contact point to project into the connection space.
US09698535B2 Connector system impedance matching
Connector inserts and receptacles that provide signal paths having desired impedance characteristics. One example may provide a connector system having a connector insert and a connector receptacle. Contacts in the connector insert may form signal paths with corresponding contacts in the connector receptacle. Additional traces in the connector insert and receptacle may be part of these signal paths. The signal paths may have a target or a desired impedance along their lengths such that the power paths electrically appear as transmission lines. Constraints on physical dimensions of the connector insert and connector receptacle contacts may result in variations in impedance along the signal paths. Accordingly, embodiments of the present invention may provide structures to reduce these variations, to compensate for these variations, or a combination thereof.
US09698530B1 Electronic apparatus having structures for fastening and protecting connectors
An electronic apparatus having structures for fastening and protecting connectors includes a main body and at least one transmission member. The main body includes an assembling portion, at least one connecting port and at least one retaining groove. The assembling portion is formed at one edge on a sidewall of the main body and has an installing surface and a setting surface. The connecting port is disposed on the installing surface of the assembling portion. The retaining groove is formed on the setting surface of the assembling portion and corresponds in position to the connecting port. The transmission member includes an output connector and a retaining block. The output connector is detachably plugged in the connecting port of the main body. The retaining block protrudes from one side of the output connector and is capable of being engaged in the retaining groove of the main body.
US09698526B2 Connector with aligning plate
A connector with an aligning plate, includes plural male terminals, a connector housing that houses the male terminals therein and is formed so that a counterpart connector is inserted thereinto, an aligning plate that is provided so as to be movable in an insertion direction of the counterpart connector into the connector housing. The connector housing includes a pair of provisional locking arms which hold the aligning plate at a provisional locking position, and the aligning plate includes provisional locking portions which engage with the pair of provisional locking arms. The connector housing and the aligning plate are provided with plural recesses and plural projections which are mutually engageable and which restrict a warp of the aligning plate in the insertion direction.
US09698525B2 Plug type connector
A plug connector is disclosed. The plug connector comprises a main housing with a cable connection end, an inner sleeve non-releasably arranged on the main housing, and an outer sleeve axially fitted over the inner sleeve.
US09698514B2 Connector
A connector (10) includes a female housing (20) for accommodating female terminals (24) and a retainer (40) mountable in female housing (20). The retainer (40) includes a retaining portion (41) that retains the female terminals (24) by being inserted into a retainer mounting hole (27) in the female housing (20). Locks (46) are adjacent to the retaining portion (41) in a direction intersecting an inserting direction of the retaining portion (41) while standing up from bases (45) integral to the retaining portion (41). The locks (46) resiliently deform by moving onto partial locking projections (30) and full locking projections (31) formed in the female housing (20), and resiliently restore to engage the partial locking projections (30) and the full locking projections (31). The lock pieces (46) are separated from the retaining portion (41).
US09698513B1 Force biased spring probe pin assembly
A force biased spring probe pin assembly includes a barrel member having a barrel wall defining an elongate internal cavity with a lower end and an upper end. The assembly also includes a first plunger member reciprocally mounted in the internal cavity proximate the lower end of the internal cavity. A spring member is positioned in the internal cavity between the plunger member and the second end of the internal cavity. Three or more conductive bearings are positioned in the internal cavity in contact with the first plunger member and the spring member. A force biased spring probe pin assembly includes a barrel member having a barrel wall defining an elongate internal cavity with a lower end and an upper end. The assembly also includes a first plunger member reciprocally mounted in the internal cavity proximate the lower end of the internal cavity and a second plunger member reciprocally mounted in the internal cavity proximate the upper end of the internal cavity. A spring member is positioned in the internal cavity between the first plunger member and the second plunger member. Three or more conductive bearings are positioned in the internal cavity in contact with the first plunger member and the spring member.
US09698508B2 Connector and substrate interconnection structure
A plug connector electrically connected to a socket connector includes a movable housing engaged with the socket connector; a fixed housing secured to a first substrate; and a plug terminal having a plug contact portion in electrical contact with the socket connector engaged with the movable housing, and a movable part configured to support the fixed housing such that the fixed housing can be displaced with respect to the movable housing in engaging and disengaging directions of the socket connector with respect to the movable housing, while maintaining the contact of the plug contact portion with the socket connector.
US09698506B2 Electric connection structure
An electric connection structure electrically connecting an electric device and a circuit board includes a connection terminal including a press-welded terminal portion welded to a device terminal of the electric device by pressing, and a press-fit terminal portion fitted in a through-hole of the circuit board by pressing. A direction of the pressing of the press-welded terminal portion against the device terminal is the same as a direction of the pressing of the press-fit terminal portion into the through-hole.
US09698503B2 Part of a conducting bar for an electrical apparatus
A part (11) of a conducting bar (5) for an electrical apparatus, such as a terminal block, the part (11) of the conductive bar (5) comprising a first planar portion extending along an extension direction (15) of the part (11) of the conducting bar (5), a second planar portion (23) extending along the extension direction (15), the extension plane (25) of the second portion (23) being transversal to the extension plane (21) of the first portion. The part (11) has a first cutout along a first contour arranged in the first portion and a second cutout along a second contour arranged in the first portion.
US09698501B2 Electrical shield connector
An electrical shield connector configured to be attached to an end of a shielded cable having a conductive wire and a shield conductor longitudinally surrounding the conductive wire. The shield connector includes a connection portion that is configured for connection with a corresponding mating electrical shield connector and a cable attachment portion that is configured to longitudinally receive an end of the shield conductor. The connection portion defines a shroud surrounding an electrical terminal attached to the conductive wire. The cable attachment portion and/or crimp wings projecting therefrom define a projection that is configured to contact and indent the shield conductor, thereby mechanically and electrically connecting the shield connector to the shield conductor. The cable attachment portion may also define a knurled pattern in an interior surface of the cable attachment portion, such as a knurled pattern having a number of rhomboid-shaped indentations.
US09698495B2 Reconfigurable MIMO and sensing antenna system
The reconfigurable MIMO and sensing antenna system combines a 2-element reconfigurable MIMO antenna system with a UWB element. The complete setup is suitable for CR platforms that require sensing UWB band availability. The design is planar in structure and includes a pair of PIFAs disposed on a dielectric substrate top surface. The UWB sensing element is disposed on the dielectric substrate bottom surface. An F-head portion of each PIFA has two arms extending to a longer peripheral edge of the substrate. An F-tail portion of each PIFA extends from the substrate's shorter peripheral edge. The two PIFAs are mirror images of each other. For each PIFA, three diode circuits include a PIN diode in combination with a varactor diode connected to and extending away from the F-tail portion of the PIFA, thereby creating separate radiating branches of the PIFA.
US09698490B2 Injection moldable cone radiator sub-reflector assembly
A dielectric cone radiator sub-reflector assembly for a reflector antenna with a waveguide supported sub-reflector is provided as a unitary dielectric block with a sub-reflector at a distal end. A waveguide transition portion of the dielectric block is dimensioned for insertion coupling into an end of the waveguide. A sub-reflector support portion of the dielectric block and the waveguide transition portion provided with a plurality of longitudinal ribs and grooves coaxial with a longitudinal axis of the assembly; the longitudinal grooves open to a proximal end of the dielectric block. The unitary dielectric block may be manufactured as a single contiguous monolithic portion of dielectric material via injection molding.
US09698488B2 Satellite antenna and waveguide filter thereof
A waveguide filter is provided. The waveguide filter includes a pipe and a first rib structure. The pipe includes a first inner wall. The first rib structure includes a first rib. The first rib is disposed in the pipe and formed on the first inner wall. The first rib includes a first section and a second section, wherein the first section and the second section extend on a first straight line and are perpendicular to the first inner wall, and a first gap is formed between the first section and the second section, and a first gap distance of the first gap is between 0.1 to 1.2 mm.
US09698487B2 Array antenna
In a multilayer substrate, eight front-side antenna portions and eight back-side antenna portions are disposed. Front-side radiation elements in the front-side antenna portions and back-side radiation elements in the back-side antenna portions are arranged in a staggered pattern when being vertically projected onto an back side of the multilayer substrate. The front-side radiation elements are disposed on a front side of the multilayer substrate, and a front-side ground layer is formed near the back side of the multilayer substrate. On the other hand, the back-side radiation elements are disposed on the back side of the multilayer substrate, and a back-side ground layer is formed near the front side of the multilayer substrate. The front-side radiation element and the back-side radiation element are disposed so as not to overlap each other when being vertically projected onto the back side of the multilayer substrate.
US09698480B2 Small antenna apparatus operable in multiple frequency bands
A first base radiation element has a first end connected to the feed point, and a second end. A second base radiation element has a first end connected to the ground point, and a second end. The first and second base radiation elements respectively include portions extending in a first direction and close to each other. The first base radiation element is branched into first and second branch radiation elements at a first branch point located at the second end of the first base radiation element, the first branch radiation element includes a portion extending in the first direction, and the second branch radiation element includes a portion extending in a second direction opposite to the first direction. The end of the second base radiation element is connected to a connecting point different from the first branch point of the first branch radiation element.
US09698477B1 Cell tower and method of use
A cell tower is manufactured from a steel plate that is pressed into a polygon form, such as a 12-sided polygon or a 16-sided polygon. The tower is designed for direct embedding into the ground or attachment to a buried portion. The base portion contains apertures sized to permit the installation of an equipment rack directly into the interior of the tower. Other apertures in the tower provide handholes for installation of the equipment, backup batteries, and cabling. The top section of the cell tower includes mounting members for one or more sets of cellular radio antennas and/or microwave antennas. The antennas, and associated remote radio units, are mounted to the top of the cell tower and are hidden from view by one or more shrouds. The shrouds provide a visible barrier, but have minimal impact on the radio frequency characteristics.
US09698472B2 Antenna device and wearable device comprising such antenna device
An antenna device for radio communications in a wearable device comprises a ground plate having an arc shape, a first antenna plate extending essentially parallel to the ground plate and connected thereto at a first end portion of the ground plate, the first antenna plate having a first feed terminal, and a second antenna plate extending essentially parallel to a the ground plate and connected thereto at a second end portion of the ground plate opposite to the first end portion of the ground plate, the second antenna plate having a second feed terminal. A gap is provided between the first antenna plate and the second antenna plate.
US09698471B2 Electronic device
An electronic device including a touch screen, a first back cover, a transmitting antenna and a receiving antenna is provided. The first back cover includes a frame and a cover body. The transmitting antenna is adjacent to an edge of the touch screen and has a feeding point for receiving a feeding signal. The receiving antenna is adjacent to the cover body of the first back cover and is electrically connected to a ground plane. The receiving antenna and the transmitting antenna are spaced apart by a coupling distance, and a signal from the receiving antenna is transmitted to the feeding point through the coupling distance and the transmitting antenna.
US09698470B2 Wireless terminal
A wireless terminal is disclosed. The wireless terminal includes a first antenna, a second antenna, a printed circuit board, a bracket, and a resonator, where the first antenna is located at one side of the printed circuit board, the second antenna is located at another side of the printed circuit board, the printed circuit board functions as a metal ground of the first antenna and the second antenna, the resonator is located on the bracket, a ground point of the resonator is located on the printed circuit board, and a clearance exists between the resonator and the printed circuit board. Not only does the wireless terminal improve isolation between multiple antennas, but also the resonator can better radiate energy of the antennas because a clearance exists between the resonator and the PCB.
US09698468B2 Mobile wireless device with multi-band antenna and related methods
A mobile wireless communications device may include a portable housing, and a printed circuit board (PCB) carried by the housing and having opposing upper and lower portions. The device may also include at least one wireless transceiver carried by the portable housing, and a satellite positioning signal receiver carried by the portable housing. An antenna assembly may be carried adjacent the upper portion of the PCB. The antenna assembly may include a horizontal conductor extending along the upper portion of the PCB in spaced relation therefrom. The horizontal conductor may be coupled to the satellite positioning receiver. The antenna assembly may also include a loop conductor extending from the horizontal conductor toward the lower portion of the PCB and in spaced relation from the PCB. The loop conductor may be coupled to the wireless transceiver.
US09698466B2 Radiating structure formed as a part of a metal computing device case
A metal computing device case includes one or more metal side faces bounding at least a portion of the metal back face. The metal computing device case includes a radiating structure including an exterior metal surface of the metal computing device case. The metal computing device case substantially encloses electronics of a computing device. The exterior metal surface is a metal plate insulated from the rest of the metal computing device case by a dielectric insert filling slots between the metal plate and the rest of the metal computing device case. The radiating structure also includes a ceramic block spaced from a metal plate by a dielectric spacer. The metal plate is insulated from the rest of the metal computing device case and is capacitively coupled with the ceramic block.
US09698465B1 Communications-tower antenna mount
An antenna mount for mounting radio antennas on a communications tower is described. The antenna mount includes a ring structure that encircles the tower and includes a channel disposed about its outer perimeter. The channel is configured to receive a plurality of antenna carriages upon which antennas are mounted on a first end. A second end of the antenna carriage is disposed in the channel and is slideably movable along the length of the channel about the perimeter of the ring structure. The antenna is thus aimable in any desired azimuthal direction by moving the antenna along the ring structure. Bands for communication of data, power, control signaling, and propulsion of the antenna carriages about the ring structure are disposed in the channel. The ring structure may include a junction that allows reorientation of antennas with respect to one another.
US09698464B2 Transmission line and electronic component
A transmission line is provided with a line portion with a first relative permittivity which is composed of a first dielectric and a conductor filler dispersed in the first dielectric, and a surrounding dielectric portion composed of a second dielectric with a second relative permittivity, wherein, the surrounding dielectric portion exists around the line portion in a cross section perpendicular to a direction in which electromagnetic waves transmit in the line portion, the first relative permittivity is 600 or more, and the second relative permittivity is smaller than the first relative permittivity. An electronic component has the transmission line. Further, an electronic component is provided with a resonator having a resonant frequency ranging from 1 GHz to 10 GHz, wherein, the resonator is formed by using the transmission line.
US09698463B2 Adjustable power divider and directional coupler
A power divider including an input port receiving an electrical power input, a coupled port transmitting a portion of the power input, and a transmitted port transferring a remaining portion of the power input from the input port. A first conductor produces an electrical field and electrically connects the input port to the transmitted port. And, a second conductor, disposed within electrical field of the first conductor, electrically connects to the coupled port, the second conductor. The first and second conductors are configured to be variably spaced to vary the coupling factor between the input and transmitted portions of the input power.
US09698461B2 Resonant coupler
A resonant coupler includes, on the main surface of a first dielectric substrate: a first resonant line disposed in a circumferential shape and having proximate first and second ends; an input line into which a signal is inputted; and a first connecting line that grounds a first end of the first resonant line, and, similar to the first dielectric substrate, includes, on the main surface of a second dielectric substrate: a second resonant line; an output line; and a second connecting line. When viewed in a direction perpendicular to the main surface of the first dielectric substrate, the first resonant line and the second resonant line have substantially matching contours, and the first resonant line and the second resonant line have a combined shape that is symmetrical about a line.
US09698458B2 UWB and IR/optical feed circuit and related techniques
A radio frequency (RF) module having a plurality of channels includes a heat sink having at least one tapered edge; a substrate disposed over a surface of the heat sink such that the tapered edge of the heat sink extends past a boundary of the substrate. RF, logic and power circuitry is disposed on the substrate and one or more RF signal ports are formed on an edge of the substrate to allow the RF module to be used in an array antenna having a brick architecture. The tapered edge heat sink provides both a ground plane for RF signal components and a thermal path for heat generating circuits disposed in the substrate.
US09698451B2 Using reference electrodes to manage batteries for portable electronic devices
The disclosed embodiments provide a system that manages use of a battery in a portable electronic device. During operation, the system uses a reference electrode in the battery to monitor an anode potential of an anode in the battery during charging of the battery in the portable electronic device. If the anode potential falls below an anode potential threshold, the system modifies a charging technique for the battery to extend a cycle life of the battery. For example, the system may reduce a charge current of the battery if the anode potential falls below the anode potential threshold to prevent degradation caused by a negative anode potential during charging of the battery.
US09698448B2 Electrolytes for magnesium electrochemical cells
An electrochemical cell includes a high voltage cathode configured to operate at 1.5 volts or greater; an anode including Mg0; and an electrolyte including an ether solvent and a magnesium salt; wherein: a concentration of the magnesium salt in the ether is 1 M or greater.
US09698447B2 Use of lithium bis(fluorosulfonyl) imide (LiFSI) in non-aqueous electrolyte solutions for use with 4.2v and higher cathode materials for lithium ion batteries
This invention relates to electrolytic solutions and secondary batteries containing same. The electrolytic solutions contain lithium bis (fluorosulfonyl) imide and asymmetric borates, asymmetric phosphates and mixtures thereof.
US09698444B2 Nonaqueous electrolyte composition, nonaqueous electrolyte secondary battery, and method for manufacturing nonaqueous electrolyte secondary battery
A nonaqueous electrolyte composition includes an electrolyte salt, a nonaqueous solvent, a matrix polymer, and a ceramic powder, wherein the ceramic powder has an average particle size of 0.1 to 2.5 μm and a BET specific surface area of 0.5 to 11 m2/g.
US09698441B2 Fuel cell module
A fuel cell module includes a fuel cell stack and FC peripheral equipment. The FC peripheral equipment includes an evaporator. At least one of evaporation pipes of the evaporator connects a water vapor discharge chamber and an inlet of a reformer to form an evaporation return pipe as a passage of water vapor. A raw fuel pipe is inserted into the evaporation return pipe for allowing a raw fuel to flow from the downstream side to the upstream side of the evaporation return pipe.
US09698433B2 Fuel cell
A fuel cell includes a membrane electrode assembly, a separator, and a sealing member. The sealing member is provided on a separator surface and includes a base seal portion, a protruding seal portion, a first recessed portion, and a second recessed portion. The protruding seal portion protrudes from the base seal portion in a stacking direction so as to block leakage of at least one of a fuel gas, an oxidant gas, and a coolant which flow along the separator surface. The first recessed portion is disposed on a first side of the protruding seal portion. The second recessed portion is disposed on a second side of the protruding seal portion opposite to the first recessed portion. The first recessed portion and the second recessed portion have a height in the stacking direction smaller than a height of the base seal portion in the stacking direction.
US09698429B2 Fuel cell and method of manufacturing same
The present application relates to a fuel cell and a method of manufacturing the same.
US09698414B2 Non-aqueous electrolyte secondary battery and method of manufacturing the same
A non-aqueous electrolyte secondary battery includes a positive electrode composite material layer containing first positive electrode active material particles containing a lithium nickel composite oxide, second positive electrode active material particles containing lithium iron phosphate, and a conductive material. A ratio of the second positive electrode active material particles in a total mass of the first positive electrode active material particles and the second positive electrode active material particles is not lower than 5 mass % and not higher than 20 mass %. A standard deviation σ representing distribution of an iron element satisfies a condition of 0.28≦σ≦0.52 when distribution of the iron element is determined by conducting area analysis with an electron probe microanalyzer in a cross-section of the positive electrode composite material layer.
US09698413B2 High-capacity cathode active material and lithium secondary battery including the same
Provided are a cathode active material having high capacity and excellent lifetime characteristics as well as being inexpensive by mixing transition metal oxide having high irreversible capacity with composite dimensional manganese oxide (CDMO) of the following Chemical Formula 1, which has high capacity and good lifetime characteristics but is difficult to be charged and discharged by being used alone, and a lithium secondary battery including the cathode active material: xMnO2.(1−x)Li2MnO3 (0
US09698411B2 Electrode for battery and production method thereof, nonaqueous electrolyte battery, battery pack, and active material
According to one embodiment, there is provided an electrode for battery which includes a current collector and an active material layer provided on the current collector. The active material layer contains particles of a lithium titanate compound having a spinel structure and a basic polymer. Here, the basic polymer is coating at least a part of the surface of the particles of the lithium titanate compound.
US09698409B2 Injection method for injecting electrolyte and injection apparatus therefor
[Object] It is an object to provide an injection method for injecting an electrolyte and an electrolyte injection apparatus which allow the electrolyte to be injected and filled into an electrode assembly within an outer can with favorable permeation, thereby easily manufacturing an electrolyte secondary battery having favorable cycle characteristics at good yield.[Solution] A solution injection nozzle 10 is inserted into a solution injection hole 101 of an outer can 100 in which an electrode assembly 110 is stored, and the solution injection hole 101 is hermetically sealed by a pressure reducing pad 11 provided so as to surround a periphery of the solution injection nozzle 10. An inside of the outer can 100 is made into a negative pressure through the pressure reducing pad 11, and an electrolyte L is supplied from the solution injection nozzle 10 into the outer can 100. The outer can 100 is rotated with the solution injection nozzle 10 as a rotation center.
US09698407B2 Rechargeable battery
A rechargeable battery includes an electrode assembly including a first electrode and a second electrode; a case for accommodating the electrode assembly; a cap plate in an opening of the case to seal the case, including a terminal hole, and connected to the first electrode through a lead tab; and first and second electrode terminals electrically coupled to the electrode assembly and protruding away from the cap plate, the first electrode terminal including plurality of lead terminals connected to the cap plate, and a plate terminal supported by the plurality of lead terminals to be spaced apart from the cap plate.
US09698403B2 High current interconnect system and method for use in a battery module
A printed circuit board (PCB) assembly includes a PCB and a high current interconnect mounted on the PCB. The high current interconnect is configured to electrically couple a first high current bladed component, a second high current bladed component, and a trace disposed on the PCB. The high current interconnect includes feet made of a conductive material that are coupled to the PCB. The trace is coupled to the feet via a weld.
US09698402B2 Method of welding a bus bar to battery cell terminals
A method of welding a bus bar to battery cell terminals to produce a bus bar clip assembly. A bus bar is provided with spring clips. The clips fit over the battery terminals and hold the bus bar and terminals in contact for welding the components together.
US09698400B2 Non-aqueous electrolyte secondary battery
The present invention provides a non-aqueous electrolyte secondary battery having an electrode body formed by stacking a positive electrode, a separator and a negative electrode and a non-aqueous electrolyte. The separator has a separator substrate made and a first porous heat resistance layer formed on a surface of the substrate on a side facing the positive electrode. A surface of the negative electrode on a side facing the separator is formed by a second porous heat resistance layer. The first and second porous heat resistance layers satisfy: (1) an average thickness of the first porous heat resistance layer is greater than that of the second porous heat resistance layer; (2) an average particle diameter of an inorganic filler contained in the first porous heat resistance layer is greater than that of an inorganic filler contained in the second porous heat resistance layer.
US09698399B2 Organic-inorganic composite layer for lithium battery and electrode module
An organic-inorganic composite layer for a lithium battery includes an organic polymer and a plurality of composite inorganic particles. The weight ratio of the organic polymer to the composite inorganic particles is 10:90 to 95:5, wherein the composite inorganic particles have at least two structural configurations stacked in staggered configuration.
US09698395B2 Energy storage apparatus
An energy storage apparatus includes one or more energy storage devices and an outer housing that houses the one or more energy storage devices. The outer housing includes a communication part defining a passageway allowing communication between an interior and an exterior of the outer housing, and the communication part includes a functional membrane that allows passage of gas and prohibits passage of liquid.
US09698391B2 Power storage device
A power storage device includes a plurality of power storage modules, a first connecting plate, and a second connecting plate. Each of the plurality of power storage modules includes a plurality of power storage cells, a first end plate, and a second end plate. The first end plate includes a first main plate and a first sub-plate. The first sub-plate includes a first securing hole. The first main plate and the first sub-plate are provided to be connected to each other in at least two positional relationships with different positions of the first securing hole. The first connecting plate includes a first reference securing hole aligned with the first securing hole. The first securing hole is secured to the first reference securing hole by a first securing member.
US09698390B2 Extremely deformable structure and lithium secondary battery made therefrom
The present disclosure relates to an extremely deformable structure comprising a basic displacement unit having an embedded form, in which m polygonal basic unit cells are disposed adjacent to each other, m separation parts are formed among the m basic unit cells, a junction part connecting the basic unit cells to each other is formed between the basic unit cells in which the junction part has a junction part pattern in which an external junction part disposed at the outer portion of the basic unit cell and an internal junction part which is not in contact with the outer portion of the basic unit cell are sequentially repeated, and the relative positions of the m basic unit cells are changed according to the junction part pattern, and thus, are activated (here, m is an integer of 4 or 6). Further, the present disclosure relates to a lithium secondary battery made from the extremely deformable structure.
US09698389B2 Method of producing organic EL device
A method of producing an organic EL device includes forming an organic EL element including a pixel electrode, a functional layer, and a counter electrode over a substrate, forming a cathode protective layer over the organic EL element, forming a cover layer over the cathode protective layer, forming an organic buffer layer over the cover layer, and forming a gas barrier layer over the organic buffer layer.
US09698386B2 Functionalization of a substrate
A method of increasing a work function of an electrode is provided. The method comprises obtaining an electronegative species from a precursor using electromagnetic radiation and reacting a surface of the electrode with the electronegative species. An electrode comprising a functionalized substrate is also provided.
US09698382B2 Organic light emitting element with increased efficiency of extracting blue light
Each of blue light emitting elements includes: a photoanode; a translucent cathode; an organic light emitting layer between the photoanode and the translucent cathode; a first functional layer between the organic light emitting layer and the photoanode; and a second functional layer between the organic light emitting layer and the translucent cathode, and has a resonator structure. The first functional layer has an optical film thickness of 48-62 nm. The translucent cathode is a stack of a first translucent conductive layer, a metal layer, and a second translucent conductive layer stacked in this order from the second functional layer side. The first translucent conductive layer has a refractivity of 2.0-2.4, and a film thickness of 85-97 nm. The metal layer has a refractivity different by 0 to 2.0 from that of the first translucent conductive layer, and has a film thickness of 2-22 nm.
US09698378B2 Encapsulation film
Provided are an encapsulating film, an electronic device and a method of manufacturing the same. An encapsulating film having excellent moisture blocking property, handleability, workability and durability and a structure including a diode encapsulated with the encapsulating film may be provided.
US09698373B2 Photoelectric device comprising the barrier film layer
A barrier film layer, a photoelectric device comprising the barrier film layer and a manufacturing method of the photoelectric device are provided. A material forming the barrier film layer includes a topological insulator, and the barrier film layer is formed on a surface of an base plate which is patterned. In this way, a better package of the photoelectric device can be achieved.
US09698370B2 Gas barrier film and gas barrier film production method
The present invention is aiming to provide a gas barrier film having excellent gas barrier properties and also having superior transparency and the like, and an efficient method for producing such a gas barrier film.The present invention provides a gas barrier film having a gas barrier layer on a base material, and a method for producing such a gas barrier film, in which the gas barrier layer includes, from the surface side toward the base material side, a first region and a second region having different refractive indices, the value of the refractive index in the first region is adjusted to a value within the range of 1.50 to 1.68, and the value of the refractive index in the second region is adjusted to a value within the range of 1.40 to below 1.50.
US09698367B2 Flexible electrode and method for manufacturing the same, electronic skin and flexible display device
The present disclosure relates to a flexible electrode and a method for manufacturing the same, an electronic skin and a flexible display device, the conductive polymer is solution treated by the ionic liquid, the nano-metal material is added to the solution treated conductive polymer to form the dispersed liquid of the conductive polymer containing the nano-metal material, the dispersed liquid is transferred to the substrate for curing to obtain the flexible electrode. The flexible electrode makes use of the flexible property of the conductive polymer such that the formed flexible electrode has good ductility and resilience. And the nano-metal material is dispersed in the conductive polymer such that the nano-metal material remedies the defect of low conductive property of the conductive polymeric material, and the flexible electrode has good conductivity.
US09698362B2 Rollable organic light emitting display system
Disclosed is a rollable organic light emitting display system capable of protecting an organic light emitting display device from an external impact. The rollable organic light emitting display system has an organic light emitting diode layer between two substrates, wherein the two substrates are capable of being rolled or unrolled, includes a protection film covering a lateral surface of at least one of the substrates so as to prevent the lateral surface of the at least one substrate from being damaged by an external impact when the two substrates are unrolled and the lateral surface of the two substrates is exposed to the external.
US09698361B2 Organic EL panel translucent substrate, control method for refractive index anisotropy of organic EL panel translucent substrate, manufacturing method for organic EL panel translucent substrate, organic EL panel, and organic EL device
Disclosed is an organic EL panel translucent substrate that can prevent or reduce the color gap/coloring of an organic EL panel. In order to achieve the above object, organic EL panel translucent substrate 201 is formed of resins 203 and 204 and is substantially optically isotropic in its in-plane direction and thickness direction.
US09698360B2 Package thin film and manufacturing method thereof, light emitting device, display panel and display device
A package thin film and a manufacturing method thereof, a light emitting device, a display panel and a display device are provided. The package thin film may comprise: a nano material layer or a polycation organic material layer, a moisture absorption layer formed on the nano material layer or the polycation organic material layer, a sealing layer for sealing the nano material layer or the polycation organic material layer and the moisture absorption layer. The package structure provided by embodiments of the present invention is formed by alternate assembly of materials (the nano material layer or the polycation organic material layer and the moisture absorption layer) with different charges.
US09698356B2 Heteroaryl-based compound and organic light-emitting diode including the same
In an aspect, an organic compound and an organic light-emitting diode (OLED) including the same are provided.
US09698353B2 Light-emitting element, light emission apparatus, authentication apparatus, and electronic machine
A light-emitting element includes an anode, a cathode, and a light emission layer. The light emission layer is arranged between the anode and the cathode and configured to emit light by energization between the anode and the cathode. The light emission layer includes a compound represented by a general formula NIR-D as a light emission material and a compound represented by a formula IRH-1 as a host material of the light emission material. The general formula NIR-D is in which each R independently indicates group comprising a phenyl group, a thiophenyl group, a furyl group, or at least one species of derivatives thereof. The formula IRH-1 is in which n indicates a natural number 1 to 12, and each R independently indicates a hydrogen atom, an alkyl group, an optionally substituted aryl group, or an arylamino group.
US09698348B2 Polymers based on fused diketopyrrolopyrroles
The present invention relates to polymers comprising one or more (repeating) unit(s) of the formula (I), wherein Y is a group of formula (II); and their use as IR absorber, organic semiconductor in organic devices, especially in organic photovoltaics and photodiodes, or in a device containing a diode and/or an organic field effect transistor. The polymers according to the invention can have excellent solubility in organic solvents 10 and excellent film-forming properties. In addition, high efficiency of energy conversion, excellent field-effect mobility, good on/off current ratios and/or excellent stability can be observed, when the polymers according to the invention are used in organic field effect transistors, organic photovoltaics and photodiodes.
US09698346B2 Thermally optimized phase change memory cells and methods of fabricating the same
A thermally optimized phase change memory cell includes a phase change material element disposed between first and second electrodes. The second electrode includes a thermally insulating region having a first thermal resistivity over the first electrode and a metallic contact region interposed between the phase change material element and the thermally insulating region, where the metallic contact layer has a second thermal resistivity lower than the first thermal resistivity.
US09698345B2 Method, system, and device for phase change memory switch wall cell with approximately horizontal electrode contact cross references
Embodiments disclosed herein may include depositing a storage component material over and/or in a trench in a dielectric material, including depositing the storage component material on approximately vertical walls of the trench and a bottom of the trench. Embodiments may also include etching the storage component material so that at least a portion of the storage component material remains on the approximately vertical walls and the bottom of the trench, wherein the trench is contacting an electrode and a selector such that storage component material on the bottom of the trench contacts the electrode.
US09698343B2 Semiconductor device structures including ferroelectric memory cells
A method of forming a ferroelectric memory cell. The method comprises forming an electrode material exhibiting a desired dominant crystallographic orientation. A hafnium-based material is formed over the electrode material and the hafnium-based material is crystallized to induce formation of a ferroelectric material having a desired crystallographic orientation. Additional methods are also described, as are semiconductor device structures including the ferroelectric material.
US09698338B2 Magnetic memory device and method of manufacturing magnetic memory device
According to one embodiment, a method of manufacturing a magnetic memory device includes a stack structure formed of a plurality of layers including a magnetic layer, the method includes forming a lower structure film including at least one layer, etching the lower structure film to form a lower structure of the stack structure, forming an upper structure film including at least one layer on a region including the lower structure, and etching the upper structure film to form an upper structure of the stack structure on the lower structure.
US09698331B2 Thermoelectric heat exchanger
The invention relates to a thermoelectric heat exchanger, comprising two pipes, wherein a first pipe encloses a second pipe. In a thermoelectric heat exchanger which has a high level of efficiency, a thermoelectric material unit is arranged between the first and second pipes, preferably without mechanical contact with said first and second pipes, and a first fluid flows around the first pipe from the outside, while a second fluid flows through the second pipe.
US09698323B2 Frame based package for flip-chip LED
A hollow frame is configured to surround the periphery of a substantially self-supporting flip-chip light emitting device. The frame may be shaped to also contain a wavelength conversion element above the light emitting surface of the light emitting device. The lower surface of the light emitting device, which is exposed through the hollow frame, includes contact pads coupled to the light emitting element for surface mounting the light emitting module on a printed circuit board or other fixture. The flip-chip light emitting device may include a patterned sapphire substrate (PSS) upon which the light emitting element is grown, the patterned surface providing enhanced light extraction from the light emitting element, through the patterned sapphire substrate.
US09698322B2 Lighting device and method of making lighting device
A lighting device comprises a solid state light emitter on a circuit board, and an optic held in place relative to the first circuit board, a voltage drop across the emitter at least 60 volts. A lighting device comprises a solid state light emitter on a first circuit board, an optic held in place relative to the first circuit board, and a non-isolated power supply. A lighting device comprises a solid state light emitter on a first circuit board, and a flame-rated optic held in place relative to the first circuit board. An optic, comprising a translucent region, a first dimension not larger than about 10 mm, a second dimension not larger than 15 mm. A flame-rated optic comprising a translucent region, structure configured to hold the optic in place relative to a circuit board. Methods of making lighting devices.
US09698319B2 LED package with lead terminals having protrusions of differing widths and method for fabricating the same
A light emitting diode (LED) package according to an exemplary embodiment of the present invention includes a base including a first lead terminal and a second lead terminal, an LED chip disposed on the base, a housing disposed on the base, the housing having a cavity in which the LED chip is disposed, and an encapsulation member having a side surface contacting the housing. The first lead terminal and the second lead terminal each have a first surface and a second surface opposite the first surface, and have an unbent form, respectively. The second surface is exposed to the outside of the LED package.
US09698310B2 Method for producing a semiconductor device
The present invention provides a method for producing a semiconductor device exhibiting the improved emission efficiency by reducing a strain between a p-contact layer and a transparent electrode. A transparent electrode made of IZO (Zinc-doped Indium Oxide) was formed on a p-type contact layer by vapor deposition or sputtering. Subsequently, a p-type cladding layer and a p-type contact layer were p-type activated and a transparent electrode was crystallized by indirect resistance heating. This heat treatment was performed under a reduced pressure at a temperature of 700° C. Next, microwave heating was performed for three to thirty minutes at a temperature of 100° C. to 350° C. by microwave irradiation with a frequency of 5.8 GHz in a nitrogen atmosphere. This reduced a strain of the transparent electrode, and improved the conductivity or translucency of the transparent electrode.
US09698307B2 Light emitting device
A side-view type light emitting device having a bottom surface thereof as a light emission surface and one side surface thereof as amounting surface for mounting on amounting substrate includes a stacked semiconductor layer having a first semiconductor layer, an active layer, and a second semiconductor layer which are stacked in that order from a side of the bottom surface; a first connecting electrode exposed from the one side surface and electrically connected to the first semiconductor layer; a metal wire having one end thereof electrically connected to an upper surface of the second semiconductor layer; a second connecting electrode exposed from the one side surface and electrically connected to the other end of the metal wire; and a resin layer which covers at least a part of each of the first semiconductor layer, the second semiconductor layer, the first connecting electrode, the second connecting electrode and the metal wire and which is configured to form an upper surface and side surfaces of the light emitting device.
US09698306B2 Large emission area light-emitting devices
Light-emitting devices, and related components, systems and methods are disclosed.
US09698304B2 Lighting system
A lighting system includes a lighting unit comprising at least one lighting device, a sensing unit configured to measure at least one of atmospheric temperature and humidity, a controlling unit configured to compare the at least one of the temperature and the humidity measured by the sensor unit with set values and determine a color temperature of the lighting unit as a result of the comparison, and a driving unit configured to drive to the lighting unit to have the determined color temperature.
US09698303B2 Light-emitting device and manufacturing method thereof
A light-emitting device is disclosed. The light-emitting diode device includes a substrate, comprising an upper surface, a lower surface and a plurality of side surfaces; and a semiconductor stack formed on the upper surface of the substrate; wherein the plurality of side surfaces comprises: a first region, adjacent to the upper surface and having a first surface roughness; a second region, comprising one or a plurality of textured areas substantially parallel to the upper surface and/or the lower surface in a side view, wherein the textured area is composed of a plurality of textured stripes and has a second surface roughness; and a third region, having a third surface roughness and being between the first region and the second region, and/or between the plurality of textured areas; wherein the first surface roughness is smaller than the second surface roughness, and the third surface roughness is smaller than the first surface roughness.
US09698299B2 Integrated circuit combination of a target integrated circuit and a plurality of thin film photovoltaic cells connected thereto using a conductive path
A device having a plurality of thin film photovoltaic cells (PV) formed over a passivation layer. The device comprises a plurality of thin film photovoltaic (PV) cells formed over the passivation layer, each PV cell includes at least a lower conducting layer (LCL) and an upper conducting layer (UCL); and a conducting path connecting at least a UCL of a first PV cell to at least a LCL of a second PV cell, wherein at least a first array of PV cells comprised of at least a first portion of the plurality of PV cells is connected by the respective UCL and LCL of each PV cell to provide a first voltage output. In an embodiment the passivation layer is formed over a target integrated circuit (TIC), the TIC having a top surface and a bottom surface.
US09698298B2 Solar battery module and manufacturing method therefor
A solar battery module and manufacturing method for a solar battery module having improved output are provided. The solar battery module 1 is a transparent substrate 10, transparent resin layer 13b, solar battery cell 12, colored resin layer 13a and back sheet 11 laminated in this order. The light-receiving surface 12a of the solar battery cell 12 faces the transparent resin layer 13b side. The backside 12b of the solar battery cell faces the colored resin layer 13a. The MFR [melt flow rate] of the transparent resin layer 13b is lower than the MFR of the colored resin layer 13a.
US09698296B2 Compensated photonic device structure and fabrication method thereof
Various embodiments of a compensated photonic device structure and fabrication method thereof are described herein. In one aspect, a photonic device may include a substrate and a functional layer disposed on the substrate. The substrate may be made of a first material and the functional layer may be made of a second material that is different from the first material. The photonic device may also include a compensation region formed at an interface region between the substrate and the functional layer. The compensation region may be doped with compensation dopants such that a first carrier concentration around the interface region of function layer is reduced and a second carrier concentration in a bulk region of functional layer is reduced.
US09698289B2 Detachment of a self-supporting layer of silicon <100>
A method for detaching a self-supporting layer of silicon of crystalline orientation <100>, particularly with the aim of applications in the field of photovoltaics, wherein the method includes the steps of: a) Implanting ionic species in a substrate made of silicon having a crystalline orientation <100> so as to create an embrittlement plane in the substrate, delimiting on both sides a self-supporting layer and a negative of the substrate, and b) Applying a heat treatment to the substrate implanted at step a) with a temperature ramp greater than 30° C./s so as to detach the self-supporting layer of silicon.
US09698288B2 Photoelectric conversion device
In order to improve the photoelectric conversion efficiency of a photoelectric conversion device, this photoelectric conversion device is provided with an electrode layer, a first semiconductor layer that is positioned on the electrode layer and contains a polycrystalline semiconductor, and a second semiconductor layer that is positioned on/above the first semiconductor layer and forms a p-n junction with the first semiconductor layer, and an average grain diameter of crystal grains in the first semiconductor layer is larger near the surface on the electrode layer side of the first semiconductor layer than the center of the first semiconductor layer in a thickness direction of the first semiconductor layer. Furthermore, the average grain diameter of the crystal grains in the first semiconductor layer is larger in a surface portion on the second semiconductor layer side of the first semiconductor layer than in the central portion.
US09698285B2 Photovoltaic device including a P-N junction and method of manufacturing
A photovoltaic device includes a substrate structure and a p-type semiconductor absorber layer, the substrate structure including a CdSSe layer. A photovoltaic device may alternatively include a CdSeTe layer. A process for manufacturing a photovoltaic device includes forming a CdSSe layer over a substrate by at least one of sputtering, evaporation deposition, CVD, chemical bath deposition process, and vapor transport deposition process. The process includes forming a p-type absorber layer above the CdSSe layer.
US09698279B2 Thin film transistor array substrate, organic light-emitting display apparatus, and method of manufacturing the thin film transistor array substrate
Provided is a thin film transistor including an active layer including a first silicon active layer, a second silicon active layer, and an oxide active layer in a space between the first silicon active layer and the second silicon active layer, a gate electrode on the active layer with a gate insulating layer disposed therebetween, and a source electrode and a drain electrode with an interlayer insulating layer disposed between the gate electrode and the source and drain electrodes, the source and drain electrodes being in contact with the first silicon active layer and the second silicon active layer, respectively.
US09698278B2 Thin film transistor and manufacturing method thereof, array substrate, display device
There are provided a thin film transistor and a manufacturing method thereof, an array substrate, a display device. The manufacturing method includes forming a gate electrode, a gate insulating layer, a metal oxide semiconductor active layer, a source electrode and a drain electrode on a substrate. The forming the metal oxide semiconductor active layer includes forming a zinc oxide-based binary metal oxide pattern layer on a substrate. The pattern layer includes a first pattern, a second pattern and a third pattern. Metal doping ions are implanted into the zinc oxide-based binary metal oxide pattern layer by using an ion implantation technology, so that a binary metal oxide of the third pattern is transformed into a multi-element metal oxide semiconductor, and the metal oxide semiconductor active layer is formed.
US09698276B2 Semiconductor device, module, and electronic device
Provided is an element with stable electrical characteristics or a device including plural kinds of elements with stable electrical characteristics. The semiconductor device includes a first insulator, a transistor over the first insulator, a second insulator over the transistor, and a third insulator over the second insulator. The second insulator includes an opening reaching the first insulator. The opening is filled with a fourth insulator. The first insulator, the third insulator, and the fourth insulator each have a lower hydrogen-transmitting property than the second insulator.
US09698274B2 Semiconductor device comprising an oxide semiconductor, module, and electronic device
A transistor with stable electrical characteristics or a transistor with normally-off electrical characteristics. The transistor is a semiconductor device including a conductor, a semiconductor, a first insulator, and a second insulator. The semiconductor is over the first insulator. The conductor is over the semiconductor. The second insulator is between the conductor and the semiconductor. The first insulator includes fluorine and hydrogen. The fluorine concentration of the first insulator is higher than the hydrogen concentration of the first insulator.
US09698273B2 Thin film transistor, method of manufacturing the same, display unit, and electronic apparatus
A thin film transistor includes: a gate electrode and a pair of source-drain electrodes provided on a substrate; an oxide semiconductor layer provided between the gate electrode and the pair of source-drain electrodes, the oxide semiconductor layer forming a channel; a protection film provided over whole of a surface above the substrate; and a gate insulating film provided on a gate electrode side of the oxide semiconductor layer, the gate insulating film having end faces part or all of which are covered with the pair of source-drain electrodes or with the protection film.
US09698272B1 Transistor and semiconductor memory device
According to one embodiment, a transistor includes a first electrode, a second electrode, a current path between the first and second electrodes, the current path including an oxide semiconductor layer, a control terminal which controls an on/off action of the current path, an insulating layer between the control terminal and the oxide semiconductor layer, a first oxide layer between the first electrode and the oxide semiconductor layer, the first oxide layer being different from the oxide semiconductor layer, and a second oxide layer between the second electrode and the oxide semiconductor layer, the second oxide layer being different from the oxide semiconductor layer.
US09698267B2 Fin-type device system and method
A transistor is disclosed and includes forming a gate of a transistor within a substrate having a surface and a buried oxide (BOX) layer within the substrate and adjacent to the gate at a first BOX layer face. The method also includes a raised source-drain channel (“fin”), where at least a portion of the fin extends from the surface of the substrate, and where the fin has a first fin face adjacent to a second BOX layer face of the BOX layer.
US09698260B1 High voltage device with low Rdson
High voltage devices and methods for forming a high voltage device are disclosed. The method includes providing a substrate having top and bottom surfaces. The substrate is defined with a device region and a recessed region disposed within the device region. The recessed region includes a recessed surface disposed lower than the top surface of the substrate. A transistor is formed over the substrate. Forming the transistor includes forming a gate at least over the recessed surface and forming a source region adjacent to a first side of the gate below the recessed surface. Forming the transistor also includes forming a drain region displaced away from a second side of the gate. First and second device wells are formed in the substrate within the device region. The first device well encompasses the drain region and the second device well encompasses the source region.
US09698259B2 Semiconductor devices including patterns in a source region
Semiconductor devices are provided. A semiconductor device includes a substrate including a well region. The semiconductor device includes a source region in the well region. The semiconductor device includes a drain region. The semiconductor device includes a gate electrode that is between the source and drain regions, when viewed in a plan view. Moreover, the semiconductor device includes first and second patterns, in the source region, that are spaced apart from each other when viewed in the plan view.
US09698258B2 Semiconductor device
The present examples relate to a semiconductor device used in an electric device or high voltage device. The present examples improve Rsp by minimizing drift region resistance by satisfying breakdown voltage by improving the structure of a drift region through which current flows in a semiconductor device to provide optimal results. Moreover, a high frequency application achieves useful results by reducing a gate charge Qg for an identical device pitch to that of an alternative technology.
US09698254B1 Homoepitaxial tunnel barriers with functionalized graphene-on-graphene and methods of making
This disclosure describes a method of making a tunnel barrier-based electronic device, in which the tunnel barrier and transport channel are made of the same material—graphene. A homoepitaxial tunnel barrier/transport device is created using a monolayer chemically modified graphene sheet as a tunnel barrier on another monolayer graphene sheet. This device displays enhanced spintronic properties over heteroepitaxial devices and is the first to use graphene as both the tunnel barrier and channel.
US09698253B2 Semiconductor fin fabrication method and Fin FET device fabrication method
A semiconductor fin fabrication method includes: providing a substrate; selectively epitaxially growing a first mask layer in a predetermined zone on the substrate; selectively epitaxially growing a first epitaxial layer on the substrate by using the first mask layer as a mask; and removing the first mask layer and a part, under the first mask layer, of the substrate by using the first epitaxial layer as a mask and by using an anisotropic etching method, so as to form a fin under the first epitaxial layer. According to the foregoing solutions, a manner in which a selective epitaxial growth technology and an anisotropic etching technology are combined is used It can be ensured that a semiconductor fin and a surface of a gate oxidized layer are perpendicular to each other, roughness of a surface of the semiconductor fin is reduced, and a fin with a smooth side surface is formed.
US09698250B2 Method for the surface etching of a three-dimensional structure
A method for etching a dielectric layer located on the surface of a three-dimensional structure formed on a face of a substrate oriented along a plane of a substrate, which includes a step of implanting ions so as to directionally create a top layer in the dielectric layer. Such top layer is thus not formed everywhere. Then, the layer in question is removed, except on the predefined zones, such as flanks of a transistor gate. A selective etching of the dielectric layer is executed relative to the material of the residual part of the top layer and relative to the material of the face of the substrate.
US09698236B2 Semiconductor device and method for manufacturing the same
It is made possible to provide a method for manufacturing a semiconductor device that has a high-quality insulating film in which defects are not easily formed, and experiences less leakage current. A method for manufacturing a semiconductor device, includes: forming an amorphous silicon layer on an insulating layer; introducing oxygen into the amorphous silicon layer; and forming a silicon oxynitride layer by nitriding the amorphous silicon layer having oxygen introduced thereinto.
US09698235B2 Field-effect transistor
The present invention provides a field-effect transistor having an accumulation-layer-operation type field-effect transistor that includes a semiconductor layer in which a source region, a channel region, and a drain region that have either an N-type or P-type conductivity in common are formed, and a gate electrode disposed adjacent to the channel region via a gate insulating film, wherein the gate insulating film is made of a dielectric having a change gradient of a relative dielectric constant in which the relative dielectric constant changes to decrease according to the magnitude of a gate voltage applied to the gate electrode.
US09698233B2 Tunnel insulation layer structures, methods of manufacturing the same, and vertical memory devices including the same
Tunnel insulation layer structures and methods of manufacturing the same are disclosed. The tunnel insulation layer structures may include a first tunnel insulation layer, a second tunnel insulation layer, a third tunnel insulation layer, a fourth tunnel insulation layer and a fifth tunnel insulation layer. The first tunnel insulation layer on a substrate has a first band gap energy. The second tunnel insulation layer on the first tunnel insulation layer has a second band gap energy which is lower than the first band gap energy. The third tunnel insulation layer on the second tunnel insulation layer has a third band gap energy which is higher than the second band gap energy. The fourth tunnel insulation layer on the third tunnel insulation layer has a fourth band gap energy which is lower than the third band gap energy. The fifth tunnel insulation layer on the fourth tunnel insulation layer has a fifth band gap energy which is higher than the fourth band gap energy.
US09698231B2 Semiconductor devices
A semiconductor device includes a substrate, a tunnel insulation pattern on the substrate, a charge storage pattern on the tunnel insulation pattern, a dielectric pattern having a width smaller than a width of the charge storage pattern on the charge storage pattern, a control gate having a width greater than the width of the dielectric pattern on the dielectric pattern, and a metal-containing gate on the control gate.
US09698230B2 MOSFET with asymmetric self-aligned contact
A semiconductor device includes a source and drain on a substrate; a first and second gate on the source, and the second gate and a third gate on the drain; a source contact over the source and between the first and second gates, the source contact including first and second portions, the first portion in contact with the source and extending between the first and second gates, and the second portion contacting the first portion and extending over the first and second gates; and a drain contact formed over the drain and between the second and third gates, the drain contact including first and second portions, the first portion contacting the drain, extending between second and third gates, and recessed with respect to the first portion of the source contact, and the second portion in contact with the first portion and extending between and over the second and third gates.
US09698225B2 Localized and self-aligned punch through stopper doping for finFET
A method for doping punch through stoppers (PTSs) includes forming fins in a monocrystalline substrate, forming a dielectric layer at a base portion between the fins and forming spacers on sidewalls of the fins down to a top portion of the dielectric layer. The dielectric layer is recessed to form gaps between the top portion of the dielectric layer and the spacer to expose the fins in the gaps. The fins are doped through the gaps to form PTSs in the fins.
US09698224B2 Silicon germanium fin formation via condensation
A method of forming a finFET device comprises forming a fin in a silicon layer of a substrate, forming a hardmask layer on a top surface of the fin, forming an insulating layer over the fin and the hardmask layer, removing a portion of the insulating layer to expose a portion of the hardmask layer, removing the exposed portion of the hardmask layer to form a cavity that exposes a portion of the silicon layer of the fin, epitaxially growing a silicon germanium (SiGe) material on exposed portions of the silicon layer of the fin in the cavity, and annealing the grown SiGe to drive germanium atoms into the silicon layer of the fin.
US09698223B2 Memory device containing stress-tunable control gate electrodes
A memory film and a semiconductor channel are formed within each memory opening that extends through a stack including an alternating plurality of insulator layers and sacrificial material layers. After formation of backside recesses through removal of the sacrificial material layers selective to the insulator layers, electrically conductive layers are formed in the backside recesses. Each electrically conductive layer includes a combination of a tensile-stress-generating metallic material and a compressive-stress-generating metallic material. The tensile-stress-generating metallic material may be ruthenium and the compressive-stress-generating metallic material may be tungsten. An anneal may be performed to provide an alloy of the compressive-stress-generating metallic material and the tensile-stress-generating metallic material.
US09698222B2 Method of fabricating semiconductor structures on dissimilar substrates
Techniques are disclosed for forming a defect-free semiconductor structure on a dissimilar substrate with a multi-aspect ratio mask. The multi-aspect ratio mask comprises a first, second, and third layer formed on a substrate. The second layer has a second opening wider than a first opening and a third opening in the first and third layers, respectively. All three openings are centered along a common central axis. A semiconductor material is grown from the top surface of the substrate and laterally onto the top surface of the first layer within the second opening. The semiconductor material disposed within and vertically below the third opening is etched by using the third layer as an etch mask so that the remaining material that laterally overflowed onto the top surface of the first layer forms a remaining structure.
US09698220B2 Semiconductor device
A MOSFET includes: a SiC layer including one main surface and provided with a plurality of contact regions; and a plurality of source electrodes formed in contact with the contact regions. In the MOSFET, in a plan view of the one main surface, a plurality of cells including the contact regions and the source electrodes are formed adjacent to one another, each of the plurality of cells having an outer circumferential shape that is a shape of hexagon including a long axis. According to the MOSFET, a contact resistance between each contact region and each source electrode can be further reduced, thereby attaining a more improved electrical property.
US09698217B1 Semiconductor device
A semiconductor device of trench gate type is provided that has achieved both large on-current and high off-state breakdown voltage. Around trench T and between it and electric field relaxation p-layer 16, low resistance n-layer 17 is provided. Low resistance n-layer 17 is formed deeper than trench T, and shallower than electric field relaxation p-layer 16, being connected to n−-layer (drift layer) 12 just thereunder, and thus low resistance n-layer 17 and n−-layer 12 are integrated to form a drift layer. Although low resistance n-layer 17 is n-type as is n−-layer 12, donor concentration thereof is set higher than that of n−-layer 12, thereby low resistance n-layer 17 having a resistivity lower than that of n−-layer 12. This low resistance n-layer 17 is provided in on-current path (between electric field relaxation p-layer 16 and trench T), whereby low resistance n-layer 17 can lower the resistance to on-current.
US09698215B2 MIM capacitor formation in RMG module
A metal-insulator-metal capacitor is provided in a replacement metal gate module having a gate cap formed on a gate. The capacitor includes a first electrode formed within a portion of the gate using a metal forming the gate. The first electrode has a horizontal component and a stack rising from at least a portion of the horizontal component. The capacitor further includes an insulator formed within a recess. The recess is formed to have a lower portion and walls rising from edges of the lower portion. The lower portion is formed on a different portion of the horizontal component than the stack. The walls are formed adjacent to a sidewall of the stack and a portion of the gate cap. The capacitor also includes a second electrode formed within the recess and on the insulator.
US09698214B1 Capacitor structure of integrated circuit chip and method of fabricating the same
In accordance with some embodiments of the present disclosure, a capacitor structure of an integrated circuit chip includes an insulation layer, a first electrode, and a second electrode. The insulation layer includes an insulation partition and has a first trench and a second trench separated from the first trench by the insulation partition. The first electrode is disposed in the first trench. The second electrode is disposed in the second trench. The first electrode first electrode is arranged along a spiral trajectory and surrounds a spiral channel. The second electrode is disposed within the spiral channel.
US09698208B1 Array substrate, display panel and display apparatus having the same, and fabricating method thereof
The present application discloses an array substrate comprising a base substrate; and a plurality of rows of pixel units and a plurality of rows of reset signal lines on the base substrate, every two adjacent rows of pixel units share one reset signal line. Every two adjacent rows of pixel units and a reset signal line between the two adjacent rows of pixel units constitute a pixel unit group, each pixel unit group comprises a plurality of columns of pixel units. Each pixel unit comprises a reset thin film transistor, each reset thin film transistor comprises a conductive semiconductor layer on the base substrate, a first insulating layer on a side of the conductive semiconductor layer distal to the base substrate, a gate electrode on a side of the first insulating layer distal to the conductive semiconductor layer, a second insulating layer on a side of the gate electrode distal to the first insulating layer, a source/drain/metal electrode layer on a side of the second insulating layer distal to the gate electrode, and a source via, a drain via, and a metal electrode via; the conductive semiconductor layer comprises a first semiconductor electrode and a second semiconductor electrode, and the source/drain/metal electrode layer comprises a source electrode, a drain electrode, and a metal electrode. The metal electrode via is at a position corresponding to an area where the reset signal line and the second semiconductor electrode overlap in plan view of the substrate, the metal electrode via exposing part of the reset signal line and part of the second semiconductor electrode. The metal electrode within the metal electrode via is electrically connected to the reset signal line and the second semiconductor electrode, the second semiconductor electrode is electrically connected to two drain electrodes of the reset thin film transistor in two neighboring pixel units in a same column within a same pixel unit group through two corresponding drain vias. The source electrode is electrically connected to the first semiconductor electrode through the source via.
US09698207B2 Element substrate and light-emitting device
A potential of a gate of a driving transistor is fixed, and the driving transistor is operated in a saturation region, so that a current is supplied thereto anytime. A current control transistor operating in a linear region is disposed serially with the driving transistor, and a video signal for transmitting a signal of emission or non-emission of the pixel is input to a gate of the current control transistor via a switching transistor.
US09698203B2 Organic light-emitting diode display with capacitive touch sensing patterns
An organic light-emitting diode (OLED) display is disclosed. In one aspect, the display includes a substrate and a display layer formed over the substrate and including a pixel area and a non-pixel area. The display also includes an upper thin layer formed over the display layer, wherein the upper thin layer comprises at least first and second conductive layers and a dielectric layer formed between the first and second conductive layers, wherein the second conductive layer is closer to the substrate than the first conductive layer, and wherein the first and second conductive layers are patterned as a touch electrode. The display further includes a light absorbing member at least partially overlapping the non-pixel area and not overlapping the pixel area.
US09698201B2 High density selector-based non volatile memory cell and fabrication
A high density non-volatile memory device is provided that uses one or more volatile elements. In some embodiments, the non-volatile memory device can include a resistive two-terminal selector that can be in a low resistive state or a high resistive state depending on the voltage being applied. A deep trench MOS (“metal-oxide-semiconductor”) transistor having a floating gate with small area relative to conventional devices can be provided, in addition to a capacitor or transistor acting as a capacitor. A first terminal of the capacitor can be connected to a voltage source, and the second terminal of the capacitor can be connected to the selector device. The small area floating gate of the deep trench transistor can be connected to the other side of the selector device, and a second transistor can be connected in series with the deep trench transistor.
US09698197B2 High-voltage flip LED chip and manufacturing method thereof
A high-voltage flip LED chip and a manufacturing method thereof. In the high-voltage flip LED chip, a P-N electrode connecting metal block is filled into an isolation trench between two adjacent chip units and is respectively filled into a first electrode hole of one chip unit and a second electrode hole of the other chip unit to serially connect the two adjacent chips. Since the chip units are interconnected by adopting large-area metal and the metal is filled into the isolation trench, not only can the high luminous efficiency of the chip be guaranteed, but also the high reliability and excellent current spreading between the units are guaranteed, the process stability can be improved, and the rate of non-defective products and the product reliability are improved; since the isolation trenches between the chip units adopt an ODR design, the reflectivity of reflectors at the trenches can be improved and the absorption by electrodes is reduced; and since the chip has large-area spacing-controllable P and N electrodes, the heat dissipating capability of the chip is guaranteed to be good and simultaneously the packaging difficulty is reduced.
US09698194B2 Dual-mode image sensor with a signal-separating color filter array, and method for same
A method for fabricating a signal-separating CFA includes forming a multi-height CFA on a substrate. The multi-height CFA includes a plurality of tall spectral filters and a plurality of short spectral filters. Each of the tall spectral filters is taller than each of the short spectral filters. The method also includes disposing a spectral-blocking layer on the multi-height CFA, and planarizing the spectral-blocking layer to expose a top surface of each of the plurality of tall spectral filters.
US09698193B1 Multi-sensor pixel architecture for use in a digital imaging system
A system and method for a multi-sensor pixel architecture for use in a digital imaging system is described. The system includes at least one semiconducting layer for absorbing radiation incident on opposites of the at least one semiconducting layer along with a set of electrodes on one side of the semiconducting layer for transmitting a signal associated with the radiation absorbed by the semiconducting layer.
US09698190B2 Image sensor comprising reflective guide layer and method of forming the same
Various structures of image sensors are disclosed, as well as methods of forming the image sensors. According to an embodiment, a structure comprises a substrate comprising photo diodes, an oxide layer on the substrate, recesses in the oxide layer and corresponding to the photo diodes, a reflective guide material on a sidewall of each of the recesses, and color filters each being disposed in a respective one of the recesses. The oxide layer and the reflective guide material form a grid among the color filters, and at least a portion of the oxide layer and a portion of the reflective guide material are disposed between neighboring color filters.
US09698189B2 Photoelectric converter and photoelectric conversion system
The disclosure provides at least a photoelectric converter, and at least a photoelectric conversion system, including a plurality of pixels each having a photoelectric conversion layer and a pixel electrode; a first electrode that supplies a potential to each of the photoelectric conversion layers of a plurality of pixels in common, and a second electrode that supplies the potential to the first electrode. The pixel electrode is formed by metal and further includes an oxide conductive film disposed between the first electrode and the second electrode.
US09698178B2 Array substrate, method for manufacturing the same, and display apparatus
A method for manufacturing an array substrate includes coating a photoresist onto an insulation layer including a gate insulation layer and an etch stop layer, wherein the gate insulation layer covers a conductive pattern and the etch stop layer covers a semiconductive pattern. The method further includes exposing the photoresist to form a photoresist partially-reserved region and a photoresist unreserved region. The method further includes performing a first etching process to at least partially remove a portion of the insulation layer located at a position corresponding to the photoresist unreserved region, to form an intermediate hole. The method further includes performing a second etching process to form the first via hole and form the second via hole at a position of the intermediate hole, thereby to reveal the semiconductive pattern and the conductive pattern at positions corresponding to the first via hole and the second via hole, respectively.
US09698175B2 Liquid crystal display panel, array substrate and manufacturing method for thin-film transistor
An LCD panel, an array substrate and a manufacturing method for TFT are disclosed. The method includes: providing a substrate; forming a first metal layer on the substrate, wherein the first metal layer includes an aluminum metal layer, an aluminum oxide layer and a molybdenum metal layer stacked sequentially; patterning the first metal layer to form a gate electrode of a TFT; sequentially forming a gate insulation layer, a semiconductor layer and an ohmic contact layer on the gate electrode; forming a second metal layer on the ohmic contact layer; and patterning the second metal layer to form a source electrode and a drain electrode of the TFT. The present invention can inhibit hillock generated by the aluminum metal layer in a high temperature environment, avoid the short circuit generated among the gate, the source and the drain electrodes of the TFT to ensure the display quality of an image.
US09698170B2 Semiconductor device, display module, and electronic device
To reduce the amplitude voltage of control signals of a MEMS device. A semiconductor device includes a MEMS device, a first transistor, a second transistor whose source or drain is electrically connected to a source or a drain of the first transistor, a third transistor which sets the potential of a gate of the first transistor to a value at which the first transistor is turned on, a fourth transistor which sets the potential of the gate of the first transistor to a value at which the first transistor is turned off, and a fifth transistor which supplies a signal to a gate of the second transistor and a gate of the fourth transistor.
US09698165B2 Array substrate, method for manufacturing the same, and display device comprising array substrate
An embodiment of the disclosure provides an array substrate comprising: a base substrate, an active layer and a transparent electrode disposed on the base substrate, an etch stop layer disposed on the active layer and configured for protecting a portion of the active layer, wherein the active layer, the transparent electrode and the etch stop layer are formed through one patterning process and one doping process, the doped region and the first transparent electrode are made of same material and are disposed on the same layer.
US09698161B2 Display device
A display device may include these elements: a first data line; a second data line; a first subpixel electrode positioned at a first half of the display device, connected to the first data line, and comprising a first member and a second member, the first member extending parallel to the first data line, the second member connecting directly to and extending perpendicular to the first member; and a second subpixel electrode positioned at a second half of the display device, connected to the second data line, and comprising a third member and a fourth member, the third member extending parallel to the second data line, the fourth member connecting directly to and extending perpendicular to the third member, wherein the second member and the fourth member are aligned and are positioned between the first member and the third member in a layout view of the display device.
US09698160B2 Method for transferring micro devices and method for manufacturing display panel
A method for transferring micro devices is provided. The method includes the following operations: providing a carrier substrate and forming micro devices on the carrier substrate; forming a fixing layer on the carrier substrate, in which the fixing layer is at least in contact with bottom parts of the micro devices; patterning the fixing layer to selectively expose a portion of the micro devices; providing a transfer device correspondingly located on the carrier substrate, and picking up the exposed micro devices by the transfer device; and providing a receiving substrate and transferring the exposed micro devices to the receiving substrate.
US09698155B2 Semiconductor devices and methods of fabricating the same
A semiconductor device includes a plurality of first insulating layers and a plurality of second layers alternately and vertically stacked on a substrate. Each of the plurality of second layers includes a horizontal electrode horizontally separated by a second insulating layer. A contact plug penetrates the plurality of first insulating layers and the second insulating layer of the plurality of second layers.
US09698152B2 Three-dimensional memory structure with multi-component contact via structure and method of making thereof
A contact via structure can include a ruthenium portion formed by selective deposition of ruthenium on a semiconductor surface at the bottom of a contact trench. The ruthenium-containing portion can reduce contact resistance at the interface with an underlying doped semiconductor region. At least one conductive material portion can be formed in the remaining volume of the contact trench to form a contact via structure. Alternatively or additionally, a contact via structure can include a tensile stress-generating portion and a conductive material portion. In case the contact via structure is formed through an alternating stack of insulating layers and electrically conductive layers that include a compressive stress-generating material, the tensile stress-generating portion can at least partially cancel the compressive stress generated by the electrically conductive layers. The conductive material portion of the contact via structure can include a metallic material or a doped semiconductor material.
US09698150B2 Semiconductor memory device and method for manufacturing the same
According to one embodiment, a semiconductor memory device includes a substrate, a first insulating film, a stacked body, and a first pillar. At least a portion of an upper layer portion of the substrate is conductive. The first insulating film is provided in a portion of the substrate. The stacked body includes conductive films and insulating films stacked alternately in a first direction. The conductive films and the insulating films are provided on the substrate and on the first insulating film. The first pillar pierces the stacked body in the first direction. The first pillar includes a first lower end portion and a first extension portion. The first lower end portion is disposed inside the first insulating film. The first extension portion is disposed inside the stacked body.
US09698146B2 Multi-gate and complementary varactors in FinFET process
A varactor includes at least one semiconductor fin, a first gate, and a second gate physically disconnected from the first gate. The first gate and the second gate form a first FinFET and a second FinFET, respectively, with the at least one semiconductor fin. The source and drain regions of the first FinFET and the second FinFET are interconnected to form the varactor.
US09698144B2 Field effect transistor having loop distributed field effect transistor cells
A Field Effect Transistor (FET) having a plurality of FET cells having a plurality of source pads, a plurality of drain pads, and a plurality of gate electrodes disposed on a surface of a substrate; each one of the FET cells having a corresponding one of the gate electrodes disposed between one of the source pads and one of the drain pads. The FET includes; a gate contact connected to the gate electrode of each one of the FET cells; a drain contact connected to the drain pad of each one of the FET cells; and a source contact connected to source pad of each one of the FET cells. The cells are disposed in a loop configuration.
US09698141B2 Semiconductor device
A semiconductor device includes a first nitride semiconductor layer having a first region, a second nitride semiconductor layer that is on the first nitride semiconductor layer and contains carbon and silicon, a third nitride semiconductor layer that is on the second nitride semiconductor layer and has a second region, a fourth nitride semiconductor layer on the third nitride semiconductor layer, the fourth nitride semiconductor layer having a band gap that is wider than a band gap of the third nitride semiconductor layer, a source electrode that is on the fourth nitride semiconductor layer and is electrically connected to the first region, a drain electrode that is on the fourth nitride semiconductor layer and is electrically connected to the second region, and a gate electrode that is on the fourth nitride semiconductor layer and is between the source electrode and the drain electrode.
US09698137B2 Electrostatic discharge (ESD) protection of capacitors using lateral surface Schottky diodes
Electrostatic Discharge (ESD) protection using lateral surface Schottky diodes is disclosed. In one embodiment, a Metal-Insulator-Metal (MIM) capacitor with ESD protection comprises a group III-V substrate, a first metal layer contacting the substrate, an insulation layer formed over the first metal layer, and a second metal layer formed over the insulation layer and also contacting the substrate. A MIM capacitor is formed by overlapping portions of the first metal layer, the insulation layer, and the second metal layer. First and second Schottky diodes are formed where the first and second metal layers, respectively, contact the substrate, such that the cathodes of the Schottky diodes are electrically connected to one another and the anodes of the Schottky diodes are electrically connected to the respective overlapping portions of the first and second metal layers.
US09698123B2 Apparatus for stacked electronic circuitry and associated methods
An apparatus includes a substrate and a pair of die that include electronic circuitry. The substrate includes a cavity. One of the die is disposed in the cavity formed in the substrate. The other die is disposed above the first die and is electrically coupled to the first die.
US09698120B2 Package process and package structure
A package process is provided. An adhesive layer is disposed on a carrier board and then plural first semiconductor devices are disposed on the adhesive layer. A first molding compound formed on the carrier board covers the sidewalls of the first semiconductor devices and fills the gaps between the first semiconductor devices so as to form a chip array board constructed by the first semiconductor devices and the first molding compound. Next, plural second semiconductor devices are flip-chip bonded to the first semiconductor devices respectively. Then, a second molding compound formed on the chip array board at least covers the sidewalls of the second semiconductor devices and fills the gaps between the second semiconductor devices. Subsequently, the chip array board is separated from the adhesive layer. Then, the first and the second molding compound are cut along the gaps between the second semiconductor devices.
US09698118B2 Method and apparatus for connecting packages onto printed circuit boards
Methods and apparatus are disclosed for attaching the integrated circuit (IC) packages to printed circuit boards (PCBs) to form smooth solder joints. A polymer flux may be provided in the process to mount an IC package to a PCB. The polymer flux may be provided on connectors of the IC package, or provided on PCB contact pad and/or pre-solder of the PCB. When the IC package is mounted onto the PCB, the polymer flux may cover a part of the connector, and may extend to cover a surface of the molding compound on the IC package. The polymer flux may completely cover the connector as well. The polymer flux delivers a fluxing component that facilitates smooth solder joint formation as well as a polymer component that offers added device protection by encapsulating individual connectors. The polymer component may be an epoxy.
US09698113B2 Chip packaging structures
A method for treating a chip packaging structure includes providing a chip packaging structure having at least a first electrical connect structure and a second electrical connect structure, and an insulation layer exposing portions of the first electrical connect structure and the second electrical connect structure; selecting a plasma gas based on materials of the first electrical connect structure and the second electrical connect structure and a type of process forming the first electrical connect structure and the second electrical connect structure, wherein metal cations are left on the insulation layer; performing a plasma treatment process using the selected plasma gas on the first electrical connect structure, the second electrical connect structure and the insulation layer, causing reaction of the metal cations to substantially convert the metal cations into electrically neutral materials; and removing the reacted metal cations from the insulation layer.
US09698112B2 Semiconductor device including a protective film
A semiconductor device includes a semiconductor chip having a wire and a passivation film formed on the outermost surface with an opening partially exposing the wire. A resin layer is stacked on the semiconductor chip and provided with a through-hole in a position opposed to a portion of the wire facing the opening. A pad is formed on a peripheral portion of the through-hole in the resin layer and in the through-hole so that an external connection terminal is arranged on the surface thereof. The peripheral portion of the resin layer is formed more thickly than the remaining portion of the resin layer other than the peripheral portion.
US09698110B2 Semiconductor device with integrated antenna
A high frequency signal can be transmitted and received in a semiconductor device. In a QFP, an antenna (frame body) is supported by three suspension leads. The antenna is arranged to be symmetrical with respect to a first virtual diagonal line of a plan view of a sealing body. One of the three suspension leads is arranged on the first virtual diagonal line. With this configuration, discontinuities of a wave of a signal in the antenna can be reduced, as a result of which the high frequency signal of 5 Gbps class can be transmitted and received in the QFP.
US09698109B2 ESD protection device
An ESD protection device 1 has a ceramic insulating material 10, first and second discharge electrodes 21 and 22, and a discharge-assisting section 51. The first and second discharge electrodes 21 and 22 are disposed somewhere of the ceramic insulating material 10. The discharge-assisting section 51 is located between the distal end portion of the first discharge electrode 21 and the distal end portion of the second discharge electrode 22. The discharge-assisting section 51 is an electrode configured to reduce the discharge starting voltage between the first discharge electrode 21 and the second discharge electrode 22. The discharge-assisting section 51 is made from a sintered body containing conductive particles and at least one of semiconductor particles and insulating particles. The first and second discharge electrodes contain at least one of the semiconductor material constituting the semiconductor particles and the insulating material constituting the insulating particles.
US09698106B2 Metal deposition on substrates
Various techniques, methods, devices and apparatus are provided where an isolation layer is provided at a peripheral region of the substrate, and one or more metal layers are deposited onto the substrate.
US09698094B2 Wiring board and electronic component device
A wiring board includes: an insulating layer; and a wiring layer including: an upper surface; a lower surface opposite to the upper surface; and a side surface between the upper surface and the lower surface, wherein the upper surface of the wiring layer is exposed from the insulating layer, and the side surface and the lower surface of the wiring layer are embedded in the insulating layer. A recess portion is formed in an outer edge portion of the upper surface of the wiring layer, and the recess portion is filled with the insulating layer.
US09698092B2 Electronic device
An electronic device, suitable for achieving a smaller size, includes a semiconductor substrate having a main surface and a back surface opposite to the main surface, a main electronic element arranged on the substrate, and a conducting layer electrically connected to the main electronic element. The substrate is formed with an element arrangement recessed portion that is recessed from the main surface and in which the main electronic element is arranged. The element arrangement recessed portion has a bottom surface facing in the thickness direction, and a side surface inclined with respect to the thickness direction of the substrate. The electronic device includes an auxiliary electronic element formed on the side surface of the element arrangement recessed portion.
US09698090B2 Semiconductor substrate and fabrication method thereof
A semiconductor substrate is disclosed. The semiconductor substrate includes a substrate body having at least an opening formed on a surface thereof, wherein the surface of the substrate body and a wall of the opening are made of an insulating material; and a circuit layer formed on the surface of the substrate body, wherein the circuit layer covers an end of the opening and is electrically insulated from the opening. The opening facilitates to increase the thickness of the insulating structure between the circuit layer and the substrate body of a silicon material to prevent signal degradation when high frequency signals are applied to the circuit layer.
US09698089B2 Substrate device and electric circuit arrangement having first substrate section perpendicular to second substrate section
An electronic circuit includes a substrate device which includes a first substrate section including a first plurality of layers attached to each other having a first orientation (x2) and a second substrate section including a second plurality of layers attached to each other. The second plurality of layers have a second orientation (x3). The first orientation (x2) and the second orientation (x3) are perpendicular with respect to one another.
US09698088B2 Semiconductor packages
Semiconductor packages include a first substrate including a central portion and a peripheral portion, at least one first central connection member attached to the central portion of the first substrate, and at least one first peripheral connection member attached to the peripheral portion of the first substrate. The first central connection member includes a first supporter and a first fusion conductive layer surrounding the first supporter.
US09698087B2 Semiconductor device, corresponding methods of production and use and corresponding apparatus
A semiconductor device includes a quadrilateral package with a first pair of opposed sides and a second pair of opposed sides. Both sides of the first pair of opposed sides are provided with electrical contact leads. Only one side of the second pair of opposed sides is provided with electrical contact leads. The side of the second pair of opposed sides without electrical contact leads is a leadless side. That side is not a molded side of the package, but rather is defined by a cut surface.
US09698085B1 Leadframe strip assembly and method of processing
A method of processing a leadframe strip having opposite first and second longitudinal ends and a plurality of leadframe panels positioned between the first and second longitudinal ends, each of the leadframe panels including an array of leadframe portions. The method includes saw cutting the leadframe rails and panels with a plurality of laterally extending saw cuts that each extend through the first and second rails and a panel connector portion of the leadframe strip positioned between adjacent panels of the leadframe strip. A method of reducing blade heating during leadframe strip singulation is described. Leadframe strip assemblies are also described.
US09698084B2 Semiconductor device and lead frame having two leads welded together
A semiconductor device includes a lead frame having terminals, a semiconductor chip electrically coupled to the terminals, and a resin part configured to encapsulate the semiconductor chip such as to expose part of the terminals, wherein a given one of the terminals includes a first lead and a second lead welded together such that an upper face of the first lead is placed against a lower face of the second lead, wherein the lower face of the second lead extends further than the upper face of the first lead toward the semiconductor chip in a longitudinal direction of the terminal, and also extends further sideways than the upper face of the first lead in a transverse direction of the terminal, and wherein an area of the lower face of the second lead is covered with the resin part, the area extending further than the upper face of the first lead.
US09698081B2 3D chip-on-wafer-on-substrate structure with via last process
Disclosed herein is a package having a first redistribution layer (RDL) disposed on a first semiconductor substrate and a second RDL disposed on a second semiconductor substrate. The first RDL is bonded to the second RDL. The package further includes an insulating film disposed over the second RDL and around the first RDL and the first semiconductor substrate. A conductive element is disposed in the first RDL. A via extends from a top surface of the insulating film, through the first semiconductor substrate to the conductive element, and a spacer is disposed between the first semiconductor substrate and the via. The spacer extends through the first semiconductor substrate.
US09698080B2 Conductor structure for three-dimensional semiconductor device
A three-dimensional semiconductor device using redundant bonding-conductor structures to make inter-level electrical connections between multiple semiconductor chips is disclosed. A first chip, or other semiconductor substrate, forms a first active area on its upper surface, and a second chip or other semiconductor substrate forms a second active area on its upper surface. According to the present invention, when the second chip has been mounted above the first chip, either face-up or face-down, the first active area is coupled to the second active area by at least one redundant bonding-conductor structure. In one embodiment, each redundant bonding-conductor structure includes at least one via portion that extends completely through the second chip to perform this function. In another, the redundant bonding-conductor structure extends downward to the top level interconnect. The present invention also includes a method for making such a device.
US09698078B2 Semiconductor module and method for manufacturing the same
A semiconductor module of the present invention includes: a semiconductor element having a first main surface and a second main surface facing the first main surface, the semiconductor element including a front surface electrode and a back surface electrode on the first main surface and the second main surface, respectively; a metal plate electrically connected to the back surface electrode of the semiconductor element through a sintered bonding material including metal nanoparticles; and a plate-shaped conductor electrically connected to the front surface electrode of the semiconductor element through the sintered bonding material including the metal nanoparticles. The metal plate and the conductor include grooves communicating between a bonding region bonded to the semiconductor element and the outside of the bonding region.
US09698074B2 Heated substrate support with temperature profile control
Methods and apparatus of substrate supports having temperature profile control are provided herein. In some embodiments, a substrate support includes: a plate having a substrate receiving surface and an opposite bottom surface; and a shaft having a first end comprising a shaft heater and a second end, wherein the first end is coupled to the bottom surface. Methods of making a substrate support having temperature profile control are also provided.
US09698073B2 Method of manufacturing element chip and element chip
In a plasma processing step in a method of manufacturing an element chip in which a plurality of element chips are manufactured by dividing a substrate, which has a plurality of element regions, the substrate is divided into element chips by exposing the substrate to first plasma. In a protection film forming step of forming a protection film covering a side surface and a second surface by exposing the element chips to second plasma of which raw material gas is mixed gas of carbon fluoride and helium, protection film forming conditions are set such that a thickness of a second protection film of the second surface is greater than a thickness of a first protection film of the side surface.
US09698072B2 Low-stress dual underfill packaging
The present invention relates generally to flip chip technology and more particularly, to a method and structure for reducing internal packaging stresses, improving adhesion properties, and reducing thermal resistance in flip chip packages by using more than one underfill material deposited in different regions of the flip chip interface. According to one embodiment, a method of forming a first underfill in an interior region of an interface such that a periphery region of the interface remains open, and forming a second underfill in the periphery region is disclosed.
US09698071B2 Die packages and methods of manufacture thereof
Die packages and method of manufacturing the same are disclosed. In an embodiment, a method of manufacturing a die package may include forming an encapsulated via structure including at least one via, a polymer layer encapsulating the at least one via, and a first molding compound encapsulating the polymer layer; placing the encapsulated via structure and a first die stack over a carrier, the at least one via having a first end proximal the carrier and a second end distal the carrier; encapsulating the first die stack and the encapsulated via structure in a second molding compound; and forming a first redistribution layer (RDL) over the second molding compound, the first RDL electrically connecting the at least one via.
US09698070B2 Arrangement having a plurality of chips and a chip carrier, and a processing arrangement
In various embodiments, an arrangement is provided. The arrangement may include a plurality of chips; a chip carrier carrying the plurality of chips, the chip carrier including a chip carrier notch; and encapsulation material encapsulating the chip carrier and filling the chip carrier notch; wherein the outer circumference of the encapsulation material is free from a recess.
US09698059B2 Semiconductor device and method of forming the same
The present invention provides a semiconductor device and a method of forming the same. The semiconductor device includes a substrate, a first transistor and a second transistor. The first transistor and the second transistor are disposed on the substrate. The first transistor includes a first channel and a first work function layer. The second transistor includes a second channel and a second work function layer, where the first channel and the second channel include different dopants, and the second work function layer and the first work function layer have a same conductive type and different thicknesses.
US09698058B2 Structure and method for FinFET device
The present disclosure provides an embodiment of a fin-like field-effect transistor (FinFET) device. The device includes a substrate having a first gate region, a first fin structure over the substrate in the first gate region. The first fin structure includes an upper semiconductor material member, a lower semiconductor material member, surrounded by an oxide feature and a liner wrapping around the oxide feature of the lower semiconductor material member, and extending upwards to wrap around a lower portion of the upper semiconductor material member. The device also includes a dielectric layer laterally proximate to an upper portion of the upper semiconductor material member. Therefore the upper semiconductor material member includes a middle portion that is neither laterally proximate to the dielectric layer nor wrapped by the liner.
US09698056B2 Method for designing layout of semiconductor device and method for manufacturing semiconductor device using the same
A method of manufacturing a semiconductor device includes providing pre-conductive lines and post-conductive lines for forming a first logic cell and a second logic cell, which are adjacent to each other, and a dummy cell and a third logic cell, which are adjacent to each other. A first conductive line, adjacent to the second logic cell, from among conductive lines of the first logic cell is spaced a first reference distance apart from a second conductive line, adjacent to the first logic cell, from among conductive lines of the second logic cell. A dummy line, which is adjacent to the third logic cell, from among conductive lines of the dummy cell is spaced a second reference distance apart from a third conductive line, which is adjacent to the dummy cell, from among conductive lines of the third logic cell. The second reference distance is greater than the first reference distance.
US09698051B2 Semiconductor chips having through silicon vias and related fabrication methods and semiconductor packages
A semiconductor chip including through silicon vias (TSVs), wherein the TSVs may be prevented from bending and the method of fabricating the semiconductor chip may be simplified, and a method of fabricating the semiconductor chip. The semiconductor chip includes a silicon substrate having a first surface and a second surface; a plurality of TSVs which penetrate the silicon substrate and protrude above the second surface of the silicon substrate; a polymer pattern layer which is formed on the second surface of the silicon substrate, surrounds side surfaces of the protruding portion of each of the TSVs, and comprises a flat first portion and a second portion protruding above the first portion; and a plated pad which is formed on the polymer pattern layer and covers a portion of each of the TSVs exposed from the polymer pattern layer.
US09698049B2 Nonvolatile memory device and method for fabricating the same
A nonvolatile memory device may include a stair-shaped structure including a first interlayer dielectric layer and a memory cell repeatedly stacked. The nonvolatile memory device may include an etch stop layer and a second interlayer dielectric layer formed over the stair-shaped structure. The nonvolatile memory device may include an isolation layer passing through the stair-shaped structure, the etch stop layer, and the second interlayer dielectric layer. The nonvolatile memory device may include protective layer interposed between the isolation layer and the etch stop layer, and the protective layer interposed between the isolation layer and the second interlayer dielectric layer. The nonvolatile memory device may include contact plugs coupled to each memory cell, respectively, by passing through the second interlayer dielectric layer and the etch stop layer.
US09698045B2 Method of manufacture for a silicon-on-plastic semiconductor device with interfacial adhesion layer
A semiconductor device and methods for manufacturing the same are disclosed. The semiconductor device includes a polymer substrate and an interfacial layer over the polymer substrate. A buried oxide layer resides over the interfacial layer, and a device layer with at least a portion of a field effect device resides over the buried oxide layer. The polymer substrate is molded over the interfacial adhesion layer and has a thermal conductivity greater than 2 watts per meter Kelvin (W/mK) and an electrical resistivity greater than 1012 Ohm-cm. Methods of manufacture for the semiconductor device include removing a wafer handle to expose a first surface of the buried oxide layer, disposing the interfacial adhesion layer onto the first surface of the buried oxide layer, and molding the polymer substrate onto the interfacial adhesion layer.
US09698042B1 Wafer centering in pocket to improve azimuthal thickness uniformity at wafer edge
A method for reducing slippage of a wafer during film deposition includes pumping out a processing chamber while the wafer is supported on lift pins or a carrier ring and lowering the wafer onto support members configured to minimize wafer slippage during deposition of the film. A multi-station processing chamber, such as a processing chamber for atomic layer deposition, can include a chuck-less pedestal at each station having wafer supports configured to prevent the wafer from moving off center by more than 400 microns. To minimize a gas cushion beneath the wafer, the wafer supports can provide a gap of at least 2 mils between the back side of the wafer and the wafer-facing surface of the pedestal.
US09698040B2 Semiconductor device carrier tape with image sensor detectable dimples
A semiconductor device carrier tape with image sensor detectable dimples is disclosed. The dimpled carrier tape is formed of a flexible strip of material. A plurality of pockets are disposed spaced apart along the length of the flexible strip of material. Each pocket is configured to hold a semiconductor device. A dimple is formed in each of the plurality of pockets where each dimple has a peripheral edge and a bottom surface. Detection of the dimple by an image sensor facilitates alignment of a semiconductor device with the pocket and precise placement of the semiconductor device in the pocket.
US09698038B2 Adapter tool and wafer handling system
An adapter tool that is configured to be attached to a loadport of a wafer handling system includes a support member, and first and second guiding elements supported by the support member. The first and second guiding elements are arranged for placing a first wafer magazine and a second wafer magazine, respectively. The adapter tool further includes a housing supported by the support member that is configured to house the first and the second wafer magazines, respectively, and first and second openings in the housing, respectively. The first and second openings are aligned with the first and second guiding elements.
US09698034B2 Substrate storage container and substrate storage container mounting table
In accordance with an embodiment, a substrate storage container includes first and second cases, a lid and a moving unit. The first case is provided with an opening to take in or out a substrate. The lid closes the opening. The second case can move in a first direction crossing a surface of the first case. The opening is provided on the surface. The moving unit moves the second case in the first direction in response to the opening of the lid.
US09698032B2 Mounting system and charging method for disc-shaped objects
A mounting system includes retaining bars which are structurally independent of one another, which can be optionally directly disconnected and directly connected relative to a support device through coupling devices that are activatable and deactivatable without tools. Using the mounting system, a method for charging a treatment device can also be carried out, with which the retaining bars are directly connected to a first support device, and following this, the retaining bars are directly connected to a second support device, in particular a rotor that is arranged in the treatment device. Following that, the mechanical connection between the first support device and the retaining bars is directly disconnected.
US09698025B2 Directed self-assembly material growth mask for forming vertical nanowires
A method includes forming at least one fin on a semiconductor substrate. A hard mask layer is formed above the fin. A first directed self-assembly material is formed above the hard mask layer. The hard mask layer is patterned using a portion of the first directed self-assembly material as an etch mask to expose a portion of the top surface of the fin. A substantially vertical nanowire is formed on the exposed top surface. At least one dimension of the substantially vertical nanowire is defined by an intrinsic pitch of the first directed self-assembly material.
US09698024B2 Partial SOI on power device for breakdown voltage improvement
Some embodiments of the present disclosure relate to a method to increase breakdown voltage of a power device. A power device is formed on a silicon-on-insulator (SOI) wafer made up of a device wafer, a handle wafer, and an intermediate oxide layer. A recess is formed in a lower surface of the handle wafer to define a recessed region of the handle wafer. The recessed region of the handle wafer has a first handle wafer thickness, which is greater than zero. An un-recessed region of the handle wafer has a second handle wafer thickness, which is greater than the first handle wafer thickness. The first handle wafer thickness of the recessed region provides a breakdown voltage improvement for the power device.
US09698021B2 Deposition methods of forming a layer while rotating the substrate in angular increments and methods of manufacturing a semiconductor device using the same
In a method of forming a layer, a substrate is loaded into a chamber and placed at a home position that is a first relative angular position. A process cycle is performed a number of times while the substrate is at the home position. The cycle includes directing source gas onto the substrate at a first location adjacent the periphery of the substrate, purging the chamber, directing reaction gas onto the substrate from the first location, and purging the chamber. The cycle is performed another number of times while the substrate is at another relative angular position, i.e., at a position rotated about its general center relative from the home position.
US09698019B2 N-work function metal with crystal structure
A method includes forming a dummy gate stack over a semiconductor substrate, wherein the semiconductor substrate is comprised in a wafer. The method further includes removing the dummy gate stack to form a recess, forming a gate dielectric layer in the recess, and forming a metal layer in the recess and over the gate dielectric layer. The metal layer has an n-work function. A portion of the metal layer has a crystalline structure. The method further includes filling a remaining portion of the recess with metallic materials, wherein the metallic materials are overlying the metal layer.
US09698018B1 Introducing self-aligned dopants in semiconductor fins
A method of introducing self-aligned dopants in semiconductor fins and the resulting device are provided. Embodiments include providing semiconductor fins on first and second portions of a substrate; forming a BSG layer on side surfaces of the semiconductor fins on the first portion of the substrate; forming a first SiN layer on the BSG layer; forming a high quality oxide layer over an upper surface of the substrate, the first SiN layer and side surfaces of the semiconductor fins on the second portion of the substrate; forming a PSG layer over the high quality oxide layer on the second portion of the substrate and side surfaces of the semiconductor fins on the second portion of the substrate; and forming a second SiN layer over the high quality oxide layer and the PSG layer.
US09698012B2 Method and apparatus for manufacturing low temperature poly-silicon film, and low temperature poly-silicon film
Disclosed are a method and an apparatus for manufacturing low temperature poly-silicon film, and a low temperature poly-silicon film. The method includes: providing a substrate; forming an amorphous silicon film; applying different temperatures to different regions of the amorphous silicon film by using an excimer laser annealing method, to change the amorphous silicon film into a molten state; and recrystallizating the amorphous silicon film in the molten state, a region having a lower temperature serving as a starting point, a region having a higher temperature serving as an end point, to form a low temperature poly-silicon film. The low temperature poly-silicon film manufactured by the above method and apparatus has a greater size of the crystalline grain and a larger electronic mobility than in the existing technology.
US09698006B2 Versatile system for self-aligning deposition equipment
The present invention provides a system (100) for aligning a dispensing apparatus (110) utilized within a semiconductor deposition chamber (102). A stationary reference apparatus (106) is disposed along the bottom of the deposition chamber. A self-alignment support system (122), comprising one or more support components (124), is intercoupled between the dispensing apparatus and a deposition system exterior component (112). The self-alignment support system is adapted to facilitate and secure repositioning of the dispensing apparatus responsive to pressure applied to the dispensing surface (114) thereof. A non-yielding offset component (126) is placed upon a first surface (108) of the stationary reference apparatus. The dispensing surface of the dispensing apparatus is engaged with the offset component, and pressure is applied to the dispensing apparatus via the offset component until a desired alignment is achieved.
US09698003B2 Ultraviolet discharge lamp apparatuses with one or more reflectors
Apparatuses are disclosed which include a discharge lamp configured to emit ultraviolet light, a power circuit configured to operate the discharge lamp, and a reflector system configured to redirect ultraviolet light emitted from the discharge lamp. In some embodiments, the apparatuses include a support structure containing the power circuit and supporting the discharge lamp. In some of such embodiments, the reflector system is configured to redirect ultraviolet light propagating away from the support structure to a region exterior to the apparatus and which is between approximately 2 feet and approximately 4 feet from a floor of a room in which the apparatus is arranged. In other embodiments, the reflector system may be additionally or alternatively configured to redirect ultraviolet light propagating away from the support structure to encircle an exterior surface of the apparatus. In any case, the reflector system may, in some embodiments, include a repositionable reflector.
US09698001B2 Gas-phase purification for accurate isobaric tag-based quantification
Described herein are mass spectrometry systems and methods which improve the accuracy of isobaric tag-based quantification by alleviating the pervasive problem of precursor interference and co-isolation of impurities through gas-phase purification. During the gas-phase purification, the mass-to-charge ratios of precursor ions within at least a selected range are selectively changed allowing ions having similar unmodified mass-to-charge ratios to be separated before further isolation, fragmentation or analysis.
US09698000B2 Integrated mass spectrometry systems
The disclosure features mass spectrometry systems that include: an ion source; a module featuring an ion trap, an ion detector, and a module housing that at least partially surrounds the ion trap and the ion detector; and a vacuum pump featuring a housing having a recess dimensioned to receive the module, so that when the module is positioned within the recess of the vacuum pump housing, a portion of the module is surrounded by the vacuum pump housing, and during operation of the system, the ion source, ion trap, ion detector, and vacuum pump are connected along a common gas flow path and heat is transferred from the vacuum pump to the module.
US09697997B2 Ion fragmentation
A collision cell for a mass spectrometer arranged to receive ions for fragmentation in a chamber and comprising an activation ion generator configured to irradiate the received ions with activation ions of the same polarity as the received ions. The activation ion generator is preferably a plasma generator, configured to generate a plasma comprising the activation ions.
US09697993B2 Non-ambipolar plasma ehncanced DC/VHF phasor
This disclosure relates to a plasma processing system for controlling plasma density across a substrate and maintaining a tight ion energy distribution within the plasma. In one embodiment, this may include using a dual plasma chamber system including a non-ambipolar plasma chamber and a DC plasma chamber adjacent to the non-ambipolar system. The DC plasma chamber provide power to generate the plasma by rotating the incoming power between four inputs from a VHF power source. In one instance, the power to each of the four inputs are at least 90 degrees out of phase from each other.
US09697986B2 Method and apparatus for an electromagnetic emission based imaging system
The present invention provides apparatus for an imaging system comprising a multitude of imaging elements upon a substrate. In some embodiments the substrate may be approximately round with a radius of approximately one inch. Various methods relating to using and producing an imaging system are discussed.
US09697985B2 Apparatus and method for inspecting a surface of a sample
The invention relates to an apparatus for inspecting a surface of a sample, wherein the apparatus comprises: at least one charged particle source for generating an array of primary charged particle beams, a condenser lens for directing all charged particle beams to a common cross-over, a lens system for directing the primary charged particle beams from the common cross-over towards the sample surface and for focusing all primary charged particle beams into an array of individual spots on the sample surface, and a position sensitive secondary electron detector positioned at least substantially in or near a plane comprising said common cross-over.
US09697982B2 Apparatus for GHz rate high duty cycle pulsing and manipulation of low and medium energy DC electron beams
An ElectroMagnetic-Mechanical Pulser can generate electron pulses at rates up to 50 GHz, energies up to 1 MeV, duty cycles up to 10%, and pulse widths between 100 fs and 10 ps. A modulating Transverse Deflecting Cavity (“TDC”) imposes a transverse modulation on a continuous electron beam, which is then chopped into pulses by an adjustable Chopping Collimating Aperture. Pulse dispersion due to the modulating TDC is minimized by a suppressing section comprising a plurality of additional TDC's and/or magnetic quadrupoles. In embodiments the suppression section includes a magnetic quadrupole and a TDC followed by four additional magnetic quadrupoles. The TDC's can be single-cell or triple-cell. A fundamental frequency of at least one TDC can be tuned by literally or virtually adjusting its volume. TDC's can be filled with vacuum, air, or a dielectric or ferroelectric material. Embodiments are easily switchable between passive, continuous mode and active pulsed mode.
US09697979B2 Microwave wave generator device with a virtual cathode oscillator and axial geometry, comprising at least one reflector and a magnetic ring, configured to be supplied by a high-impedance generator
A microwave wave generator device with oscillating virtual cathode, with axial geometry, includes at least one first reflector positioned in a cylindrical waveguide downstream of a thin anode, positioned at the entrance of the cylindrical waveguide, between a cathode and the cylindrical waveguide. The device further includes a tight magnetic ring of width (LM) along the longitudinal axis (z), positioned externally around the cylindrical waveguide, between the thin anode and the first reflector.
US09697978B2 Multi-frequency klystron designed for high efficiency
A multi-frequency klystron has an electron gun which generates a beam, a circuit of bunch-align-collect (BAC) tuned cavities that bunch the beam and amplify an RF signal, a collector where the beam is collected and dumped, and a standard output cavity and waveguide coupled to a window to output RF power at a fundamental mode to an external load. In addition, the klystron has additional bunch-align-collect (BAC) cavities tuned to a higher harmonic frequency, and a harmonic output cavity and waveguide coupled via a window to an additional external load.
US09697975B2 Circuit breakers with moving contact arm with spaced apart contacts
Circuit breakers with moving contacts having a rocking movement, e.g., heel-toe action, are configured to direct arcing across one of two (first and second) spaced apart contacts on a moving arm to an adjacent arc chute to thereby alleviate deterioration due to arcing and improve conductivity of the first moving contact over time.
US09697964B2 Locomotive positive power bus contactor method of assembly
A method of manufacturing a power contactor from an existing contactor having a magnetic amplifier that comprises a blowout coil and a ferromagnetic core, and an arc chute for extinguishing an arc generated by opening the existing contactor under a current load is disclosed. The method includes removing a bolt assembly from the existing contactor and at least one side plate from the existing contactor. The method also includes removing the ferromagnetic core from the existing contactor.
US09697963B2 On-load tap changer
The invention relates to an on-load tap-changer (1) having a switching tube (15), an energy accumulator (13) for adjusting a switch position of the switching tube (15), a detector (200) for detecting a switch position of the on-load tap-changer (1), and an on-load tap-changer mechanism (100). The switching tube (15) and the detector (200) are both mechanically coupled to the energy accumulator (13) via the on-load tap-changer mechanism (100).
US09697961B2 Photovoltaic bypass switching
A PhotoVoltaic (PV) panel bypass switching arrangement includes first and second switches. The first switch is to be coupled between a power system and a first end of a circuit path of the PV panel in which PV cells are connected, and is controllable to connect the first end of the circuit path to a power system and to disconnect the first end of the circuit path from the power system. The second switch is to be coupled between (i) a point between the first switch and the power system and (ii) a point between a second end of the circuit path and the power system, and is controllable to open and close a bypass circuit path that bypasses the circuit path. The first and second switches are controlled based on a determination as to whether the circuit path of the PV panel is to be bypassed.
US09697959B2 Geometric switch and circuits including the same
The present invention provides a mechanically-actuated switch comprising a deformable conductive element providing a conductive path between a first terminal and a second terminal, wherein the effective geometry of the conductive element changes suddenly upon deformation to cause a disproportionately large change in a resistance between the first and second terminals. The switch can be made from lightweight and soft materials, and is particularly suited for integration with dielectric elastomer devices. Also disclosed are various circuits and a method for controlling circuits including the switch.
US09697957B2 Electrochemical capacitor and semiconductor chip having an electrochemical capacitor
An integrable electrochemical capacitor and methods for manufacturing the same are disclosed. The electrochemical capacitor comprises a first electrode comprising a first rigid piece having a first porous portion, a second electrode comprising a second rigid piece having a second porous portion, and an electrolyte in contact with the first porous portion and the second porous portion. The structure allows the electrochemical capacitor to be manufactured without a separator film between the electrodes and is compatible with semiconductor manufacturing technologies. The electrochemical capacitor can also be manufactured within a SOI layer 8.
US09697956B2 Diketopyrrolopyrole (DPP)-based sensitizers for electrochemical or optoelectronic devices
The present invention relates to compounds of formula (I) based on DPP moiety being useful as metal-free organic sensitizers or dyes of type D-π-A in electrochemical or optoelectronic devices, their use as sensitizer or dye and an electrochemical or optoelectronic device comprising a compound of the invention.
US09697953B2 Multilayer ceramic electronic component and board having the same
There is provided a multilayer ceramic electronic component including: a multilayer ceramic capacitor (MLCC) including first and second external electrodes disposed to be spaced apart from one another on a mounting surface thereof; and first and second terminal electrodes including upper horizontal portions disposed on lower surfaces of the first and second external electrodes, lower horizontal portions disposed to be spaced apart from the upper horizontal portions downwardly, and curved vertical portions connecting one ends of the upper horizontal portions and one ends of the lower horizontal portions, having “⊂” and “⊃” shapes, and disposed on the mounting surface of the MLCC in a facing manner.
US09697949B2 Transformer and high voltage power supply apparatus having the same
A transformer including first coil unit and second unit, wherein one or more coils are wound on the bobbin of insulating material in at least one of the first coil unit and the second unit, and wherein the bobbin is formed with at least one partitioning flange for partitioning a coil winding surface of the bobbin into two winding surfaces along the longitudinal direction of the bobbin, is disclosed.
US09697946B2 Electronic component
An electronic component is provided which includes a helical coil having good coil characteristics and high reliability without peeling or breakage in each insulator layer. As compared to an existing configuration in which coil patterns are disposed on insulator layers 2a to 2d, respectively, so as to fully overlap each other in a plan view, portions where coil patterns 11 to 14 intersect each other in a plan view are dispersed and the number of the coil patterns 11 to 14 overlapping each other in each intersection portion is small. Thus, a change in thickness of a multilayer body in which the respective insulator layers 2a to 2d are stacked is suppressed. Therefore, the pressure applied when the respective insulator layers 2a to 2d are pressure-bonded is uniformly transmitted to the entire multilayer body, and thus it is possible to provide an electronic component having good coplanarity and high reliability.
US09697943B2 Laminating magnetic cores for on-chip magnetic devices
A laminating structure includes a first magnetic layer, a second magnetic layer, a first spacer disposed between the first and second magnetic layers and a second spacer disposed on the second magnetic layer.
US09697933B2 PTC device
The present invention relates to a new PTC device having a configuration with which protrusion of solder paste and/or an excess portion of epoxy resin do not adversely affect a jig. Such PTC device 30 comprises a PTC member 32 and leads 34 and 36 electrically connected to both sides of the PTC member the PTC member comprises a PTC element 38 and metal electrodes 40 and 42 placed on both sides of the PTC element respectively, each lead is electrically connected to the metal electrode respectively via an electrically conductive connection portion 50, and at least one 36 of the leads has a concave portion which is defined with a bottom portion 44 located adjacently to the metal electrode of the PTC member and a wall portion 46 surrounding the electrically conductive connection portion which connects the leads to the metal electrode.
US09697932B2 Method for manufacturing insulated wire
There is provided a method for manufacturing an insulated wire, including at least: coating an outer periphery of a running wire with an insulation coating material discharged from a coating material discharging tank; baking the insulation coating material by an incinerator, the insulation coating material being used for coating the outer periphery of the running wire; and cooling the running wire by a cooling mechanism so that a temperature of the running wire before being coated with the insulation coating material, is a specific temperature, based on a temperature of the running wire detected by a temperature detector, wherein the coating, the baking, and the cooling are repeated.
US09697928B2 Automated assembly sensor cable
An automated assembly sensor cable has a generally wide and flat elongated body and a registration feature generally traversing the length of the body so as to identify the relative locations of conductors within the body. This cable configuration facilitates the automated attachment of the cable to an optical sensor circuit and corresponding connector. In various embodiments, the automated assembly sensor cable has a conductor set of insulated wires, a conductive inner jacket generally surrounding the conductor set, an outer jacket generally surrounding the inner jacket and a registration feature disposed along the surface of the outer jacket and a conductive drain line is embedded within the inner jacket. A strength member may be embedded within the inner jacket.
US09697926B2 Flat cable
A flat cable includes a number of pairs of differential signal wires and a number of power wires distributed on two sides of the differential signal wires. The differential wires are horizontally and vertically arranged in a matrix.
US09697910B1 Multi-match error detection in content addressable memory testing
An aspect includes a method of multi-match error detection in content addressable memory (CAM) testing. The method includes loading a content addressing row of a CAM section with a row test address word. Data value rows of a random access memory (RAM) section are loaded with unique test patterns in each of the data value rows having a same number of on-state bits per data value row. A row test is initiated to search for a matching content addressing row in the CAM section corresponding to the row test address word. A row test result is received as one or more data value rows from the RAM section identified as having a content addressing row in the CAM section that matches the row test. The row test result is compared to an aspect of one or more of the unique test patterns to determine whether the row test has failed.
US09697909B2 Shift register
A shift register comprises a first switch, a second switch, a third switch, and a fourth switch. The first switch selectively conducts a first clock signal to a first output terminal as a first output signal based on a voltage level over the control terminal. The second switch selectively forces a voltage level of the first output signal to be equal to a voltage level of a second clock signal based on both of the second clock signal and a third clock signal inverted to the second clock signal. The third switch selectively defines a voltage over the control terminal to be a first voltage based on a first input signal. The fourth switch selectively forces the voltage level over the control terminal to be equal to the voltage level of the second clock signal based on both of the second clock signal and the third clock signal.
US09697908B1 Non-discharging read-only memory cells
Various implementations described herein may refer to and may be directed to non-discharging read-only memory cells. For instance, in one implementation, an integrated circuit may include a read-only memory (ROM) array including a plurality of ROM cells arranged into a column, where the column is disposed proximate to a bit line and to a reference voltage line. The plurality of ROM cells arranged into the column may include a plurality of non-discharging ROM cells positioned adjacently to one another, where each non-discharging ROM cell has a source terminal, a drain terminal, or both coupled to at least one adjacent non-discharging ROM cell. In addition, the plurality of non-discharging ROM cells may be coupled to the bit line using two or fewer connections.
US09697907B2 Apparatuses and methods using dummy cells programmed to different states
Apparatuses and methods for reducing capacitive loading are described. One apparatus includes a first memory string including first and second dummy memory cells, a second memory string including third and fourth dummy memory cells, and a control unit configured to provide first and second control signals to activate the first and second dummy memory cells of the first memory string and to further deactivate at least one of the third and fourth dummy memory cell of the second memory string.
US09697902B2 Nonvolatile semiconductor memory device and data programming method for memory cells
According to one embodiment, a nonvolatile semiconductor memory device includes memory cell units, bit lines, word lines, and a controller. Each of the memory cell units includes a plurality of memory cells connected in series. Bit lines are connected respectively to the corresponding memory cell units. Each of the word lines is commonly connected to control gates of the corresponding memory cells of the memory cell units. The controller is configured to control a programming operation of data to the memory cells. The controller is configured to execute a first procedure including programming the data to the memory cell connected to the (4n−3)th (n being a natural number) bit line and the memory cell connected to the (4n−2)th bit line, and a second procedure including programming the data to the memory cell connected to the (4n−1)th bit line and the memory cell connected to the 4nth bit line.
US09697899B1 Parallel deflate decoding method and apparatus
Described are apparatuses, methods and storage media associated with performing deflate decompression using multiple parallel content addressable memory cells.
US09697897B2 Memory device with combined non-volatile memory (NVM) and volatile memory
A memory device includes a volatile memory cell, a non-volatile memory cell, and a transfer system connected between the volatile memory cell and the non-volatile memory cell. The transfer circuit allows data transfer from the volatile memory cell to the non-volatile memory cell when the memory device is operating in a first mode, and from the non-volatile memory cell to the volatile memory cell when the memory device is operating in a second mode.
US09697895B1 Integrated circuit
An integrated circuit according to an embodiment includes: a plurality of first wiring lines; a plurality of second wiring lines intersecting with the plurality of first wiring lines; a plurality of resistive change memory elements provided in cross regions of the plurality of first and second wiring lines, each of which includes a first electrode connected to a corresponding first wiring line, a second electrode connected to a corresponding second wiring line, and a resistive change layer provided between the first and second electrodes, and in each of which a resistive state between the first electrode and the second electrode can be programmed from one of a first resistive state and a second resistive state, which has a larger resistance value than the first resistive state, to the other; and a driver driving the plurality of first and second wiring lines.
US09697889B1 Method and apparatus for read assist to achieve robust static random access memory (SRAM)
According to one general aspect, an apparatus may include a bit cell configured to store a bit of information. The apparatus may include a first voltage configured to supply the bit cell with power. The apparatus may include a wordline driver configured to cause the bit to be read from the bit cell. The wordline driver may be configured to operate during a read operation at a second voltage that is lower than the first voltage, wherein the second voltage is determined by charge sharing between a plurality of capacitances. The wordline driver may include a switch configured to disconnect the wordline driver from the first voltage before an input word line signal is applied to the wordline driver, and wherein the switch is responsive to a clock signal.
US09697887B2 SRAM bit-line and write assist apparatus and method for lowering dynamic power and peak current, and a dual input level-shifter
Described is an apparatus comprising a plurality of memory arrays, local write assist logic units, and read/write local column multiplexers coupled together in a group such that area occupied by the local write assist logic units and the read/write local column multiplexers in the group is smaller than it would be when global write assist logic units and the read/write global column multiplexers are used. Described is a dual input level-shifter with integrated latch. Described is an apparatus which comprises: a write assist pulse generator operating on a first power supply; one or more pull-up devices coupled to the write assist pulse generator, the one or more pull-up devices operating on a second power supply different from the first power supply; and an output node to provide power supply to a memory cell.
US09697885B1 Semiconductor memory device and method for transferring weak cell information
A semiconductor memory device includes: a weak cell controller for programming weak cell information, outputting the weak cell information in response to an initialization signal or a write end signal, and outputting a read end signal whenever the weak cell information is outputted; a memory cell array region that includes memory cells for storing data in response to a row active signal and a column selection signal, and includes a first cell region for storing the weak cell information; an information transfer control circuit for generating a column address based on a column counting signal generated by using the read end signal, and generating a row address whenever the column counting signal reaches a predetermined value in response to the initialization signal; a row circuit for enabling the row active signal; and a column circuit for outputting the column selection signal by decoding the column address.
US09697884B2 Variable width memory module supporting enhanced error detection and correction
Described are memory modules that support different error detection and correction (EDC) schemes in both single- and multiple-module memory systems. The memory modules are width configurable, and support the different EDC schemes for relatively wide and narrow module data widths. Data buffers on the modules support the half-width and full-width modes, and also support time-division-multiplexing to access additional memory components on each module in support of enhanced EDC.
US09697881B2 Methods of operating ferroelectric memory cells, and related ferroelectric memory cells and capacitors
Methods of operating a ferroelectric memory cell. The method comprises applying one of a positive bias voltage and a negative bias voltage to a ferroelectric memory cell comprising a capacitor including a top electrode, a bottom electrode, a ferroelectric material between the top electrode and the bottom electrode, and an interfacial material between the ferroelectric material and one of the top electrode and the bottom electrode. The method further comprises applying another of the positive bias voltage and the negative bias voltage to the ferroelectric memory cell to switch a polarization of the ferroelectric memory cell, wherein an absolute value of the negative bias voltage is different from an absolute value of the positive bias voltage. Ferroelectric memory cells are also described.
US09697880B2 Self-referenced read with offset current in a memory
Self-referenced reading of a memory cell in a memory includes first applying a read voltage across the memory cell to produce a sample voltage. After applying the read voltage, a write current is applied to the memory cell to write a first state to the memory cell. After applying the write current, the read voltage is reapplied across the memory cell. An offset current is also applied while the read voltage is reapplied, and the resulting evaluation voltage from reapplying the read voltage with the offset current is compared with the sample voltage to determine the state of the memory cell.
US09697879B2 Memory device with shared read/write circuitry
In some examples, a memory device may be configured to use shared read circuitry to sample a voltage drop across both a bit cell and a resistive circuit in order to perform a comparison that produces an output corresponding to the bit stored in the bit cell. The shared read circuitry can include a shared sense amplifier as well as shared N-MOS and P-MOS followers used to apply read voltages across the bit cell and resistive circuit.
US09697874B1 Monolithic memory comprising 1T1R code memory and 1TnR storage class memory
Providing for a monolithic memory device comprising a combination of a one-transistor, one-resistor (1T1R) memory array, and a one-transistor, multiple-resistor (1TnR, where n is a suitable integer greater than 1) memory array is described herein. By way of example, the monolithic memory device can be a stand-alone device, configured to perform functions in response to predetermined conditions and generate an output(s), or can be a removable device that can be connected to and operable with another device. In various embodiments, the 1TnR array having high memory density can serve as storage class memory (SCM) for the monolithic memory device, and the 1T1R array having high performance and efficacy can serve as code memory. In addition to the foregoing, the 1T1R array and the 1TnR array can be fabricated from at least one common layer or a common processing step, to simplify and lower cost of fabricating disclosed memory devices.
US09697873B2 Memory arrays
Some embodiments include memory arrays. The memory arrays can have global bitlines extending along a first horizontal direction, vertical local bitlines extending perpendicularly from the global bitlines, and wordlines extending along a second horizontal direction which is perpendicular to the first horizontal direction. The global bitlines may be subdivided into a first series at a first elevational level, and a second series at a second elevational level which is different from the first elevational level. The global bitlines of the first series can alternate with the global bitlines of the second series. There can be memory cell material directly between the wordlines and the vertical local bitlines. The memory cell material may form a plurality of memory cells uniquely addressed by wordline/global bitline combinations. Some embodiments include cross-point memory cell units that have areas of about 2F2.
US09697866B2 Device and method for measuring pitch and roll torques
Embodiments of the invention provide a device for measuring pitch and roll torques. The device comprises a sensor plate having a horizontal cross member, a vertical cross member and a surrounding member connecting ends of the horizontal and vertical cross members, wherein the horizontal cross member and the vertical cross member intersect each other at a centre region of the sensor plate; a VCM coil attached to the sensor plate and configured to generate a pitch and a roll torque when an electrical current is applied to the VCM coil; a first strain gauge attached to a surface of the horizontal cross member and configured to detect a horizontal strain caused by the pitch and roll torques; and a second strain gauge attached to a surface of the vertical cross member and configured to detect a vertical strain caused by the pitch and roll torques.
US09697865B2 Method and system for providing universal follow-me functionality
A method and system includes a plurality of video players and a plurality of remote control devices for implementing follow-me functionalities. Each remote control device has a unique ID and can control all the video players. The method and system receives a first control signal from a first remote control device to interrupt playback of a program by a first video player, interrupts playback of the program at the first video player, and stores the ID of the first remote control device and the status of the playback of the program. The method and system then receives a second control signal from a second remote control device to resume playback of the program at a second video player, checks the stored ID and the ID of the second remote control device, and if the two IDs are identical, resumes playback of the program at the second video player according to the status.
US09697862B2 Disk-shaped glass substrate, magnetic-disk glass substrate, method for manufacturing magnetic-disk glass substrate, and magnetic disk
A disk-shaped glass substrate for a magnetic-disk glass substrate includes an outer circumference having a roundness of 1.3 μm or less. A first reference circle is obtained with a least squares method from a first outline corresponding to a shape of a lap around the outer circumference. A second reference circle is obtained with a least squares method from a second outline obtained by performing low-pass filtering using a period in which the number of peaks per lap is 150 as a cut-off value on the first outline. A ratio of the second peak count value defined by the number of peaks of the second outline that project outward in a radial direction from the second reference circle to the first peak count value defined by the number of peaks of the first outline that project outward in a radial direction from the first reference circle is 0.2 or less.
US09697861B2 Magnetic disk substrate with specified changes in height or depth between adjacent raised or lowered portions and an offset portion on a main surface within a range of 92.0 to 97.0% in a radial direction from a center, a magnetic disk with substrate and a magnetic disk device with magnetic disk
A magnetic disk substrate having a flat main surface, an end face, and a chamfered face formed between the main surface and the end face. The substrate has an offset portion, present on the main surface within a range of 92.0 to 97.0% in a radial direction from a center of the substrate. A distance from the center of the substrate to the end face of the substrate in a radial direction is 100%, the offset portion being raised or lowered with respect to a virtual straight line connecting two points on the main surface, set at positions of 92.0% and 97.0%. A maximum distance from the virtual straight line to the offset portion in a direction perpendicular to the virtual straight line is a “maximum offset value.”
US09697859B1 Heat-assisted magnetic recording (HAMR) medium including a bi-layer that enables use of lower laser current in write operations
A heat-assisted magnetic recording (HAMR) medium includes a substrate, a bi-layer, a heat-sink layer, and a magnetic-recording layer. The bi-layer includes a seed layer disposed on the substrate, and a thermal-transport-control layer (TTCL) disposed on seed layer. The heat-sink layer is disposed on the TTCL; and the magnetic-recording layer is disposed on the heat-sink layer. The bi-layer is configured to enable use of a 50% thinner heat-sink layer that allows use of a reduced operating current of a laser in HAMR write operations while maintaining about the same write performance parameters as a HAMR medium that includes a thermal-barrier layer (TBL) and twice as thick heat-sink layer. A HAMR data-storage device that incorporates the HAMR medium within a HAMR disk, and a method for making the HAMR medium are also described.
US09697858B2 Perpendicular magnetic recording medium
A perpendicular magnetic recording medium is disclosed in which crystal axis orientation dispersion, crystal grain diameter, and crystal grain diameter dispersion in a magnetic recording layer are reduced. The perpendicular magnetic recording medium has a structure having, stacked sequentially on a non-magnetic substrate, at least an amorphous underlayer, a lower orientation control layer made of Ru or Ru alloy of an hcp structure, an upper orientation control layer that is made of alloy containing an element selected from the group consisting of Co and Ni and an element selected from the group consisting of Cr, W, and Mo and that has an fcc or hcp structure, an intermediate layer, and a magnetic recording layer.
US09697857B1 Three dimensional data storage media
A three dimensional magnetic recording media can consist of a coupling layer disposed between first and second vertically stacked recording layers. The coupling layer can provide exchange or antiferromagnetic coupling and allow the respective recording layers to be individually heat selected to different first and second coupling strengths through application of heat from a heat source.
US09697855B1 Perpendicular magnetic recording (PMR) write head with multiple layer trailing shield
Bits per inch (BPI) is increased, and faster risetime is achieved while adjacent track erasure (ATE) is maintained at an acceptable level by inserting a 10-12 kG magnetic (TS0) layer between a 19-24 kG hot seed layer and 16-19 kG magnetic layer in a trailing shield structure at the ABS. A back portion (TY0) of the 10-12 kG magnetic layer is formed in a back gap connection between a back portion of the 16-19 kG magnetic layer and a trailing side of the main pole layer. A front side of the TY0 layer is 1-2 microns from the ABS and thereby improves BPI and writer speed. Accordingly, throat height in the write head may be reduced to less than 500 nm and thereby enables better bit error rate (BER). The TS0 layer is responsible for maintaining clean ATE near a far side of the writer track.
US09697854B1 Heat assisted magnetic recording write apparatus having an inverse tapered waveguide
A heat assisted magnetic recording (HAMR) write apparatus has a media-facing surface (MFS) and includes a pole, coil(s) and a waveguide. The waveguide is optically coupled with a laser and directs energy toward the MFS. The waveguide includes an entrance, a bottom and a mode converter having a core, an inner cladding, high index layer(s) and an outer cladding. The core has sides that diverge in width. The core has a first index of refraction. The outer cladding has a second index of refraction less than the first index of refraction. The inner cladding has a third index of refraction not greater than the second index of refraction. The inner cladding is between the high index layer(s) and the core. The high index layer(s) are between the inner and outer cladding. The high index layer(s) have a high index of refraction greater than the second index of refraction.
US09697851B2 Note-taking assistance system, information delivery device, terminal, note-taking assistance method, and computer-readable recording medium
A note-taker terminal (200) and an information delivery device (100) are used. The information delivery device (100) includes a breathing detection unit (104) that specifies breathing sections from silent sections of uttered speech, a data processing unit (105) that determines, for every allocated time period of a note-taker, whether a breathing section exists in a range based on an end point of the allocated time period, and generates, if a breathing section exists, speech data of the utterance from a start point of the allocated time period until the breathing section, and, if a breathing section does not exist, speech data of the utterance from the start point until the end point of the allocated time period, and a data transmission unit (106) that transmits the speech data to the note-taker terminal (200). The note-taker terminal (200) receives the speech data, and transmits input text data to a user terminal (300) of a note-taking user.
US09697849B1 Systems and methods for audio based synchronization using energy vectors
Multiple audio files may be synchronized using energy vectors produced from energy portions of individual frequency energy representations. Individual energy samples and time values of individual energy vectors may be compared using a multi-resolution framework to correlate energy samples and time values of multiple audio tracks to one another.
US09697847B2 Acoustic signal processing system capable of detecting double-talk and method
An acoustic signal processing system and method. In accordance with an embodiment, the acoustic signal processing system includes an adaptive filter that filters a signal from a frequency band reservation module and generates a filter signal that is received by a subtractor. The subtractor generates an error signal that is used by a double-talk indicator module to generate a control signal that indicates the presence of double-talk.
US09697840B2 Enhanced chroma extraction from an audio codec
The present document relates to methods and systems for music information retrieval (MIR). In particular, the present document relates to methods and systems for extracting a chroma vector from an audio signal. A method (900) for determining a chroma vector (100) for a block of samples of an audio signal (301) is described. The method (900) comprises receiving (901) a corresponding block of frequency coefficients derived from the block of samples of the audio signal (301) from a core encoder (412) of a spectral band replication based audio encoder (410) adapted to generate an encoded bitstream (305) of the audio signal (301) from the block of frequency coefficients; and determining (904) the chroma vector (100) for the block of samples of the audio signal (301) based on the received block of frequency coefficients.
US09697839B2 Methods and apparatus for audio watermarking
Methods and apparatus for audio watermarking are disclosed. Example methods disclosed herein include obtaining a watermarked noise signal having energy in a first frequency band, the watermarked noise signal being associated with a first operating state of a device. Disclosed example methods also include adjusting the watermarked noise signal based on an ambient audio level sensed by an audio sensor. Disclosed example methods further include emitting the adjusted watermarked noise signal via a speaker in response to determining that the device is in the first operating state.
US09697837B2 Secured audio channel for voice communication
A security device for hindering data theft and data leaks via audio channel of a computer system is based on passing the audio signals through a coding vocoder that receives input audio signal from a computer and compressing the signal to a low bit-rate digital data indicative of human speech; and a decoding vocoder that decompress the digital data back to a secure audio signal. The data transfer of the protected audio channel is intentionally limited not to exceed the bit-rate needed to carry vocoder-compressed human speech which is well below the capabilities of unprotected audio channel. Both analog and digital audio ports may be protected. Hardware bit-rate limiter protect the system from software hacking.
US09697836B1 Authentication of users of self service channels
An interactive voice response (IVR) system comprises a memory storing recorded segments of speech by individuals, and a processor configured to enroll individuals. The enrollment process may comprise retrieving one or more of said recorded segments of speech by an individual from said memory and using the retrieved segments to create a voice print for the individual. The suitability of the voice print for authenticating the individual in an IVR system is then tested. This may be done using segments of speech of a predetermined maximum duration such as three seconds or some other amount commensurate with the typical duration of a voice response in an IVR system. An individual may be enrolled as suitable for IVR authentication if the voice print passed the suitability test. Individuals may be authenticated using a voice print only if the voice print has passed the suitability test.
US09697834B2 Text formatter with intuitive customization
A computer implemented method and system of formatting text output from a speech recognition system is provided. The method includes determining if a user correction to a text output from a speech recognition system can be accomplished by changing a formatting setting associated with the speech recognition system. The formatting setting is changed based on an inferential indication that the change to the formatting setting is acceptable to the user and/or an explicit confirmation from the user that the change to the formatting setting is acceptable.
US09697833B2 Audio-visual speech recognition with scattering operators
Aspects described herein are directed towards methods, computing devices, systems, and computer-readable media that apply scattering operations to extracted visual features of audiovisual input to generate predictions regarding the speech status of a subject. Visual scattering coefficients generated according to one or more aspects described herein may be used as input to a neural network operative to generate the predictions regarding the speech status of the subject. Predictions generated based on the visual features may be combined with predictions based on audio input associated with the visual features. In some embodiments, the extracted visual features may be combined with the audio input to generate a combined feature vector for use in generating predictions.
US09697827B1 Error reduction in speech processing
Features are disclosed for reducing errors in speech recognition processing. Methods for reducing errors can include receiving multiple speech recognition hypotheses based on an utterance indicative of a command or query of a user and determining a command or query within a grammar having a least amount of difference from one of the speech recognition hypotheses. The determination of the least amount of difference may be based at least in part on a comparison of individual subword units along at least some of the sequence paths of the speech recognition hypotheses and the grammar. For example, the comparison may be performed on the phoneme level instead of the word level.
US09697820B2 Unit-selection text-to-speech synthesis using concatenation-sensitive neural networks
Systems and processes for performing unit-selection text-to-speech synthesis are provided. In one example process, a sequence of target units can represent a spoken pronunciation of text. A set of predicted acoustic model parameters of a second target unit can be determined using a set of acoustic features of a first candidate speech segment of a first target unit and a set of linguistic features of the second target unit. A likelihood score of the second candidate speech segment with respect to the first candidate speech segment can be determined using the set of predicted acoustic model parameters of the second target unit and a set of acoustic features of the second candidate speech segment of the second target unit. The second candidate speech segment can be selected for speech synthesis based on the determined likelihood score. Speech corresponding to the received text can be generated using the selected second candidate speech segment.
US09697818B2 Systems and methods for dynamically improving user intelligibility of synthesized speech in a work environment
A method and apparatus that dynamically adjust operational parameters of a text-to-speech engine in a speech-based system are disclosed. A voice engine or other application of a device provides a mechanism to alter the adjustable operational parameters of the text-to-speech engine. In response to one or more environmental conditions, the adjustable operational parameters of the text-to-speech engine are modified to increase the intelligibility of synthesized speech.
US09697817B2 Tunable acoustic attenuation
An acoustic attenuation device extends from a first end to a second end and includes first and second sheets. A plurality of webs positioned between the first and second sheets cooperates with the first and second sheets to form a series of sound attenuation chambers containing a volume and mass of fluid. A first panel secured to the sheets closes the chambers at the first end of the device. A second panel secured to the sheets closes the chambers at the second end of the device. The device further includes first and second openings associated with each chamber and through which excited fluid resonates. The first and second openings extend through the first sheet into each chamber. The first openings have an invariable cross-section. At least one of the second openings has an adjustable cross-section for varying a resonant frequency of the chamber.
US09697813B2 Music context system, audio track structure and method of real-time synchronization of musical content
A system is described that permits identified musical phrases or themes to be synchronized and linked into changing real-world events. The achieved synchronization includes a seamless musical transition—achieved using a timing offset, such as relative advancement of an significant musical “onset”, that is inserted to align with a pre-existing but identified music signature, beat or timebase—between potentially disparate pre-identified musical phrases having different emotive themes defined by their respective time signatures, intensities, keys, musical rhythms and/or musical phrasing. The system operates to augment an overall sensory experience of a user in the real world by dynamically changing, re-ordering or repeating and then playing audio themes within the context of what is occurring in the surrounding physical environment, e.g. during different phases of a cardio workout in a step class the music rate and intensity increase during sprint periods and decrease during recovery periods.
US09697810B2 Strainer for a snare drum
A strainer is provided for a snare drum having a bottom drumhead. The strainer includes a snare assembly including a snare carrier and a plurality of snares coupled therewith. A throw-side component includes a bracket member releasably mounted to the snare drum and a slide member moveable relative to the bracket member and engaging the snare carrier. The slide member includes a slider handle fixed thereto and a locking toggle such that when the strainer is coupled to the snare drum, manual movement of the slider handle causes the snares to move toward the bottom drumhead, with the locking toggle being constructed and arranged to be 1) moved to a first, locking position engaging the bracket member so as to lock the slide member to the bracket member, and 2) moved to a second, release position releasing the slide member from engagement with the bracket member.
US09697809B2 Guitar tremolo bridge
A tremolo bridge for a guitar comprising a body, a neck attached to said body, a headstock attached to said neck, a plurality of tuners disposed on said headstock and adjacent the neck, at least one post extending from said body, each of said at least one post further comprising a V-shaped notch, and a plurality of strings, whereby each string of said plurality of strings is attached to the tremolo bridge, extends along the neck of the guitar, and is attached to a corresponding one of said plurality of tuners disposed on the headstock, said tremolo bridge comprising: a base plate, a block extending from said base plate, a tremolo arm attached to said base plate, and a locking mechanism for locking the position of the tremolo bridge.
US09697808B1 Stringed musical instrument with rotating neck
Provided is a foldable stringed having a rotating neck in which the fret board in the folded position is opposite the rear face and the mechanism employs a flexible cable system under variable tension.
US09697807B2 Electric guitar system for quick changes
An instant access guitar system allowing easy access to cavities in the body portion of the electric guitar. The cavities are covered by plates, a pick guard, flexible laminates or other suitable cover materials. The covers are held in place by (1) cut-outs in the guitar body and (2) magnets that magnetically attach to magnetic material mounted in the guitar body. The appearance of the guitar may be changed by changing the pick guard and the decorative laminate on the headstock. The sound of the guitar may be changed by having unique pickups and wiring releases pre-built in multiple configurations on multiple pick guards as modules to change in and out of the guitar at will with no tools or solder.
US09697806B2 Self-refresh control method, sink device thereof and display system thereof
A self-refresh control method for a display system includes receiving a frame from a video source of the display system; storing the frame in a storage module of the display system according to a writing timing sequence signal; accessing data stored in the storage module as a self-refresh frame according to a reading timing sequence, for outputting the self-refresh frame to a display device of the display system; and adjusting the reading timing sequence signal according to the writing timing sequence signal and the reading timing sequence signal.
US09697804B2 Presenting data in a graphical overlay
A system and computer program product for displaying data in a graphical overlay. The system overlays a first lens, including a first dataset, on a first region of the graphical overlay while a second lens, including a second dataset, overlaps the first lens. The first and second datasets are simultaneously displayed, and a correlation between the datasets is determined. Separation of the first and second lenses preserves a circumscribed region within each lens. The first dataset corresponds to first orientation position of the first lens. Rotation of the first lens to a second orientation position reconfigures the first dataset to provide a modified first dataset which corresponds to the second position. A rotational position may also be associated with points in time, a first position corresponding to a first point in time and the first dataset representing the first dataset at the first point in time.
US09697802B2 Display and display control circuit
A display control circuit of a display performs generation of overdrive processed data and detection of a proper direction of overdriving from current frame uncompressed compressed data obtained by performing compression processing and uncompression processing on compressed data corresponding to image data of a current frame, and previous frame uncompressed compressed data obtained by performing the compression processing and the uncompression processing on image data of a previous frame, and generates post-correction overdrive processed data by correcting the overdrive processed data according to the detected proper direction. The display control circuit transmits post-correction compressed data obtained by compressing the post-correction overdrive processed data to a driver as transfer compressed data.
US09697799B2 Perceptual luminance nonlinearity-based image data exchange across different display capabilities
A handheld imaging device has a data receiver that is configured to receive reference encoded image data. The data includes reference code values, which are encoded by an external coding system. The reference code values represent reference gray levels, which are being selected using a reference grayscale display function that is based on perceptual non-linearity of human vision adapted at different light levels to spatial frequencies. The imaging device also has a data converter that is configured to access a code mapping between the reference code values and device-specific code values of the imaging device. The device-specific code values are configured to produce gray levels that are specific to the imaging device. Based on the code mapping, the data converter is configured to transcode the reference encoded image data into device-specific image data, which is encoded with the device-specific code values.
US09697795B2 Video processing device and method
The present disclosure discloses a video processing device and method, the device comprising a dual matrix selecting module and a dual channel color data processing module. Due to the use of the dual channel color data processing module, two groups, i.e. an odd group and an even group, of pixel data can be processed simultaneously within one clock period. Since two dithering matrices are used when two adjacent frames of images are displayed, the structure is simple, and the processing speed is high. The present disclosure uses the algorithm period of two frame cycle for dithering in time and uses the dithering matrix of 2*2 for dithering in space, so as to achieve the effect of dithering 8 bit video data using 6 bit display data. Moreover, due to the use of two dithering matrices, the display performance of the display can be improved, two groups, i.e. an odd group and an even group, of pixel data are processed simultaneously within one clock, which reduces the working frequency of the circuit.
US09697793B2 Flat display apparatus and control circuit and method for controlling the same
In an exemplary flat display apparatus and control circuit and method for controlling the flat display apparatus, the flat display apparatus includes a plurality of gate driving units, each of which controls the operation of a scan line in the flat display apparatus. The flat display apparatus provides a first gate high level voltage signal and a second gate high level voltage signal to the gate driving units such that the first and second gate high level voltage signals are used as voltage signals transmitted to corresponding scan lines. The first and second gate high level voltage signals respectively include a falling edge with a slope. Duration time of the falling edge of the first gate high level voltage signal is longer than that of the falling edge of the second gate high level voltage signal.
US09697784B2 Liquid crystal device, method of driving liquid crystal device, and electronic apparatus
A liquid crystal device having a first substrate, a second substrate, and liquid crystal provided between the first substrate and the second substrate includes: a plurality of scanning lines provided in the first substrate; a plurality of data lines provided in the first substrate; a plurality of switching elements provided in correspondence with intersections of the plurality of scanning lines and the plurality of data lines; a plurality of pixel electrodes connected to the plurality of switching elements; a common electrode provided in correspondence with the pixel electrodes; a control circuit that alternately supplies a first voltage and a second voltage higher than the first voltage to the common electrode; and a data line driving circuit that alternately supplies a positive-polarity image signal, of which an electric potential is higher than the first voltage, and a negative-polarity image signal, of which an electric potential is lower than the second voltage, to the plurality of data lines.
US09697781B2 Liquid crystal display device with a plurality of synchronized timing controllers and display driving method thereof
The present invention provides a liquid crystal display device (LCD) and display driving method thereof. The LCD includes display panel; scan driver; a plurality of data drivers; first timing controller, for controlling scan driver, receiving and processing first signal, outputting synchronization signal and first driving control signal, the first driving control signal controlling first data driver to drive display of all pixels in a part of pixel rows of n pixel rows; and second timing controller, for receiving synchronization signal and second data signal, processing second data signal, outputting second driving control signal, second driving control signal controlling second data driver to drive display of all pixels in the other part of pixel rows of the n pixel rows. As such, through modifying input and output of two timing controllers, the present invention makes two timing controllers to synchronously support high resolution output of LCD.
US09697778B2 Reverse driving pulses in electrophoretic displays
An electrophoretic medium comprises a fluid and at least one species of particles disposed, When a first addressing impulse is applied to the medium, the first species of particles move in one direction relative to the electric field, but when a second addressing impulse, larger than the first addressing impulse, is applied to the medium, the first species of particles move in the opposed direction relative to the electric field.
US09697776B2 Organic light emitting display device and driving method thereof
An organic light emitting display device includes a storage area, a degradation compensator, and a display driver. The storage area stores accumulated data for a plurality of pixels. The degradation compensator determines degrees of degradation of the pixels based on the accumulated data, selects a flat up mode or a flat down mode, selects a reference pixel based on the selected mode, generates ratios of a maximum emission brightness of the reference pixel to a maximum emission brightness of the pixels as first coefficients, and generates modulated data for the pixels using the first coefficients and margin ratios. The panel driver transforms the modulated data to data voltages for the pixels, adds the modulated data to the accumulated data, and stores the accumulated data in the storage area.
US09697775B2 AMOLED pixel driving circuit and pixel driving method that implements threshold voltage compensation by directly gaining threshold voltage of driving TFT
The present invention provides an AMOLED pixel driving circuit and a pixel driving method. The AMOLED pixel driving circuit utilizes a 8T1C structure, comprising a first, a second, a third, a fourth, a fifth and a sixth, a seventh and an eighth thin film transistors (T1, T2, T3, T4, T5, T6, T7, T8), a capacitor (C1) and an organic light emitting diode (OLED). The AMOLED pixel driving circuit, by directly gaining the second thin film transistor (T2), i.e. the drive thin film transistor, can effectively compensate the threshold voltage of the drive thin film transistor and stabilize the current flowing through the organic light emitting diode (OLED) to ensure the uniform brightness of the organic light emitting diode (OLED) and improve the display effect of the pictures. The unnecessary irradiance of the organic light emitting diode (OLED) can be avoided to reduce the electrical power consumption.
US09697774B2 Organic light emitting display having a variable power supply for organic light emitting diode sensing and method of driving the same
An organic light-emitting display comprises a first transistor comprising a gate electrode connected to a scan line, a first electrode connected to a data line, and a second electrode connected to a first node, a second transistor comprising a gate electrode connected to the first node, a first electrode connected to a first power supply voltage, and a second electrode connected to a third node, a third transistor comprising a gate electrode connected to a sensing control line, a first electrode connected to the data line, and a second electrode connected to the third node and an organic light-emitting device comprising an anode connected to the third node and a cathode connected to a second power supply voltage, wherein the first power supply voltage is set to a level of a sensing voltage for a period of time during which the sensing voltage is provided to the data line.
US09697772B2 Light emitting device and method of driving the light emitting device
A light emitting device that achieves long life, and which is capable of performing high duty drive, by suppressing initial light emitting element deterioration is provided. Reverse bias application to an EL element (109) is performed one row at a time by forming a reverse bias electric power source line (112) and a reverse bias TFT (108). Reverse bias application can therefore be performed in synchronous with operations for write-in of an image signal, light emission, erasure, and the like. Reverse bias application therefore becomes possible while maintaining a duty equivalent to that of a conventional driving method.
US09697767B2 LED pixel unit circuit, driving method thereof, and display panel
Provided are an AMOLED pixel unit circuit, a driving method thereof and a display panel for realizing the threshold voltage compensation. The AMOLED pixel unit circuit includes: a light emitting module: a driving module configured to drive the light emitting module; a light emitting control module configured to control the light emitting module to emit light; a threshold compensation module configured to perform threshold voltage compensation for the driving module; a data voltage writing module configured to input a data voltage to the driving module; and an initialization module configured to initialize the threshold compensation module. The threshold voltage compensation is realized by modifying the pre-charging fashion to fixedly set the gate of the driving TFT to be at a data level lower than the high level such that the subthreshold saturation cutoff state is reached before the drain-source voltage becomes zero in the compensation stage.
US09697764B2 Display device having bent display area for reduced bezel width
The present disclosure relates to a display panel having a structure in which the left and right lateral side bezel areas are bent downward to reduce the width of bezel area visible to a user. The display device includes a transparent cover plate and a flexible display layer secured to the transparent cover plate. The transparent cover includes a flat portion. The flexible display layer includes a display area and a non-display area. The display area includes an upper flat area extending along a first plane below the flat portion of the transparent cover plate. The non-display area extends from at least an edge of the display area and at least part of the non-display area extends along a second plane for connection to receive a signal for displaying an image on the flexible display layer. A signal line between a signal source and the non-display area transmit the signal from the signal source to the non-display area.
US09697761B2 Conversion method and conversion system of three-color data to four-color data
The invention provides a conversion method of three-color data to four-color data, including steps: A) converting input RGB data to intermediate RGBW data according to first, second and third predetermined saturation parameters; B) obtaining first, second and third saturation adjust parameters according to the intermediate RGBW data and standard RGBW data; C) using the first, second and third saturation adjust parameters to respectively adjust the first, second and third predetermined saturation parameters; D) using the first, second and third predetermined saturation parameters after being adjusted to convert the input RGB data to output RGBW data. The invention further includes a conversion system of three-color data to four-color data.
US09697755B1 Modular and freely combinable tension fabric popup display
The invention discloses a freely combinable tension fabric popup display, the tension fabric popup display includes an exhibit grid frame, and aluminum grooved straight rods. The eight sides on the two planes of the exhibit grid frame are connected to the aluminum grooved straight rods. A popup display with a preset size and shape is provided by combining a plurality of tension fabric popup displays as needed. The aluminum grooved straight rods for the adjacent tension fabric popup displays are locked by a plurality of fasteners. The display before or after the combination is formed by inserting the silicon strips at the edges of the display into the grooves of grooved straight rods. The tension fabric popup displays of the invention can be combined freely to form various shapes, which are seamlessly attached by the fasteners.
US09697753B2 Shelf label holder
A main body of a label holder is made of an opaque material and includes a main panel having a top end, a bottom end and a plurality of bends that define the main panel into a plurality of sections. The sections include a first substantially vertical section having a front facing surface that is spaced behind a front facing surface of a second substantially vertical section by a depth of a substantially horizontal section. A sign sleeve is at least partially made of a transparent material and is coupled to the front facing surface of the first substantially vertical section. The sign sleeve is located between the front facing surface of the first substantially vertical section and a plane that is in alignment with the front facing surface of the second substantially vertical section.
US09697751B2 Interactive representation of clusters of geographical entities
Various embodiments enable, in a mapping context, various visual entities to be clustered into groups that do not occlude one another. In at least some embodiments, individual clusters are represented on a map by a puddle defined by a computed contour line. Users can interact with the puddle to acquire more information about the puddle's content. In at least some embodiments, user interaction can include zooming operations, clicking operations, hovering operations and the like.
US09697749B2 Interactive education system with physiological modeling
Patient simulator systems for teaching patient care are provided. In some instances, the patient simulator systems include a patient body comprising one or more simulated body portions. Generally, the patient simulator systems of the present disclosure provide physiological modeling. In one embodiment, the patient simulator includes a maternal simulator comprising a maternal circulatory model, a maternal cardiac ischemia model, and a maternal respiratory model and a fetal simulator comprising a fetal circulatory model, a fetal cardiac ischemia model, and a fetal central nervous system model. A controller in communication with the maternal and fetal simulators coordinates parameters of the maternal circulatory model, the maternal cardiac ischemia model, the maternal respiratory model, the fetal circulatory model, the fetal cardiac ischemia model, and the fetal central nervous system model to simulate physiological characteristics of a natural mother and fetus. Methods of utilizing the patient simulator systems are also provided.
US09697745B2 Auxiliary sensor for touchscreen device
Exemplary embodiments are described wherein an auxiliary sensor is removably attached to a touchscreen computing device and is communicably coupled to the device to provide additional user input to the computing device. In accordance with some embodiments, the additional user input may be used to affect how the computing device interprets and processes gestural user input from the touchscreen, or to simulate such input. In accordance with an illustrative embodiment, the auxiliary sensor establishes an optical path near the surface of the touchscreen and sensing user contact by observing blockage of the optical path by a user's pointing member.
US09697734B2 Information display device for vehicle and information display method for vehicle
An information display device for a vehicle includes a object detection sensor that detects a target object positioned around a host vehicle, and a display unit that displays a first object marker which is displayed so as to surround the target object detected by the object detection sensor on a display area positioned between a driver of the host vehicle and the target object, and in a case where a distance from the host vehicle to the target object is long, that displays a second object marker with a degree of emphasis of the vertical components suppressed compared to a degree of emphasis of the vertical components of the first object marker in a case where the distance from the host vehicle to the target object is short.
US09697731B2 Precision traffic indication
Precision traffic flow indication may involve receiving device data over a period of time representing a plurality traffic flow readings associated with a road involving a plurality of subsections. Calculating traffic flows and determining road subsections having similar traffic flows may also be involved. Also, indicating a different traffic flow level for a first subsection and a second subsection of road may be involved.
US09697730B2 Spatial clustering of vehicle probe data
A method and apparatus for identifying parking areas may include identifying a plurality of coordinates representing vehicle spatial data, partitioning the plurality of coordinates into at least two groups of vehicle locations based on at least one condition existing when the plurality of coordinates was identified, clustering the vehicle spatial data for a first group of the at least two groups of vehicle locations based on proximity, comparing dimensions of the clustered vehicle spatial data for the first group with other location data within the vehicle transportation network information, and defining a respective location of the clustered vehicle spatial data as a parking area of a plurality of parking areas. Each parking area is associated with a respective location in a vehicle transportation network. The parking area information may be used in the identification of a route from an origin to a primary destination.
US09697729B2 Systems and methods for estimating traffic signal information
Traffic signal information is estimated based on positioning system data obtained from a plurality of vehicles. Each data set includes the position and the velocity of a vehicle as functions of time. For an intersection having a traffic signal, an average acceleration of the vehicles when leaving the intersection is estimated, and an average deceleration of the vehicles when approaching the intersection is estimated. For each of a subset of the vehicles, a stop duration at the intersection is estimated based on the average acceleration, the average deceleration, and the positioning system data for the respective vehicle. A duration of a red phase of the traffic signal is estimated based on the stop duration of each of the subset of the vehicles.
US09697728B2 Projection system, projection apparatus, and method for operating projection apparatus
A projection system, a projection apparatus, and a method for operating the projection apparatus are provided. According to a characteristic of a sound transmitted between the projection apparatus and an electronic device external to the projection apparatus, the projection apparatus is adapted to be controlled by the electronic device or is adapted to control the electronic device to execute a corresponding operation.
US09697727B2 Remote control apparatus
A remote control apparatus wirelessly connected with a host apparatus comprises a wireless transmission unit, a control unit and an operation unit. The wireless transmission unit is wirelessly connected with the host apparatus. The control unit is electrically connected with the wireless transmission unit and the operation unit. The host apparatus is configured with an integration application unit, and the control unit authenticates the integration application unit and acquires a permission for operating at least one function of an operation system of the host apparatus. The operation unit can receive an operation mode, and the control unit generates a control signal according to the operation mode. The control unit transmits the control signal to the host apparatus through the wireless transmission unit for choosing one of the operation system and the integration application unit to trigger at least one event according to the control signal.
US09697724B2 Transmission line measuring device and method for connectivity and monitoring
A method for connecting low power radios into a self-assembling and self-healing network with multiple portals to higher speed networks such as, but not limited to, electrical or optical Ethernet is provided for monitoring transmission lines, for example. A clamp or other device is provided that includes an integral or associated current transformer and associated circuitry with design elements to address high temperature operation or other operating parameters. An arrangement of sensors is provided (e.g., sensors can be associated with clamps or positioned along infrastructure being monitored and without dependence on any clamps or other devices) that are designed to communicate and operate in an geographically distributed array to provide increased and autonomous monitoring of large utility, highway, communication and similar networks. A unique collection of sensors (e.g., an anemometer with no moving parts) provides comprehensive diagnostics for improved operation of large geographic scale utility, highway, communication and similar infrastructure.
US09697721B1 Systems, methods, components, and software for detection and/or display of rear security threats
Across the planet, the fear of physical attacks is experienced daily by millions of men and women, especially those walking or running alone in secluded areas. In many instances, attacks start from behind, exploiting a weakness in our forward-facing vision system. To address this, the present inventor devised, among other things, a rear-facing clip-on sensor that attaches to the back of a user, detecting rear-approaching objects or persons, and vibrating or beeping to alert the user. In some embodiments, the clip-on sensor includes a digital camera and a wireless transceiver to communicate with a smartphone or smartwatch, not only allowing the smartphone or smartwatch to alert the user via audible, visible, and/or tactile (haptic) alarms, but also to send SOS signals and real-time audio and/or video signals to designated persons or security services.
US09697720B1 Multifunctional personal emergency safety device
A personal emergency safety device operates with the push of a button to warn of an emergency problem situation. The device is discretely configured as a belt buckle that calls up to three numbers with the push of a single button and provides location information as well as audio and video recording.
US09697719B2 Security system, security arrangement and method therfore
The present invention relates to a security system for personal protection, having a first unit and a second unit separate from the first unit, wherein the first unit has a camera device, a microphone device, a siren device, a safety device, an attachment device, and a communication device for communication wirelessly with the second unit. The second unit has a microphone device and a communication device for communication wirelessly with the first unit. The second unit further has a communication device for wirelessly sending an alarm message to a network of one or more recipients. The security system is configured to, when triggered to send an alarm message, activate the microphone device of the first unit and the microphone device of the second unit, such that the alarm message contains an audio recording from an environment of a user of the security system. A method and a security arrangement therefore are also presented.
US09697715B2 System and method for locating a patient
A method for tracking a patient in a medical facility is disclosed. The method includes determining whether a patient is to be moved, indicating the time at which the patient should start to be moved, and interrogating a RFID sensor on the patient at a predetermined time interval to determine when the patient has been moved.
US09697705B2 Tactile sensation providing apparatus and control method for tactile sensation providing apparatus
A tactile sensation providing apparatus includes a touch sensor 11, a tactile sensation providing unit 13 configured to vibrate a touch face of the touch sensor 11, a tactile sensation provision control unit 14 configured to control drive of the tactile sensation providing unit 13, and a main control unit 17 configured to control an operation of the tactile sensation provision control unit 14 based on an output of the touch sensor 11. The main control unit 17 determines whether an object is touching a predetermined area of the touch face based on the output of the touch sensor 11, and starts the operation of the tactile sensation provision control unit 14 when determining that the object is touching the predetermined area, or stops the operation of the tactile sensation provision control unit 14 when determining that the object is not touching the predetermined area.
US09697703B2 Capsule for guiding light and associated contactless payment device
A capsule is provided that aligns with at least one light source. The capsule includes a rim having its opaqueness interrupted to as to form at least four transparent portions. The capsule is capable of being oriented according to at least two positions: a first position in which two of the at least four portions, simultaneously let through light coming from the at least one light source; and a second position in which the rim blocks light coming from the at least one light source.
US09697702B2 Display device and method for controlling the same
A display device is provided, which includes a display configured to display a user interface (UI) screen, a status display which includes a plurality of light emitting elements arranged on an outline region of the display, and a controller configured to control a light emitting status of the plurality of light emitting elements so as to provide a light interaction in which the plurality of light emitting elements operate in a preset display pattern based on an interaction occurring on the UI screen.
US09697701B2 Foot actuated doorbell button assembly
A foot actuated doorbell button assembly can comprise a housing that contains a button as well as a pedal that can be stepped on to actuate the button. The housing can be configured to mount to a wall or to the ground so that the pedal is positioned at or near the ground where it can be easily stepped on. The housing can contain wired or wireless circuitry to allow the doorbell button assembly to be used with virtually any of the existing doorbell assemblies currently available.
US09697697B2 Card game
“n” cards of a first hand may be dealt. None to all of the n cards may be discarded. When card(s) are discarded, card(s) may be drawn to complete the first hand to have n cards to form a final first hand. The final first hand may be duplicated to a second hand of n cards, or card(s) may be selected from the final first hand to duplicate to a second hand and additional card(s) drawn to have n cards. None to all of the n cards of the second hand may be discarded. When card(s) are discarded, card(s) may be drawn to complete the second hand to have n cards to form a final second hand. A determination of whether the final first and second hands are winning hands may be made.
US09697694B2 Gaming device and methods of allowing a player to play a gaming device having selectable awards
A gaming machine for providing a slot game to a player is described herein. The gaming machine includes a display device and a controller for displaying a game to a player. The controller is configured to randomly determine an outcome of the game and display the outcome on the display device, determine a first award as a function of the outcome, and determine a second award as a function of the first award. The first award includes a first number of free games and a first award multiplier. The second award includes a second number of free games and a second award multiplier. The controller allows the player to select one of the first award and the second award and responsively provides the selected one of the first award and the second award to the player.
US09697693B2 Interactive slot machine method and apparatus using a key group from a plurality of groups
A gaming device that does not employ pay lines is provided, and has a playfield that is subdivided into a plurality of groups. The configuration of the groups could be done manually by the player, or at random, and changes for each game. At least one key group is used to define key symbols that must be repeated at other groups for a winning combination of symbols to occur.
US09697690B2 Gaming system and method of gaming
There is described a gaming system including an award controller for allocating an award at a plurality of gaming machines. The award controller is arranged to allocate, in response to a win at a first gaming machine of the plurality of gaming machines, an award to a player of at least one further gaming machine of the plurality of gaming machines based on a location of the at least one further gaming machine.
US09697689B2 Gaming machine
There is disclosed a gaming machine having a plurality of jackpot prizes associated with it, a player's eligibility to win one of the plurality of jackpot prizes being dependent upon an amount wagered. In a one aspect there is provided a gaming machine having a game control means arranged to play a game, a bet selecting arrangement for selecting one of a number of predetermined amounts to wager on the outcome of the game, each of said predetermined amounts to wager having at least one dedicated jackpot prize associated with it, a first display means configured to display the outcome of said game, wherein in the event that a predetermined winning event occurs said game includes the award of at least one dedicated jackpot prize associated with a respective selected predetermined amount wagered on the game.
US09697686B2 Computer-implemented system, method and device for displaying the total count and value of casino chips
Disclosed is a computer-implemented method for displaying the total count and value of casino chips stored by a casino dealer during dealing. The method comprises receiving transmissions representative of the reception of casino chips within a groove of a dealer tray, keeping count of the number of chips within the groove at any given time by keeping count of the number of transmissions received, aggregating the values of the individual chips within the groove at any given time and displaying the count and the aggregated value of the chips on a display panel located on the dealer tray.
US09697681B2 Gaming system for tracking player activity during virtual sessions at a gaming machine
A gaming system has a central authority connected to a plurality of gaming machines. Player activity is tracked at the gaming machines during regular gaming sessions and during virtual gaming sessions. Such data is transmitted to the central authority for providing player points in a player account file of a central database. Regular gaming sessions occur between player card insertion and player card removal. Virtual gaming sessions may occur prior to player card insertion as well as after player card insertion. For example, a coin-in event prior to player card insertion will establish a virtual session, and credits remaining on the credit meter at a card-out event will establish a virtual gaming session.