Document Document Title
US09667384B2 Apparatus and method for transmitting and receiving forward error correction packet
A method and an apparatus for transmitting and receiving a packet in a broadcasting and communication system are provided. The method includes splitting a source packet block including source packets into a plurality of source packet subblocks, converting the source packet subblocks to source symbol subblocks, respectively, generating a plurality of first repair symbol blocks by encoding the source packet subblocks using a first error correction code, configuring an error correction source packet by adding a source error correction payload IDentifier (ID) to source symbols included in the source symbol subblocks and configuring an error correction repair packet by adding a repair error correction payload ID to repair symbols included in the first repair symbol subblocks, and transmitting the error correction source packet and the error correction repair packet.
US09667381B2 Packet decoding method and apparatus
A method and an apparatus for encoding and decoding packets using a polar code is provided. The method includes acquiring a plurality of blocks constituting the packet, extracting a plurality of codeword candidates corresponding to the blocks, selecting some of the codeword candidates in a descending order of posterior probability among the codeword candidates corresponding to the blocks, combining the selected codeword candidates into a plurality of codeword combinations, selecting a codeword combination having the highest posterior probability and passed Cyclic Redundancy Check (CRC) test without error among the plurality of codeword combinations, and decoding the selected codeword combination. The packet encoding and decoding apparatus and method of the present disclosure is capable of encoding and decoding packets in a unit of blocks efficiently.
US09667379B2 Error control coding for orthogonal differential vector signaling
Using a transformation based, at least in part, on a non-simple orthogonal matrix, data may be transmitted over a data bus in a manner that is resilient to one or more types of signal noise, that does not require a common reference at the transmission and acquisition points, and/or that has a pin-efficiency that is greater than 50% and may approach that of single-ended signaling. Such transformations may be implemented in hardware in an efficient manner. The transformation may be combined with methods from forward error correction to lower the required transmission power.
US09667378B2 Multi-granular feedback reporting and feedback processing for precoding in telecommunications
A communications system comprises a second device (28) and a first device (30). The first device (30) is of a type which receives, on a downlink over a radio interface from a second device, precoded information (29). In an example mode the first device 28 generates a multi-part feedback signal (22) which is configured to affect content of a precoder matrix (40) utilized by the second device (28). On an uplink over the radio interface to the second device, at least two different parts of the multi-part feedback signal are transmitted with two respective different transmission granularities in time and/or frequency.
US09667375B2 Channel establishment method and device
A channel establishment method and device are provided. The method includes: establishing a media channel between a first node and a second node; establishing a signal channel between a third node and a fourth node after the media channel is established, wherein the signal channel passes a frequency slot matrix of one or more intermediate nodes between the third node and the fourth node and a traffic engineering link between any two nodes; and allocating frequency spectrum to the signal channel from available frequency spectrum of the traffic engineering link, wherein the frequency spectrum includes multiple split frequency spectrums which bear one optical channel and each of which contains a plurality of optical carriers or only contains a single optical carrier. The solution can address the problem as to how to effectively plan and manage frequency spectrum for an introduced flexible grid technology and improve waveband frequency spectrum efficiency.
US09667374B2 Method and apparatus for construction of compact optical nodes using wavelength equalizing arrays
Example embodiments of the present invention relate to An optical node comprising of at least two optical degrees; a plurality of directionless add/drop ports; and at least one wavelength equalizing array, wherein the at least one wavelength equalizing array is used to both select wavelengths for each degree, and to perform directionless steering for the add/drop ports.
US09667369B2 Interface circuit for transmitting and receiving digital signals between devices
A video signal and an audio signal are TMDS transmitted from a source device to a sink device. Through a reserved line and a HPD line provided separately from a TMDS transmission line, an Ethernet™ signal is bidirectionally transmitted, and also, a SPDIF signal is transmitted from the sink device to the source device. The Ethernet™ signal bidirectionally transmitted between Ethernet™ transmitter/receiver circuits is differentially transmitted by an amplifier and is received by the amplifier. The SPDIF signal from a SPDIF transmitter circuit is common-mode transmitted from an adder and is received by the adder to be supplied to the SPDIF receiver circuit.
US09667368B2 Telecommunication system using multiple nyquist zone operations
Telecommunication systems using multiple Nyquist zone operations are provided. In one aspect, a telecommunication system can include a first section and a second section. The first section can receive signals from at least one transmitting base station or transmitting terminal device. The received signals have frequencies in multiple frequency bands. The first section can also sample the received signals such that the received signals are aliased. The first section can also combine the aliased signals from the frequency bands into a combined frequency band in a common Nyquist zone. The second section can extract signals from the combined frequency band. The extracted signals are to be transmitted at frequencies in a frequency band from a Nyquist zone that is different than the common Nyquist zone. The second section can also transmit the extracted signals to at least one receiving base station or receiving terminal device. Other embodiments are disclosed.
US09667363B2 Reporting a modified signal quality value during antenna diversity imbalance
A device may determine a first signal quality value associated with a wireless signal received by a first antenna of the device, may determine a second signal quality value associated with a wireless signal received by a second antenna of the device, and may determine a combined signal quality value based on the first signal quality value and the second signal quality value. The device may apply an offset value to the first signal quality value to form a modified signal quality value, may compare the combined signal quality value and the modified signal quality value, and may selectively report the modified signal quality value or the combined signal quality value based on comparing the combined signal quality value and the modified signal quality value.
US09667360B2 Proximate communication with a target device
Systems and methods may use proximate communication to retrieve information pertaining to a target device. In one example, the method may include detecting the target device within a vicinity of a user device, receiving an information request response communication including information pertaining to the target device, and receiving an operation request response communication including information pertaining to a performed operation.
US09667359B2 Periodic calibration for communication channels by drift tracking
A method and system that provides for execution of a first calibration sequence, such as upon initialization of a system, to establish an operation value, which utilizes an algorithm intended to be exhaustive, and executing a second calibration sequence from time to time, to measure drift in the parameter, and to update the operation value in response to the measured drift. The second calibration sequence utilizes less resources of the communication channel than does the first calibration sequence. In one embodiment, the first calibration sequence for measurement and convergence on the operation value utilizes long calibration patterns, such as codes that are greater than 30 bytes, or pseudorandom bit sequences having lengths of 2N−1 bits, where N is equal to or greater than 7, while the second calibration sequence utilizes short calibration patterns, such as fixed codes less than 16 bytes, and for example as short as 2 bytes long.
US09667358B2 Impairment compensation
A method is provided for compensating for impairment of an electrical signal output from a device under test (DUT), the impairment resulting from an impairment network. The method includes measuring an impaired electrical signal received at an electronic analyzer via the impairment network; applying a coded pulse sequence to the impairment network; estimating an impairment transfer function corresponding to the impairment based on the applied pulse sequence; and correcting the measured electrical signal using the impairment transfer function to determine the electrical signal output from the DUT.
US09667353B2 Methods of providing body area network communications when a user touches a button of a wireless electronic device, and related wireless electronic devices and wearable wireless electronic devices
Methods of providing communications between a wearable first wireless electronic device and a second wireless electronic device are provided. The methods include establishing a Body Area Network (BAN) link, through a human body of a user that is wearing the wearable first wireless electronic device, between the wearable first wireless electronic device and the second wireless electronic device, when the user touches a conductive button on the second wireless electronic device. Related wireless electronic devices and wearable wireless electronic devices are also provided.
US09667347B2 Optical transmitter, optical receiver, method of compensating non-linear distortion, and communication apparatus
A non-linear distortion compensator includes: a first signal generator configured to generate a signal with a second multivalued level lower than a first multivalued level from an input signal; a non-linear distortion calculator configured to calculate non-linear distortion of the signal with the first multivalued level based on the signal with the second multivalued level generated by the first signal generator; and a non-linear compensator configured to compensate the non-linear distortion of the signal with the first multivalued level based on the non-linear distortion calculated by the non-linear distortion calculator.
US09667345B2 Method, apparatus, and system for encoding and decoding visible light signal
The present disclosure provides a method, an apparatus, and a system for encoding and decoding a visible light signal. The encoding method includes the following steps: dividing to-be-transmitted data into a plurality of data units, where each data unit includes one or more bits; converting the data units into a plurality of electrical signal units, where for each electrical signal unit, the number of level transitions is used to represent the one or more bits of a corresponding data unit, and an interval indicated by a predetermined level exists between adjacent electrical signal units, where a level in each electrical signal unit has a first level duration, and the predetermined level between adjacent electrical signal units has a second level duration; combining the electrical signal units to obtain an encoded electrical signal; and transmitting the encoded electrical signal in a visible light signal form.
US09667342B2 Optical phase noise extracting device and optical phase noise extraction method
An apparatus includes: a first measurer configured to measure first phase data indicating a temporal variation in a phase of a non-transferred signal that is an optical signal modulated by an optical phase modulation scheme and output from a transmitting device to an optical transmission path as the non-transferred signal; a second measurer configured to second phase data indicating a temporal variation in the phase of the optical signal transferred by the optical transmission path as a transferred signal on a side of a receiving device; a generator configured to generate differential data indicating a difference between the first phase data and the second phase data; and an extractor configured to use the differential data to extract, from the optical signal on the side of the receiving device, optical phase noise generated due to the optical transmission path.
US09667337B2 Intelligent broadband relay for wireless networks for connectivity to mobile or portable devices
An ultrawideband radio transceiver/repeater provides a low cost infrastructure solution that merges wireless and wired network devices while providing connection to the plant, flexible repeater capabilities, network security, traffic monitoring and provisioning, and traffic flow control for wired and wireless connectivity of devices or networks. The ultrawidebande radio transceiver/repeater can be implemented in discrete, integrated, distributed or embedded forms.
US09667332B1 MIMO network system and interference eliminating method thereof
A MIMO network system and an interference eliminating method thereof are provided. MIMO network system includes a first mobile station and a base station. The base station has a plurality of antennas which are used for transmitting data to the first mobile station and receiving data from a second mobile station at the same time. The first mobile station determines an interference quality value according to a signal from the second mobile station and transmits the interference quality value to the base station. The base station determines a first receiving performance of the first mobile station according to the interference quality value and adjusts an antenna setting of the antennas according to the first receiving performance.
US09667331B2 Restricted aperiodic CSI measurement reporting in enhanced interference management and traffic adaptation
A method, an apparatus, and a computer program product for wireless communication are provided. The apparatus may be a UE. The UE determines a first CSI subframe set including a first set of subframes of a frame and a second CSI subframe set including a second set of subframes of the frame. Subframes in the first set of subframes are different than subframes in the second set of subframes. The UE determines a CSI reference subframe in one of the first CSI subframe set or the second CSI subframe set. The UE measures CSI in the CSI reference subframe. The UE receives an aperiodic CSI request in a triggering subframe in one of the first CSI subframe set or the second CSI subframe set. The triggering subframe is after the CSI reference subframe.
US09667326B2 Transmission method, transmission device, reception method and reception device
A transmission method includes mapping processing, phase change processing, and transmission processing. In the mapping processing, a plurality of first modulation signals and a plurality of second modulation signals are generated using a first mapping scheme, and a plurality of third modulation signals and a plurality of fourth modulation signals are generated using a second mapping scheme. In the phase change processing, a phase change is performed on the plurality of second modulation signals and the plurality of fourth modulation signals using all N kinds of phases. In the transmission processing, the first modulation signals and the second modulation signals are respectively transmitted at a same frequency and a same time from different antennas, and the third modulation signals and the fourth modulation signals are respectively transmitted at a same frequency and a same time from the different antennas.
US09667324B2 Diversity receiver front end system with amplifier phase compensation
Diversity receiver front end system with amplifier phase compensation. A receiving system can include a first amplifier disposed along a first path, corresponding to a first frequency band, between an input of the receiving system and an output of the receiving system. The receiving system can include a second amplifier disposed along a second path, corresponding to a second frequency band, between the input of the receiving system and the output of the receiving system. The receiving system can include a first phase-shift component disposed along the first path and configured to phase-shift the second frequency band of a signal passing through the first phase-shift component based on a phase-shift caused by the first amplifier at the second frequency band.
US09667321B2 Predictive recommendation engine
Systems and methods for alerting a user device when an objective is mastered according to a piecewise Gaussian distribution updated according to a Bayesian method are disclosed herein. The system can include a user device having a network interface to exchange data with a server via a communication network, and an I/O subsystem to convert electrical signals to user interpretable outputs user interface. The system can include a server that can: receive a response from the user device; identify a user associated with the response; receive user attribute data; identify a next objective; provide a data packet from the aggregation of data packets to the user via the user device; receive a response from the user device; update the user attribute data according to a Bayesian method; and generate and provide an alert to the user device.
US09667314B1 Programmable repeater circuits and methods
An integrated circuit includes a buffer circuit, a receiving circuit, and a programmable repeater circuit. The programmable repeater circuit includes a routing input and an enable input. The programmable repeater circuit buffers an input signal received at the routing input from the buffer circuit through a first conductor to generate an output signal that is provided to an input of the receiving circuit through a second conductor only in response to an enable signal at the enable input enabling the programmable repeater circuit.
US09667313B2 Communication system for telephone line access with crosstalk mitigation
The present disclosure includes systems and techniques relating to wired communication channels, such as telephone lines in a bundled telephone cable. In some implementations, a system includes telephone lines bundled together; electronic equipment including a first transceiver device for each of the telephone lines, which is configured to coordinate transmissions over a respective telephone line; and second transceiver devices coupled respectively with the telephone lines such that each second transceiver device is respectively paired with a first transceiver device; each pair of first and second transceiver devices is configured to communicate over the respective telephone line connecting the pair using a Medium Access Control (MAC) cycle split into predefined time slots for downstream communication and upstream communication; and the first transceiver devices are synchronized with each other to align the MAC cycle and the predefined time slots across the telephone lines.
US09667311B2 Pulse position modulation scheme impulse radio transmitter and radio communication system
A pulse position modulation scheme impulse radio transmitter includes: a bipolar return-to-zero type short-pulse generator; a bandpass filter that has a predetermined pass frequency band and which allows an output of the bipolar return-to-zero type short-pulse generator to pass; a transmission amplifier that amplifies an output of the bandpass filter; and a transmission antenna, wherein the bipolar return-to-zero type short-pulse generator includes: a trigger flip-flop with a position modulation function that outputs a pulse-width-variable pulse in each period of a clock signal, the pulse-width-variable pulse being inverted in each period of the clock signal and the pulse width of the pulse-width-variable pulse differing in accordance with transmission data; and a pulse generation filter that generates a positive pulse or a negative pulse in accordance with a direction in which a varying edge of the pulse-width-variable pulse changes.
US09667310B2 Efficient rake receiver finger selection
A receiver for receiving an input signal is disclosed. The receiver includes a processor, a memory, a plurality of sub-receivers configured to receive a plurality of versions of the input signal through a plurality of transmission channels, a sub-receiver selection module configured to select one more of the plurality of sub-receivers using expected contributions to signal-to-noise (SNR) of an output signal based on an uncertainty of the estimated contributions. The receiver also includes a combiner to combine outputs of the selected sub-receivers to produce the output signal.
US09667308B2 Method and apparatus for generating a spread-spectrum clock
This disclosure provides an apparatus for generating a spread-spectrum clock, which comprises: a multi-phase clock generator generating a pre-determined number of first clock signals having substantially identical period and different phases; a spread spectrum clock controller producing an instruction signal according to a first pre-determined spread spectrum target; and a clock selector receiving the instruction signal and dynamically selecting a clock signal from the first clock signals according to the instruction signal so as to produce a first spread spectrum signal; wherein the first spread spectrum signal has a spread spectrum corresponding to the first pre-determined spread spectrum target.
US09667305B2 Receiver-transmitter
A receiver-transmitter includes active two-face phased arrays comprising transmit-receive modules. Each module includes two radiating elements, a transmitter, two receivers, two isolator switches, mixers and a phase shifter. The two-face phased arrays are either unidimensional or two-dimensional. The arrays are arranged in the horizontal plane at an angle of 75-105° to each other while keeping the capability of all-around looking. The transmit-receive module is provided with an additional phase shifter. Each phase shifter can be permanently connected, via a selector switch, to one of the receivers or to the transmitter, and the transmitter is connected, via a switch and circulators, to the radiating elements. Alternatively, each phase shifter can be connected to the radiating elements with the use of different frequencies and/or with the use of a different signal coding, corresponding to different frequencies and coding of the receivers receiving mode.
US09667294B2 Ultra-low power long range transceiver
A low power long range transceiver is presented. The transceiver includes: an antenna configured to receive an RF signal; an analog front-end circuit configured to receive the RF signal from the antenna and pre-condition the RF signal by at least one of amplify the RF signal, shift frequency of the RF signal and filter the RF signal; and a demodulator configured to receive the preconditioned signal from the front-end circuit and an assertion trigger signal signifying an end of a predefined time period, where the demodulator, in response to the assertion trigger signal, outputs a data value for a given data bit in the RF signal. A controller is also configured to receive the assertion trigger signal and, in response to the assertion trigger signal, disables at least one component of the transceiver, thereby reducing power consumption.
US09667288B1 Time varying notch filter
The present disclosure includes systems and techniques relating to time-varying notch filter. In one implementation, an apparatus includes a time-variant notch filter and a controller. The time-variant notch filter includes a notch depth and a notch bandwidth centered on a notch frequency. At least one of the notch depth or the notch bandwidth is based on a coefficient of the notch filter. The controller is configured to estimate a power of a packet being received and compare the estimated power of the packet to a predetermined threshold. The controller is also configured to set, conditioned on determining that the estimated power of the packet is greater than the predetermined threshold, a value of the coefficient to a first value such that the packet bypasses the time-variant notch filter.
US09667285B2 Flexible multi-channel wireless audio receiver system
A flexible multi-channel diversity wireless audio receiver system for routing, processing, and combining multiple radio frequency (RF) signals containing audio signals received on respective antennas is provided. The wireless audio receiver system provides flexible routing of multiple RF signals in different selectable modes, and low latency uninterrupted reception of signals in harsh RF environments by combining multiple RF signals to maximize signal-to-noise ratio. The audio output may be generated in an uninterrupted fashion and mitigate multipath fading, interference, and asymmetrical noise issues. Received RF signals may also be cascaded by the wireless audio receiver system to allow daisy chaining.
US09667279B2 Systems and methods for a universal antenna module
Systems and methods are provided for wireless communication circuitry (202) that includes (1) a first antenna matching circuit (213) configured to tune a first antenna (208) to a first subset of a plurality of frequency bands or a second subset of the frequency bands, and including a first switch (220) with selectable states corresponding to the first and second subsets; (2) a second antenna matching circuit (215) configured to tune a second antenna (210) to a third subset of the frequency bands or a fourth subset of the frequency bands, and including a second switch (222) with selectable states corresponding to the third and fourth subsets; and (3) a third antenna matching circuit (211) configured to tune a third antenna (206) to a fifth subset of the frequency bands. The circuitry is operable with a plurality of service providers associated with the fifth subset and one of the other subsets.
US09667278B2 Radio communication device and method for controlling the radio communication device
A determiner determines that the voice communication frequency of the voice band to be used by a subject station for a voice communication with a distant station is permitted to be changed to the voice communication frequency of a selected distant station, the voice communication frequency of the selected distant station being included in predetermined information disclosed by the selected distant station, when the predetermined information satisfies a predetermined condition set in the subject station. When an instruction to change the voice communication frequency to the voice communication frequency of the selected distant station is issued, a frequency change controller performs a control to change the voice communication frequency if the determiner determines that the voice communication frequency is permitted to be changed.
US09667275B2 Apparatus and method for transmitting and receiving packet in broadcasting and communication system
A method and an apparatus for transmitting and receiving a packet in a broadcasting and communication system are provided. The method and apparatus allows a receiver to recognize data in a packet lost due to data loss occurring in a network. To this end, Forward Error Correction (FEC) control-related information is generated, a packet including the generated FEC control-related information is generated, and the packet is transmitted. The FEC control-related information includes at least one of FEC configuration-related information and FEC encoding configuration-related information.
US09667273B2 Apparatus and method for correcting error in mobile communication system using non-binary low-density parity-check codes
Various embodiments of the present disclosure adjusts the size (nm) of a message input to a corresponding check node in case the unsatisfied check equation increases as the iteration count increases.Another embodiment of the present disclosure relates to a method for selecting a message and grasps the data distribution characteristics of the message vector values converted using the signal to noise ratio (SNR) and modulation and coding scheme (MCS) parameters of the receiver to select the message value with a value smaller than the threshold value in each message vector.
US09667271B2 Path encoding and decoding
This invention relates to a system, method and computer program product for encoding an input string of binary characters including: a cellular data structure definition including a starting empty cell; one or more path definitions defining paths through the data structure; a character reading and writing engine for writing a binary character to an empty cell with a predefined initial position; a next cell determination engine for determining a next empty cell by methodically checking cells along one of the paths in the data structure until an empty cell is located; a loop facilitator for looping back to the writing next character step and the determining next cell step until there are no more data characters or a next empty cell is not determined; and a serialization deserialization engine for methodically serializing the data structure into a one dimensional binary string of characters representing an encoded string of alphanumeric characters.
US09667269B2 Technique for compressing XML indexes
A database server exploits the power of compression and a form of storing relational data referred to as column-major format, to store XML documents in shredded form. The column values that are to be stored for shredded XML documents are separately analyzed for a XML document to determine whether to store a particular column in column-major format or row-major format, and what compression technique to use, if any.
US09667266B1 VDD-referenced sampling
A voltage sampling circuit is provided that may directly connect a non-zero power supply voltage VDD to switching circuits during input voltage sampling, setting a common mode voltage without using reference voltages produced by a reference voltage generator circuit, and without requiring a common mode buffer circuit. The voltage sampling circuit may be used in an operational amplifier input stage such as for a pipelined ADC circuit, or in a comparator circuit. A SAR ADC circuit is also provided, comprising a control circuit, the voltage sampling circuit, a capacitor array, and a comparator circuit for comparing outputs occurring from charge redistributions. The voltage sampling circuit may enable increased power efficiency, avoid leakage concerns, and increase maximum input voltage swing. Reference plate switches in the voltage sampling circuit may include gate-boosted devices or thicker-oxide I/O devices. The devices may include n-channel field-effect transistors or high threshold voltage p-channel field-effect transistors.
US09667261B2 Integrated circuit and clock data recovery circuit
An integrated circuit includes a comparator capable of generating an up/down signal by comparing a feedback signal with a reference signal; a restoration signal generation unit capable of enabling a restoration signal when the up/down signal maintains an identical value for greater than or equal to a first specific time and changes afterwards; a processing circuit including one or more stages for sequentially processing the up/down signal, wherein a last one of the one or more stages holds a process result thereof for a second specific time when the restoration signal is enabled; and a feedback unit capable of generating the feedback signal in response to the process result of the last stage.
US09667260B2 Current synthesizer correction
An adjustable current-synthesizer may generate synthesized current representative of an actual current, according to a model of a circuit that produces the actual current. The current synthesizer may under-sample a current sense signal derived from the actual current to obtain a few samples of the actual current, which are then used to adjust the synthesized current, thereby ensuring accuracy of the synthesized current. Sample values of the actual current are compared with corresponding generated values of the synthesized current to obtain offset values. In order to maintain monotonicity in the synthesizer results, the offset values are used to make adjustments to the slope of the synthesized current. The slope of the synthesized current may also be adjusted according to the slope of the actual current. Sub-Nyquist sampling of the actual current may be performed on the down-slope, with up-slope adjustments made based on the offset adjustment and down-slope adjustment.
US09667257B2 Secure manufacturing of programmable devices
According to an embodiment, a programmable logic device includes a plurality of logic blocks and a logic unit. The logic blocks are grouped into one or more partitions. The logic unit controls external access to the one or more partitions, controls programming of the one or more partitions and controls interconnection and operation of the one or more partitions during operation of the programmable logic device.
US09667255B2 Multiple gate voltage generation for FET switches in radio frequency circuits
Circuits and corresponding methods that provide for selection among multiple different positive and/or multiple different negative FET gate drive voltages for FETs in which well-tuned gate drive voltages are needed or desirable for optimal results in a radio frequency integrated circuit. Embodiments include FET gate drive variable voltage generator configurations which provide multiple different positive and/or multiple different negative FET gate drive voltages. In alternative embodiments, an IC may include multiple positive voltage generators and/or multiple negative voltage generators, each voltage generator providing an output voltage different from at least one other voltage generator. The voltage generators include charge pump based circuits and digital-to-analog converters. Each FET device requiring a well-tuned gate drive voltage is selectably coupled to at least one set of positive and negative voltage generators.
US09667253B2 Input pin state detection circuit and method therefor
A state-detection circuit facilitates the detection of the state of an input pin relative to several different types of input circuits. According to an example embodiment, a state-detection circuit includes a plurality of comparators and circuit components, configured to provide a plurality of binary output signals that collectively indicate a state of an input pin to which the comparators are coupled. The state-detection circuit is configured to facilitate the detection of several different types of input circuits, based upon the binary output signals.
US09667249B2 Domestic appliance device
A household appliance apparatus includes a display screen and an input unit which has at least one substantially transparent input device. In order to achieve advantageous ease of use with little design expenditure, the input device covers only a partial region of the display screen. The input device may hereby be configured as a conductive layer.
US09667245B2 High voltage zero QRR bootstrap supply
An electrical circuit arranged in a half bridge topology. The electrical circuit includes a high side transistor; a low side transistor; a gate driver and level shifter electrically coupled to a gate of the high side transistor; a gate driver electrically coupled to a gate of the low side transistor; a capacitor electrically coupled in parallel with the gate driver and level shifter; a voltage source electrically coupled to an input of the gate driver and level shifter and an input of the gate driver; and, a bootstrap transistor electrically coupled between the voltage source and the capacitor. A GaN field-effect transistor is synchronously switched with a low side device of the half bridge circuit.
US09667240B2 Systems and methods for starting up analog circuits
Circuits, systems, and methods for starting up analog devices are provided. One circuit includes an output node at an output voltage (VOUT), a comparator configured to be coupled to a reference voltage (VREF), a feedback loop coupling the output node to the comparator, and a turbo circuit coupled between the output and the output node. The turbo circuit is configured to increase VOUT, the comparator is configured to compare VOUT and VREF, and the turbo circuit is enabled and disabled based on the comparison of VOUT and VREF. One system includes an analog device coupled to the above circuit. A method includes enabling the startup portion to start up the driver portion when VOUT is outside a predetermined voltage of VREF, disabling the startup portion when VOUT is within the predetermined voltage, and enabling the driver portion to drive the analog device subsequent to disabling the startup portion.
US09667238B2 Duty cycle correction circuit and image sensing device including the same
A duty cycle correction circuit includes an inversion block suitable for generating a first inverted clock that is in an inversion relationship with a first clock and a second inverted clock that is in an inversion relationship with a second clock, in response to the first clock and the second clock, and a correction block suitable for generating a first corrected clock having a corrected duty cycle relative to the first clock and a second corrected clock having a corrected duty cycle relative to the second clock, based on a logic state of the first clock, a logic state of the second clock, a logic state of the first inverted clock, and a logic state of the second inverted clock.
US09667237B2 Hardware delay compensation in digital phase locked loop
In a digital phase locked loop comprising a PLL loop including a first software-implemented controlled oscillator (SDCO) responsive to a control value to generate output phase and frequency values locked to a reference input signal, and a hardware-implemented controlled oscillator responsive to output phase and frequency values from said first SDCO to synthesize said clock signals, hardware delays are compensated for by sampling said synthesized clock signals, or derivatives thereof, to generate synthesized clock phase values. The synthesized clock signal phase values are compared with feedback phase values derived from the PLL loop to generate a compensation value to modify the synthesized clock signals or derivatives thereof.
US09667232B2 System and method for parallel configuration of hybrid energy storage module
A hybrid energy storage system is configured to control pulsed power. A first dynamo-electric machine is coupled to an inertial energy storage device and has multiple input stator windings configured to accept input power from a source. A polyphase output stator winding is configured to deliver electric power having a first response time to a DC bus. A secondary energy storage system is coupled to the DC bus and is configured to convert its stored energy to electric power in a bidirectional manner. A second dynamo-electric machine has an input stator winding and at least one polyphase output stator winding coupled to a converter, the converter coupled to a DC output. A polyphase boost exciter is configured to derive energy from the DC bus and excite the second machine tertiary stator winding, wherein the second machine is configured to be excited at a faster rate than the first response time of the first machine.
US09667231B1 Fast frequency divider circuit using combinational logic
The various technologies presented herein relate to performing on-chip frequency division of an operating frequency of a ring oscillator (RO). Per the various embodiments herein, a conflict between RO size versus operational frequency can be addressed by dividing the output frequency of the RO to a frequency that can be measured on-chip. A frequency divider circuit (comprising NOR gates and latches, for example) can be utilized in conjunction with the RO on the chip. In an embodiment, the frequency divider circuit can include a pair of latches coupled to the RO to facilitate dividing the oscillating frequency of the RO by 2. In another embodiment, the frequency divider circuit can include four latches (operating in pairs) coupled to the RO to facilitate dividing the oscillating frequency of the RO by 4. A plurality of ROs can be MUXed to the plurality of ROs by a single oscillation-counting circuit.
US09667228B2 Apparatus for and method of programmable matching network for multiple signal types
An apparatus and method are provided. The apparatus includes a multiplexer, including a first input, a second input, a third input, and an output; a first transistor, including a gate, a first terminal, and a second terminal; a first variable capacitor, including a first terminal, a second terminal, and an input; a first inductor, including a first terminal and a second terminal; a second transistor, including a gate, a first terminal, and a second terminal; a second inductor mutually coupled to the first inductor, including a first terminal and a second terminal; a balun-bias switch, including a first input, a second input, a third input, and an output; a second capacitor, including a first terminal, and a second terminal; and a port-switch, including a first input, a second input, a third input, and an output.
US09667219B2 Phase noise measurement and filtering circuit
Methods and apparatuses for measuring a phase noise level in an input signal are disclosed. An input signal can be delayed to generate a delayed version of the input signal. Next, a phase difference can be detected between the input signal and the delayed version of the input signal. A phase noise level in the input signal can then be determined based on the detected phase difference. The measured phase noise level can then be used to suppress phase noise in the input signal.
US09667218B2 Temperature controlled acoustic resonator comprising feedback circuit
An acoustic resonator device includes an annular acoustic resonator, a heater coil and a heat sensor. The annular acoustic resonator is positioned over a trench formed in a substrate of the acoustic resonator device. The heater coil is disposed around a perimeter of the annular acoustic resonator, the heater coil including a resistor configured to receive a heater current. The heat sensor is configured to adjust the heater current in response to a temperature of the heater coil. A feedback circuit is used to control a temperature of the acoustic resonator device.
US09667212B2 Gain control method, module, and wireless signal receiver using the same
An exemplary embodiment of a method illustrates a gain control method executed in a wireless signal receiver. The gain control method has the following steps. A wideband channel is continuously monitored to check whether an interference signal exists in a wireless signal. When the interference signal exists in the wireless signal, an interference received signal strength indicator is obtained. A front end gain of the wireless signal receiver is controlled according to the interference received signal strength indicator. When the interference signal exists in the wireless signal, the wireless signal receiver is prohibited from using a maximum front end gain.
US09667211B1 Variable gain and slope active topology
A circuit includes an electrical gain element, a variable reactance element, and a controller. The electrical gain element is arranged to receive and change an amplitude of a signal over a set frequency range. The variable reactance element is connected to the electrical gain element. The controller is configured to control the variable reactance element to have a reactance such that the electrical gain element has a set gain slope as a function of signal frequency over the set frequency range.
US09667209B2 Amplifying device and offset voltage correction method
An output voltage delay time caused by the relationship between offset voltage and input voltage is shortened. A single power supply amplifying device includes first and second amplifying units, a state detecting unit, and an offset voltage correcting unit. The first amplifying unit has differential pair transistors and amplifies the difference between input voltages. The second amplifying unit amplifies a first output voltage of the first amplifying unit. The state detecting unit detects a state where a negative offset voltage that causes a second output voltage of the second amplifying unit to be lower than the input voltage occurs, and a potential of the input voltage is lower than the absolute value of the negative offset voltage. The offset voltage correcting unit then corrects the negative offset voltage to a positive offset voltage that causes the second output voltage to be higher than the input voltage.
US09667200B2 Peak detecting cascode for breakdown protection
Peak detecting cascode for breakdown protection. In some embodiments, a power amplifier can include an amplifying transistor configured to amplify a radio-frequency (RF) signal, and a bias circuit coupled to a bias node of the amplifying transistor and configured to yield a bias voltage at the bias node. The power amplifier can further include a bias adjustment circuit that couples an output node of the amplifying transistor and the bias circuit. The bias adjustment circuit can be configured to adjust the bias voltage in response to a potential difference between the output node and the bias node exceeding a threshold value.
US09667198B2 Power amplifier
The disclosed power amplifier has: a first amplifying unit and a second amplifying unit provided with a plurality of amplifying circuits connected in parallel in which a bias voltage can be adjusted in accordance with a control signal supplied from outside, the first amplifying unit and the second amplifying unit for amplifying an input signal by each amplifying circuit and combining and outputting the amplified signal; a divider for dividing the input signal to the first amplifying unit and the second amplifying unit; and a combiner for combining and outputting an output signal of the first amplifying unit and an output signal of the second amplifying unit.
US09667196B2 Envelope tracking power converter
A tracking power converter for a radio frequency power amplifier includes a boost converter circuit, a switching network circuit, a filter circuit, and a controller circuit. The boost converter circuit provides a boosted voltage in response to a battery voltage. The switching network provides a switching signal in response to the boosted voltage, a first switch enable signal, a second switch enable signal, and a third switch enable signal. The filter circuit provides a power converter output voltage in response to the switching signal. The controller circuit provides the first switch enable signal, the second switch enable signal, and the third switch enable signal in response to a predetermined reference voltage, the switching voltage, the boosted voltage, and the battery voltage.
US09667191B2 Ultrasound lens cleaner driver with frequency selectable oscillator
A frequency selectable driver circuit (driver circuit) includes a current drive transistor between a first and second node for driving a frequency selectable oscillator (FSO) coupled therebetween that includes a first LC network including an inductor L2 and a capacitor C2 in series and a second LC network in series with the first LC network. The second LC network includes a capacitor bank including capacitors in parallel including switches for switching (selectable capacitors) and an inductor L3 in parallel to the capacitor bank. Values of L2 and C2 provide a low frequency point fL which the LC network is overall capacitive, and in a frequency range between fa and fb above fL with only a portion of selectable capacitors selected a capacitance of the capacitor bank and value of L3 results in an overall impedance for the second LC network that is capacitive between fa and fb and inductive elsewhere.
US09667190B2 Device for controlling sample temperature during photoelectric measurement and solar cell measurement device using same
Disclosed herein is a device for controlling a sample temperature during photoelectric measurement of the sample. The device for controlling a sample temperature during photoelectric measurement of the sample includes: a sample stage to which a measurement target sample is fixed; a cooling unit for cooling the sample by injecting air; and a temperature measuring unit having a thermometer that measures a temperature of the sample. The device has an effect of easily controlling the temperature of a measurement target sample by employing a direct control method for a sample temperature, in which air or cooled air is injected to the sample.
US09667189B2 Control of electrically excited synchronous machine drives for ride through and controlled braking operations
One exemplary embodiment is method of operating an electrically excited synchronous machine (EESM) system. The system includes a converter operatively coupled with one or more stator windings, an exciter operatively coupled with one or more field windings, a controller operatively coupled with the converter and the exciter, and a power supply operatively coupled with the converter and the exciter. The controller determines whether a power supply fault condition exists and whether EESM system is operating in a motor mode or a generator mode. If the power supply fault condition exists and the EESM system is operating in the motor mode, entering one of a motor ride through control mode and a motor controlled braking control mode If the power supply fault condition exists and the EESM system is operating in the generator mode, entering one of a generator ride through control mode and a generator controlled braking control mode.
US09667188B2 Flow control actuator
An actuator (1′) for driving a regulating element (30) for controlling a fluid flow in a flow channel (29) includes an electric motor (4) for driving the regulating element (30) and a control unit (2) for controlling a current provided to the electric motor (4). A resistive element (3) including a resistor (5) and a NTC thermistor (6) connected in parallel across the resistor (5) is positioned in a current path from the control unit (2) to the motor (4). Accordingly, when the ambient temperature increases, the decreasing resistance of the resistive element (3) counterbalances the increasing resistance of the motor windings, resulting in a less varying current from the control unit (2) to the motor (4) and therewith in a less varying output torque of the motor (4).
US09667186B2 Rotation angle estimation module for sensorless vector control of PMSM
A rotation angle estimation module is provided. The rotation angle estimation module includes: a fixed flux instruction estimation unit calculating a rotating flux (λsd, λsq) and a fixed flux instruction (λsα*, λsβ*) based on a rotation angle θ and the current (Isα, Isβ) of a fixed coordinate system; a fixed flux estimation unit calculating a fixed flux (λsα, λsβ) based on the voltage (Vsα, Vsβ) of the fixed coordinate system, and the current (Isα, Isβ) and fixed flux error (Δsα, Δsβ) of the fixed coordinate system; a fixed flux error estimation unit using the fixed flux instruction (λsα*, λsβ*) and the fixed flux (λsα, λsβ) to calculate the fixed flux error (Δsα, Δsβ) and feed the errors back to the fixed flux estimation unit; and a trigonometric function calculation unit calculating the rotation angle θ based on the rotating flux (λsd, λsq) and the fixed flux (λsα, λsβ).
US09667185B2 Method and device for operating an electromotive fan drive
A method and a device for operating a closed-loop or open-loop speed-controlled electric motor of a fan drive, which motor is connected to an on-board system voltage of a motor vehicle and the motor speed of which is set to a defined first desired speed, wherein, if the on-board system voltage fluctuates, the motor speed is set to a desired speed that is lower compared with the first desired speed.
US09667182B2 Method for controlling a brushless electric motor
The invention describes a method for controlling a sensorless, brushless DC motor that is controlled via a bridge circuit preferably using pulse width modulation (PWM) having precommutation. According to the invention, in the braking operation each commutation interval is divided into two phases. A drive phase, lasting from the start of the commutation interval up to zero crossing in which the motor is controlled with the normal PWM, and a braking phase, lasting from zero crossing up to the next commutation time in which at least two motor phases are short-circuited and/or in which the PWM is operated with recovered energy. The efficiency of the control circuit is as low as possible so as to ensure that the braking energy is consumed in the control circuit.
US09667180B2 Inverter
An inverter includes a first series circuit in which a first switching element and a second switching element are connected in series; a capacitor connected in parallel to the first series circuit; a first current detection device that detects current that flows in the first series circuit; and a discharge test execution device that outputs a signal of bringing the first switching element and the second switching element to a conducting state, and that outputs a signal of switching one of the first switching element and the second switching element to a non-conducting state before predefined power flows in the first switching element, based on a detection result by the first current detection device.
US09667179B2 Multi-phase motor control apparatus and electric power steering apparatus using the same
A multi-phase motor control apparatus that reduces the occurrence of the vibrations and the noises by setting the shift amount per time more finely after realizing a reduction in processing ability of a CPU by using a one-shunt type current detection circuit and an electric power steering apparatus using the same. The apparatus includes a PWM-signal generating section that generates plural second each-phase PWM-signals within two control periods based on the current estimation value and the carrier signal, and in a case that a phase shift amount of a predetermined phase in a just before control period is zero and a phase shift amount of a predetermined phase in a present control period is not zero, the phase shift control section gradually increases the phase shift amount from zero in the present control period and a next control period, and uses the second each-phase PWM-signals in the next control period.
US09667172B2 Inverter
An inverter for the selective feeding of effective power and reactive power into a power grid has two serially connected intermediate circuit capacitors, the joint connection of which defines a median voltage level between a positive voltage level and a negative voltage level. It also has first, second, third, and fourth semiconductor switches having free-wheeling diodes respectively connected in parallel, which are arranged serially in this sequence between the positive and the negative voltage levels, the joint connection of the second and third semiconductor switches being connected to the power grid via a choke. The inverter also has serially connected first and second diodes, the joint connection of which is at the median voltage level, and whose second connection is connected to the joint connection of the first and second semiconductor switches and of the third and fourth semiconductor switches. Joint connections of two of the first to fourth semiconductor switches are connected to additional chokes, which by additional semiconductor switches form switchable paths for accepting free-wheeling currents. In this manner, it is possible to avoid putting stress on diodes as a result of the reverse recovery effect.
US09667168B2 System and method for synchronous rectification with enhanced detection of small currents
A system and method of synchronous rectification includes a synchronous rectifier circuit. The synchronous rectifier circuit includes a direct current (DC) load coupled between a DC output node and a ground node, an alternating current (AC) source applying an AC waveform to an AC input node, an upper switch coupled between the DC output node and the AC input node, and a lower switch coupled between the AC input node and the ground node. In a first state, the upper switch is turned on and the lower switch is turned off. In a second state, the upper switch is turned off and the lower switch is turned on. In a third state, the lower switch is operated in an enhanced detection mode. The synchronous rectifier circuit transitions from the second state to the third state when the voltage of the AC input node increases above a threshold voltage.
US09667165B2 Power conversion apparatus
A power conversion apparatus includes a semiconductor module that includes a main body containing at least one semiconductor element, power terminals projecting from the main body to be connected to a high-voltage DC power supply and high-voltage signal terminals projecting from the main body, and is configured to convert a DC power supplied from the high-voltage DC power supply to an AC power by switching operation of the semiconductor element. The power conversion apparatus further includes a low-voltage component connected to a low-voltage DC power supply and a control circuit board on which a control circuit for controlling the switching operation of the semiconductor element is formed. The control circuit board is connected with low-voltage signal terminals extending from the low-voltage component and the high-voltage signal terminals. The low-voltage and high-voltage signal terminals are solder-connected to the control circuit board.
US09667164B2 Voltage-source converter full bridge module IGBT configuration and voltage-source converter
The invention relates to a full Bridge module, for connecting an electrical device such as a DC capacitor to an electrical circuit. The full bridge module comprises: a first and a second terminal to connect to the electrical circuit; a third and a fourth terminal to connect to the electrical device. The full bridge module further comprises a first to a fourth switch that connect the first and the second terminal to the third and fourth terminal. The first and the second switches are arranged on a first surface, the third and the fourth switches being arranged on a second surface that is parallel to the first surface. The invention relates also to a Voltage-source converter.
US09667163B1 Five phase power distribution system
A system for providing increased energy efficiency and harmonic reduction has a source of three phase AC electrical potential, a three phase to five phase power transformer converter coupled to the source of three phase AC electrical potential, a five phase cable coupled to the three phase to five phase power transformer converter, and at least one load coupled to the five phase cable.
US09667161B2 Power converter and method for controlling power converter that adjust duty cycle of switching circuit based on input voltage
A power converter includes a switching circuit, a power conversion circuit that receives an input voltage via the switching circuit and converts the input voltage into an output voltage, an input voltage sense circuit that detects the input voltage and generates an input voltage sense signal, and a PWM controller that adjusts a duty cycle of the switching circuit based at least in part on the input voltage sense signal. The power converter also includes an output sense circuit that detects the output voltage and generates an output voltage sense signal, wherein the PWM controller adjusts the duty cycle of the switching circuit based at least in part on the input voltage sense signal and the output voltage sense signal.
US09667160B1 Step-down direct current converter
A step-down DC converter configured to smooth ripple voltage. The step-down DC converter includes a ripple-filtering inductor, a power isolating and converting unit, a power switch, a first capacitor, a second capacitor, a first rectifying switch, a second rectifying switch, and a first inductor. The power isolating and converting unit includes a plurality of windings for separating the step-down-DC converter into an input stage and an output stage. The power switch and the first capacitor are arranged at the input stage, and the first capacitor is connected to the power switch. The second capacitor, the first rectifying switch, the rectifying switch, and the first inductor are arranged at the output stage, the second capacitor is connected to one terminal of the first inductor, and the other terminal of the first inductor is connected to the first rectifying switch and the second rectifying switch.
US09667152B2 Power conversion system and power conversion method
A power conversion system includes at least two power converters and a current sharing bus, each power converter including a switching circuit, a power conversion circuit configured to receive an input voltage via the switching circuit and to provide a local output current, an output sense circuit configured to detect the local output current and to generate a local output current sense signal, a current sharing terminal coupled to the local output current sense signal via a resistor and coupled to the current sharing bus; and a PWM controller configured to adjust a duty cycle of the switching circuit based at least in part on the local output current sense signal provided by the output sense circuit and an average current signal on the current sharing bus.
US09667151B2 Integrated magnetic component and converter using the same
An integrated magnetic component includes a magnetic core and a plurality of windings. The magnetic core includes at least four magnetic columns. The windings include a primary winding, a first secondary winding, a second secondary winding, and an inductor winding. The primary winding, the first secondary winding and the second secondary winding are wound on one of the magnetic columns. The inductor winding is wound on another magnetic column, and the inductor winding is coupled to the connection where the first secondary winding and the second secondary winding couple to each other. By integrating a transformer and a filter inductor into the integrated magnetic component, the number of the magnetic components, the overall volume, and the weight may be reduced while the mechanical properties may be promoted and the loss of the component connections may be reduced.
US09667132B2 Flyback converter
According to one aspect, embodiments herein provide a flyback converter comprising an input, an output, a rectifier, a transformer having a primary winding and a secondary winding, a switch, the switch being closed in a first mode of operation and open in a second and third mode of operation, and a regenerative snubber circuit, wherein the flyback converter is configured such that in the first mode of operation, the DC power from the rectifier charges the transformer, wherein the flyback converter is configured such that, in the second mode of operation, the snubber circuit is configured to store leakage energy from the primary winding, and wherein the flyback converter is configured such that, in the third mode of operation, the snubber circuit is configured to provide the stored energy to the primary winding. The flyback converter may also have high power factor at the input while operating from AC input.
US09667123B2 Electric motor having a thermal fuse
An electric motor for driving a motor vehicle component, particularly a fan wheel for cooling coolant water, contains a rotor that is rotatably mounted opposite a stator, and an electronic system. The electronic system contains a punched grid provided with a plastic over-mold and a current path which conducts the motor current and has two current path ends spaced apart from one another forming an interruption point that is bridged by a thermal fuse. The thermal fuse has a spring-loaded contact bridge which is held so as to pivot about an axis that extends perpendicularly to the plane in which the interruption point lies.
US09667119B2 Rotational damper
An electric rotational damper includes a generator which including a stator and a rotor; a damper housing having a housing attachment, wherein the stator is connected with the damper housing, and wherein the housing attachment and the stator in fixed rotative relationship with the damper housing; a transmission connecting a coupling lever with the rotor of the transmission of the rotational damper; a housing part connected with and co-rotating with the transmission, wherein the housing part is in surrounding relationship with the rotor, and wherein the housing attachment is in surrounding relationship with the housing part; and a centrifugal brake arranged between the housing part and the housing attachment.
US09667117B2 Magnetically coupled flywheel
A stabilization system for a rotating load, such as a flywheel, includes a mechanical bearing to continuously support a shaft of the rotating load so as to hold the shaft at a substantially fixed axis of rotation. A magnetic stabilization assembly includes a plurality of electromagnets arranged around the shaft. Control circuitry for controls a resultant magnetic field generated by the electromagnets such that the magnetic field acts on a ferromagnetic element of the shaft to reduce imbalance forces acting on the shaft.
US09667114B2 Stator, manufacturing method therefor, and rotary electric machine that includes stator
A stator is configured so as to have an annular shape by linking core blocks that are each produced by laminating electromagnetic steel sheets and that each have a yoke portion and a tooth portion by bendable first linking portion, concentrated winding coils are each produced by winding a conductor wire around the tooth portion for a number of turns so as to pass through concave spaces that are formed by the trunk portions and first and second guiding portions of first and second insulating bobbins, and current-carrying member holding portions that hold first current-carrying members that configure the concentrated winding coils into alternating-current connections are constituted by holding grooves that are each formed so as to open radially outward and so as to pass through the first guiding portions circumferentially, and that are arranged in three layers in an axial direction.
US09667110B2 Rotor of permanent magnet motor having air gaps at permanent magnet end portions
A rotor of a motor includes a rotor core; permanent magnet insertion holes that are formed in an outer circumferential portion of the rotor core along a circumferential direction and in each of which an air gap extending in an outer circumferential direction, is formed in both end portions in a state where a permanent magnet is inserted; and a permanent magnet inserted in each of the permanent magnet insertion holes, wherein a thin portion is formed between the air gap and an outer circumference of the rotor core, rounded corner portions are formed at two locations on an outer circumference side in the air gap, and a radius of curvature of any one of the corner portions is equal to or more than half a width of the air gap in a circumferential direction.
US09667101B2 Power supply system, control method thereof, and recording medium
A power supply system controls output powers of a plurality of power supply apparatus for realizing optimal conversion efficiency between input power and output power. The power supply system includes a plurality of power conversion units that convert an input power supplied from the input side into an output power for supplying the output power to a load connected to the output side; a power measurement unit that measures the output power of the power conversion unit; and a power supply control unit that calculates the input power to the power conversion unit in response to the output power of the power conversion units measured by the power measurement unit, and calculates the output power of the power conversion unit realizing the minimum calculated input power as an optimal output power, and controls the power conversion units based on the calculated optimal output power.
US09667100B2 Voltage monitoring control device and voltage monitoring control method
A centralized voltage control device connected to a first local voltage control device adjusting the control amount every second cycle such that a voltage of a transformer-type voltage control apparatus is maintained within a range between voltage upper and lower limit values updated every first cycle and a second local voltage control device adjusting the control amount of a reactive-power-modified voltage control apparatus every third cycle, wherein the centralized voltage control device includes a load and power-generation-amount estimation unit estimating a load and power-generation-amount distribution every first cycle under condition of a mean load and mean power generation, condition of a minimum load and maximum power generation, and condition of a maximum load and minimum power generation, a voltage-fluctuation-band estimation unit estimating a voltage fluctuation band, an optimal-voltage-distribution determination unit determining a control target value of the first local voltage control device, and a voltage upper-and-lower-limit-value determination unit.
US09667097B2 System and method for maintaining proper phase neutral wiring in a power system
According to one aspect, embodiments of the invention provide a method of operating a UPS system, the method comprising receiving, at an input of a first UPS, input power from a power source, generating, with a first analysis circuit, a first signal indicative of a characteristic of the input power, receiving, at the analysis circuit, a second signal from a second analysis circuit of a device coupled to the power source, the second signal indicative of a characteristic of input power received at the second analysis circuit, analyzing with the analysis circuitry, the first signal and the second signal, determining, whether an improper wiring condition exists at the input, in response to a determination that an improper wiring condition does not exist, providing output power to an output of the first UPS, and in response to a determination that an improper wiring condition does exist, de-energizing the first UPS.
US09667092B2 Power charging kit with wireless and direct charging connectivity
A power charging kit is provided for charging one or more electronic devices. The power charging kit includes a portable charger unit that includes wireless power transmission components, such as a transmitter and a receiver for recharging the portable charger unit as well as electronic devices via wireless power transmission methods. The portable charger unit also includes at least one power connection for connecting the portable charger unit with an external power source, or at least one electronic device, or both, for direct charge connectivity. Said at least one power connection can be a power connection port or a power connector cable, attached to a charger housing, each capable of acting as a power input, a power output, or both. The power charging kit also includes a wireless charging mat that also has wireless and direct charging functionality. A processing unit controls operation of the portable charger unit for wireless and direct charging.
US09667088B2 Double-sided bidirectional wireless power device
A double-sided bidirectional wireless power device includes a base and a support board. The base includes a power member. The support board has first and second surfaces and is erected on the base and includes a wireless bidirectional power module built therein, which includes a wireless bidirectional power circuit, an induction resonance circuit, a current/voltage detection unit, and a logic control unit that are electrically connected. To operate, the wireless bidirectional power module receives and converts an alternating current signal into electrical power to be transmitted to the power member for storage. The power member is also operable to transmit electrical power to the wireless bidirectional power module to be converted into an alternating current signal for transmission to an electronic device. The presently disclosed device allows for the simultaneous charging of two electronic devices via the first and second surfaces of the support board.
US09667087B2 Switchable energy storage device and method for operating a switchable energy storage device
Switchable energy storage device (10), having: —at least two energy storage modules (1) connected in series, wherein each energy storage module (1) comprises at least one electrical energy storage cell (3) which can be connected into an operating current circuit by means of a semiconductor switch (2), characterized in that the energy storage device (10) has an electrically isolated, inductive coupling device (5) for charging the energy storage cells (3).
US09667086B2 Mobile terminal
A mobile terminal is provided with a housing, a battery pack, and a secondary-side non-contact charging module. In a plan view along the thickness direction of the housing, the battery pack is arranged in a first area, and the secondary-side non-contact charging module is arranged in a second area that is adjacent to the first area. The secondary-side non-contact charging module overlaps with the intersection of a center line for the second area, said center line following the direction in which the first area and the second area are adjacent to each other, and a center line for the width direction of the housing, said center line being orthogonal to the direction in which the first area and the second area are adjacent to each other in the second area.
US09667085B2 Wireless charger for electronic device
A wireless charger for an electronic device is provided, which includes one or more charge cells formed by one or more structures of transmitting inductance coils, each of the charge cells receiving an electronic device, and an electric power supply circuit of transmitting coils. The transmitting coils surround the charge cells on at least two sides, respectively, and generate a uniformly distributed magnetic field such that the magnetic fields, generated by currents in parts of the structure of the transmitting coils, are mutually subtracted out of the charge cells and summarized inside the charge cell in an area in which the electronic device for reception of energy is located.
US09667083B2 Battery management control method
A battery management method and apparatus. In one embodiment of the method, a source current is divided into Ic and Icr. Ic is transmitted to and charges a battery. A first voltage is generated that is related to Icr. The first voltage is converted into a first digital signal. A processing unit receives and processes the first digital signal in accordance with instructions stored in a memory. The transmission of Ic to the battery is interrupted in response to the processing unit processing the first digital signal. Current provided by the battery is divided into Idc and Idcr. Idc is transmitted to a device. A second voltage is generated that is related to Idcr. The second voltage is converted into a second digital signal. The processing unit receives and processes the second digital signal in accordance with instructions stored in the memory. The transmission of Idc to the battery is interrupted in response to the processing unit processing the second digital signal.
US09667080B2 Charging device
The purpose of the invention is to stabilize the output of a charging device by removing noise components back to the output side of the charging device. The charging device (100) charges a secondary battery (30) by using power supplied from an external power supply (20). A charging unit (102) has a primary coil (150) and a secondary coil (151), converts the power supplied from the external power supply (20) into a charging power, and supplies the charging power to the secondary battery (30). A noise removing unit (103) removes noise components included in the charging power that is supplied to the secondary battery (30) by the charging unit (102).
US09667078B2 Rapid charging and power management of a battery-powered fluid analyte meter
A system and method is described for rapid charging and power management of a battery for a meter. A charger component is operably associated with the meter and is capable of executing a rapid charge algorithm for a rechargeable battery. The algorithm includes monitoring for a connection to an external power source and implementing a charging routine of a battery at a first charge rate and then at a second charge rate. The second charge rate is lower than the first charge rate. A temperature rise in the rechargeable battery due to the first charge rate has a negligible heat transfer effect on the fluid sample. The meter can also include a power switch for controlling current flow to a battery fuel gauge. The power switch is open when the meter enters into a sleep mode. The state of battery charge is determined after the meter exits the sleep mode.
US09667076B2 Standby battery product and stackable charging system thereof
An electrical charging system includes a charging socket and a standby battery product. The charging socket has a socket casing, and a power input interface on the socket casing and electrically connected to a first conductive contact that extends above the socket casing. The standby battery product has a battery casing with a battery housed inside the battery casing, the battery casing further including a conductive pin and a second conductive contact, with the conductive pin and second conductive contact electrically connected to the battery. When the battery casing is placed on top of the socket casing, the conductive pin is aligned with, and contacts, the first conductive contact, creating a charging path that is defined by the power input interface (which receives external power), the first conductive contact of the socket casing, the conductive pin of the battery casing, and the electricity storage unit of the battery product.
US09667074B2 Apparatus and method for updating remote standalone firmware
A charging device may include firmware configured to execute and control charging functions and updating functions performed by the charging device. The firmware includes a first section configured to store instructions associated with the charging functions and a second section configured to store instructions associated with updating the first section. The charging device may also include a charging slot for insertion of one of a rechargeable device and an updating device. The charging device may further include a micro-controller configured to execute instructions stored on the firmware. Responsive to the updating device being inserted into the charging slot, the charging device executes instructions stored in the second section to enter an updating mode and update the firmware.
US09667068B2 System, method, and computer program product for a switch mode current balancing rail merge circuit
A system, method, and computer program product are provided for merging two or more supply rails into a merged supply rail. The method comprises receiving two or more current measurement signals associated with two or more supply rails, selecting one supply rail from the two or more supply rails, based on the current measurement signals, and enabling the selected supply rail to source current into a merged supply rail.
US09667067B2 Electric power socket control system
An electric power socket control system comprises a cloud server, a wireless network sharer, at least an electric power socket device including a wireless network interface circuit and an electric quantity detection circuit, and a handheld device, wherein the electric power socket device can connect to the cloud server through the wireless network of the wireless network sharer and receive instructions for controlling the electric power socket device via the cloud server. In addition, the handheld device includes a built-in control software allowing to connect to the cloud server, in which the control software can be used to build the basic data of the electric power socket device and further select that, during a time interval, the system can perform power supply/power break operations to the electric power socket device automatically and randomly at non-fixed time.
US09667065B2 Battery management system and method
A battery-management method is performed by a battery-operated device. The method includes allocating a first portion of a battery capacity to a first function and a second portion of the battery capacity to a second function. The method further includes simultaneously displaying a first indicator relating to the first portion of the battery capacity and a second indicator relating to the second portion of the battery capacity.
US09667060B1 Adjusting over current protection values during changes in load current
The systems and methods described are for adjusting over current protection values during changes in load current. In one aspect, a method includes, monitoring a load current amplitude value at a power input connected to an electrical load; determining a rate of change of the load current amplitude value; determining whether the rate of change of the load current amplitude value exceeds a predefined rate threshold value; in response to determining that the rate of change of the load current amplitude value exceeds the predefined rate threshold value: adjusting an over current protection value from a first over current protection value to an adjusted over current protection value for a first predefined amount of time; and at the expiration of the first predefined amount of time, at least partially reversing the adjustment to the over current protection value.
US09667056B2 Microgrid system structured to detect overload conditions and take corrective actions relating thereto
A distribution manager includes a main bus, a first connection coupled to the main bus through a first circuit breaker and being structured to couple the distribution manager to an inter-microgrid connection system, a second connection coupled to the main bus through a second circuit breaker and being structured to couple the distribution manager to the inter-microgrid connection system, and a third circuit breaker coupled to the main bus and being structured to be coupled to a load. The distribution manager is configured to detect an overload condition and in response thereto (i) request to bring an offline distributed source online, (ii) if an offline distributed source cannot be brought online, request to shed the load, and (iii) if the load cannot be shed, cause the second circuit breaker to downwardly adjust the trip curve thereof.
US09667054B2 Adapter for sealing cover for electrical interconnections
An assembly includes: a threaded stem having an external helical male thread, the male thread defining a root having a first diameter, a crest having a second diameter, and flanks defining a third diameter; and a sealing adapter having an annular body, an outer surface, and an internal female thread, the female thread defining a crest having a fourth diameter, a root having a fifth diameter, and flanks defining a sixth diameter. The sealing adapter is threaded onto the threaded stem such that the female thread engages the male thread. Prior to assembly, the fourth diameter is less than the first diameter, the fifth diameter is less than the second diameter, and the sixth diameter is less than the third diameter.
US09667053B2 Adjustable floor box
An electrical floor box assembly includes a box having a bottom wall, a plurality of side walls and a top portion having an opening at a top end thereof for providing access to the electrical box. An adapter has an open top end, an open bottom end and a passage extending between the top end and bottom end. The adapter has an outer dimension complementing a dimension of the opening in the electrical box and is received in the opening for movement between a retracted position and an extended position within the opening. The electrical box and adapter are configured for coupling and fixing the axial movement of the adapter with respect to the electrical box by rotation of the adapter to a locking position. In one embodiment, the electrical box and the adapter have interlocking teeth that mate with each other to prevent axial movement of the adapter. A locking member is provided to fix the position of the adapter relative to the electrical box to prevent rotation of the adapter.
US09667052B2 Matched seal feedthrough
A matched seal feedthrough comprising: a support body having at least one passage opening, wherein the support body has a first coefficient of thermal expansion α1; at least one functional element; and an electrical insulation fixing material consisting of a glass material, wherein the fixing material has a second coefficient of thermal expansion α2, and the second coefficient of thermal expansion α2 is substantially the same as the first coefficient of thermal expansion α1; wherein the at least one functional element has an outside circumferential surface and is held in the at least one passage opening by the fixing material, the outside circumferential surface includes at least partially a coating with at least one of nickel and nickel alloy resulting in a coated region and an uncoated region of the outside circumferential surface, and the fixing material covers the coated and uncoated region at least partially.
US09667049B1 Electrical box assembly for poured concrete floors
An electrical box assembly for concrete pours. The electrical box assembly includes an electrical box with a sidewall defining an electrical enclosure and a leveling ring for accepting the mounting of an electrical component to the box. Mounting bosses within the electrical box extend longitudinally along the inner surface of the sidewall and facilitate a means for mounting the leveling ring to the electrical box. The leveling ring includes a flange that is adapted to overlap the top rim of the electrical box. Component attachment arms on the leveling ring enable mounting of an electrical component to the electrical box assembly. Cover attachment arms on the leveling ring facilitate mounting of an electrical cover to the electrical box assembly. The electrical box assembly eliminates the need for clips and adhesive for leveling an electrical component with respect to the surface of a concrete poured surface.
US09667046B2 Weatherproof box with clamping hub
An electrical box assembly includes an electrical box having a side wall and an open top end and a conduit access port opening extending through the side wall and having a dimension to receive a conduit. A seal is received in the opening for surrounding the conduit. A clamp is positioned in the opening in the side wall and is positioned between the side wall and the seal for contacting an outer surface of the seal. An actuator is coupled to the electrical box and extends through the side wall into the opening in the side wall to contact the conduit clamp to constrict said conduit clamp and seal into clamping engagement with the conduit.
US09667045B2 Wire harness and connector
The present invention makes it possible to prevent the erroneous fitting of a connector (40) and to smoothly perform a fitting operation. A plurality of connectors (40) are aligned in a direction intersecting a front-rear direction. The front face of a housing (41) is oriented in the direction facing a counterpart housing (71) at fitting each connector (40). The housing (41) is provided with a through portion (52) passing through the housing (41) in the direction intersecting the front-rear direction. A plurality of electrical wires (100) extended out from each connector (40) are densely arranged in the through portion (52) so that the free movement of the electrical wires is restricted.
US09667043B2 Device for high frequency current damping
A device for damping of high frequency currents is provided. The device includes a conductor extending along a main axis, a first damping path including a first damping element extending along a first axis and a second damping path including a second damping element extending along a second axis. The first and second damping elements are arranged on opposite sides of the conductor. The main axis, the first axis and the second axis are different and separate from each other. The first damping element and the second damping element are spaced apart from the conductor and electrically connected in parallel with the conductor between a first position and a second position along the conductor. Further, from the first position to the second position, a resistance of the conductor is lower than a resistance of either one of the first and second damping paths.
US09667041B2 Electrically insulating cover for terminal assembly
A terminal assembly may be provided which utilizes an electrically insulating cover to electrically isolate upper portions of screw terminals. The electrically insulating cover could be made from plastic, rubber or some other electrical insulator, and could be mounted on a frame configured to engage with a frame supporting the screw terminals. While lower portions of the screw terminals may continue to electrically connect with electrical connectors for receiving load stab conductors (from a unit), upper portions of the screw terminals may be electrically isolated to protect from short-circuit, and/or shock, such as while a door or access panel of a wire-way is removed. The electrically insulating covers may also include cable glands for circumferentially surrounding wires leading to the screw terminals. A retainer clip may also be used to securely hold the electrically insulating covers to the frame supporting the screw terminals.
US09667039B2 Device and method for injecting ions into a stream of air
A device and method for injecting ions into a stream of air. The device comprises a housing; an electric circuit inside the housing; an electrically conductive element coupled to the electric circuit for emitting ions, at least a portion of the conductive element being exposable to at least a portion, of the stream of air for injecting the ions into the stream of air; and a heater element disposed inside the housing for heating one or more circuit elements of the electric circuit.
US09667038B2 Shielding assembly
An electrical field shielding assembly comprises at least one electrically conductive, shielding element (12) that is hingably mounted on the electrical field shielding assembly, wherein the or each shielding element (12) is hingably movable between an open position in which an access opening in the electrical field shielding assembly is created and a closed position in which the access opening in the electrical field shielding assembly is closed.
US09667037B2 Prechamber spark plug for a gas-powered internal combustion engine
A prechamber spark plug for a gas-powered internal combustion engine having: a metallic body, an insulator, a center conductor connected to a center electrode, a ground electrode, and a cap that is attached to a front end of the body and forms a prechamber. The prechamber can be subdivided into a front part and a back part by an imaginary separating plane that is perpendicular to the center conductor at an end face of the center electrode. The front part of the prechamber is located on the front side of the separating plane, and the back part is located inside the body on the back side of the separating plane so that the volume of the back part is larger than the volume of the front part. Apart from its connection to the front part of the prechamber, the back part is closed in a gas-tight manner.
US09667035B1 Method for preparing organic polymer thin film laser
The present disclosure provides a preparation method of a polymer film laser. Polymer materials are dissolved in an organic solvent, a polymer solution is spin-coated on a substrate with or without a grating structure, and a homogeneous polymer thin film is formed. For the substrate without the grating structure, an interference pattern of an ultraviolet laser is used to interact with a thin polymer film, and one-dimensional or multi periods grating structures with multi directions are formed. The substrate with the thin polymer film is immersed in a hydrochloric acid solution or water and the polymer film with the grating structure peels off the substrate to obtain the polymer film laser. A pump beam is used to excite the polymer film to generate fluorescence, which is reflected and gained by the grating to obtain laser outputs.
US09667031B2 Current driver for diode laser system
An architecture for current driver circuitry for diode laser systems is contemplated whereby the circuitry is both modular and minimally complex with respect to the number of components and connections.
US09667029B2 Semiconductor laser light source
In conventional semiconductor laser light sources, since intervals of light emitter waveguides are changed or stresses which are applied on chips of a laser array are controlled in the production process, there exists a problem that the productivity is lowered. A structure of a heat sink 3a, on which a semiconductor laser array 2 is mounted in which a plurality of semiconductor lasers are arrayed at equal intervals in a stripe width direction, is configured so that the heat radiation efficiencies of the plurality of semiconductor lasers are not constant between the central region and other regions in the stripe width direction. Concretely, the heat sink is configured in such a way that an area of a second region in a second surface of the heat sink is smaller than an area of a fourth region in the second surface with which the semiconductor laser radiation portion except for the central side of the plurality of semiconductor lasers in the stripe width direction are in contact, when each of the areas is converted into an area per semiconductor laser.
US09667027B2 Nanosecond pulse laser device and alternate laser wavelength output method thereof
The present invention relates to a nanosecond pulse laser device. The nanosecond pulse laser device of the present invention comprises: a light source which outputs a nanosecond pulse laser beam; a lens which focuses the laser beam; a Raman shift optical fiber which generates pulse lasers corresponding to a plurality of wavelengths through stimulated Raman scattering of the focused laser beam; a wavelength divider which divides, from among the pulse lasers, the pulse lasers of a predetermined wavelength; an optical switch which selects the pulse lasers outputted from the wavelength divider to mutually alternate the wavelengths in response to a switch control signal which is applied from the outside; and a wavelength combiner which combines and outputs the pulse lasers whose wavelengths are alternatively outputted from the switch.
US09667026B2 Optical-coupler based modulation-averaging structures for self-seeded colorless WDM-PON
A connected optical waveguide structure comprises n four-port optical couplers, where n is greater than one; and n waveguide loops, each loop having a corresponding perimeter; wherein each of the n perimeters is different from each of the other n−1 perimeters. In one embodiment, for any pair of the n loops, the ratio of the larger perimeter to the smaller perimeter is greater than five halves (5/2).
US09667024B2 Suppression of stimulated Brillouin scattering in higher-order-mode optical fiber amplifiers
An HOM-based optical fiber amplifier is selectively doped within its core region to minimize the presence of dopants in those portions of the core where the unwanted lower-order modes (particularly, the fundamental mode) of the signal reside. The reduction (elimination) of the gain medium from these portions of the core minimizes (perhaps to the point of elimination) limits the amount of amplification impressed upon the backward-propagating Stokes wave. This minimization of amplification will, in turn, lead to a reduction in the growth of the Stokes power that is generated by the Brillouin gain, which results in increasing the amount of power present in the desired, forward-propagating HOM amplified optical signal output.
US09667023B2 Ultra-high power single mode fiber laser system with non-uniformly configure fiber-to-fiber rod multimode amplifier
A high power fiber laser system includes a booster winch is configured as a fiber amplifier extending over free space, pump source and laser head including a reflective element which receives pump light and reflects toward the output end of the booster in a counter signal-propagating direction. The booster is configured with concentric and coextending frustoconically shaped (“MM”) core and cladding around the core. The core includes a mode transition region expanding between small diameter SM input and large diameter MM output core ends and configured so that amplification of high order modes is substantially suppressed as a single mode (“SM”) signal light propagates from the input to output core ends. The laser head receives output ends of respective pump light delivery fibers and signal fiber, respectively. The pump source is structured with a plurality of independent sub pumps arranged around the booster. The laser head supports a segmented mirror configured to reflect pump lights from respective pump sub-sources to the output end of the booster in a counter propagating direction, wherein the booster is configured to emit the amplified signal light reaching up to MW power levels substantially in the SM.
US09667016B2 Connecting blade, method of producing connecting blade, and electrical connector including connecting blade
A connecting blade includes an insulation board having an adjustment region; and paired differential lines disposed on the insulation board. Each of the paired differential lines has contact points at both ends thereof for connecting to a circuit connecting member. The paired differential lines include a straight pair and a cross pair. The straight pair is formed of two first lines not crossing each other. The cross pair is formed of two second lines having a crossing region where the two second lines cross each other without contacting with each other. The cross pair is arranged so that the cross pair contacts with the adjustment region at least partially. The adjustment region has a specific size and a permittivity so that a signal transmission time lag between the cross pair and the straight pair is reduced.
US09667012B2 Air-tight and water-tight electrical bonding device
A bonding device electrically bonds metallic surfaces through serrated metal teeth which embed into each metal surface as a fastener is tightened. A sealing material circumferentially outward and inward from the teeth create an air-tight and water-tight seal around the teeth, protecting the bonding location. The device can have an extended central collar extending axially from the through-hole in the center of the device, which will allow it to be installed in holes, or on a stud without the use of adhesives or other retaining methods.
US09667005B2 Base terminal block and auxiliary terminal block for switchboards and two-tier terminal block assembly comprising base terminal block and auxiliary terminal block
A switchboard base terminal block for connecting electrical wires comprising an insulating body having one top side and a bottom side opposite in a vertical direction, and at least two respective flanks opposite to each other in a longitudinal direction; wherein inside the body there is formed at least: a first pair of seats; a first space centered on a central vertical axis and bounded in the longitudinal direction by respective first partitions extending parallel to the vertical direction spaced from each other in the longitudinal direction by an amount such as to define a size of the space suitable for housing a jumper of the screw type; an undercut with base formed in the top side of the terminal block, presenting a first central opening for connecting externally the central space for insertion of the respective screw jumper, and means for coupling with corresponding means of an add-on terminal block for forming a two-tier terminal block in the vertical direction wherein said coupling means are adapted for determining a stable and non-decouplable along the vertical direction coupling with the corresponding coupling means of the add-on terminal block.
US09667002B1 Connector assembly with an unshielded twisted pair circuit
A connector assembly includes a housing having housing cavities extending between a mating end and a loading end. The housing having module latches associated with corresponding housing cavities. Contact modules are received in corresponding housing cavities. Each contact module having first and second module cavities extending between a front end and a rear end of the contact modules. The contact modules being held within the housing cavity by the corresponding module latch. Each contact module having an unshielded twisted pair (UTP) circuit, the UTP circuit includes first and second signal wires and first and second terminals terminated to the first and second signal wires. The signal wires being twisted along a length of the first and second signal wires.
US09667000B1 Radio frequency coaxial connector assembly and method of manufacturing same
A coaxial connector assembly includes an inner contact terminating a center conductor of a coaxial cable, an insulator holding the inner contact, and an outer contact, which surrounds the insulator and the inner contact, terminating a shield braid of the cable. The outer contact is formed into a barrel shape and includes a seam extending along an entire length of the outer contact. The coaxial connector assembly further includes an outer ferrule and a seamless inner ferrule. The seamless inner ferrule has a first ferrule portion with a first diameter and a second ferrule portion with a second diameter that is different from the first diameter. The first ferrule portion surrounds at least a portion of the outer contact. The shield braid is sandwiched between the second ferrule portion and the outer ferrule. A method of manufacturing the coaxial connector assembly is also provided.
US09666998B1 Ground contact module for a contact module stack
A ground contact module includes a ground leadframe having a ground contact with a transition portion extending between mating and terminating ends. A ground dielectric body holds the ground leadframe. The ground dielectric body has a low loss layer overmolded over the ground leadframe. The ground dielectric body has a lossy band separate and discrete from the low loss layer and attached thereto in proximity to the ground contact such that the lossy band is electrically coupled to the ground contact. The lossy band is manufactured from lossy material having conductive particles in a dielectric binder material and absorbs electrical resonance propagating through the contact module stack.
US09666995B1 EMI containment cage member
A connector assembly includes a cage member for EMI containment for a pluggable module having a cage sleeve defining a chamber, a base coupled to the cage sleeve, and a cage liner received in the chamber. The cage liner defines a module cavity configured to receive a pluggable module. The cage sleeve extends between a front end and a rear end and includes a plurality of cage walls defining the chamber and surrounding a communication connector at or near the rear end. The cage liner is electrically connected to the cage sleeve and surrounds a mating perimeter of the pluggable module. The cage liner extends a majority of a length of the pluggable module within the chamber to provide EMI shielding for the pluggable module. The cage liner provides an electrical path between the pluggable module and the cage sleeve.
US09666989B2 Connector
A connector includes a detector (60) movable to a standby position and a detection position with respect to a housing (10). The detector (60) is kept at the standby position in the process of connecting two housings (10, 90) and is biased by biasing members (80) and brought to the detection position when the two housings (10, 90) are properly connected. The detector (60) includes a resilient arm (65) configured to slide on a sliding surface (32) of the housing (10) while being resiliently deformed in the process of reaching the detection position.
US09666983B2 Connector
A connector (40) is avoided from becoming large sized by avoiding a guiding used upon fitting from becoming large. A counterpart housing (71) includes a cylindrical hood (72). A housing (41) includes a housing body (42) that can be fitted in the hood (72). The counterpart housing (71) is allowed to be angularly displaced about an axis parallel to a fitting direction of the housings (41, 71). One side of an opening edge of the hood (72) is configured as a counterpart arc portion (74) that curves in an arc shape along an angular displacement direction. One side of a front face of the housing body (42) in the fitting direction is configured as an arc portion (64) that curves in an arc shape along the angular displacement direction, and is configured capable of entering into the hood (72) by being guided by the counterpart arc portion (74).
US09666982B1 Electrical connector having latch release collar
An electrical connector includes a circular housing having a cavity configured to receive a mating connector. The housing holds power terminals in the cavity. The housing has a mating end having a generally circular cross-section. The housing has a flexible latch at the mating end configured to engage a latch of the mating connector. The flexible latch has a pull hook extending therefrom. A release collar is slidably coupled to the housing at the mating end in an axial direction between a forward position and a rearward position. The release collar has an actuator ramp facing the pull hook. The actuator ramp engages the pull hook to actuate the flexible latch to release the flexible latch from a latch of the mating connector as the release collar is moved in the axial direction to the rearward position.
US09666978B2 Cable clamping system for strain relief and grounding
An electronics module includes a cable clamp chassis projecting outward from a wall of the module. The cable clamp chassis includes first and second cable mounting locations adapted to receive respective first and second cables. The cable mounting locations each include an axially extending recess located adjacent a first reference plane. Each of the cable mounting locations includes an inner surface with an innermost point that lies tangent to a second reference plane that is parallel to and offset from the first reference plane such that the first and second cables are arranged in a zero stack configuration. A clamp is secured to the cable clamp chassis and adapted to secure the first and second associated cables in the first and second cable receiving locations.
US09666975B1 Sealed wall plate
A wall plate including a plate having a front surface and a rear surface, a rear perimeter wall extending away from the rear surface, a gasket having a rear surface positioned adjacent the rear perimeter wall, and wherein the gasket rear surface is flexible and folds upon contact with a mounting surface.
US09666973B1 Self-locking connector coupling
A connector coupling that has a body, an inner sleeve receiving the body, at least one self-locking pawl pivotably coupled to the inner sleeve that is configured to toggle between first and second positions in engagement with ratchet teeth of the body, and an outer sleeve surrounding the inner sleeve. The inner and outer sleeves are rotatable together in opposite mating and unmating directions. At least one spring member is attached to the outer sleeve and is configured to bias the pawl. When the pawl is in the first position engaging the ratchet teeth, the inner and outer sleeves are rotatable together in the mating direction only and prevented from rotating in the unmating direction and when the pawl is in the second position engaging the ratchet teeth, the inner and outer sleeves are rotatable together in the unmating direction only and prevented from rotating in the mating direction.
US09666970B2 Connector
A connector includes: a first connector housing which allows a second connector housing to be fitted in a fitting direction; and a retainer which is inserted, in an insertion direction perpendicular to the fitting direction, into the first connector housing, and which includes: a housing lock arm engaged with a lock protrusion provided in the first connector housing to position the retainer in a temporary lock position and a regular lock position when the retainer is inserted into the first connector housing; and a terminal lock portion engaged with a terminal metal fitting provided in the first connector housing to prevent the terminal metal fitting from dropping off when the retainer is positioned in the regular lock position. The retainer includes an arm support portion which supports both ends of the housing lock arm extending in the insertion direction.
US09666969B2 Connector assembly contact having an outwardly projecting primary lance
A contact for a plug connector has: a housing; and a primary lance which projects obliquely outwardly over the housing counter to a plug-in direction and which is inwardly deflectable for restraining the contact plugged into a contact chamber of a plug connector. The primary lance has both a stiffened region and a resiliently deformable region which is curved and extends at least partially in the plug-in direction. The stiffened region has a crimp that extends in the longitudinal direction. A supporting region is additionally provided, against whose contact surface the primary lance rests in response to a tensile load on the contact.
US09666967B2 Printed circuit board connector for non-planar configurations
A mesh network of printed circuit boards (PCBs) including a first PCB coupled to a second rigid PCB by way of an interlocking connection is provided. The interlocking connection has a degree of freedom that allows the first and second PCBs to form a twist angle between each other; the interlocking connector configured to provide electrical coupling between active components disposed in each of the first and second PCBs. A method of forming a substrate fabric including a mesh network as above is also provided. Further provided is a method of activating the mesh network of printed circuit boards as above.
US09666959B2 Wire harness
A wire harness includes a plurality of covered electrical wires where an insulation sheath is peeled off of each covered electrical wire to expose a lead wire end portion, a connection terminal fixed to an end portion of the covered electrical wire, a heat-shrinkable tube having a hot-melt adhesive laminated to an inner surface thereof covering a predetermined area in a heat-shrunk state, and a connector that irremovably houses the connection terminal in each terminal insertion hole. A connection-side end surface of the connector that is on a side where the connection terminal is connected is positioned so as to conform to an end of the heat shrunk heat-shrinkable tube near a first barrel portion. The connector has a holding tube portion extending integrally from the connection-side end surface and that covers the heat shrunk heat-shrinkable tube, the holding tube portion having a tubular hole that holds the heat-shrinkable tube.
US09666957B2 Connector terminal
The connector terminal includes a first connector terminal and a second connector terminal to be fit into the first connector terminal, the first connector terminal including a flat spring making contact with a certain area of the second connector terminal, the certain area including a free end of the second connector terminal, and a terminal body including a pair of sidewalls between which the flat spring is disposed, the second connector terminal being formed in the certain area with two or more first projections each extending in a first direction in which the second connector terminal is fit into the first connector terminal, at least two first projections among the first projections making contact with the flat spring between the sidewalls.
US09666949B2 Partially dielectric loaded antenna elements for dual-polarized antenna
A partially dielectric loaded divided horn waveguide device for a dual-polarized antenna is described. The partially dielectric loaded divided horn waveguide device may include a polarizer, a waveguide horn, multiple individual waveguides dividing a horn port of the waveguide horn, and multiple dielectric elements partially filling the individual waveguides. The dielectric elements may include a dielectric member extending along a corresponding individual waveguide and one or more matching features for matching signal propagation between the partially dielectric loaded individual waveguides and free space. Various components of the partially dielectric loaded divided horn waveguide device may be tuned for enhanced signal propagation between the waveguide horn and the individual waveguides, and between the individual waveguides and free space.
US09666948B1 Compact cross-link antenna for next generation global positioning satellite constellation
An inter-satellite cross-link antenna for a communications satellite in a constellation of satellites in earth orbit. The complete cross-link system is an array of eight quadrifilar helix antennas with a new design which is eight times smaller than previous designs, and has superior inter-satellite communications performance. The quadrifilar helix antenna is designed with a length, diameter, helix pitch angle and ground plate connectivity which is matched to the UHF inter-satellite communication frequency to provided a toroidal radiation pattern with high signal strength in a direction normal to the antenna axis and very low signal strength in an axial direction. The array of eight quadrifilar helix antennas does not require interleaving with the L-band GPS antenna aperture on the satellite, and does not block or interfere with the earth-directed GPS signals.
US09666946B1 Four element reconfigurable MIMO antenna system
The four element reconfigurable MIMO antenna system includes four conducting PIFA elements disposed on a top surface of a rectangular dielectric substrate. For each PIFA, an F-head portion of the PIFA defines two arms extending to a long peripheral edge of the substrate. An F-tail portion of the PIFA extends from a short peripheral edge of the substrate. A first PIFA and a second PIFA are mirror images of each other, and a third PIFA and a fourth PIFA are mirror images of each other. A meander pattern of conducting material extends from a bottom region of the F-tail portion of the PIFAs. For each PIFA, PIN/varactor diode bias circuits are disposed on the substrate's top surface, connecting to and extending away from a unique location on the F-tail portion of the PIFA, thereby creating separate radiating branches of the PIFA to achieve reconfigurability.
US09666945B2 Multi-band antenna and apparatus and method for adjusting operating frequency of the multi-band antenna in a wireless communication system
An apparatus and method for adjusting an operating frequency of a multi-band antenna and a system supporting the same in a wireless communication system are provided, in which a plurality of shorting pins spaced from a radiation patch by difference distances, and a switch connects one of the shorting pins to the radiation patch.
US09666933B2 Wireless local area network antenna array
A wireless local area network (“WLAN”) antenna array (“WLANAA”) is disclosed. The WLANAA may include a circular housing having a plurality of radial sectors and a plurality of primary antenna elements. Each individual primary antenna element of the plurality of primary antenna elements may be positioned within an individual radial sector of the plurality of radial sectors.
US09666932B2 Array antenna with shaped beam pattern for toll road collection system applications
A system for properly illuminating a toll collection zone without illuminating any areas outside the toll collection zone in which vehicles may be found, while minimizing lost tolls due to shadowing of shorter vehicles by taller vehicles. In one embodiment, a linear array antenna is configured to illuminate a rectangular collection zone from a point offset from the center of the roadway. The linear array antenna is configured to produce an asymmetric antenna pattern providing RF illumination over the rectangular collection zone sufficient for reliable reading of vehicle RF tags in the collection zone, and which also minimizes spillover of RF power outside the collection zone.
US09666931B2 Radio frequency electric power conversion mechanism
A radio frequency electric power conversion mechanism of the present invention includes a circuit board including a fiber reinforced resin board, instead of an expensive ceramic circuit board. The radio frequency electric power conversion mechanism has a combined configuration of a plurality of fiber reinforced resin boards laminated to each other with a conductive foil therebetween, a via hole array made of an electric conductor passing through the boards, a transmission line closely adhered to the surface of a board, and a waveguide having a notch in a part of the waveguide on the aperture side. The radio frequency electric power conversion mechanism further has other structural features.
US09666930B2 Interface between a semiconductor die and a waveguide, where the interface is covered by a molding compound
The embodiments described herein provide for the formation of circuit waveguide interfaces during a wafer-scale die packaging (WSDP) process. Specifically, during the packaging process singulated die are arranged on a wafer-like panel and covered with molding compound that will provide the bodies of the packages. A circuit waveguide interface is formed in the molding compound and subsequent metallization layers. This circuit waveguide interface can include an array of first conductors arranged in the molding compound, and a reflector interface and excitation element formed during metallization.
US09666927B1 Compact folded Y-junction waveguide
A high bandwidth, low signal error, compact waveguide includes a conductive body including a waveguide input portion and a plurality of waveguide output portions disposed coplanar with the input waveguide portion. The waveguide further includes a common junction joining the input waveguide portion and the plurality of output waveguide portions. A septum is disposed proximate the common junction collinear with a centerline of the input waveguide portion. The waveguide further includes a plurality of iris elements disposed proximate the common junction transverse to the centerline of the input waveguide portion. The septum and the plurality of iris elements changes an impedance of the common junction to match the impedance across the entire waveguide bandwidth.
US09666920B2 Device for transmitting energy across a separating wall, where the wall includes a conductive element with a hole therein which passes through the wall
A device for transmitting energy comprises: a wall separating two media; and at least one conductive element passing through the wall, the conductive element comprising an energetically conductive material extending in a longitudinal direction. The conductive element is joined to the wall and comprises a hole passing through the wall and extending in a direction substantially parallel to the longitudinal direction on either side of the surfaces of the wall, over respective lengths that are larger than or equal to the largest dimension of a cross section of the conductive element considered level with the wall, the maximum ratio of the area of the cross section of the conductive element with the hole to the area of the cross section of the conductive element without the hole level with the wall being higher than or equal to a threshold comprised between 0.85 and 0.95.
US09666913B2 Heat transfer device
A heat transfer device for a motor vehicle may include a pump and a heat exchanger. The heat exchanger may have a first inlet and a first outlet for a refrigerant, and a second inlet and a second outlet for a coolant. The pump and the heat exchanger may be mounted to each other forming a common assembly.
US09666910B2 System and method for controlling a thermostatic valve for an electrochemical power source for use in a marine environment
A system for controlling, in a marine environment, a thermostatic valve coupled to an electrochemical type of electric power source, the thermostatic valve being provided with: a valve body; a first fluid inlet receiving a hot electrolytic fluid; a second fluid inlet receiving a cold electrolytic fluid; an outlet providing a mixed electrolytic fluid, resulting from mixing the hot and cold electrolytic fluids; and an adjusting element, which may be controlled to regulate the mixing. A control unit receives a reference temperature signal, variable over time, and a temperature measurement signal from a temperature sensor connected to the outlet of the thermostatic valve; and executes a control algorithm implementing fuzzy logic for generating a control signal for the adjusting element, as a function of the reference temperature signal, to reduce an error between the temperature measurement signal and the reference temperature signal.
US09666909B2 Electrode laminate comprising electrodes with different surface areas and secondary battery employed with the same
Disclosed herein is an electrode laminate including a positive electrode having a positive electrode material coating layer formed on a positive electrode current collector, a negative electrode having a negative electrode material coating layer formed on a negative electrode current collector, and a porous polymer film interposed between the positive electrode and the negative electrode, wherein the positive electrode, the negative electrodes, and the porous polymer films are laminated in a height direction on the basis of a plane such that the negative electrodes constitute outermost electrodes of the electrode laminate, and the positive electrode material coating layer has a larger coating area than the negative electrode material coating layer.
US09666903B2 Lithium ion secondary battery
There is provided a cylindrical pin-type lithium-ion secondary battery having excellent high temperature storage characteristics and charge-discharge cycle characteristics. The battery includes: a bottom-closed cylindrical battery case having an opening portion; a wound-type electrode assembly and a non-aqueous electrolyte housed in the battery case; and a sealing plate sealing the opening portion. The battery has: an outer diameter R of 3 to 6.5 mm; a height H of 15 to 65 mm; an amount of the non-aqueous electrolyte per discharge capacity of 1 mAh of 1.7 to 2.8 μL; and a packing ratio of 71 to 85%.
US09666901B2 Additive for electrolyte solution, non-aqueous electrolyte solution including the additive and lithium secondary battery including the electrolyte solution
An additive for an electrolyte solution includes a lithium salt having an oxalato complex as an anion and a compound represented by following Chemical Formula 1. Wherein, a represents C or Si, b represents H or F, and n represents an integer of 1 to 5. A non-aqueous electrolyte solution including the additive and a lithium secondary battery including the electrolyte solution also are provided.
US09666900B2 Rechargeable lithium battery and method of preparing same
A rechargeable lithium battery and a method of preparing the same are described. The rechargeable lithium battery includes a positive electrode including a positive active material; a negative electrode including a negative active material; and a liquid electrolyte including a lithium salt and a non-aqueous organic solvent. A separator is interposed between the negative electrode and positive electrode and includes a support. A fluoro-based polymer layer is positioned on both sides of the support. The positive electrode includes the positive active material in an amount from about 30 to about 70 mg/cm2.
US09666899B2 Active cathode layer for metal-sulfur secondary battery
A preloaded cathode layer, comprising: (A) An integral porous structure having massive surfaces greater than 100 m2/g or pores with a size from 1.0 nm to 100 nm, wherein multiple conductive particles, platelets or filaments, without a conductive filler, form a 3-D conductive network; and (B) a metal polysulfide preloaded in the pores or deposited on the massive surfaces, selected from: (a) an MxSy, (x=1-3 and y=1-10) wherein M is a metal element selected from a non-lithium alkali metal, an alkaline metal selected from Mg or Ca, a transition metal, a metal from groups 13 to 17, or a combination thereof, or (b) Li2S6, Li2S7, Li2S8, Li2S9, or Li2S10, wherein the metal polysulfide contains a thin coating or small particles with a thickness or diameter less than 20 nm and occupies a weight fraction of from 1% to 99%.
US09666894B2 Battery module and method for manufacturing the same
Provided are a battery module and a method for manufacturing the same. The battery module includes: a plurality of battery cells spaced apart from each other by a predetermined interval and stacked in parallel with each other; a plurality of heat exchange members integrally formed by connecting parts connecting between two partition walls neighboring to each other among partition walls each slid between the battery cells, respectively; and a filler applied onto the heat exchange members.
US09666892B2 Cell, cell stack device, module, and module housing device
The cell of the present invention includes an element portion and a first layer. The element portion includes a first electrode layer, a second electrode layer and a solid electrolyte layer. The first electrode layer serves as a tubular support body. The solid electrolyte layer is located between the first electrode layer and the second electrode layer. The solid electrolyte layer contains an oxide as a primary component and a first content of a rare earth element. The solid electrolyte layer has a thickness of 30 μm or less. The solid electrolyte layer has a region devoid of the second electrode layer. The first layer is located in the region. The first layer contains the oxide as a primary component and a second content of the rare earth element. The second content is different from the first content. The first layer has a higher strength than the solid electrolyte layer.
US09666891B2 Gas phase modification of solid oxide fuel cells
A solid oxide fuel cell comprising an electrolyte, an anode and a cathode. In this fuel cell at least one electrode has been modified with a promoter using gas phase infiltration.
US09666890B2 Fuel cell
A solid oxide fuel cell includes a cell stack, a reformed gas introduction path introducing a reformed gas into the cell stack, an oxidizing agent gas introduction path introducing an oxidizing agent gas into the cell stack, and a cooling gas introduction path introducing a cooling gas into the oxidizing agent gas introduction path. A heat-absorption part absorbing heat is provided in a periphery of the cell stack, and the cooling gas introduction path is connected with the oxidizing agent gas introduction path through the heat-absorption part.
US09666888B2 Combined power generation system and unit, method, and program for controlling the same
The system includes an exhaust fuel gas line, an exhaust-fuel-gas supplying line, a recirculating line that circulates the exhaust fuel gas to the SOFC, a shut-off valve in a vent line that splits off on the upstream side of the branching point, an orifice on the downstream side of the shut-off valve, a water supplying portion that supplies water to the recirculating line, and a DPX that measures the system pressure difference of the SOFC, and, when stopping power generation by the SOFC or when power generation by the SOFC comes to an abnormal stop, the shut-off valve is opened, while causing a predetermined amount of pressure loss in the vent line by using the orifice, and thus, the water flow volume of the water supplying portion is controlled so that the pressure difference measured by the DPX reaches a predetermined value.
US09666886B2 Condensed water removing method and apparatus of gas diffiusion layer and catalyst layer of fuel cell and apparatus
Disclosed are a method and an apparatus for removing condensed water in a gas diffusion layer and a catalyst layer of a fuel cell. The method comprises steps of: a step of determining whether the condensed water is generated in the gas diffusion layer and the catalyst layer of the fuel cell; a step of reducing and supplying an amount of air supplied to a cathode of the fuel cell at a predetermined level, when it is determined that the condensed water is generated in the gas diffusion layer and the catalyst layer in the step of determining; a step of measuring a temperature of a stack of the fuel cell; and a step of increasing the amount of air supplied to the cathode of the fuel cell to an amount of air prior to being reduced at the predetermined operation level, when the measured temperature of the stack of the fuel cell is elevated to a predetermined temperature.
US09666878B2 Method for fabricating catalytic 3D network material
A method for fabricating a catalytic 3-dimensional network material comprises steps: mixing an aqueous solvent with a nitrogen-containing carbon material whose surface is doped with nitrogen atoms to form a first dispersion liquid, and mixing the first dispersion liquid with ammonium carboxymethyl cellulose to form a first gel; undertaking a freeze-drying process of the first gel to remove water from the first gel to form a first product; and undertaking a low-temperature heating process of the first product at a temperature of 50-380° C. to cure the first product into a 3D network material doped with nitrogen atoms. The catalytic 3D network material of the present invention has a very high specific surface area to increase the catalytic efficiency.
US09666867B2 Aluminum alloy foil for electrode collector and production method therefor
An object of the present invention is to provide an aluminum alloy foil for an electrode current collector, the foil having a high strength after the drying step while keeping a high electrical conductivity. Disclosed is a method for manufacturing an aluminum alloy foil for electrode current collector, including: maintaining an aluminum alloy ingot comprising 0.03 to 0.1% of Fe, 0.01 to 0.1% of Si, 0.0001 to 0.01% of Cu, 0.005% or less of Mn, with the rest being Al and unavoidable impurities, at 550 to 620° C. for 1 to 20 hours, and subjecting the resulting ingot under a hot rolling with a starting temperature of 500° C. or higher and an end-point temperature of 255 to 300° C.
US09666866B2 Transition metal hexacyanometallate electrode with water-soluble binder
A method is provided for fabricating a transition metal hexacyanometallate (TMHCM) electrode with a water-soluble binder. The method initially forms an electrode mix slurry comprising TMHCF and a water-soluble binder. The electrode mix slurry is applied to a current collector, and then dehydrated to form an electrode. The electrode mix slurry may additionally comprise a carbon additive such as carbon black, carbon fiber, carbon nanotubes, graphite, or graphene. The electrode is typically formed with TMHCM greater than 50%, by weight, as compared to a combined weight of the TMHCM, carbon additive, and binder. Also provided are a TMHCM electrode made with a water-soluble binder and a battery having a TMHCM cathode that is made with a water-soluble binder.
US09666864B1 Vertically oriented graphene-supported anode
An electrode morphology and architecture for energy storage applications that increases the rate of charge/discharge, battery life, and decreases cost. The morphology and architecture directed towards a method and apparatus incorporating a graphene supported anode including a substrate, a vertically oriented graphene support arrangement coated with silicon or the like, in an electrolyte.
US09666863B2 Nano silicon-carbon composite material and preparation method thereof
The invention relates to a nano silicon-carbon composite negative material for lithium ion batteries and a preparation method thereof. A porous electrode composed of silica and carbon is taken as a raw material, and a nano silicon-carbon composite material of carbon-loaded nano silicon is formed by a molten salt electrolysis method in a manner of silica in-situ electrochemical reduction. Silicon and carbon of the material are connected by nano silicon carbide, and are metallurgical-grade combination, so that the electrochemical cycle stability of the nano silicon-carbon composite material is improved. The preparation method of the nano silicon-carbon composite material provided by the invention comprises the following steps: compounding a porous block composed of carbon and silica powder with a conductive cathode collector as a cathode; using graphite or an inert anode as an anode, and putting the cathode and anode into CaCl2 electrolyte or mixed salt melt electrolyte containing CaCl2 to form an electrolytic cell; applying voltage between the cathode and the anode; controlling the electrolytic voltage, the electrolytic current density and the electrolytic quantity, so that silica in the porous block is deoxidized into nano silicon by electrolytic reduction, and the nano silicon-carbon composite material for lithium ion batteries is prepared at the cathode.
US09666858B2 Negative electrode for secondary battery, and process for production thereof
A negative electrode for a secondary battery according to the present invention has a collector and a negative electrode active material layer formed on a surface of the collector and containing negative electrode active material particles. In the negative electrode active material layer, an insulating material is arranged between the negative electrode active material particles so as not to develop conductivity by a percolation path throughout the negative electrode active material layer. It is possible in this configuration to effectively prevent the occurrence of a short-circuit current due to an internal short circuit and the generation of heat due to such short-circuit current flow in the secondary battery while securing the battery performance of the secondary battery.
US09666851B2 Separator and electrochemical device having the same
The present invention refers to a separator and an electrochemical device having the same. The separator of the present invention comprises a non-woven fabric substrate obtained from fibers and having multiple pores formed between the fibers; and a polymer coating layer formed on a part or the whole of the surface of the fibers, wherein the polymer coating layer comprises a polymer having a tensile strength of 80 MPa or more, a tensile modulus of 3,000 MPa or more and a flexural modulus of 3,000 MPa or more.The separator of the present invention can reduce costs for manufacturing electrochemical devices, and it can control the size of pores present in the non-woven fabric substrate to prevent the generation of a leak current and provide improved mechanical strength.
US09666845B2 Power storage module and fixing structure of power storage module
A power storage module that has a plurality of power storage cells stacked in a stacking direction, a pair of insulating end power storage cell holders superimposed at opposite ends in the stacking direction, and a pair of end plates superimposed at opposite ends in the stacking direction of the end power storage cell holders. In a mounted state, a lower end in a vertical direction of the end power storage cell holder projects downward from lower ends in a vertical direction of the power storage cell and the end plate. The end power storage cell holder includes a first face opposing the end plate and a second face opposing the power storage cell. A first drainage channel is formed on the first face and extends vertically downwardly and bends outward in the stacking direction. A second drainage passage extends vertically and is formed on the second face.
US09666842B2 Rechargeable battery pack
A rechargeable battery pack is disclosed. In one aspect, the rechargeable battery pack includes a holder accommodating a plurality of unit cells, wherein each unit cell includes a rechargeable battery, and a case accommodating the holder. The case includes a bottom portion and a cover placed over the bottom portion and the holder. The holder includes a plurality of protrusions that protrude toward the bottom portion and the bottom portion has a plurality grooves defined to respectively correspond to the protrusions.
US09666841B1 Router having removable cellular communication module
A router includes a printed circuit board, a housing enclosing the printed circuit board, the housing having a recess formed therein, and a removable cell pack containing a cellular module configured to be received within the recess and electrically connected to the printed circuit board.
US09666830B2 Organic light emitting device and method for manufacturing the same
Disclosed is an organic light emitting device (OLED) that may include a first electrode including at least two conductive units that are immediately adjacent to each other; a second electrode facing the first electrode; an organic layer between the first electrode and the second electrode; and an auxiliary electrode electrically connected to the first electrode, the auxiliary electrode including at least two branch points that are immediately adjacent to each other, each branch point having at least three branches, wherein a resistance between the at least two branch points is 35Ω or less, and wherein a resistance between the at least two conductive units is 2,000Ω or more and 600,000Ω or less.
US09666826B2 Electroluminescent device including an anthracene derivative
An electroluminescent device comprises a cathode, an anode, and has therebetween a light emitting layer (LEL), the device further containing an electron transport layer (ETL) comprising an anthracene compound on the cathode side of the LEL and an organic electron injection layer (EIL) between the ETL and the cathode comprising a phenanthroline compound, wherein the thickness of the EIL and LEL are such that the ratio of the thickness of the EIL to LEL is greater than 0.125.
US09666825B2 Light-emitting element, light-emitting device, electronic device, and lighting device
A light-emitting element with high reliability that can keep favorable characteristics after long-time driving is provided. In addition, a light-emitting device having a long lifetime including the light-emitting element is provided. Moreover, an electronic device and a lighting device having a long lifetime are provided. In a light-emitting element including an EL layer between a pair of electrodes, a light-emitting layer included in the EL layer has a stacked-layer structure which is different from the conventional structure, whereby the light-emitting element can keep favorable characteristics after long-time driving even in the case where carrier balance is changed over time due to driving of the light-emitting element or a light-emitting region is shifted due to the change.
US09666820B2 Light-emitting device and manufacturing method thereof
An object of the invention is to improve the reliability of a light-emitting device. Another object of the invention is to provide flexibility to a light-emitting device having a thin film transistor using an oxide semiconductor film. A light-emitting device has, over one flexible substrate, a driving circuit portion including a thin film transistor for a driving circuit and a pixel portion including a thin film transistor for a pixel. The thin film transistor for a driving circuit and the thin film transistor for a pixel are inverted staggered thin film transistors including an oxide semiconductor layer which is in contact with a part of an oxide insulating layer.
US09666819B2 Organic light emitting diode and display device including the same
An organic light emitting diode includes a first electrode layer disposed on a base substrate, a second electrode layer disposed on the first electrode layer and facing the first electrode layer, an emitting layer disposed between the first electrode layer and the second electrode layer, a hole transport region disposed between the emitting layer and the first electrode layer, an auxiliary layer disposed between the hole transport region and the emitting layer, the auxiliary layer including a first material and a second material, and an electron transport region disposed between the emitting layer and the second electrode layer, in which a lowest unoccupied molecular orbital (LUMO) energy level of the first material is higher than a LUMO energy level of the emitting layer, and a LUMO energy level of the second material is lower than the LUMO energy level of the emitting layer.
US09666818B2 Tandem-type organic photoelectric conversion element and solar battery
A tandem-type organic photoelectric conversion element has at least a first electrode, a second electrode, and a plurality of bulk heterojunction layers each comprising a p-type organic semiconductor material and an n-type organic semiconductor material. The tandem-type organic photoelectric conversion element and a solar battery are characterized in that when the absorption wavelengths of the bulk heterojunction layers are such that a second bulk heterojunction layer absorbs up to a longer wavelength than a first bulk heterojunction layer, the LUMO energy level (LUMO(n1)) of the film of the n-type semiconductor in the first bulk heterojunction layer and the LUMO energy level (LUMO(n2)) of the film of the n-type semiconductor in the second bulk heterojunction layer satisfy the following equation (1): 0.4 eV≧LUMO(n1)−LUMO(n2)≧0.1 eV  (1).
US09666816B2 Growth of ordered crystalline organic films
There is disclosed methods utilizing organic vapor phase deposition for growing bulk organic crystalline layers for organic photosensitive devices, heterojunctions and films made by such methods, and devices using such heterojunctions. There is also disclosed new methods for manufacturing heterojunctions and organic photosensitive devices, and the heterojunctions and devices manufactured thereby.
US09666815B2 Surface treatment of hydrophobic ferroelectric polymers for printing
An embodiment is a method and apparatus to treat surface of polymer for printing. Surface of a polymer having a surface energy modified for a time period to control a feature characteristic and/or provide a hysteresis behavior. A material is printed on the surface to form a circuit pattern having at least one of the controlled feature characteristic and the hysteresis behavior.
US09666814B2 Display device and method of manufacturing the same
A display device includes: a central area having a display area on a substrate; and a peripheral area around the central area; a plurality of pads arranged along one direction in the central area; a plurality of insulating patterns adjacent the plurality of pads; and a slit between the plurality of insulating patterns in the peripheral area, wherein the slit is formed by removing at least a portion of an insulating material of the plurality of insulating patterns.
US09666809B2 Compound and organic light-emitting device including the same
An organic light-emitting device including a first electrode, a second electrode and an organic layer disposed between the first electrode and the second electrode is provided.
US09666808B2 Organic electroluminescence element
An organic electroluminescent element having a small reduction rate in the luminance immediately after the start of light emission is provided. The organic electroluminescent element includes a substrate, a pair of electrodes including an anode and a cathode, disposed on the substrate, a light emitting layer disposed between the electrodes, and at least one organic layer disposed between the light emitting layer and the anode, in which at least one kind of a specific compound including a fluorene structure is contained in at least one organic layer between the light emitting layer and the anode, and at least one kind of a specific compound including a carbazole structure or a fluorene structure is contained as a light emitting material in the light emitting layer.
US09666804B2 Copolymer and organic solar cell using same
The present specification provides a copolymer, and an organic solar cell including one or more layers of organic material layers that include the copolymer.
US09666802B2 Photoresist employing photodimerization chemistry and method for manufacturing organic light emitting diode display using the same
A highly fluorinated photoresist employing a photodimerization chemistry and a method for manufacturing an organic light emitting diode display using the same. The photoresist includes a copolymer that is made from two different monomers. When the copolymer is used as a photoresist, the photoresist has the characteristic that it becomes insoluble when exposed to an ultraviolet light having a wavelength of 365 nm.
US09666799B2 Concave word line and convex interlayer dielectric for protecting a read/write layer
An alternating stack of electrically conductive layers and electrically insulating layers is formed over global bit lines formed on a substrate. The alternating stack is patterned to form a line stack of electrically conductive lines and electrically insulating lines. Trench isolation structures are formed within each trench to define a plurality of memory openings laterally spaced from one another by the line stack in one direction and by trench isolation structures in another direction. The electrically conductive lines are laterally recessed relative to sidewall surfaces of the electrically insulating lines. A read/write memory material is deposited in recesses, and is anisotropically etched so that a top surface of a global bit line is physically exposed at a bottom of each memory opening. An electrically conductive bit line is formed within each memory opening to form a resistive random access memory device.
US09666798B1 Switching elements, resistive random access memory devices including the same, and methods of manufacturing the switching elements and the resistive random access memory devices
A method of manufacturing a switching element is provided. The method includes forming a pillar-shaped structure having a first electrode, an insulation layer and a second electrode which are stacked on a substrate. A tilted doping process is performed to inject dopants into at least a portion of the insulation layer. The tilted doping process forms a threshold switching operation region in the insulation layer.
US09666796B2 Method for making phase change memory cell
A method for making phase change memory cell includes following steps. A carbon nanotube wire is located on a surface of the substrate, wherein the carbon nanotube wire includes a first end and a second end opposite to the first end. A bending portion is formed by bending the carbon nanotube wire. A first electrode, a second electrode, and a third electrode are applied on the surface of the substrate, wherein the first electrode is electrically connected to the first end, the second electrode is electrically connected to the second end, and the third end is spaced from the bending portion of the carbon nanotube wire. A phase change layer is deposited to cover the bending structure and electrically connects to the third electrode.
US09666794B2 Multi-stage element removal using absorption layers
An MTJ structure and method for providing the same are described. The method may include providing a free layer, a pinned layer, and a nonmagnetic spacer layer between the free layer and the pinned layer. Providing the free layer and/or the pinned layer may include depositing a portion of the desired MTJ layer, depositing a sacrificial layer, annealing the MTJ and sacrificial layer, removing at least a portion of the sacrificial layer, and depositing a remaining portion of the desired MTJ layer. The steps of depositing a sacrificial layer, annealing, and removing the sacrificial layer may be repeated multiple times with process conditions selected for each stage so as to reduce the risk of damage to the underlying MTJ layer. The desired MTJ layer may be the free layer, the pinned layer, or both.
US09666789B2 Semiconductor device having pinned layer with enhanced thermal endurance
A semiconductor device is provided having a free layer and a pinned layer spaced apart from each other. A tunnel barrier layer is formed between the free layer and the pinned layer. The pinned layer may include a lower pinned layer, and an upper pinned layer spaced apart from the lower pinned layer. A spacer may be formed between the lower pinned layer and the upper pinned layer. A non-magnetic junction layer may be disposed adjacent to the spacer or between layers in the upper or lower pinned layer.
US09666788B2 Integrated circuit package having a split lead frame
A magnetic field sensor includes a lead frame having a plurality of leads, at least two of which have a connection portion and a die attach portion. A semiconductor die is attached to the die attach portion of the at least two leads. The sensor further includes at least one wire bond coupled between the die and a first surface of the lead frame. The die is attached to a second, opposing surface of the lead frame in a lead on chip configuration. In some embodiments, at least one passive component is attached to the die attach portion of at least two leads.
US09666786B2 Volume wave resonators on micromachined vertical structures
A bulk wave piezoelectric resonator operating at a predetermined frequency includes a substrate block, having a plane face, a first thickness and consisting of a first material, a resonant plate having a length, width and second thickness, and consisting of a second piezoelectric material, first and second metal electrodes at least partly covering the resonant plate on each side and partly facing each other. The resonant plate is fixed perpendicularly in the vicinity of the plane face of the substrate block so that the width of the resonant plate and the first thickness of the substrate block have the same direction, and the first material, the second material, the first thickness of the block of substrate, the length, the width, the second thickness of the resonant plate are configured for trapping bulk waves at the operating frequency of the resonator and for producing a plane-plane type bulk wave piezoelectric resonator.
US09666785B2 Piezoelectric driving device, robot, and driving method of the same
A piezoelectric driving device includes a vibrating plate, and a piezoelectric vibrating body including a substrate, and piezoelectric elements provided on the substrate. The piezoelectric element includes a first electrode, a second electrode, and a piezoelectric body, and the first electrode, the piezoelectric body, and the second electrode are laminated in this order on the substrate. The piezoelectric vibrating body is installed on the vibrating plate so that the piezoelectric element is interposed between the substrate and the vibrating plate. A wiring pattern including a first wiring corresponding to the first electrode and a second wiring corresponding to the second electrode is formed on the vibrating plate, the first electrode and the first wiring are connected to each other through a first laminated conducting portion, and the second electrode and the second wiring are connected to each other through a second laminated conducting portion.
US09666782B2 P-type semiconductor composed of magnesium, silicon, tin, and germanium, and method for manufacturing the same
A manufacturing method for a p-type semiconductor formed by sintering a compound represented by the general chemical formula: Mg2SiXSnYGeZ (where X+Y+Z=1, X>0, and Y>0, Z>0). The p-type semiconductor has a composition in which X is in the range of 0.000.00, and Y is in the range of 0.60≦Y≦0.95, and Z satisfies either of the relationships: −1.00Y+1.00≧Z≧−1.00Y+0.75, where 0.60≦Y≦0.90 and Z>0.00, and −2.00Y+1.90≧Z≧−1.00Y+0.75, where 0.90≦Y≦0.95 and Z>0.00.
US09666780B2 Light-emitting device and manufacturing method thereof
The present disclosure provides a light-emitting device and manufacturing method thereof. The light-emitting device comprises: a metal connecting structure; a barrier layer on the metal connecting structure, the barrier layer comprising a first metal multilayer on the metal connecting structure and a second metal multilayer on the first metal multilayer; a metal reflective layer on the barrier layer; and a light-emitting stack electrically coupled to the metal reflective layer, wherein the first metal multilayer comprises a first metal layer comprising a first metal material and a second metal layer comprising a second metal material, and the second metal multilayer comprises a third metal layer comprising a third metal material and a fourth metal layer comprising a fourth metal material.
US09666779B2 Semiconductor light emitting diode chip with current extension layer and graphical current extension layers
A semiconductor light emitting diode chip relates to the field of production technologies of a light emitting diode. In the present invention, corresponding graphical current extension layers are respectively disposed below an N pad and a P pad, and in all light emitting compound areas, there is electronic compound light emitting. Compared with the prior art, an area of a light emitting compound area is increased, which can effectively improve current distribution and light emitting brightness of a chip. In addition, graphical current extension can effectively increase an adhesion of a pad on a surface and improve the reliability of a chip.
US09666777B2 Light emitting device
A package for a light emitting device includes a resin molding and first to third leads. The first lead is disposed near a first corner of a substantially rectangular shape of the resin molding, and has a first exposed part exposed from one of two side surfaces that share the first corner while the first lead is not exposed from the resin molding on the other of the two side surfaces. The second lead is disposed near a second corner, and has a second exposed part exposed from one of two side surfaces that share the second corner while the second lead is not exposed from the resin molding on the other of the two side surfaces. The third lead has a plurality of lower surface exposed parts that are exposed from a lower surface of the resin molding.
US09666776B2 Semiconductor light emitting device and multiple lead frame for semiconductor light emitting device
A semiconductor light emitting device that is excellent in radiating heat and that can be molded into a sealing shape having intended optical characteristics by die molding is provided. The semiconductor light emitting device includes: a lead frame including a plate-like semiconductor light emitting element mounting portion having an LED chip mounted on a main surface, and a plate-like metal wire connecting portion extending over a same plane as the semiconductor light emitting element mounting portion; a metal wire electrically connecting the LED chip and the metal wire connecting portion; a thermosetting resin molded by die molding or dam-sheet molding so as to completely cover the LED chip and the metal wire; and a resin portion provided to surround the lead frame and having the thickness not greater than the thickness of the lead frame.
US09666765B2 Display device using semiconductor light emitting device and method of manufacturing the same
A display device including a plurality of semiconductor light emitting devices mounted on a substrate, and a phosphor layer including a plurality of phosphor portions configured to convert a wavelength of light and a plurality of partition wall portions formed between the plurality of phosphor portions. Further, a least one of the plurality of partition wall portions overlaps with at least one of the plurality of semiconductor light emitting devices along a thickness direction of the phosphor layer.
US09666761B2 Light-emitting device
A light-emitting device includes a substrate that is capable of transmitting light, a conductive layer that includes a first conductive portion provided on the substrate and a second conductive portion which is provided on the substrate so as to be adjacent to the first conductive portion, The second conductive portion is thinner than the first conductive portion. A light emitting layer is provided on the first conductive portion. A first electrode is provided on the second conductive portion. A second electrode is provided on the light emitting layer. In some embodiments, a backside surface of the substrate may be processed to be optically rough so as to limit internal reflections.
US09666759B2 Growth substrate, nitride semiconductor device and method of manufacturing the same
Disclosed is a method of manufacturing a light emitting device. More particularly, disclosed are a growth substrate, a nitride semiconductor device and a method of manufacturing a light emitting device. The method includes preparing a growth substrate including a metal substrate, forming a semiconductor structure including a nitride-based semiconductor on the growth substrate, providing a support structure on the semiconductor structure, and separating the growth substrate from the semiconductor structure.
US09666757B2 Vertical light emitting diode and fabrication method
A vertical LED with current blocking structure and its associated fabrication method involve an anisotropic conductive material and a conductive substrate with concave-convex structure. The anisotropic conductive material forms a bonding layer with vertical conduction and horizontal insulation between the concave-convex substrate and the light-emitting epitaxial layer, thereby forming a vertical LED with current blocking function.
US09666751B2 Method for producing an electrically conductive contact on a solar cell
A method is provided for producing an electrically conductive contact on a rear face and/or front face of a solar cell. The method interconnects solar cells in a cost-effective manner and ensures that cell damage, which leads to a reduction in power, is avoided. The rear face and/or front face of the solar cell is treated in the region of the contact and, after the treatment in the region, a pasty adhesive or an adhesive tape is applied in strips.
US09666748B2 Integrated on chip detector and zero waveguide module structure for use in DNA sequencing
A semiconductor structure for use in single molecule real time DNA sequencing technology is provided. The structure includes a semiconductor substrate including a first region and an adjoining second region. A photodetector is present in the first region and a plurality of semiconductor devices is present in the second region. A contact wire is located on a surface of a dielectric material that surrounds the photodetector and contacts a topmost surface of the photodetector and a portion of one of the semiconductor devices. An interconnect structure is located above the first region and the second region, and a metal layer is located atop the interconnect structure. The metal layer has a zero waveguide module located above the first region of the semiconductor substrate. A DNA polymerase can be present at the bottom of the zero waveguide module.
US09666746B2 Conductive base for forming wiring pattern of collector sheet for solar cells, and method for producing collector sheet for solar cells
Provided are: a conductive base for forming a wiring pattern of a collector sheet for solar cells, which has good rust inhibiting properties and solderability without using an organic rust inhibitor that may harm a solar cell element; and a method for producing a collector sheet for solar cells, said method using the conductive base. A conductive base for forming a wiring pattern of a collector sheet for solar cells, which is a conductive base (30) wherein a zinc layer (320) composed of zinc is formed on the surface of a copper foil (310), is used. The conductive base for forming a wiring pattern of a collector sheet for solar cells is characterized in that the zinc layer (320) does not contain chromium and the amount of zinc therein is more than 20 mg/m2 but 40 mg/m2 or less.
US09666743B2 Josephson junction readout for graphene-based single photon detector
A detector for detecting single photons of infrared radiation. In one embodiment a waveguide configured to transmit infrared radiation is arranged to be adjacent a graphene sheet and configured so that evanescent waves from the waveguide overlap the graphene sheet. In some embodiments the waveguide is omitted and infrared light propagating in free space illuminates the graphene sheet directly. A photon absorbed by the graphene sheet from the evanescent waves heats the graphene sheet. The graphene sheet is coupled to the weak link of a Josephson junction, and a constant bias current is driven through the Josephson junction, so that an increase in the temperature of the graphene sheet results in a decrease in the critical current of the Josephson junction and a voltage pulse in the voltage across the Josephson junction. The voltage pulse is detected by the pulse detector.
US09666741B2 Power generating apparatus and power generating system equipped with such power generating apparatus
A power generating apparatus according to an aspect of the invention includes a plurality of pn stacks, each formed by stacking a p-type semiconductor layer and an n-type semiconductor layer one on top of the other, and a mode switching unit which effects switching to a photovoltaic power generation mode or a thermal power generation mode by connecting the plurality of pn stacks with each other. The mode switching unit effects switching to the photovoltaic power generation mode by connecting the p-type semiconductor layers in parallel with each other and the n-type semiconductor layers in parallel with each other between the plurality of pn stacks. The mode switching unit effects switching to the thermal power generation mode by connecting the p-type semiconductor layer and the n-type semiconductor layer 11b in series between different ones of the pn stacks.
US09666733B2 Solar cell using printed circuit board
A solar cell using a printed circuit board (PCB) includes a substrate that is formed of an insulating material and in and through which a plurality of fixing holes and communication holes are alternately formed; a plurality of photoelectric effect generators that have ball or polyhedral shapes fixed to the substrate to be disposed over the plurality of fixing holes, and generate photoelectric effects by receiving light through light-receiving portions that are exposed to an upper portion of the substrate; a plurality of upper electrodes that are formed on a top surface of the substrate, and are connected to the respective light-receiving portions of the photoelectric effect generators; and a plurality of lower electrodes that are formed on a bottom surface of the substrate to be connected to respective non-light-receiving portions of the photoelectric effect generators, and communicate with the plurality of upper electrodes through the plurality of communication holes.
US09666726B2 Localized fin width scaling using a hydrogen anneal
Transistors and methods for fabricating the same include annealing channel portions of one or more semiconductor fins that are uncovered by a protective layer in a gaseous environment to reduce fin width, to produce a fin profile that is widest at the bottom and tapers toward the top, and to round corners of the one or more semiconductor fins.
US09666723B2 Semiconductor device
An object of the present invention is to provide a semiconductor device in which stored data can be held even when power is not supplied for a certain time. Another object is to increase the degree of integration of a semiconductor device and to increase the storage capacity per unit area. A semiconductor device is formed with a material capable of sufficiently reducing off-state current of a transistor, such as an oxide semiconductor material that is a wide-bandgap semiconductor. With the use of a semiconductor material capable of sufficiently reducing off-state current of a transistor, the semiconductor device can hold data for a long time. Furthermore, a wiring layer provided under a transistor, a high-resistance region in an oxide semiconductor film, and a source electrode are used to form a capacitor, thereby reducing the area occupied by the transistor and the capacitor.
US09666721B2 Semiconductor device including pellet-like particle or flat-plate-like particle
High field-effect mobility is provided for a semiconductor device including an oxide semiconductor. Further, a highly reliable semiconductor device including the transistor is provided. In a transistor in which a stack of oxide semiconductor layers is provided over a gate electrode layer with a gate insulating layer provided therebetween, an oxide semiconductor layer functioning as a current path (channel) of the transistor and containing an n-type impurity is sandwiched between oxide semiconductor layers having lower conductivity than the oxide semiconductor layer. In the oxide semiconductor layer functioning as the channel, a region on the gate insulating layer side contains the n-type impurity at a higher concentration than a region on the back channel side. With such a structure, the channel can be separated from the interface between the oxide semiconductor stack and the insulating layer in contact with the oxide semiconductor stack, so that a buried channel can be formed.
US09666704B2 Semiconductor device
A semiconductor substrate is provided with a first cell region, the first cell region including: an n-type emitter region; a p-type first top body region; an n-type first barrier region; an n-type first pillar region; and a p-type first bottom body region, the semiconductor substrate may further comprise: an n-type drift region; a p-type collector region; an n-type cathode region, the n-type first barrier region may include a first peak position where a peak of the n-type impurity density is present within a part linked to the n-type first pillar region, and a second peak position where a peak of the n-type impurity density is present within a part in contact with the gate insulating layer, and a depth of the first peak position from a front surface of the semiconductor substrate is different from a depth of the second peak position from the front surface of the semiconductor substrate.
US09666698B2 Method for manufacturing semiconductor device
A transistor with stable electrical characteristics is provided. Provided is a method for manufacturing a semiconductor device that includes, over a substrate, an oxide semiconductor, a first conductor, a first insulator, a second insulator, and a third insulator. The oxide semiconductor is over the first insulator. The second insulator is over the oxide semiconductor. The third insulator is over the second insulator. The first conductor is over the third insulator. The oxide semiconductor has a first region and a second region. To form the first region, ion implantation into the oxide semiconductor is performed using the first conductor as a mask, and then hydrogen is added to the oxide semiconductor using the first conductor as a mask.
US09666697B2 Semiconductor device and method for manufacturing semiconductor device including an electron trap layer
A manufacturing method of a semiconductor device in which the threshold voltage is adjusted is provided. The semiconductor device includes a first semiconductor, an electrode electrically connected to the first semiconductor, a gate electrode, and an electron trap layer between the gate electrode and the first semiconductor. By performing heat treatment at higher than or equal to 125° C. and lower than or equal to 450° C. and, at the same time, keeping a potential of the gate electrode higher than a potential of the electrode for 1 second or more, the threshold voltage is increased.
US09666691B2 Epitaxy profile engineering for FinFETs
A method of forming an integrated circuit structure includes providing a wafer including a substrate and a semiconductor fin at a major surface of the substrate, and performing a deposition step to epitaxially grow an epitaxy layer on a top surface and sidewalls of the semiconductor fin, wherein the epitaxy layer includes a semiconductor material. An etch step is then performed to remove a portion of the epitaxy layer, with a remaining portion of the epitaxy layer remaining on the top surface and the sidewalls of the semiconductor fin.
US09666690B2 Integrated circuit and method for fabricating the same having a replacement gate structure
An integrated circuit includes a first replacement gate structure. The first replacement gate structure includes a layer of a first barrier material that is less than 20 Å in thickness and a layer of a p-type workfunction material. The replacement gate structure is less than about 50 nm in width.
US09666689B2 Semiconductor device and method for manufacturing the same
An object is to reduce the number of photomasks used for manufacturing a transistor and manufacturing a display device to less than the conventional one. The display device is manufactured through, in total, three photolithography steps including one photolithography step which serves as both a step of forming a gate electrode and a step of forming an island-like semiconductor layer, one photolithography step of forming a contact hole after a planarization insulating layer is formed, and one photolithography step which serves as both a step of forming a source electrode and a drain electrode and a step of forming a pixel electrode.
US09666687B1 Method for forming semiconductor structure
The present invention provides a method for forming a semiconductor structure, at least including the following steps: first, four sacrificial patterns are formed on a substrate, and a plurality of spacers are then formed surrounding each sacrificial pattern. Next, the four sacrificial patterns are removed, and a photoresist layer is formed between each spacer, covering parts of each spacer. Afterwards, a first etching process is performed to partially remove each spacer, and the photoresist layer is then removed, and a second etching process is then performed, to remove each spacer again, and to form four nanowire hard masks.
US09666686B2 MOS devices having epitaxy regions with reduced facets
An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region. The second silicon germanium region comprises a portion in the opening. The second silicon germanium region has a second germanium percentage greater than the first germanium percentage. A silicon cap substantially free from germanium is over the second silicon germanium region.
US09666685B2 RF power transistor
A radio frequency (RF) power transistor includes a semiconductor heterostructure, a gate electrode, a drain electrode and a source electrode. The drain electrode includes an ohmic contact and a Schottky contact extending from the ohmic contact toward the gate electrode, spaced apart from the gate electrode (4) by a distance (LGD), and having a length (LEXT) being not less than 2 μm and not greater than 4 μm. A ratio of the length (LEXT) to a sum of the length (LEXT) and a distance (LGD) is greater than 0.83 and less than 0.98.
US09666683B2 Surface treatment and passivation for high electron mobility transistors
A High Electron Mobility Transistor (HEMT) and a method of forming the same are disclosed. The method includes epitaxially growing a first III-V compound layer and epitaxially growing a second III-V compound layer over the first III-V compound layer, wherein a first native oxide layer is formed on the second III-V compound layer. The method further includes in-situ treating the first native oxide layer with a first gas, thereby converting the first native oxide layer into a first crystalline oxide layer. The method further includes forming a first crystalline interfacial layer over the first crystalline oxide layer and forming a dielectric passivation layer over the first crystalline interfacial layer.
US09666681B2 Silicon carbide semiconductor device and method for manufacturing same
A trench has first to third side surfaces respectively constituted of first to third semiconductor layers. A first side wall portion included in a first insulating film has first to third regions respectively located on the first to third side surfaces. A second insulating film has a second side wall portion located on the first side wall portion. The second side wall portion has one end and the other end, the one end being connected to the second bottom portion of the second insulating film, the other end being located on one of the first and second regions, the other end being separated from the third region.
US09666680B1 Flash cell and forming process thereof
A flash cell includes a gate and an erase gate. The gate is disposed on a substrate, wherein the gate includes a control gate on the substrate and a floating gate having a tip between the substrate and the control gate. The erase gate is disposed beside the gate, wherein the tip points toward the erase gate. The present invention also provides a flash cell forming process including the following steps. A gate is formed on a substrate, wherein the gate includes a floating gate on the substrate. An implantation process is performed on a side part of the floating gate, thereby forming a first doped region in the side part. At least a part of the first doped region is oxidized, thereby forming a floating gate having a tip.
US09666674B2 Formation of large scale single crystalline graphene
A method for transfer of a two-dimensional material includes forming a spreading layer of a two-dimensional material on a first substrate. The spreading layer has at least one monolayer. A stressor layer is formed on the spreading layer. The stressor layer is configured to apply stress to a closest monolayer of the spreading layer. The closest monolayer is exfoliated by mechanically splitting the spreading layer wherein at least the closest monolayer remains on the stressor layer. The at least one monolayer is stamped against a second substrate to adhere remnants of the two-dimensional material on the at least one monolayer to the second substrate to provide a single monolayer on the stressor layer. The single monolayer is transferred to a third substrate.
US09666672B2 FinFET device
A device includes a first fin including a first semiconductor material. A first dielectric layer is disposed over a top surface of the first fin. A sidewall of the first dielectric layer has a dip-shape profile. A second dielectric layer is disposed along sidewalls of the first fin. A top surface of the second dielectric layer is substantially coplanar with the top surface of the first fin. A second fin includes a second semiconductor material different from the first semiconductor material. An isolation region is disposed between the first fin and the second fin.
US09666671B2 Semiconductor device with composite drift region and related fabrication method
A device includes a semiconductor substrate, a body region in the semiconductor substrate having a first conductivity type and in which a channel is formed during operation, source and drain regions in the semiconductor substrate and having a second conductivity type, the source region being disposed on the body region, and a composite drift region in the semiconductor substrate, having the second conductivity type, and through which charge carriers from the source region drift to reach the drain region after passing through the channel. The composite drift region includes a first section adjacent the channel, a second section adjacent the drain region, and a third section disposed between the first and second sections. The first and second sections have a lower effective dopant concentration level than the third section.
US09666667B2 Apparatuses and methods including a superjunction transistor
Aspects of the present disclosure are directed toward apparatuses, methods, and systems that include at least two regions of a first semiconductor material and at least two regions of second semiconductor material that are alternatively interleaved. Additionally, the apparatuses, methods, and systems include a first electrode and a second electrode that can operate both as a source and drain. The apparatuses, methods, and systems also include a first gate electrode having multiple portions on the first semiconductor material and a second gate electrode having multiple portions on the second semiconductor material that bidirectionally control current flow between the first electrode and the second electrode.
US09666666B2 Dual-gate trench IGBT with buried floating P-type shield
A method of manufacturing an insulated gate bipolar transistor (IGBT) device comprising 1) preparing a semiconductor substrate with an epitaxial layer of a first conductivity type supported on the semiconductor substrate of a second conductivity type; 2) applying a gate trench mask to open a first trench and second trench followed by forming a gate insulation layer to pad the trench and filling the trench with a polysilicon layer to form the first trench gate and the second trench gate; 3) implanting dopants of the first conductivity type to form an upper heavily doped region in the epitaxial layer; and 4) forming a planar gate on top of the first trench gate and apply implanting masks to implant body dopants and source dopants to form a body region and a source region near a top surface of the semiconductor substrate.
US09666658B2 Organic light emitting diode display and manufacturing method thereof
Disclosed is an organic light emitting diode (OLED) display including an organic light emitting diode (OLED) display including an insulation substrate and a first electrode disposed on the insulation substrate. A pixel defining layer surrounds the first electrode. The pixel defining layer forms a pixel area on the first electrode. An organic emission layer is disposed on the first electrode in the pixel area. An electrode connecting portion is disposed on the pixel defining layer. A second electrode is disposed on the organic emission layer. The second electrode is connected to the electrode connecting portion.
US09666642B2 Variable resistance memory device and method of driving the same
A variable resistance memory device and a driving method thereof are provided. The variable resistance memory device includes a base layer and a pillar-shaped gate electrode formed on the base layer and extending substantially perpendicular to a surface of the base layer. A current transfer layer is formed to surround the pillar-shaped gate electrode. A variable resistance layer formed in an outer portion of the current transfer layer. A blocking layer blocks a path of current flowing through the current transfer layer based on a voltage applied voltage to the pillar-shaped gate electrode, and diverts the current flowing through the current transfer layer to the variable resistance layer.
US09666639B2 Spin torque transfer memory cell structures and methods
Spin Torque Transfer (STT) memory cell structures and methods are described herein. One or more STT memory cell structures comprise a STT stack including: a pinned ferromagnetic material in contact with an antiferromagnetic material; a tunneling barrier material positioned between a ferromagnetic storage material and the pinned ferromagnetic material; a multiferroic material in contact with the ferromagnetic storage material; and a first electrode and a second electrode, wherein the antiferromagnetic material, the pinned ferromagnetic material, and the ferromagnetic storage material are located between the first electrode and the second electrode. The STT memory cell structure can include a third electrode and a fourth electrode, wherein at least a first portion of the multiferroic material is located between the third and the fourth electrode.
US09666636B2 Process module for increasing the response of backside illuminated photosensitive imagers and associated methods
Backside illuminated photosensitive devices and associated methods are provided. In one aspect, for example, a backside-illuminated photosensitive imager device can include a semiconductor substrate having multiple doped regions forming a least one junction, a textured region coupled to the semiconductor substrate and positioned to interact with electromagnetic radiation where the textured region includes surface features sized and positioned to facilitate tuning to a preselected wavelength of light, and a dielectric region positioned between the textured region and the at least one junction. The dielectric region is positioned to isolate the at least one junction from the textured region, and the semiconductor substrate and the textured region are positioned such that incoming electromagnetic radiation passes through the semiconductor substrate before contacting the textured region. Additionally, the device includes an electrical transfer element coupled to the semiconductor substrate to transfer an electrical signal from the at least one junction.
US09666625B2 Method of making low profile sensor package with cooling feature
A sensor device and method of making same that includes a silicon substrate with opposing first and second surfaces, a sensor formed at or in the first surface, a plurality of first contact pads formed at the first surface which are electrically coupled to the sensor, and a plurality of cooling channels formed as first trenches extending into the second surface but not reaching the first surface. The cooling channels instead can be formed on one or more separate substrates that are attached to the silicon substrate for cooling the silicon substrate.
US09666622B2 Semiconductor integrated circuit device
Provided is a semiconductor integrated circuit device having pixel regions in a photodiode array region and having, in each of the pixel regions, a waveguide holding hole having a substantially perpendicular sidewall above the photodiode and embedded with a silicon oxide-based sidewall insulating film reaching the bottom surface of the hole and two or more silicon nitride-based insulating films having a higher refractive index on the inner side of the hole. This structure makes it possible to prevent deterioration of pixel characteristics of an imaging device, such as CMOS sensor, which is rapidly decreasing in size.
US09666619B2 CMOS image sensor structure
A semiconductor device includes a carrier, a substrate, light-sensing devices and a bonding layer. The substrate overlies the carrier, and has a first surface and a second surface opposite to the first surface. The substrate includes inverted pyramid recesses in the second surface. The light-sensing devices are disposed on the first surface of the substrate. The bonding layer is disposed between the substrate and the carrier.
US09666618B2 Pixel array with individual exposure control using at least two transfer gates for a pixel or pixel region
A pixel array includes a plurality of pixel structures, with each pixel structure having a photo-sensitive element for generating charge in response to incident light; a charge conversion element; a first transfer gate and a second transfer gate connected in series between the photosensitive element and the charge conversion element or between the photosensitive element and a supply line; and an output stage. A first transfer gate control line is connected to the first transfer gates of a first sub-set of the pixel structures in the array; and a second transfer gate control line connected to the second transfer gates of a second sub-set of the pixel structures in the array. The first sub-set of pixel structures and second sub-set of pixel structures partially overlap, having at least one pixel structure in common between them.
US09666617B2 Imaging device, electronic apparatus, and method of manufacturing imaging device
An imaging device includes: a photodiode configured to perform photoelectric conversion and to generate electric charge in accordance with an amount of received light; a floating diffusion section configured to accumulate the electric charge generated in the photodiode; a reading circuit configured to output a pixel signal having a voltage in accordance with a level of the electric charge accumulated in the floating diffusion section, the reading circuit including one or a plurality of transistors each having a gate that is electrically connected to a wiring used for selecting a pixel; and an insulating section extending into part or whole of a bottom surface of the floating diffusion section, part or whole of bottom surfaces of source-drain regions in the one or the plurality of transistors, or both. The photodiode, the floating diffusion section, the reading circuit, and the insulating section are provided in a semiconductor layer.
US09666615B2 Semiconductor on insulator substrate with back bias
A semiconductor on insulator substrate includes an electrically conductive layer disposed between an electrically insulating handle layer and the semiconductor layer to facilitate the application of a back bias. The connection of the electrically conductive layer to a reference voltage reduces the effects of trapped or fixed charges associated with the handle layer on the threshold voltage of a transistor formed on the semiconductor layer. Silicon-based devices formed on glass, plastic, and quartz substrates are among the devices that can benefit from the application of a back bias.
US09666614B2 Semiconductor display device
It is an object of the present invention to provide a semiconductor display device having an interlayer insulating film which can obtain planarity of a surface while controlling film formation time, can control treatment time of heating treatment with an object of removing moisture, and can prevent moisture in the interlayer insulating film from being discharged to a film or an electrode adjacent to the interlayer insulating film. An inorganic insulating film containing nitrogen, which is less likely to transmit moisture compared with an organic resin, is formed so as to cover a TFT. Next, an organic resin film containing photosensitive acrylic resin is applied to the organic insulting film, and the organic resin film is partially exposed to light to be opened. Thereafter, an inorganic insulting film containing nitrogen, which is less likely to transmit moisture compared with an organic resin, is formed so as to cover the opened organic resin film. Then, in the opening part of the organic resin film, a gate insulating film and the two layer inorganic insulating film containing nitrogen are opened partially by etching to expose an active layer of the TFT.
US09666608B2 Array substrate and display device
An array substrate includes a first electrode located above a switching element through a first insulating film, a second electrode located above the first electrode through a second insulating film, and a connection portion that is located to pass through the first insulating film, first electrode, and second insulating film and electrically connects a drain electrode of the switching element and the second electrode. The connection portion is disposed in an avoidance region provided by carving out a gate line connected to the switching element.
US09666607B2 Display device
A display device includes a signal line disposed on a substrate. A signal input line is disposed on the substrate and connected to a driver. A first insulating layer is disposed on the signal line. A second insulating layer is disposed on the signal input line and the first insulating layer. First contact holes penetrate the first insulating layer and the second insulating layer and expose a portion of the signal line. Second contact holes penetrate the second insulating layer and expose a portion of the signal input line. A connecting member connects the signal line and the signal input line through the first and the second contact holes and is disposed on the second insulating layer. The first and the second contact holes are alternately arranged in the second insulating layer.
US09666604B2 Display device
A display device includes a first pixel, a second pixel, a first substrate, and a second substrate. The first pixel includes a first pixel electrode, a first conductive film, and a first transistor. The first pixel electrode is electrically connected to the first transistor. The first conductive film includes a region functioning as a common electrode. The second pixel includes a second pixel electrode, a second conductive film, and a second transistor. The second pixel electrode is electrically connected to the second transistor. The second conductive film includes a region functioning as a common electrode. The first conductive film and the second pixel electrode are provided on the same plane. A first insulating film is provided over the first conductive film and the second pixel electrode. The first pixel electrode and the second conductive film are provided over the first insulating film.
US09666603B2 Liquid crystal display device with oxide thin film transistor
A display device is discussed. The display device includes a substrate having a display area and a pad area in a periphery of the display area, the display area including a plurality of pixel regions; a thin film transistor having a channel layer, and on the substrate; a gate link line and a first common voltage line arranged to cross each other, and having a first insulation film interposed therebetween; a second common voltage line and a data link line arranged to cross each other, and having second insulation film interposed therebetween; a first pattern disposed on the first insulation film; and a second pattern disposed. on the second insulation film, wherein the channel layer, the first pattern and the second pattern are formed of the same material.
US09666602B2 Thin-film transistor substrate and method of manufacturing the thin-film transistor substrate
A thin film transistor substrate includes the following elements: a base substrate, a data line disposed on the base substrate, a source electrode contacting the data line, a drain electrode spaced from the source electrode, a channel disposed between the source electrode and the drain electrode, a pixel electrode electrically connected to the drain electrode, a gate insulation pattern disposed on the channel, and a gate electrode disposed on the gate insulation pattern.
US09666599B2 Display device having a multilayered undercoating layer of silicon oxide and silicon nitride
According to one embodiment, a display device includes an underlying insulation layer formed on a surface of a resin layer, and a thin-film transistor formed above the surface of the resin layer via the underlying insulation layer. The underlying insulation layer includes a three-layer multilayer structure of a first silicon oxide film, a silicon nitride film formed above the first silicon oxide film, and a second silicon oxide film formed above the silicon nitride film.
US09666598B2 Semiconductor device with an integrated heat sink array
An integrated heat sink array is introduced in SOI power devices having multiple unit cells, which can be used to reduce the temperature rise in obtaining more uniform temperature peaks for all the unit cells across the device area, so that the hot spot which is prone to breakdown can be avoided, thus the safe operating area of the device can be improved. Also the array sacrifice less area of the device, therefore results in low Rdson.
US09666595B2 Semiconductor memory device and method of manufacturing the same
A semiconductor memory device includes a first layer, a plurality of memory areas, a plurality of contact wires, a first shunt wire, and a second shunt wire. The memory areas are provided on the first layer in a first direction. The contact wires have a longitudinal direction in a second direction perpendicular to the first layer. The contact wires are provided between the adjacent memory areas on the first layer in a third direction intersecting the first direction. The first shunt wire commonly connects the contact wires. The second shunt wire extends in the first direction and is electrically connected to the first shunt wire.
US09666592B2 Memory devices and methods of fabricating the same
A memory device includes a substrate having common source regions thereon, common source lines extending along a surface of the substrate and contacting the common source regions, respectively, and channel structures extending away from the surface of the substrate between the common source lines. The common source lines define a unit cell of the memory device therebetween. The memory device further includes an electrode stack structure having interlayer insulating layers and conductive electrode layers that are alternately stacked along sidewalls of the channel structures. The conductive electrode layers define respective gates of selection transistors and memory cell transistors of the memory device. An isolation insulating layer, which includes a portion of a sacrificial layer, is disposed between adjacent ones of the interlayer insulating layers in the stack structure. The isolation insulating layer divides at least one of the conductive electrode layers in the stack structure into electrically separate portions.
US09666591B2 Non-volatile memory with silicided bit line contacts
An approach to use silicided bit line contacts that do not short to the underlying substrate in memory devices. The approach provides for silicide formation in the bit line contact area, using a process that benefits from being self-aligned to the oxide-nitride-oxide (ONO) nitride edges. A further benefit of the approach is that the bit line contact implant and rapid temperature anneal process can be eliminated. This approach is applicable to embedded flash, integrating high density devices and advanced logic processes.
US09666590B2 High stack 3D memory and method of making
A method of making a monolithic three dimensional NAND device includes forming a stack of alternating layers of a first material and a second material different from the first material over a substrate, forming a mask layer over the stack and patterning the mask layer to form at least on opening in the mask layer to expose a top layer of the stack. The method also includes forming a metal block in the at least one opening in the mask layer, etching the stack by metal induced localized etch using the metal block in the at least one opening in the mask layer to form at least one opening in the stack and forming at least one layer of the NAND device in the at least one opening.
US09666589B1 FinFET based flash memory cell
A method of manufacturing a semiconductor device is provided including providing a semiconductor substrate, forming a first plurality of semiconductor fins in a logic area of the semiconductor substrate, forming a second plurality of semiconductor fins in a memory area of the semiconductor substrate, forming an insulating layer between the fins of the first plurality of semiconductor fins and between the fins of the second plurality of semiconductor fins, forming an electrode layer over the first and second pluralities of semiconductor fins and the insulating layer, forming gates over semiconductor fins of the first plurality of semiconductor fins in the logic area from the gate electrode layer, and forming sense gates and control gates between semiconductor fins of the second plurality of semiconductor fins in the logic area from the gate electrode layer.
US09666587B1 Semiconductor device and method
A structure and method for the formation and use of fuses within a semiconductor device is provided. The fuses may be formed within the third metal layer and are formed so as to be arranged perpendicularly to active devices located on an underlying semiconductor substrate. Additionally, the fuses within the third metal layer may be formed thicker than an underlying second metal layer.
US09666581B2 FinFET with source/drain structure and method of fabrication thereof
A method of semiconductor fabrication that includes providing a plurality of fins extending from a substrate is described. Each of the plurality of fins has a top surface and two opposing lateral sidewalls. A gate structure is formed over a first region of each of the plurality of fins and interfaces the top surface and the two opposing lateral sidewalls. A source/drain epitaxial feature is formed on a second region of each of the plurality of fins. The source/drain epitaxial feature interfaces the top surface and the two opposing lateral sidewalls. An air gap is provided which is defined by at least one surface of the source/drain epitaxial feature.
US09666580B1 Nitride semiconductor device and method of manufacturing the same
A nitride semiconductor device includes a conductive substrate and a nitride semiconductor layer. The nitride semiconductor layer is disposed on the conductive substrate. The nitride semiconductor layer includes a first transistor structure of a lateral type and a second transistor structure of a lateral type. The conductive substrate includes a first potential control region and a second potential control region capable of controlling potential independently from the first potential control region. In planar view of the nitride semiconductor layer, the first transistor structure overlaps the first potential control region and the second transistor structure overlaps the second potential control region.
US09666577B2 On-SOI integrated circuit equipped with a device for protecting against electrostatic discharges
The invention relates to an IC with an electrostatic discharge protection device. There is a buried insulant layer 50 nm or less in thickness and first and second bipolar transistors on the insulant layer, one being an npn transistor and the other a pnp transistor. The base of the first transistor is merged with the collector of the second transistor and the base of the second transistor is merged with the collector of the first transistor. The first and second bipolar transistors are configured to selectively conduct a discharge current between two electrodes of the protection device. There is a first semiconductor ground plane under the insulant layer, being electrically biased, extending until it is plumb with the base of the first bipolar transistor, exhibiting a first type of doping identical to that of the base of the first bipolar transistor with a doping density at least ten times greater.
US09666575B2 Semiconductor arrangement facilitating enhanced thermo-conduction
A semiconductor arrangement includes a well region and a first region disposed within the well region. The first region includes a first conductivity type. The semiconductor arrangement includes a first gate disposed above the well region on a first side of the first region. The first gate includes a first top surface facing away from the well region. The first top surface has a first top surface area. The semiconductor arrangement includes a first gate contact disposed above the first gate. The first gate contact includes a first bottom surface facing towards the well region. The first bottom surface has a first bottom surface area. The first bottom surface area covers at least about two thirds of the first top surface area.
US09666574B1 Semiconductor device structure and manufacturing method thereof
Some embodiments of the present disclosure provide a semiconductor device. The semiconductor device includes a first transistor configured to include a first threshold voltage level. The first transistor includes a gate structure. The gate structure includes a first component including a first conductive type. A second transistor configures to include a second threshold voltage level different from the first threshold voltage level. The second transistor includes a gate structure. The gate structure includes a second component including the first conductive type. At least one extra component is disposed over the second component. The least one extra component includes a second conductive type opposite to the first conductive type. The first transistor and the second transistor are coupled such that the number of the least one extra component is determined by a desired voltage difference between the first threshold voltage level and the second threshold voltage level.
US09666569B2 Switch circuit of cascode type having high speed switching performance
Provided is switch circuit including first and second transistors, a source pad connected to a second node of the second transistor through a first signal path and connected to a gate node of the first transistor through a second signal path, a gate pad connected to a gate node of the second transistor through a third signal path; and a drain pad connected to a first node of the first transistor through a fourth signal path, wherein a second node of the first transistor and a first node of the second transistor are connected to each other through a fifth signal path, and the gate node of the first transistor and the second node of the second transistor are connected to each other through a sixth signal path separated from the first and second signal paths.
US09666565B2 Optical device and method for manufacturing same
The present invention relates to an optical device and a method for manufacturing the same. The technical object of the invention is to realize a surface emitting body which allows heat generated from a light-emitting chip to be easily dissipated, eliminates the need for an additional wiring layer, and allows a singular light emitting chips or a plurality of light emitting chips to be arranged in series, in parallel, or in series-parallel. The present invention discloses an optical device comprising: a substrate; a plurality of light emitting chips disposed on the substrate; a plurality of conductive wires which electrically connect the substrate with the light emitting chips such that the plurality of light emitting chips are connected to each other in series, in parallel or in series-parallel; and a protective layer which covers the plurality of light emitting chips and the plurality of conductive wires on the substrate.
US09666556B2 Flip chip packaging
An integrated circuit (IC) package includes a first substrate; a second substrate disposed over the first substrate; a plurality of connectors disposed between the first and second substrates such to electrically couple the first and second substrate; a constraint layer disposed over the first and second substrates such that a cavity is formed between the constraint layer and the first substrate; and a molding material disposed within the cavity and extending through the constraint layer. The constraint layer has a top surface and an opposing bottom surface and the molding material extends from the top surface to the bottom surface of the constraint layer.
US09666551B1 Semiconductor chip, semiconductor package including the same, and method of manufacturing semiconductor chip
The semiconductor chip including a semiconductor device layer including a pad region and a cell region, a plurality of uppermost wirings formed on the semiconductor device layer to be arranged at an equal distance in the cell region, a passivation layer formed in the cell region and the pad region, and a plurality of thermal bumps disposed on the passivation layer to be electrically insulated from the plurality of uppermost wirings may be provided. The semiconductor device layer may include a plurality of through silicon via (TSV) structures in the pad region. The plurality of uppermost wirings may extend in parallel along one direction and have a same width. The passivation layer may cover at least a top surface of the plurality of uppermost wirings in the cell region and includes a top surface having a wave shape.
US09666549B2 Methods for solder for through-mold interconnect
Generally discussed herein are systems and apparatuses that include an extended TSBA ball and techniques for making the same. According to an example, a technique can include forming a circuit substrate including forming a circuit on a substrate, the circuit exposed along an upper surface of the substrate, wherein the substrate is for coupling the circuit with a die along a lower surface of the circuit substrate. A molding can be formed onto an upper surface of the circuit substrate, over the circuit of the circuit substrate. An opening can be defined in the molding so that the opening can extend to a top surface of the molding to at least a portion of the circuit. Solder can be formed into the opening, including conforming the solder to the opening and the circuit substrate.
US09666548B2 Method of fabricating connection structure for a substrate
A connection structure for a substrate is provided. The substrate has a plurality of connection pads and an insulation protection layer with the connection pads being exposed therefrom. The connection structure includes a metallic layer formed on an exposed surface of each of the connection pads and extending to the insulation protection layer, and a plurality of conductive bumps disposed on the metallic layer and spaced apart from one another at a distance less than or equal to 80 μm, each of conductive bumps having a width less than a width of each of the connection pads. Since the metallic layer covers the exposed surfaces of the connection pads completely, a colloid material will not flow to a surface of the connection pads during a subsequent underfilling process of a flip-chip process. Therefore, the colloid material will not be peeled off from the connection pads.
US09666547B2 Method of refining solder materials
The invention includes solder materials having low concentrations of alpha particle emitters, and includes methods of purification of materials to reduce a concentration of alpha particle emitters within the materials. The invention includes methods of reducing alpha particle flux in various lead-containing and lead-free materials through purification of the materials. The invention also includes methods of estimating the fractionation of a low concentration of one or more alpha particle emitters during purification of a material.
US09666544B2 Package substrate differential impedance optimization for 25 GBPS and beyond
A package design method is disclosed for the optimization of package differential impedance at data rates of 25 Gb/s and beyond. The method optimizes the differential impedance of package vertical interconnections of BGA ball, via, and PTH as well as around the joint between the vertical interconnection and the horizontal interconnection of trace. At 8 ps rise time, a <5% impedance variation is obtained with a 0.8 mm BGA ball pitch and a 10-layer buildup substrate and a <10% impedance variation is obtained with a 1 mm BGA ball pitch and a 14-layer buildup substrate. The method is applicable to all BGA package designs running at 25 Gb/s and beyond.
US09666542B2 Wiring substrate and manufacturing method thereof
A wiring substrate is provided with a support substrate (31), an insulating layer (32), and a wiring layer (33). The support substrate (31) is formed with a hole (34) including an opening portion in one surface of the support substrate (31). The insulating layer (32) is formed on a surface of the support substrate (31) opposite to the one surface thereof including the opening portion. The wiring layer (33) includes a wiring pattern of a predetermined structure on the insulating layer (32). Further, an orthographic projection to be obtained when the wiring pattern is projected on a predetermined surface of the support substrate (31), and an orthographic projection to be obtained when the hole (34) is projected on the predetermined surface of the support substrate (31) include a shared portion.
US09666541B2 Electronic device, manufacturing method of the same, and network system
An electronic device includes: a substrate; a first all-solid-state secondary cell provided on the substrate, the first all-solid-state secondary cell including a first electrode layer, a solid electrolyte layer, and a second electrode layer; a first transistor including a first source drain, a second source drain electrically connected to the second electrode layer, and a first gate electrode; a first terminal electrically connected to the first electrode layer; a second terminal to control a potential of the first gate electrode; a third terminal electrically connected to the first source drain; and a sealing layer covering the first all-solid-state secondary cell and the first transistor, wherein the first terminal, the second terminal, and the third terminal are exposed on an upper surface of the sealing layer.
US09666540B2 Semiconductor device and method of forming prefabricated heat spreader frame with embedded semiconductor die
A semiconductor device is made by mounting a prefabricated heat spreader frame over a temporary substrate. The heat spreader frame includes vertical bodies over a flat plate. A semiconductor die is mounted to the heat spreader frame for thermal dissipation. An encapsulant is deposited around the vertical bodies and semiconductor die while leaving contact pads on the semiconductor die exposed. The encapsulant can be deposited using a wafer level direct/top gate molding process or wafer level film assist molding process. An interconnect structure is formed over the semiconductor die. The interconnect structure includes a first conductive layer formed over the semiconductor die, an insulating layer formed over the first conductive layer, and a second conductive layer formed over the first conductive layer and insulating layer. The temporary substrate is removed, dicing tape is applied to the heat spreader frame, and the semiconductor die is singulated.
US09666539B1 Packaging for high speed chip to chip communication
Disclosed are chip packaging structures for high speed chip to chip and chip to carrier communications and methods of making such structures. The chip packaging structures do not require an interposer containing through silicon vias and/or provide structures having reduced warping.
US09666536B2 Package structure and fabrication method thereof
The present invention provides a package structure and fabrication method thereof. The method includes providing a first carrier having a metal layer; forming a dielectric layer on the metal layer; forming a plurality of conductive pillars embedded into the dielectric layer and protruding from a surface of the dielectric layer, and disposing an electronic component on the surface of the dielectric layer; forming an encapsulating layer on the dielectric layer to encompass the plurality of conductive pillars, the dielectric layer and the electronic component; removing a portion of the encapsulating layer and the first carrier such that two ends of each of the plurality of conductive pillars are exposed from the encapsulating layer and the dielectric layer. Therefore, the present invention effectively reduces manufacturing costs and the need for an opening process while manufacturing the conductive pillars can be eliminated.
US09666535B2 Flexible display panel
Embodiments of the present invention disclose a flexible display panel. The flexible display panel at least comprises an display area, a fanout area and a driver circuit area, wherein the fanout area is positioned between the display area and the driver circuit area to connect the display area with the driver circuit area, and the fanout area comprises at least one zig-zag fanout wire, each of which comprises a plurality of fanout wire segments divided by bending points. In the technical solutions of the present invention, by utilizing a zig-zag wiring manner, damage to metal wires when bending is reduced, bending resistance of the fanout area is improved and damage to the screen when bending the flexible display panel is avoided or reduced.
US09666532B2 Twisted array design for high speed vertical channel 3D NAND memory
Roughly described, a memory device has a multilevel stack of conductive layers. Vertically oriented pillars each include series-connected memory cells at cross-points between the pillars and the conductive layers. SSLs run above the conductive layers, each intersection of a pillar and an SSL defining a respective select gate of the pillar. Bit lines run above the SSLs. The pillars are arranged on a regular grid which is rotated relative to the bit lines. The grid may have a square, rectangle or diamond-shaped unit cell, and may be rotated relative to the bit lines by an angle θ where tan(θ)=±X/Y, where X and Y are co-prime integers. The SSLs may be made wide enough so as to intersect two pillars on one side of the unit cell, or all pillars of the cell, or sufficiently wide as to intersect pillars in two or more non-adjacent cells.
US09666527B1 Middle of the line integrated eFuse in trench EPI structure
A fuse includes a semiconductor layer having a dielectric material formed thereon. An epitaxially grown material is formed in a trench within the dielectric material. The epitaxially grown material includes a peak region. A fuse metal is formed over the peak region and extends along sidewalls of the trench and over the dielectric material outside the trench. Contacts are formed outside the trench connecting to fuse metal over the dielectric material.
US09666525B2 Three-dimensional semiconductor memory device
Three-dimensional (3D) semiconductor memory devices capable of improving reliability may be provided. For example, a three dimensional (3D) memory device, in which a plurality of memory cell strings are vertically arranged, may include a substrate, a stack structure of alternating a plurality of interlayer dielectric (ILD) layers and a plurality of gate electrodes, at least one of the ILD layers including pores, a vertical structure penetrating the stack structure and electrically connected to the substrate, and a data storage layer between the stack structure and the vertical structure.
US09666518B1 Semiconductor device
A semiconductor device includes a plurality of metal patterns formed on a ceramic substrate, and a semiconductor chip mounted on some of the plurality of metal patterns. Also, a plurality of hollow portions are formed in peripheral portions of the plurality of metal patterns. In addition, the plurality of hollow portions are not formed in a region overlapping the semiconductor chip in the plurality of metal patterns. Furthermore, the plurality of hollow portions are provided in a plurality of metal patterns arranged at a position closest to the peripheral portion of the top surface of the ceramic substrate among the plurality of metal patterns.
US09666516B2 Electronic packages and methods of making and using the same
An electronic package and a method of making the same in provided. The electronic package includes a dielectric layer and a conformal masking layer disposed on at least a portion of the dielectric layer. The electronic package further includes a routing layer disposed on at least a portion of the masking layer and a micro-via disposed at least in part in the conformal masking layer and the routing layer. Further, at least a portion of the routing layer forms a conformal electrically conductive layer in at least a portion of the micro-via. Also, the conformal masking layer is configured to define a size of the micro-via. The electronic package further includes a semiconductor die operatively coupled to the micro-via.
US09666508B2 Gallium arsenide devices with copper backside for direct die solder attach
Systems, apparatuses, and methods related to the design, fabrication, and manufacture of gallium arsenide (GaAs) integrated circuits are disclosed. Copper can be used as the contact material for a GaAs integrated circuit. Metallization of the wafer and through-wafer vias can be achieved through copper plating processes disclosed herein. Direct die solder (DDS) attach can be achieved by use of electroless nickel plating of the copper contact layer followed by a palladium flash. GaAs integrated circuits can be singulated, packaged, and incorporated into various electronic devices.
US09666506B2 Heat spreader with wiring substrate for reduced thickness
A semiconductor device includes a wiring substrate, a semiconductor element mounted on the wiring substrate, a heat dissipation plate arranged on an upper surface of the semiconductor element with an adhesive arranged in between, and an encapsulation resin filling a gap between the heat dissipation plate and the wiring substrate. The heat dissipation plate includes a body and a projection. The body is overlapped with the semiconductor element in a plan view and has a larger planar shape than the semiconductor element. The projection is formed integrally with the body. The projection projects outward from an end of the body and is located below the body. The encapsulation resin covers upper and lower surfaces of the projection. The body includes an upper surface exposed from the encapsulation resin.
US09666504B2 Heat sink for cooling of power semiconductor modules
A heat sink for cooling at least one power semiconductor module, and that includes a basin for containing a cooling liquid. The basin has a contact rim for receiving the base plate and that includes a surface that is sloped inwards to the basin.
US09666503B2 Semiconductor package and electronic system including the same
A semiconductor package and an electronic system including the same include a package board having an electric circuit pattern. A semiconductor chip is mounted on the package board and electrically connected with the circuit pattern of the package board. A non-contact temperature detector is provided with the semiconductor package and detects a temperature of an external heat source without making contact with the external heat source. A temperature controller controls the semiconductor chip according to the temperature of the external heat source that is detected by the non-contact temperature detector.
US09666501B2 Semiconductor device including a lead frame
A semiconductor device including a die pad having a front surface made of Cu; a semiconductor chip disposed so as to be opposed to the front surface of the die pad; a bonding layer provided between the die pad and the semiconductor chip; and a plurality of leads disposed around the die pad, wherein the die pad and the plurality of leads make up a lead frame in cooperation with each other, a cavity is fabricated on the surface of the plurality of leads, and a projecting portion is fabricated next to the cavity.
US09666499B2 Semiconductor device with encapsulant
Described are techniques related to semiconductor devices that make use of encapsulant. In one implementation, a semiconductor device may be manufactured to include at least an encapsulant that includes at least glass particles.
US09666498B2 Ring-frame power package
The present disclosure relates to a ring-frame power package. The ring-frame power package includes a thermal carrier and a ring structure. The thermal carrier has a carrier surface. The ring structure is disposed over the carrier surface of the thermal carrier so that a portion of the carrier surface is exposed through an interior opening of the ring body. The ring structure also includes one or more interconnect tabs that extend outward from an outer periphery of the ring body. Each interconnect tab includes a top plated area that covers at least a portion of a top surface and a bottom plated area that covers at least a bottom surface of the respective interconnect tab. Notably, each top plated area also covers a contact portion of the ring body that is adjacent to the respective interconnect tab. Each top plated area is electrically coupled to the corresponding bottom plated area.
US09666492B2 CMOS implementation of germanium and III-V nanowires and nanoribbons in gate-all-around architecture
Architectures and techniques for co-integration of heterogeneous materials, such as group III-V semiconductor materials and group IV semiconductors (e.g., Ge) on a same substrate (e.g. silicon). In embodiments, multi-layer heterogeneous semiconductor material stacks having alternating nanowire and sacrificial layers are employed to release nanowires and permit formation of a coaxial gate structure that completely surrounds a channel region of the nanowire transistor. In embodiments, individual PMOS and NMOS channel semiconductor materials are co-integrated with a starting substrate having a blanket layers of alternating Ge/III-V layers. In embodiments, vertical integration of a plurality of stacked nanowires within an individual PMOS and individual NMOS device enable significant drive current for a given layout area.
US09666486B1 Contained punch through stopper for CMOS structures on a strain relaxed buffer substrate
A semiconductor structure is provided in which the diffusion of arsenic is retarded. The structure includes a strain relaxed silicon germanium alloy buffer layer located on a surface of a silicon substrate. A boron-containing p-well region is located in a first region of a carbon doped silicon germanium alloy layer and on a first portion of the strain relaxed silicon germanium alloy buffer layer, and a phosphorus-containing n-well region is located in a second region of the carbon doped silicon germanium alloy layer and on a second portion of the strain relaxed silicon germanium alloy buffer layer. A tensily strained silicon material is located on a surface of the p-well region, and a compressively strained germanium-containing material is located on a surface of the n-well region.
US09666484B2 Integrated circuit protected from short circuits caused by silicide
An integrated circuit is formed on a semiconductor substrate and includes a trench conductor and a first transistor formed on the surface of the substrate. The transistor includes: a transistor gate structure, a first doped region extending in the substrate between a first edge of the gate structure and an upper edge of the trench conductor, and a first spacer formed on the first edge of the gate structure and above the first doped region. The first spacer completely covers the first doped region and a silicide is present on the trench conductor but is not present on the surface of the first doped region.
US09666482B1 Self aligned silicon carbide contact formation using protective layer
A silicon-carbide substrate that includes a doped contact region and a dielectric layer is provided. A protective layer is formed on the dielectric layer. A structured mask is formed on the protective layer. Sections of the protective layer and the dielectric layer that are exposed by openings in the mask are removed. The structured mask is removed. A metal layer is deposited such that a first portion of the metal layer directly contacts the doped contact region and a second portion of the metal layer lines the remaining sections of the protective layer and the dielectric layer. A first rapid thermal anneal process is performed. After performing the first rapid thermal anneal process, the second portion of the metal layer and the remaining section of the protective layer are removed without removing the first portion of the metal layer.
US09666478B2 Methods of forming wiring structures and methods of manufacturing semiconductor devices
In a method of forming a wiring structure, an insulating interlayer is formed on a substrate. The insulating interlayer includes an opening and has pores distributed therein and exposed at a surface thereof. The insulating interlayer is exposed to a silane compound to form a pore sealing layer on the surface of the insulating interlayer and a sidewall of the opening. A conductive pattern filling the opening is formed on the pore sealing layer.
US09666477B2 Method of manufacturing semiconductor device
A method of manufacturing a semiconductor device includes forming a first insulating film as a portion of a laminated insulating film on a substrate in which a plurality of circuit configurations is formed; polishing the first insulating film; measuring a film thickness distribution of the first insulating film; and forming a second insulating film as a portion of the laminated insulating film on the polished first insulating film at a film thickness distribution differing from the film thickness distribution of the first insulating film to correct a film thickness of the laminated insulating film.
US09666475B2 Semiconductor structure with airgap
A field effect transistor (FET) with an underlying airgap and methods of manufacture are disclosed. The method includes forming an amorphous layer at a predetermined depth of a substrate. The method further includes forming an airgap in the substrate under the amorphous layer. The method further includes forming a completely isolated transistor in an active region of the substrate, above the amorphous layer and the airgap.
US09666470B2 Receptacle device, device and method for handling substrate stacks
The invention relates to a retaining system for handling substrate stacks, including a retaining surface for retaining a first substrate, and one or more recesses provided relative to the retaining surface, for retaining first magnetic bodies for securing the first substrate relative to a second substrate that is aligned with the first substrate. Second magnetic bodies are applied on a holding side of the second substrate.
US09666466B2 Electrostatic chuck having thermally isolated zones with minimal crosstalk
A substrate support assembly includes a ceramic puck and a thermally conductive base having an upper surface that is bonded to a lower surface of the ceramic puck. The thermally conductive base includes a plurality of thermal zones and a plurality of thermal isolators that extend from the upper surface of the thermally conductive base towards a lower surface of the thermally conductive base, wherein each of the plurality of thermal isolators provides approximate thermal isolation between two of the plurality of thermal zones at the upper surface of the thermally conductive base.
US09666464B2 Substrate processing apparatus and substrate processing method
Provided is a substrate processing apparatus including: a carry-in area where a placing table is provided to place thereon a carrying container including a take-out opening, a flange formed on an upper portion of a side formed with the take-out opening, and a recess formed on a top surface of the flange; a transfer area maintained under an atmosphere different from that of the carry-in area; a partition wall configured to partition the carry-in area and the transfer area and formed with an opening; a door configured to open/close the opening; a carrying container pressing unit configured to press the carrying container placed on the placing table against the partition wall so that the take-out opening of the carrying container faces the opening of the partition wall; and a carrying container holding unit configured to be inserted into the recess to press the carrying container against the partition wall.
US09666457B2 Adsorption device for rotatable heating
An adsorption device for rotatable heating is provided with an adsorption heating plate, a support needle driving device, a rotary sliding ring, and a turning shaft. The adsorption heating plate is amounted at the top of the turning shaft, and a wafer is arranged at the top of the adsorption heating plate. The rotary sliding ring is connected to the turning shaft in which a vacuum channel and a connection wire channel are arranged. Support needles are connected to the output end of the support needle driving device, run through the adsorption heating plate, and are arranged at the bottom of the wafer uniformly. The adsorption device incorporates the wafer adsorption function, the wafer rotating function with controllable speed, and the heating function for heating the wafer to reach different temperatures, thereby providing adsorption and heating rotation at the same time.
US09666455B2 Substrate cleaning apparatus
A substrate cleaning apparatus cleans a surface of a substrate such as a semiconductor wafer and dries the substrate. The substrate cleaning apparatus includes a process chamber having a substrate conveying unit configured to hold a substrate horizontally with its upper surface facing upwardly and to convey the substrate in one direction, and a cleaning unit configured to clean the surface of the substrate in non-contact state by supplying a cleaning liquid to the surface of the substrate which is moving in the process chamber. The substrate apparatus has an inert gas blowing unit configured to blow an inert gas toward the front and reverse surfaces of the substrate which has been cleaned in the cleaning unit to produce an inert gas atmosphere in the process chamber while drying the substrate with the inert gas.
US09666453B2 Semiconductor package and a substrate for packaging
A semiconductor package is provided, which includes: a substrate having a metal pattern layer; a semiconductor die formed on the substrate; and an underfill filled between the substrate and the semiconductor die. At least an opening is formed in the metal pattern layer to reduce the area of the metal pattern layer on the substrate, thereby reducing the contact area between the underfill and the metal pattern layer, hence eliminating the underfill delamination.
US09666450B2 Substrate and assembly thereof with dielectric removal for increased post height
An interconnection substrate includes a plurality of electrically conductive elements of at least one wiring layer defining first and second lateral directions. Electrically conductive projections for bonding to electrically conductive contacts of at least one component external to the substrate, extend from the conductive elements above the at least one wiring layer. The conductive projections have end portions remote from the conductive elements and neck portions between the conductive elements and the end portions. The end portions have lower surfaces extending outwardly from the neck portions in at least one of the lateral directions. The substrate further includes a dielectric layer overlying the conductive elements and extending upwardly along the neck portions at least to the lower surfaces. At least portions of the dielectric layer between the conductive projections are recessed below a height of the lower surfaces.
US09666449B2 Conductors having a variable concentration of germanium for governing removal rates of the conductor during control gate formation
An embodiment of a method of forming a control gate includes forming a conductor having a concentration of germanium that varies with a thickness of the conductor, and removing portions of the conductor at a variable rate that is governed, at least in part, by the concentration of the germanium.
US09666448B2 Methods of forming patterns
A method of forming patterns includes forming an array of pillars on an underlying layer stacked on an etch target layer, forming a separation wall layer on the pillars to provide separation walls covering sidewalls of the pillars, forming a block copolymer layer on the separation wall layer, annealing the block copolymer layer to form first domains located between the pillars, and a second domain surrounding and isolating the first domains, selectively removing the first domains to form second openings, selectively removing the pillars to form fourth openings, forming fifth openings that extend from the second and fourth openings to penetrate the underlying layer, forming a sealing pattern that covers and seals dummy openings among the fifth openings, and forming seventh openings that extend from the fifth openings exposed by the sealing pattern to penetrate the etch target layer.
US09666436B2 Ion implantation methods
Provided are methods of forming an ion implanted region in a semiconductor device. The methods comprise: (a) providing a semiconductor substrate having a plurality of regions to be ion implanted; (b) forming a photoresist pattern on the semiconductor substrate, wherein the photoresist pattern is formed from a chemically amplified photoresist composition comprising a matrix polymer having acid labile groups, a photoacid generator and a solvent; (c) coating a descumming composition over the photoresist pattern, wherein the descumming composition comprises: a matrix polymer; a free acid; and a solvent; (d) heating the coated semiconductor substrate; (e) contacting the coated semiconductor substrate with a rinsing agent to remove residual descumming composition and scum from the substrate; and (f) ion implanting the plurality of regions of the semiconductor substrate using the photoresist pattern as an implant mask. The methods find particular applicability in the manufacture of semiconductor devices.
US09666435B2 Apparatus and process for integrated gas blending
A system (10) for delivery of dilute fluid, utilizing an active fluid source (12), a diluent fluid source (14), a fluid flow metering device (24) for dispensing of one of the active and diluent fluids, a mixer (38) arranged to mix the active and diluent fluids to form a diluted active fluid mixture, and a monitor (42) arranged to sense concentration of active fluid and/or diluent fluid in the diluted active fluid mixture, and responsively adjust the fluid flow metering device (24) to achieve a predetermined concentration of active fluid in the diluted active fluid mixture. A pressure controller (34) is arranged to control flow of the other of the active and diluent fluids so as to maintain a predetermined pressure of the diluted active fluid mixture dispensed from the system. The fluid dispensed from the system then can be adjustably controlled by a flow rate controller, e.g., a mass flow controller, to provide a desired flow to a fluid-utilizing unit, such as a semiconductor process tool. An end point monitoring assembly is also described, for switching fluid sources (12, 15) to maintain continuity of delivery of the diluted active fluid mixture.
US09666434B2 Method for forming fine patterns of semiconductor device
A method for forming fine patterns includes patterning a hard mask layer on an etch target layer to form sacrificial pillars and a first opening disposed between the sacrificial pillars and exposing the etch target layer, forming a block copolymer layer on the etch target layer exposed through the first opening, phase-separating the block copolymer layer to form first block patterns spaced apart from the sacrificial pillars and a second block pattern, forming first holes by etching the etch target layer exposed by removing the first block patterns, and forming second holes in the etch target layer exposed by removing the sacrificial pillars, the second holes being different from the first holes.
US09666430B2 Method of manufacturing semiconductor device and substrate processing apparatus
A film is formed on a substrate by performing a cycle at least twice, the cycle including a nucleus formation process for forming nuclei on the substrate and a nucleus growth suppression process for suppressing growth of the nuclei. A time required for the nucleus growth suppression process is less than or equal to a time required for the nucleus formation process. Alternatively, the nucleus formation process is further performed after the cycle is repeatedly performed a plurality of times.
US09666426B2 Methods and apparatus for uniformly metallization on substrates
An apparatus for substrate metallization from electrolyte is provided. The apparatus comprises: an immersion cell containing metal salt electrolyte; at least one electrode connecting to at least one power supply; an electrically conductive substrate holder holding at least one substrate to expose a conductive side of the substrate to face the at least one electrode; an oscillating actuator for oscillating the substrate holder with an amplitude and a frequency; at least one ultrasonic device with an operating frequency and an intensity, disposed in the metallization apparatus; at least one ultrasonic power generator connecting to the ultrasonic device; at least one inlet for metal slat electrolyte feeding; and at least one outlet for metal salt electrolyte draining.
US09666425B2 Gas discharge lamp
A gas discharge lamp has an inner bulb with a discharge vessel with two sealing sections thereon, from which electrodes protrude into the discharge vessel, each electrically connected with a conductor in the associated sealing section to supply current to the electrodes. The lamp also has an outer bulb surrounding the discharge vessel, leaving a cavity therebetween. Close to at least one of the electrodes in or near a transitional area between the discharge vessel and the associated sealing section on an outside of the inner bulb is arranged potential-free a conductive structure which on application of a voltage to the electrodes influences the electrical field adjacent the electrodes such that a discharge arc travels from the electrode first in the direction of a wall section of the discharge vessel adjacent the electrode and then over the inside of the wall toward the other electrode.
US09666421B2 Mass spectrometry data display device and mass spectrometry data display program
A mass spectrometry data display device in which the mass axis (m/z axis) is made into a ring shape and the intensity axis is the radial direction thereof, and peak information (in the drawing, the compound name and structural formula candidates) are arranged in a ring shape in correspondence with the peaks along the outer circumference of the mass spectrum and displayed together therewith on a screen.
US09666420B2 System and method of detection and quantification by mass spectrometry and by activating ionised molecular species
Disclosed is a system and method of mass spectrometry, including: a. ionizing an analyte to form a precursor ion (A) having a mass-to-charge ratio (m/z), in which m represents the mass and z the electric charge number; b. activating the precursor ion (A) by interaction with a beam of neutral species, ions, electrons or photons, having an energy chosen on the basis of the physicochemical properties of the precursor ion, the activation being suitable for producing a product ion (B, C) having the same mass m as the precursor ion (A) and an electric charge number z′ such that z′ is a non-zero integer different from z; c. separating the product ion (B, C, E, F) having a predefined mass-to-charge ratio (m/z′); d. detecting the product ion (B, C) having the predefined mass-to-charge ratio (m/z′).
US09666413B2 Ion implantation apparatus and control method for ion implantation apparatus
Provided is an ion implantation apparatus including: a vacuum processing chamber in which an ion implantation process for a wafer is performed; one or more load lock chambers that are used for bringing the wafer into the vacuum processing chamber and taking out the wafer from the vacuum processing chamber; an intermediate conveyance chamber that is disposed to be adjacent to both the vacuum processing chamber and the load lock chamber; a load lock chamber-intermediate conveyance chamber communication mechanism including a gate valve capable of sealing a load lock chamber-intermediate conveyance chamber communication port; and an intermediate conveyance chamber-vacuum processing chamber communication mechanism including a movable shielding plate capable of shielding a part or the whole of the intermediate conveyance chamber-vacuum processing chamber communication port.
US09666410B2 Charged particle beam device
Proposed is a charged particle beam device including an arithmetic processing unit that generates an image of a sample, based on a detection signal that is detected based on irradiation to the sample with a charged particle beam emitted from a charged particle source. The arithmetic processing unit searches a second image as a search target image with use of a first image as a template, and when a region corresponding to the first image is not detected in the second image, the arithmetic processing unit searches a third image that represents a region larger than a region displayed in the second image, with use of a second template.
US09666405B1 System for imaging a signal charged particle beam, method for imaging a signal charged particle beam, and charged particle beam device
The present disclosure provides a system for imaging a signal charged particle beam emanating from a sample by impingement of a primary charged particle beam. The system includes a detector arrangement having a first detection element for detecting a first signal charged particle sub-beam of the signal charged particle beam originating from a first spot on the sample and a second detection element for detecting a second signal charged particle sub-beam of the signal charged particle beam originating from a second spot on the sample, wherein the first detection element and the second detection element are separated from each other, and signal charged particle optics. The signal charged particle optics includes a coil configured to generate a magnetic field having a magnetic field component parallel to a longitudinal axis of the coil, wherein the magnetic field acts on the first signal charged particle sub-beam and the second signal charged particle sub-beam propagating along the longitudinal axis, and wherein an aspect ratio of the coil is at least 1, and a controller configured to adjust the magnetic field of the coil such that the first signal charged particle sub-beam is directed towards the first detection element and the second signal charged particle sub-beam is directed towards the second detection element.
US09666404B2 Charged particle source arrangement for a charged particle beam device, charged particle beam device for sample inspection, and method for providing a primary charged particle beam for sample inspection in a charged particle beam
The present disclosure provides a charged particle source arrangement for a charged particle beam device. The charged particle source arrangement includes: a first vacuum region and a second vacuum region; a charged particle source in the first vacuum region, wherein the charged particle source is configured to generate a primary charged particle beam; and a membrane configured to provide a gas barrier between the first vacuum region and the second vacuum region, and wherein the membrane is configured to let at least a portion of the primary charged particle beam pass through the membrane, wherein a first vacuum generation device is connectable to the first vacuum region and a second vacuum generation device is connectable to the second vacuum region.
US09666400B2 Field emission electron source and field emission device
A field emission electron source includes a linear carbon nanotube structure, an insulating layer and at least one conductive ring. The linear carbon nanotube structure has a first end and a second end. The insulating layer is located on outer surface of the linear carbon nanotube structure. The first conductive ring includes a first ring face 1301 and a second ring face, an end surface of the linear carbon nanotube structure, and the first ring face are coplanar.
US09666396B2 Electromagnetic inductive load control device
With a relay control device according to an embodiment, a regenerative current from a relay coil which is disposed in a relay flows through a coil energy absorption circuit, which is connected to the low side of the relay coil, toward the ground. A current detection resistor, which is a shunt resistor, is connected further toward the ground side of the coil energy absorption circuit than a coil surge absorption resistor, and the potential of the current detection resistor is compared to a reference potential, with a current detection circuit. Furthermore, on the basis of the result of the comparison with the current detection circuit, an off-duty period of the PWM control is terminated before the current which flows through the relay coil becomes less than or equal to a minimum drive current.
US09666395B2 Power semiconductor module
Provided is a power semiconductor module wherein stress generated at a soldering section of a relay terminal is relaxed. A power semiconductor module (1) is provided with a substrate (2), relay terminals (9, 10), external connecting terminals (13, 14) and a relay terminal holding member (6). The relay terminals (9, 10) are connected to the substrate (2) with a solder (4) therebetween. The external connecting terminals (13, 14) are bonded to the relay terminals (9, 10), respectively. The non-conductive relay terminal holding member (6) holds end portions of the relay terminals (9, 10) said end portions being on the side bonded to the solder (4).
US09666393B1 High voltage vertical break disconnect switch with blade position detector and rollover indicator
A blade position detector and rollover indicator is operatively attached to an elongated movable switch-blade assembly of a horizontally mounted high voltage vertical break disconnect switch. The blade position detector and rollover indicator is gravity responsive and attached in predetermined position to the elongated disconnect blade assembly that reacts when the proper angle of closure of the blade is obtained in an intermediated closed switch position and finally when the proper angle of blade rollover is obtained in a fully closed switch position to provide a visual indication of full closure of the disconnect switch.
US09666392B2 Electric switching device
An electric switching device contains a first contact piece and a second contact piece. The first contact piece can be driven by a first kinematic chain. The second contact piece can be driven by a second kinematic chain. The electric switching device contains a first switching point and a second switching point, which are electrically connected in series, the first contact piece being associated with the first switching point and the second contact piece with the second switching point.
US09666391B2 Retractable snap domes
A retractable snap dome in a keyboard, serving as a force resistor for a key in a conventional manner, includes an additional collapsed state wherein the key can be retracted by an electromechanical polymer (EMP) actuator to a persistent down position. In one embodiment, the EMP actuator is a bimorph EMP actuator that can be actuated to bring the key from down position to up position, ready for conventional keyboard operation, and vice versa. Such operations allow the keyboard to have a desirable decreased thickness relative to conventional keyboards. Thus, a keyboard of the present invention finds application in ultra-slim electronic devices. When provided in a notebook computer wherein the keyboard is folded against a video or graphic display, the keyboard keys may be placed in the retracted down position, thereby preventing the keys from pressing against the video or graphical display with a force that may damage the display.
US09666387B2 Waterproof button structure
A waterproof button structure includes a housing, a button cap, a plurality of waterproof elements and a fastening member. The housing has a first surface and a second surface, and is formed with a pair of through holes and a groove. The button cap is capable of correspondingly moving a long a normal direction of the first surface of the housing, and includes a pair of button shafts respectively inserted in the pair of through holes. The waterproof elements are disposed between the button shafts and the through holes. The fastening member is assembled to the button shafts and is disposed correspondingly to the second surface. The fastening member includes a bent portion. The bent portion is disposed in protrusion towards the groove and includes a protrusion. When the button cap is pressed, the protrusion is abutted against a press switch.
US09666386B2 Keyboard integrated pushbutton with multi illumination
A multi-illuminated pushbutton, including a substrate having a switch and a button cap. A lighting board may be affixed to the substrate, the lighting board having a first light source, a second light source, and a through channel disposed between the first light source and the second light source. The button cap can have a first window for transmission of light from the first light source, a second window for transmission of light from the second light source, and a button base disposed through the channel of the lighting board and in operable relation with the switch. The button base can be shaped to prevent substantially all light emitted from the first light source from transmission through the second window and prevents substantially all light emitted from the second light source from transmission through the first window.
US09666385B2 Housing with disassembly indicator
A housing containing its own record of any private and unwarranted disassembly includes a first shell, a second shell detachably connected with the second shell, a consumer disassembly indication structure. The consumer disassembly indication structure includes a circuit board, a plurality of switches, a computer chip, a plurality of conductive bodies, and a plurality of insulative bodies. The plurality of switches are fixed on the circuit board and each is electrically connected with the computer chip. The computer chip is configured to record electric connections between the conductive bodies and switches, the original electric connections being changed to other or no connections after any disassembly of the housing.
US09666383B2 Electrical contact device and low-voltage single-pole phase unit incorporating such an electrical contact device
The invention relates to an electric contact device that is part of an electric switching device able to allow or interrupt the passage of the electric current, comprising at least one moving support (33, 35) and a contact pad (60, 62) mounted on the moving support (33, 35), the moving support (33, 35) being able to move to position the contact pad (60, 62) in contact with a fixed contact surface (38, 40) connected to an electrical conductor, the contact pad (60, 62) comprising a contact surface (34, 36) designed to cooperate with said fixed contact surface (38, 40). The contact surface (34, 36) of the contact pad (60, 62) comprises a first spherical portion, comprising an actual zone of contact with said fixed contact surface (38, 40) in the position allowing the passage of current, and, in the continuation of the first spherical portion, a second convex portion with a variable shape going from spherical to cylindrical.The invention also relates to a low-voltage single-pole phase unit comprising such an electrical contact device.
US09666382B2 Silver and copper alloyed rivet contact
The present invention is a rivet contact including a head portion and a foot portion having a smaller width than the head portion, wherein the head portion contains a contact material layer having at least a top containing an Ag-based contact material; the rest of the head portion and the foot portion contain a base material containing Cu or a Cu alloy; and a barrier layer including an Ag alloy is provided at a junction interface between the contact material and the base material. Here, an Ag alloy obtained in such a manner that one or more base metal elements of Sn, In, Cu, Ni, Fe, Co, W, Mo, Zn, Cd, Te, and Bi are added to Ag by 0.03 to 20 mass % is preferably used as the Ag alloy constituting the barrier layer.
US09666379B2 Nickel supercapacitor engine starting module
This invention relates to a supercapacitor assembly having an asymmetric supercapacitor, a diode, and a switch in parallel with the diode. The asymmetric supercapacitor has at least one positive electrode, at least one negative electrode, and at least one separator impregnated with an electrolyte. The diode has an anode and a cathode, the cathode being electrically connected to the supercapacitor.
US09666376B2 Conductive paste and solid electrolytic capacitor including the same
A solid electrolytic capacitor that includes a valve action metal base, an insulating layer, a solid electrolyte layer, a carbon layer and an electrode layer sequentially formed in one of two parts of the valve action metal base. The electrode layer is formed from a conductive paste that includes at least a conductive filler, a thermosetting resin containing a phenoxy resin, and a curing agent.
US09666375B2 Voltage smoothing circuit, voltage conversion circuit, and method for controlling voltage to be applied to multilayer capacitor
A voltage smoothing circuit includes a first multilayer capacitor, a second multilayer capacitor, and a regulator including an input terminal electrically connected to the second multilayer capacitor and an output terminal electrically connected to the first multilayer capacitor. The regulator calculates a first voltage applied to the first multilayer capacitor based on a second voltage applied to the second multilayer capacitor from the input terminal such that a potential difference which is applied to the first multilayer capacitor decreases or increases when a potential difference which is applied to the second multilayer capacitor increases or decreases, and outputs the first voltage from the output terminal.
US09666374B2 Capacitor component
A capacitor component includes an element assembly, a first external electrode, and a second external electrode. The element assembly includes first and second internal electrode layers, a first connecting conductive layer extending along a fifth outer surface of the element assembly and connected to each of the first internal electrode layers, a first covering insulating layer covering the first connecting conductive layer, a second connecting conductive layer extending along a sixth outer surface of the element assembly and connected to each of the second internal electrode layers, and a second covering insulating layer covering the second connecting conductive layer. Only a portion of the first internal electrode layers are extended to the third outer surface and connected to the first external electrode, and only a portion of the internal electrode layers are extended to the fourth outer surface and connected to the second external electrode.
US09666371B2 Multilayer ceramic capacitor
A multilayer ceramic capacitor has a laminate comprising dielectric layers stacked alternately with internal electrode layers of different polarities, wherein: the dielectric layers contain ceramic grains whose primary component is BaTiO3; the ceramic grains contain at least one type of donor element (D) selected from the group that includes Nb, Mo, Ta, and W, and at least one type of acceptor element (A) selected from the group that includes Mg and Mn; and the ratio of the concentration of the donor element (D) and that of the acceptor element (A) (D/A) is greater than 1 at the center parts of the ceramic grains, while the D/A ratio is less than 1 at the outer edge parts of the ceramic grains (if A=0, then D/A=∞ and D=A=0 never occurs).
US09666370B2 Multilayer ceramic capacitor and method for producing the same
A dielectric ceramic that forms dielectric ceramic layers of a multilayer ceramic capacitor contains a Ba and Ti containing perovskite compound, Ca, R (R denotes a rare earth element, such as La), M (M denotes Mn or the like), and Si. The Ca content ranges from 0.5 to 2.5 molar parts, the R content ranges from 0.5 to 4 molar parts, the M content ranges from 0.5 to 2 molar parts, and the Si content ranges from 1 to 4 molar parts, based on 100 molar parts of Ti. In perovskite crystal grains, the Ca diffusion depth is 10% or less of the average grain size of the crystal grains, and the Ca concentration in a Ca diffusion region is 0.2 to 5 molar parts higher than the Ca concentration near the center of each of the crystal grains.
US09666369B2 Dielectric ceramic composition and multilayer ceramic capacitor containing the same
There are provided a dielectric ceramic composition and a multilayer ceramic capacitor containing the same. The dielectric ceramic composition according to the present disclosure may contain a main base material ingredient and a first accessory ingredient, wherein the first accessory ingredient contains samarium (Sm) and other rare earth (RE) elements, and a ratio (a/b) of a content (a) of samarium (Sm) to a content (b) of other rare earth elements in the first accessory ingredient satisfies 0.1≦a/b≦2.0.
US09666368B2 Film capacitor
A film capacitor having: a stack of at least one dielectric resin film formed of polypropylene and a plurality of vapor-deposited metal films which are superposed on each other such that the at least one dielectric film and the plurality of vapor-deposited metal films are alternately arranged; and two external electrodes formed on a pair of side surfaces of the stack; wherein cover films are formed of a polyolefin-based hot-melt resin on a pair of side surfaces of the stack other than the side surfaces on which the two external electrodes are formed, such that the cover films cover entireties of those side surfaces and are fusion-bonded to end faces of the at least one dielectric film exposed at those side surfaces.
US09666363B2 Surface-mount inductor and method for manufacturing the same
A surface-mount inductor having a coil formed by winding a wire and a molded body for accommodating the coil, wherein the coil includes: a pair of first rolls of wire of a rectangular section which are wound in a two-roll arrangement, both ends of the wire being positioned at their outermost turns; and a pair of second rolls wound in positions adjacent to and each on opposite sides of the first rolls to partially overlap the first rolls, whereby the ends of the wire are brought out from the outermost turns of the second rolls as lead ends, with winding axis of the coil being parallel with the molded body and the lead ends extending over the surface of the mounting face.
US09666361B2 Rare-earth bond magnet manufacturing method
A method for producing a bonded rare-earth magnet according to an embodiment of the present invention includes the steps of: providing a rapidly solidified rare-earth magnet alloy powder; providing a solution in which a resin that is in solid phase at an ordinary temperature is dissolved in an organic solvent; mulling the rapidly solidified rare-earth magnet alloy powder and the solution together and vaporizing the organic solvent, thereby making a bonded rare-earth magnet compound in which magnet powder particles that form the rapidly solidified rare-earth magnet alloy powder are coated with the resin; making a compressed compact by compressing the bonded rare-earth magnet compound under a pressure of 1000 MPa to 2500 MPa; and thermally treating the compressed compact. If the rapidly solidified rare-earth magnet alloy powder to be mulled is 100 mass %, the solution includes 0.4 mass % to 1.0 mass % of the resin and 1.2 mass % to 20 mass % of the organic solvent.
US09666354B2 Transformer
A transformer includes a primary winding unit, a secondary winding unit and a magnetic core. The primary winding unit includes a first input primary winding part and a first shielding winding part. The first input primary winding part is electrically connected to at least one switch component, and the first input primary winding part is electrically connected to the first shielding winding part. The secondary winding unit is inductively coupled to the primary winding unit, and the first shielding part is disposed between the first input primary winding part and the secondary winding part. Then, the primary winding unit and the secondary winding unit are assembled to the magnetic core.
US09666351B2 Device comprising a high voltage apparatus including a fluid and equipment for detecting one or more physical properties of the fluid
A device including a high voltage apparatus enclosing a fluid for providing cooling and/or electrical insulation of the apparatus, and a detector for one or more physical properties of the fluid positioned spaced apart from the housing. The device includes a pipe assembly for housing a fluid, whereby the pipe assembly is arranged between the detector equipment and the housing such that the fluid is extended without interruption in the pipe assembly. The fluid in the pipe assembly is in communication with the fluid in the housing, and the detector equipment is in direct communication with the fluid in the pipe assembly. The detector equipment is positioned below a top level of the housing and at a safe distance from the housing of the apparatus, which makes it possible to carry out inspection, testing, maintenance, and calibration of the detector equipment without taking the high voltage apparatus out of operation.
US09666349B2 Magnetically actuated shut-off valve
A magnetic actuator assembly is disclosed, and includes a core, wiring, and a gate assembly. The core is constructed of a magnetic material, and includes a first end and a second end. The wiring is wound around a portion of the core. A predetermined amount of electric current is applied to the wiring to induce a magnetic field within the core. The gate assembly is positioned between the first end and a second end of the core. The gate assembly comprises a first gate member traveling between the first end and a second end of the core based on a threshold force being applied to the gate assembly. The threshold force is created by the magnetic field.
US09666348B2 Vibration actuator
A vibration actuator includes: a movable element having a magnet that is supported to be rotatable around a shaft, a weight supported to be rotatable together with the magnet, and an elastic supporting member wherein a rotation of the magnet and the weight is supported elastically; a coil that is supplied with an AC current at a frequency that is equal to a resonant frequency of the movable element; and a magnetic pole member that causes the movable element to undergo reciprocating a rotational vibration around the shaft through applying rotational torques in different directions alternatingly to the magnet by changing magnetic poles through the AC current that is applied to the coil.
US09666344B2 Superconducting magnet system for head imaging
A superconducting magnet system for head imaging is disclosed which includes a cryocooler, a high-pressure helium container, a self-excitation heat pipe and a superconducting magnet. A second stage coldhead of the cryocooler is connected to the high-pressure helium container for converting the helium gas in the high-pressure helium container into liquid helium. The self-excitation heat pipe forms a closed cooling loop, and liquid helium in the high-pressure helium container flows circularly in the self-excitation heat pipe. The self-excitation heat pipe cools the superconducting magnet, wherein part of the liquid helium in the self-excitation heat pipe is converted into the helium gas due to the heat disturbance generated by the superconducting magnet, and the helium gas interacts with the liquid helium to generate liquid helium vibration.
US09666342B2 Magneto-dielectric polymer nanocomposites
In accordance with the present invention, novel superparamagnetic magneto-dielectric polymer nanocomposites are synthesized using a novel process. The tunability of the dielectric/magnetic properties demonstrated by this novel highly-viscous solvent-free polymer nanocomposite that is amenable to building 3D electromagnetic structures/devices by using processes such as 3D printing, compression molding or injection molding, when an external DC magnetic field is applied, exceeds what has been previously reported for magneto-dielectric polymer nanocomposite materials.
US09666341B2 Production method for anisotropic bonded magnet and production apparatus for same
A method for production of an anisotropic bonded magnet includes: aligning magnetic pole bodies which include an even number of permanent magnets arranged uniformly around an outer periphery of an annular cavity filled with magnetic raw material, aligning magnetic fields to cause rare-earth anisotropic magnet powder to be semi-radially aligned; compressively molding the semi-radially aligned magnet raw material to obtain an annular compact; discharging the compact from the annular cavity; demagnetizing causing the aligning magnetic pole bodies to relatively move only in circumferential direction with respect to the compact after the molding step thereby to apply demagnetization magnetic fields to the compact; The demagnetization magnetic fields are applied from the aligning magnetic pole bodies with opposite poles to those during the alignment step, and the demagnetization magnetic fields are in directions for cancelling the magnetization of the compact caused by the aligning magnetic fields.
US09666338B2 Method for producing a cable harness and cable harness
A cable harness is surrounded in certain regions by a sheath made of a casting compound. In order to ensure a defined delimitation of the casting compound, even if there is an insert part protruding from the sheath, the method for sealing a tool opening provides that a pressure element is pressed in the radial direction against the insert part. The insert part is clamped between the pressure element and a support element, and the support element remains in the cable harness as a consumable element. The insert part is particularly designed as a heat protection element. The cable harness is used particularly in a thermally stressed environment for a motor vehicle.
US09666336B2 Termination unit
A termination unit for a superconductor network. Including a primary system that includes a first superconductor cable. Also a first superconducting coil and a first auxiliary magnetizing coil, each coil wound around the first superconductor cable. Also a terminal including a first leg, the first leg including an aperture configured to receive the first superconductor cable. The first leg defining a clearance about the first superconductor cable at ambient temperature and arranged to firmly clamp onto the first superconductor cable at a cryogenic temperature. The termination unit including a cooling system arranged to enclose and cool the primary system to cryogenic temperatures.
US09666318B2 Storage, transportation and disposal system for used nuclear fuel assemblies
An integrated storage, transportation and disposal system for used fuel assemblies is provided. The system includes a plurality of sealed canisters and a cask sized to receive the sealed canisters in side by side relationship. The plurality of sealed canisters include an internal basket structure to receive a plurality of used fuel assemblies. The internal basket structure includes a plurality of radiation-absorbing panels and a plurality of hemispherical ribs generally perpendicular to the canister sidewall. The sealed canisters are received within the cask for storage and transportation and are removed from the cask for disposal at a designated repository. The system of the present invention allows the handling of sealed canisters separately or collectively, while allowing storage and transportation of high burnup fuel and damaged fuel to the designated repository.
US09666314B2 Device and method for repairing a damaged area in an underwater wall region of a container or tank
A device of repairing a damaged area in an underwater wall region of a container or tank, in particular in the wall region of a tank of a nuclear reactor installation. The device has a guide system that can be mounted along a side wall, at a distance therefrom, and can be secured thereto. At least one first carriage is fitted onto the track of the guide system and movable in a longitudinal direction of the guide system. On the carriage there is displaceably mounted a receptacle for a repair overlay, which can be applied with an adhesive surface to the wall region containing the damaged area. At least one suction mount that is connected to a suction line is disposed on the first carriage and can be suctioned to the side wall.
US09666310B1 Accident-tolerant oxide fuel and cladding
Systems and methods for accident tolerant oxide fuel. One or more disks can be placed between fuel pellets comprising UO2, wherein such disks possess a higher thermal conductivity material than that of the UO2 to provide enhanced heat rejection thereof. Additionally, a cladding coating comprising zircaloy coated with a material that provides stability and high melting capability can be provided. The pellets can be configured as annular pellets having an annulus filled with the higher thermal conductivity material. The material coating the zircaloy can be, for example, Zr5Si4 or another silicide such as, for example, a Zr-Silicide that limits corrosion. The aforementioned higher thermal conductivity material can be, for example, Si, ZrxSiy, Zr, or Al2O3.
US09666309B2 Method and device for repairing memory
Provided are a method and device for repairing memory. The method includes: determining spare lines with priority to be used for repair, and searching for a repair solution by using the spare line with priority and failure counters for lines without priority.
US09666307B1 Apparatuses and methods for flexible fuse transmission
Apparatuses and methods for transmitting fuse data from fuse arrays to latches are described. An example apparatus includes: a plurality of fuse arrays, each fuse array of the plurality of fuse arrays being configured to store input data; a fuse circuit that receives the input data and provides the input data on a bus; and a plurality of redundancy latch circuits coupled to the bus, including a plurality of pointers and a plurality of latches associated with the plurality of corresponding pointers that load data on the bus. The fuse circuit may control loading of the input data by controlling a location of a pointer among the plurality of corresponding pointers responsive to the input data.
US09666303B2 Leveraging chip variability
Embodiments are described that leverage variability of a chip. Different areas of a chip vary in terms of reliability under a same operating condition. The variability may be captured by measuring errors over different areas of the chip. A physical factor that affects or controls the likelihood of an error on the chip can be varied. For example, the voltage supplied to a chip may be provided at different levels. At each level of the physical factor, the chip is tested for errors within the regions. Some indication of the error statistics for the regions is stored and then used to adjust power used by the chip, to adjust reliability behavior of the chip, to allow applications to control how the chip is used, to compute a signature uniquely identifying the chip, etc.
US09666301B2 Scannable memories with robust clocking methodology to prevent inadvertent reads or writes
An example scannable register file includes a plurality of memory cells and, a shift phase of a scan test shifts data bits from a scan input through the plurality of memory cells to a scan output. The shifting can be performed by, on each clock cycle, reading one of the plurality of memory cells to supply the scan out and writing one of the plurality of memory cells with the data bit on a scan input. To perform sequential reads and writes on each clock cycle, the scannable register can generate a write clock that, during the shift phase, is inverted from the clock used for functional operation. The write clock is generated without glitches so that unintended writes do not occur. Scannable register files can be integrated with scan-based testing (e.g., using automatic test pattern generation) of other modules in an integrated circuit.
US09666297B1 Memory device, memory system including the same and operation method of the memory system
A memory system includes: a first memory device including a first internal voltage generation circuit; and a second memory device including a second internal voltage generation circuit, wherein the first memory device and the second memory device receive an identical chip enable signal, and when the chip enable signal is disabled, the first internal voltage generation circuit and the second internal voltage generation circuit are controlled in a standby mode, and when the chip enable signal is enabled, the first internal voltage generation circuit and the second internal voltage generation circuit are independently controlled to have one mode between a weak active mode and a strong active mode.
US09666296B1 Semiconductor memory device
A semiconductor memory device includes a memory cell array having memory strings that include memory cells and first and second selection transistors. During a read operation, a controller applies a first voltage higher than ground to a source line, and a second voltage to a first and second selection gate lines that are connected to a selected memory string. The second voltage is also applied to the first selection gate lines connected to non-selected memory strings during a first period of the read operation. A third voltage higher than ground and lower than the second voltage is applied to the first selection gate lines connected to non-selected memory strings during a second period of the read operation subsequent to the first period.
US09666294B2 Method and apparatus for reading data stored in flash memory by referring to binary digit distribution characteristics of bit sequences read from flash memory
A method for reading data stored in a flash memory includes at least the following steps: controlling the flash memory to perform a plurality of read operations upon a plurality of memory cells included in the flash memory; obtaining a plurality of bit sequences read from the memory cells, respectively, wherein the read operations read bits of a predetermined bit order from the memory cells by utilizing different control gate voltage settings; and determining readout information of the memory cells according to binary digit distribution characteristics of the bit sequences.
US09666292B2 Method of determining default read voltage of non-volatile memory device and method of reading data of non-volatile memory device
A method of determining a default read voltage of a non-volatile memory device which includes a plurality of first memory cells, each of which stores a plurality of data bits as one of a plurality of threshold voltages corresponding to a plurality of logic states, includes programming a first data to the first memory cells so that the logic states of the first memory cells are balanced or equally used. The method includes applying a first default read voltage included in default read voltages to word lines coupled to the first memory cells, and measuring a first ratio of first on-cells, each of which has a threshold voltage smaller than or equal to the first default read voltage, among the first memory cells, and modifying the first default read voltage based on the first ratio and a first reference value corresponding to the first default read voltage.
US09666286B2 Self-timed SLC NAND pipeline and concurrent program without verification
A hierarchical-GBL/LBL NAND array with a plurality of LG and MG groups in either orthogonal BL/CSL scheme or parallel BL/SL scheme including a plurality of block-decoders with a shared self-timed delay control circuit and a plurality of fully-shielding dynamic CACHE registers made of 2 local broken metal lines within the array and DRAM-like SA is provided. Each DCR capacitor is flexibly expandable by connecting multiple CLGs made by the local broken metal lines of the LGs to form a CMG of a larger MG. Based on the NAND array, multiple randomly selected WLs in multiple random blocks within multiple random LGs within one MG can be selected on basis of one WL per block per LG for performing an ABL pipeline and concurrent SLC program without verification, and on basis of one WL per block per MG for performing an ABL-like or HBL pipeline and concurrent SLC read.
US09666285B2 Method and system for asynchronous die operations in a non-volatile memory
A mass storage memory system and method of operation are disclosed. The memory system includes an interface adapted to receive data from a host system, a plurality of memory die and a controller, where the controller is configured to read or write data synchronously across a plurality of die connected to different channels based on a first command, and to read or write data asynchronously and independently in different die in the same channel based on a second command. The controller may program data in a maximum unit of programming for a single memory die. The controller may be a plurality of controllers each configured to select which die of an exclusive subset of die to write data based on characteristics of the die in the subset. The plurality of die may be multi-layer, and multi-partition per layer, flash memory die.
US09666283B2 Nonvolatile memory devices and driving methods thereof
Nonvolatile memory devices including memory cell arrays with a plurality of cell strings connected between a substrate and a plurality of bit lines and selected by selection lines, and a gating circuit configured to drive the selection lines in at least two directions.
US09666279B2 Non-volatile memory for high rewrite cycles application
A non-volatile memory has an array of non-volatile memory cells. Each of the non-volatile memory cells includes a coupling device formed on a first well, a read device, a floating gate device formed on a second well and coupled to the coupling device, a program device formed on the second well, and an erase device formed on a third well and coupled to the first floating gate device. The read device, the program device, and the erase device are formed on separate wells so as to separate the cycling counts of a read operation, a program operation and an erase operation of the non-volatile memory cell.
US09666271B2 Semiconductor device including a transistor with an oxide semiconductor film channel coupled to a capacitor
To provide a semiconductor device which can write and read a desired potential. The semiconductor device includes a first transistor (Tr), a second Tr, and a capacitor. In the semiconductor device, operation of writing data is performed by a first step and a second step. In the first step, a low voltage is applied to a bit line and a first wiring to turn on the first Tr and the second Tr. In the second step, a first voltage is applied to the first wiring, and application of the low voltage to the bit line is stopped. Operation of reading the data is performed by a third step and a fourth step. In the third step, a high voltage is applied to the first wiring. In the fourth step, application of the high voltage to the first wiring is stopped, and a low voltage is applied to a capacitor line.
US09666266B1 Power control over memory cell arrays
In disclosed circuit arrangements, memory cell arrays are addressed by a first portion of an input address, and memory cells within each memory cell array are addressed by a second portion of the input address. A first first-in-first-out (FIFO) buffer is coupled to the memory cell arrays and delays the second portion of each input address to the memory cell arrays for a sleep period. Control circuits respectively coupled to the memory cell arrays include second FIFO buffers and decode the first portion of each input address and generate corresponding states of enable signals. The control circuits store the corresponding states of the enable signals in the second FIFO buffers concurrently with input of the second portion of each input address to the first FIFO buffer. The second FIFO buffers delay output of the corresponding states of the enable signals to the memory cell arrays for the sleep period. Each control circuit further switches a corresponding memory cell array into a sleep mode in response to all states of the enable signal in the corresponding second FIFO buffer being in a non-enabled state.
US09666264B1 Apparatus and method for memory calibration averaging
A method and apparatus for memory calibration averaging is disclosed. In one embodiment, a memory subsystem includes a memory and a memory controller. The memory controller includes a calibration control circuit that periodically performs calibrations of the memory subsystem. Calibration may be performed for a delay applied to a data strobe used to synchronized transfers of data between the memory controller and the memory, and a reference voltage used to distinguish between a logic 0 and a logic 1 during memory reads. Following the performance of a calibration, the values of the delay and the reference voltage may be set based on an average of a most recent number of calibrations.
US09666260B2 Refresh verification circuit, semiconductor apparatus and semiconductor system
A refresh verification circuit may include a filtering circuit configured to receive a refresh pulse and to generate a filtering pulse in response to a duration of the enable period of the refresh pulse.
US09666259B1 Dual mode sensing scheme
A method of sensing a data value stored at a memory cell according to a dual mode sensing scheme includes determining, at a sensing circuit, whether a resistance of a magnetic tunnel junction (MTJ) element is within a first range of resistance values, within a second range of resistance values, or within a third range of resistance values. The MTJ element is included in the memory cell. The method also includes determining the data value stored at the memory cell according to a first mode of operation if the resistance of the MTJ element is within the first range of resistance values or within the third range of resistance values. The method further includes determining the data value stored at the memory cell according to a second mode of operation if the resistance of the MTJ element is within the second range of resistance values.
US09666244B2 Dividing a storage procedure
Apparatuses, systems, methods, and computer program products are disclosed for storage operations for a non-volatile medium. A control module may be configured to divide a storage procedure into multiple portions. An execution module may be configured to execute multiple portions of a storage procedure independently. A storage request module may be configured to satisfy a storage request for one or more storage elements of a storage procedure between at least a pair of portions of a storage procedure.
US09666243B2 Method and circuit for controlling programming current in a non-volatile memory array
A memory device having: a cross-point memory array; a current supply circuit adapted to supply a programming current to a selected row line of the array during a programming operation to change the resistive state of a selected memory cell coupled between the selected row line and a selected column line of the array; a leakage current detection circuit coupled to the column lines except the selected column line and adapted to detect leakage currents during the programming operation; and a current limit generation circuit adapted to generate a current limit based on the sum of the leakage currents and on a reference current, and to supply the current limit to the current supply circuit to limit the programming current.
US09666240B2 Semiconductor device with decreased overlapping area between redistribution lines and signal lines
A semiconductor device includes, a semiconductor chip having a first surface over which bonding pads are positioned, a second surface which faces away from the first surface, and a plurality of signal lines formed over the first surface, extending in a first direction; a plurality of redistribution lines formed over the first surface, having one set of ends electrically coupled to the bonding pads of the semiconductor chip, and extending in a direction oblique to the first direction; and a plurality of redistribution pads disposed over the first surface, and electrically coupled with an other set of ends of the redistribution lines which face away from the one set of ends.
US09666235B2 Particulate filter
Certain exemplary aspects of the present disclosure are directed towards an apparatus including a base deck forming a sealed cavity. A filter coupled to a surface of the base deck within the cavity filters particulate from a flow of gas in the cavity. The recirculation filter including a protrusion extending over a surface of a storage medium within the cavity that diverts gas from a surface of the storage medium toward the filter. A bypass channel, defined by a portion of the cavity and a portion of the filter, in conjunction with the protrusion forms a pressure differential that draws a first portion of the diverted gas through the filter by bypassing the filter with a second portion of the diverted gas.
US09666230B2 Package and container assembly and method of manufacturing same
A package assembly including a first layer having a bottom surface and a top surface, and at least two panels coupled to the top surface of the first layer such that a first panel is disposed along a right edge of the first layer and the second panel is disposed along a left edge of the first layer, the first panel being pivotally engaged to the second panel along an axis, the at least two panels having formed therein a recess.
US09666228B2 Shingled magnetic recording data store
Implementations disclosed herein provide a method comprising storing data in a two level key-value data store in an SMR storage device, wherein a first level of the data store comprises a journal of incoming host operations and a second level of the data store comprises a plurality of ordered data stores, ordered based on a predetermined ordering criterion.
US09666225B2 Efficient recovery of the codeword interleave address
In one embodiment, a system includes a data processing unit configured to read encoded data from a magnetic tape medium. The data processing unit is also configured to decode a plurality of codeword interleaves (CWIs) from the encoded data, each CWI being a row in a sub data set logically organized into a two-dimensional array. The array includes a predetermined number of rows and columns of predetermined lengths. The data processing unit is also configured to determine an address for a first-written CWI without successfully decoding a corresponding codeword interleave designation (CWID) from the encoded data, each CWID specifying an address for a corresponding CWI. Also, each CWID is calculated as a function of a logical track number and a CWI set number.
US09666223B2 Enhanced tape library cataloging
A tape-based data storage system, according to one embodiment, includes: a tape library having: a plurality cells, each of the cells being configured to store one or more tape cartridges therein, and at least an antenna of a near field communication reader positioned at each of the cells. Moreover, each of the antennas are positioned relative the associated cell to be in direct communication with a near field communication tag coupled to a tape cartridge stored in the associated cell. Other systems, methods, and computer program products are described in additional embodiments.
US09666221B2 Apparatus including a perpendicular magnetic recording layer having a convex magnetic anisotropy profile
An apparatus may include a first magnetic layer, a first exchange break layer formed on the first magnetic layer, a second magnetic layer formed on the first exchange break layer, a second exchange break layer formed on the second magnetic layer, and a third magnetic layer formed on the second exchange break layer. The first magnetic layer has a first magnetic anisotropy energy, Hk1, the second magnetic layer has a second magnetic anisotropy energy, Hk2, and the third magnetic layer has a third magnetic anisotropy energy, Hk3. In some embodiments, Hk1−Hk2 is less than Hk2−Hk3. In some embodiments, the apparatus may be a perpendicular magnetic recording medium.
US09666220B2 Devices including a near field transducer and at least one associated adhesion layer
Devices that include a near field transducer (NFT), the NFT having a disc and a peg, and the peg having five surfaces thereof; and at least one adhesion layer positioned on at least one of the five surfaces of the peg, the adhesion layer including one or more of the following: yttrium (Y), tin (Sn), iron (Fe), copper (Cu), carbon (C), holmium (Ho), gallium (Ga), silver (Ag), ytterbium (Yb), chromium (Cr), tantalum (Ta), iridium (Ir), zirconium (Zr), yttrium (Y), scandium (Sc), cobalt (Co), silicon (Si), nickel (Ni), molybdenum (Mo), niobium (Nb), palladium (Pd), titanium (Ti), rhenium (Re), osmium (Os), platinum (Pt), aluminum (Al), ruthenium (Ru), rhodium (Rh), vanadium (V), germanium (Ge), tin (Sn), magnesium (Mg), iron (Fe), copper (Cu), tungsten (W), hafnium (Hf), carbon (C), boron (B), holmium (Ho), antimony (Sb), gallium (Ga), manganese (Mn), silver (Ag), indium (In), bismuth (Bi), zinc (Zn), ytterbium (Yb), and combinations thereof.
US09666218B1 Thermal assisted magnetic head provided with light detector that detects reflected light
A thermal assisted magnetic recording head has a magnetic head slider and a light source unit that is fixed to the magnetic head slider. A first surface of the light source unit and a second surface of the magnetic head slider face each other via a gap. The light source unit includes a light source that emits laser light from an emission part that is positioned on the first surface and a photodetector that detects the laser light. The magnetic head slider includes a waveguide through which the laser light that is incident on an incident part positioned on the second surface propagates, near-field light generation means for generating near-field light on an air bearing surface, the near-field light being generated from the laser light that propagates through the waveguide, and a recording magnetic pole that is provided adjacent to the near-field light generation means and that has an end part positioned on the air bearing surface. A medium for propagating the laser light is continuously formed along a path that includes the gap and that extends from the emission part to a light receiving surface of the photodetector.
US09666214B1 Free layer magnetic reader that may have a reduced shield-to-shield spacing
A magnetic read apparatus includes a read sensor, a shield structure and a side magnetic bias structure. The read sensor includes a free layer having a side and a nonmagnetic spacer layer. The shield structure includes a shield pinning structure and a shield reference structure. The nonmagnetic spacer layer is between the shield reference structure and the free layer. The shield reference structure is between the shield pinning structure and the nonmagnetic spacer layer. The shield pinning structure includes a pinned magnetic moment in a first direction. The shield reference structure includes a shield reference structure magnetic moment weakly coupled with the pinned magnetic moment. The side magnetic bias structure is adjacent to the side of the free layer.
US09666213B1 Updating a partially overlapped track via two or more readers
In response to a command to update a target track, two tracks or more are concurrently read. The two tracks or more tracks include a top track that partially overlaps the target track. Data of the top track is stored in a memory, and the update data is written over at least part of the target track. The stored data is written on the recording medium over the top track or at a different location.
US09666211B2 Information processing apparatus, information processing method, display control apparatus, and display control method
There is provided an information processing apparatus including an information acquiring unit that acquires information to identify an editing point of content including a voice, on the basis of language analysis of the content, and an information output unit that outputs the acquired information.
US09666208B1 Hybrid audio representations for editing audio content
The present disclosure includes a hybrid waveform system that displays a hybrid waveform to a user. In general, the hybrid waveform system provides a hybrid waveform to a user that uses converted readable text and waveforms to represent an audio segment. By providing a user with a hybrid waveform, the hybrid waveform system offers users with a number of benefits, such as providing an audio display that enables a user to quickly ascertain context information and audio information typically missing from audio transcriptions.
US09666200B2 Methods and systems for efficient recovery of high frequency audio content
The present document relates to the technical field of audio coding, decoding and processing. It specifically relates to methods of recovering high frequency content of an audio signal from low frequency content of the same audio signal in an efficient manner. A method for determining a first banded tonality value (311, 312) for a first frequency subband (205) of an audio signal is described. The first banded tonality value (311, 312) is used for approximating a high frequency component of the audio signal based on a low frequency component of the audio signal. The method comprises determining a set of transform coefficients in a corresponding set of frequency bins based on a block of samples of the audio signal; determining a set of bin tonality values (341) for the set of frequency bins using the set of transform coefficients, respectively; and combining a first subset of two or more of the set of bin tonality values (341) for two or more corresponding adjacent frequency bins of the set of frequency bins lying within the first frequency subband, thereby yielding the first banded tonality value (311, 312) for the first frequency subband.
US09666199B2 Automatic conversion of speech into song, rap, or other audible expression having target meter or rhythm
Captured vocals may be automatically transformed using advanced digital signal processing techniques that provide captivating applications, and even purpose-built devices, in which mere novice user-musicians may generate, audibly render and share musical performances. In some cases, the automated transformations allow spoken vocals to be segmented, arranged, temporally aligned with a target rhythm, meter or accompanying backing tracks and pitch corrected in accord with a score or note sequence. Speech-to-song music applications are one such example. In some cases, spoken vocals may be transformed in accord with musical genres such as rap using automated segmentation and temporal alignment techniques, often without pitch correction. Such applications, which may employ different signal processing and different automated transformations, may nonetheless be understood as speech-to-rap variations on the theme.
US09666198B2 Reconstruction of audio scenes from a downmix
Audio objects are associated with positional metadata. A received downmix signal comprises downmix channels that are linear combinations of one or more audio objects and are associated with respective positional locators. In a first aspect, the downmix signal, the positional metadata and frequency-dependent object gains are received. An audio object is reconstructed by applying the object gain to an upmix of the downmix signal in accordance with coefficients based on the positional metadata and the positional locators. In a second aspect, audio objects have been encoded together with at least one bed channel positioned at a positional locator of a corresponding downmix channel. The decoding system receives the downmix signal and the positional metadata of the audio objects. A bed channel is reconstructed by suppressing the content representing audio objects from the corresponding downmix channel on the basis of the positional locator of the corresponding downmix channel.
US09666195B2 Method and apparatus for decoding stereo loudspeaker signals from a higher-order ambisonics audio signal
Decoding of Ambisonics representations for a stereo loudspeaker setup is known for first-order Ambisonics audio signals. But such first-order Ambisonics approaches have either high negative side lobes or poor localization in the frontal region. The invention deals with the processing for stereo decoders for higher-order Ambisonics HOA. The desired panning functions can be derived from a panning law for placement of virtual sources between the loudspeakers. For each loudspeaker a desired panning function for all possible input directions at sampling points is defined. The panning functions are approximated by circular harmonic functions, and with increasing Ambisonics order the desired panning functions are matched with decreasing error. For the frontal region between the loudspeakers, a panning law like the tangent law or vector base amplitude panning (VBAP) are used. For the rear directions panning functions with a slight attenuation of sounds from these directions are defined.
US09666194B2 Recording and entertainment system
A recording and entertainment system is provided. A mobile kiosk is capable or being outfitted with one or more cameras for capturing visual content, an audio recording system, a display device, a computer to control recording, storing, processing, and playing the captured visual and audio content. The captured video and audio are then processed and edited to produce remembrance products in various forms, including videos. Karaoke function is provided by a means for recognizing songs being performed and displaying lyrics on the display. Camera tilt, noise suppression, noise cancelation, voice control of the computer, a battery pack to free kiosk for movement, means for internet communication of the visual and audio content, means for confirming that objects of the visual content capture are within the field of view, robotic control of the kiosk, and interactive gaming means are additional features that can be utilized with the system.
US09666191B1 Laser-based system and optical microphone having increased bandwidth
Laser-based system and optical microphone having increased bandwidth. The system includes a laser microphone to transmit a laser beam towards a human speaker; to receive an optical feedback signal reflected back from the human speaker; and to perform self-mixing interferometry. An optical feedback signal bandwidth enhancer improves the bandwidth of the optical feedback signal, to improve the quality of remote speech detection that is based on the optical feedback signal. The bandwidth enhancement utilizes takes into account one or more of: the identity of the face-region hit by the laser beam; the skin color or shade; obstruction of the skin by hair or by accessories; ability to allocate increased processing resources for processing of the optical feedback signal; ability to modify modulation frequency of the optical feedback signal; Signal to Noise Ratio (SNR) estimation; bandwidth estimation; acoustic-optical transmission channel estimation; or other suitable parameters.
US09666190B2 Speech recognition using loosely coupled components
An automatic speech recognition system includes an audio capture component, a speech recognition processing component, and a result processing component which are distributed among two or more logical devices and/or two or more physical devices. In particular, the audio capture component may be located on a different logical device and/or physical device from the result processing component. For example, the audio capture component may be on a computer connected to a microphone into which a user speaks, while the result processing component may be on a terminal server which receives speech recognition results from a speech recognition processing server.
US09666187B1 Model for enabling service providers to address voice-activated commands
Methods and systems are described herein related to enabling service providers to address voice-activated commands. An example method may involve: receiving a first utterance on a computing device, where the first utterance includes a first command; selecting a service action corresponding to the first command; determining a selected service provider for the selected service action, where the selected service provider is selected from a plurality of service providers; and sending a service fulfillment request to the selected service provider to execute the selected service action.
US09666186B2 Voice identification method and apparatus
Embodiments of the present invention provide a voice identification method, which includes: obtaining voice data; obtaining a confidence value according to the voice data; obtaining a noise scenario according to the voice data; obtaining a confidence threshold corresponding to the noise scenario; and if the confidence value is greater than or equal to the confidence threshold, processing the voice data. An apparatus is also provided. The method and apparatus that flexibly adjust the confidence threshold according to the noise scenario greatly improve a voice identification rate under a noise environment.
US09666185B2 Automatic data-driven dialog discovery system
Methods and systems for providing help prompts to a user of an automated dialog system are presented. In some embodiments, a computing device may receive a help request from the user of an automated dialog system. The help request may comprise a user request for information about one or more capabilities of the automated dialog system. The computing device may identify information expected to be input by the user to request that the automated dialog system perform its one or more capabilities. A natural language help prompt may be generated to provide guidance to the user to provide the identified information expected to be input.
US09666184B2 Method and apparatus for training language model and recognizing speech
A method and apparatus for training a neural network language model, and a method and apparatus for recognizing speech data based on a trained language model are provided. The method of training a language model involves converting, using a processor, training data into error-containing training data, and training a neural network language model using the error-containing training data.
US09666183B2 Deep neural net based filter prediction for audio event classification and extraction
Disclosed is a feature extraction and classification methodology wherein audio data is gathered in a target environment under varying conditions. From this collected data, corresponding features are extracted, labeled with appropriate filters (e.g., audio event descriptions), and used for training deep neural networks (DNNs) to extract underlying target audio events from unlabeled training data. Once trained, these DNNs are used to predict underlying events in noisy audio to extract therefrom features that enable the separation of the underlying audio events from the noisy components thereof.
US09666181B2 Systems and methods for tuning automatic speech recognition systems
A tuning system for tuning a speech recognition system includes a transmitter for sending a user response to a speech recognition system. The user response is based at least in part on a test stimulus that may be generated by the control system. A receiver receives a recognized response from the speech recognition system; this recognized response is based at least in part on the associated user response. An adjustment module adjusts at least one parameter of the speech recognition system based at least in part on at least one of the test stimulus, the associated user response, and the recognized response.
US09666180B2 Synthesized audio message over communication links
A communication device establishes an audio connection with a far-end user via a communication network. The communication device receives text input from a near-end user, and converts the text input into speech signals. The speech signals are transmitted to the far-end user using the established audio connection while muting audio input to its microphone. Other embodiments are also described and claimed.
US09666179B2 Speech synthesis apparatus and method utilizing acquisition of at least two speech unit waveforms acquired from a continuous memory region by one access
A waveform memory that stores a plurality of speech unit waveforms corresponding to respective speech units, wherein an address order of the speech unit waveforms is determined by a sort order of speech units included in a speech unit sequence corresponding to a phoneme sequence of training data, and the speech units included in the speech unit sequence are selected so as to synthesize a speech of the phone sequence.
US09666178B2 Device for aiding communication in the aeronautical domain
A device for aiding communication in the aeronautical domain, wherein the device includes a transceiver and data processor assembly that records audio messages corresponding to all the incoming and outgoing audio communications, transcribes the messages, in real time, into textual messages, displays the textual messages, and enables an audio play back of the audio messages.
US09666177B2 Audio system, method for generating an audio signal, computer program and audio signal
The invention relates to an audio system for generating an audio signal. More specifically the invention relates to an audio system, especially an audio alarm system, for generating an audio signal comprising means for generating a component of the audio signal at a base frequency and means for generating further components of the audio signal at other frequencies than the base frequency, whereby the base and the other frequencies are separated from each other by separating frequency bands in order to enhance the loudness of the audio signal. The invention furthermore relates to a method for generating an audio signal, a computer program and an audio signal.
US09666176B2 Systems and methods for adaptive noise cancellation by adaptively shaping internal white noise to train a secondary path
A processing circuit may include: (i) an adaptive filter having a response that generates an anti-noise signal from a reference microphone signal, wherein the response is shaped in conformity with the reference microphone signal and a playback corrected error, and wherein the playback corrected error is based on a difference between an error microphone signal and a secondary path estimate; (ii) a secondary path estimate filter configured to model an electro-acoustic path of a source audio signal and having a response that generates a secondary path estimate from the source audio signal; (iii) a secondary coefficient control block that shapes the response of the secondary path estimate filter in conformity with the source audio signal and the playback corrected error by adapting the response of the secondary path estimate filter to minimize the playback corrected error; and (iv) a noise injection portion for injecting a noise signal into the source audio signal, wherein the noise signal is shaped based on the playback corrected error.
US09666172B1 Acoustic drum shell including inserts
A metal shell and metal inserts of an acoustic drum. In some examples, an acoustic drum having a metal shell can include one or more metal inserts configured to control the tone of the drum. In some configurations, the one or more inserts can form a portion of a bearing edge at one or more openings of the shell. Moreover, in some examples the inserts can be fitted to be in contact with the shell. The shape and configuration of the metal inserts can therefore control and refine the tone of the drum, allowing, for example, a drum with a metal shell to have a tone resembling that of a wooden drum with the sensitivity and power of a metal drum.
US09666171B2 Drum mounting and tuning system providing unhindered and isolated resonance
Some embodiments provide a drum structural framework comprising a top shell mount, bottom shell mount, rod holders, and tension rods. The top shell mount and bottom shell mount are mounted to either ending edge of a drum shell disposed between the two mounts. A first set of the rod holders are coupled to the top shell mount and an aligned second set of the rod holders are coupled to the bottom shell mount. The tension rods link the two sets of rod holders without hindering resonance of the drum shell. Tuning assemblies on the rod holders adjust the distance separating the top shell mount from the bottom shell mount, thereby controlling the force imposed on the drum shell. Each rod holder includes one or more dampeners that isolate energy passing from the drumhead to the shell from also reverberating throughout the structural framework of the tension rods and rod holders.
US09666170B2 Drum apparatus and method of use
A drum apparatus comprising at least a front wall, a snare bar rotatably installed substantially parallel to and offset from the front wall inner surface and having at least one snare wire extending substantially vertically therefrom so as to be adjacent to and selectively in contact with the front wall inner surface, and a rocker assembly comprising a lever mechanically coupled to the snare bar at a first end of the lever and further comprising an actuator leg pivotally coupled to and extending downwardly from an opposite second end of the lever pivotally installed within the drum apparatus on a support post coupled to the lever intermediate the first and second ends thereof, whereby the drum apparatus is shifted between first and second operational modes by selectively positioning the drum apparatus either substantially flat or tipped back so as to raise or lower the actuator leg.
US09666169B2 Fingernail pick apparatus and method
A fingernail pick having improved fingernail attachment systems and playing surfaces that are shaped for improved sound quality and ease of playing of stringed instruments.
US09666168B2 Board for stringed instrument, method of manufacturing board for stringed instrument, and stringed instrument
A board for a stringed instrument which forms a front plate or a back plate of a stringed instrument, includes: a laminated plate that is obtained by laminating a plurality of veneers having a uniform thickness by an adhesive, at least one of the veneers having a different planar shape than the other veneers, in which the laminated plate is curved to be convex toward one surface side and has a thin portion and a thick portion.
US09666164B2 Image processing apparatus and image processing method
An image processing apparatus includes: a pattern identification unit configured to perform pattern identification for first image data; a first data conversion unit configured to perform first data conversion for the first image data, after a pattern of the first image data is identified, to generate second image data; a second data conversion unit configured to perform second data conversion for the second image data to generate third image data; and a process selection unit configured to determine whether or not to perform at least one of the pattern identification, the first data conversion, or the second data conversion according to a measured value that is input from an outside or an on/off state of a call mode.
US09666161B2 Method and system for replacing theme of a mobile terminal on the basis of a user's clothes color
A method and a system are provided for replacing the theme of a mobile terminal on the basis of a user's clothes color, including: setting an RGB value interval of clothes through analyzing the RGB values of all pixels of the clothes location in the obtained image and calculating the clothes RGB average, analyzing the RGB values of all pixels of every theme on a mobile terminal, calculating the theme RGB value average; when the theme RGB average is within the clothes RGB average interval, and replacing the theme of the mobile terminal by the theme corresponding to the theme RGB average. Thus, the mobile terminal becomes more interesting.
US09666158B2 Apparatus and method of controlling screens in a device
An apparatus and a method of controlling screens in a device are provided. The apparatus includes a display configured to include a first screen and a second screen overlapped over the first screen, and a controller configured to control display of partial information of the first screen hidden by the second screen to be viewable by changing an attribute of the second screen, upon detecting a gesture on the second screen while information is being displayed separately on the first and second screens.
US09666157B2 Application to measure display size
A method includes initializing a software program configured to determine a display height and a display width on a display, receiving input dimensions of a standard sized object into the software program, determining the display height and the display width based on the input dimensions of a standard sized object, and outputting the display height and the display width from the software program.
US09666156B2 Two-stage DAC architecture for LCD source driver utilizing one-bit serial charge redistribution DAC
A two-stage digital-to-analog converter for outputting an analog voltage in response to a M-bit digital input code includes a one-bit serial charge redistribution digital-to-analog converter having a high reference voltage input node for receiving a high reference voltage and a low reference voltage input node for receiving a low reference voltage. A voltage selector sets the high reference voltage and low reference voltage to selected levels depending on at least a portion of the M-bit digital input code.
US09666155B2 Data lines driver of display apparatus includng the same and method of driving display panel using the same
A data lines driver includes a digital to analog converter configured to generate a normal data voltage based on a data signal, a buffer configured to buffer the normal data voltage and a power-on/reset part configured to generate an initial data voltage varying according to time and to selectively output either the initial data voltage or the normal data voltage.
US09666152B2 Shift register unit, gate driving circuit and display device
Provided are a shift register unit, a gate driving circuit and a display device, wherein the shift register unit includes: a pull-up module connected to a clock signal line and a signal output terminal; at least two pull-down modules both connected to a low level signal line and the signal output terminal; a control module connected to the pull-up module and the pull-down modules, for controlling the pull-up module to be turned on, so that the pull-up module outputs a high level signal input from the clock signal line to the signal output terminal, and for controlling the at least two pull-down modules to be turned on alternatively, so that the at least two pull-down modules output a low level signal input from the low level signal line to the signal output terminal, and for controlling one of the at least two pull-down modules to be turned on while controlling the other pull-down modules of the at least two pull-down modules to be discharged. The shift register unit can reduce over-bias of a gate of a pull-down TFT effectively, thus improving stability of the shift register unit.
US09666145B2 Method and apparatus for controlling brightness compensation for pixel units of display device
The present disclosure provides a method for controlling brightness compensation for pixel units of a display device, comprising: driving white subpixels in the pixel units to compensate the pixel units for the brightness according to predetermined pixel units whose brightness is to be compensated for in the display device and compensating grayscale voltages corresponding to the brightness of the pixel units to be compensated.
US09666142B2 Display capable of reducing passive matrix coupling effect
A display has a panel, a plurality of first traces and a plurality of second traces. The panel has a first passive matrix and a first coupling capacitor group. The first passive matrix has a plurality of first pixels, and the first coupling capacitor group has a plurality of first coupling capacitors. Each of the first pixels is coupled to a first storage capacitor and corresponds to at least a specific first coupling capacitor of the plurality of first coupling capacitors. The first storage capacitor is coupled to a specific first trace of the plurality of first traces and a specific second trace of the plurality of second traces. The specific first coupling capacitor is coupled to another first trace and the specific second trace, and the specific first coupling capacitor is not directly connected to any of the first pixels.
US09666141B2 Display apparatus and method of driving the same
A display apparatus includes a display panel including a first subpixel having a first primary color, a second subpixel having a second primary color; and a transparent subpixel; a panel driver which sets grayscale data of the first subpixel, the second subpixel and the transparent subpixel; a light source part which provides light to the display panel, where the light source comprises a first light source and a second light source having colors different from each other; and a light source driver which turns on the first light source during a first subframe, turns on the second light source during a second subframe, and turns on the first light source during a third subframe, and a first frame comprises the first subframe, the second subframe and the third subframe.
US09666139B2 Terminal apparatus and method of controlling the same
A terminal apparatus includes a light modulation unit to perform an automatic light modulation of a touch panel, an illuminance sensor, a proximity sensor, an illuminance determination unit to determine whether or not an illuminance detected by the illuminance sensor varies, and an operation determination unit to determine whether or not an operation of the touch panel occurs near the illuminance sensor, wherein the light modulation unit suspends the automatic light modulation when the operation of the touch panel occurs before a first time elapses after the detected illuminance decreases, and the light modulation unit suspends the automatic light modulation when the operation determination unit determines that the operation of the touch panel does not occur before the first time elapses after that the detected illuminance decreases and then the proximity sensor detects an object before a second time elapses.
US09666132B2 Pixel circuit, method for driving the same and display apparatus
The present disclosure discloses a pixel circuit, a method for driving the pixel circuit and a display apparatus. The pixel circuit comprises multiple rows of pixel units and a row sharing unit. Each row of pixel units includes a plurality of sub-pixel units, and each sub-pixel unit includes a light-emitting element. The row sharing unit includes a plurality of row-driving light-emitting control modules. The plurality of sub-pixel units comprised in each row of pixel units is connected to a corresponding signal line. Each row-driving light-emitting control modules is connected to a light-emitting control signal. Each row-driving light-emitting control module is connected to each sub-pixel unit comprised in a corresponding row of pixel units through the signal line, so as to drive the light-emitting element comprised in the sub-pixel unit to emit light under the control of the light-emitting control signal.
US09666130B2 Pixel circuit, display device, and method of driving pixel circuit
A pixel circuit, display device, and method of driving a pixel circuit enabling source-follower output with no deterioration of luminance even with a change of the current-voltage characteristic of the light emitting element along with elapse, enabling a source-follower circuit of n-channel transistors, and able to use an n-channel transistor as an EL drive transistor while using current anode-cathode electrodes, wherein a source of a TFT 111 as a drive transistor is connected to an anode of a light emitting element 114, a drain is connected to a power source potential VCC, a capacitor C111 is connected between a gate and source of the TFT 111, and a source potential of the TFT 111 is connected to a fixed potential through a TFT 113 as a switching transistor.
US09666127B2 Scan driving apparatus and display apparatus including the same
A display apparatus includes a display panel including a plurality of scan lines and a plurality of pixels connected to the plurality of scan lines, and a scan driving unit to supply a scan signal to each of the plurality of pixels via the plurality of scan lines, the scan driving unit including a scan signal generation unit to generate the scan signal supplied to each of the plurality of scan lines, and a plurality of buffers respectively corresponding to the plurality of scan lines, each one of the plurality of buffers outputting a scan signal to a corresponding one of the plurality of scan lines, wherein each of the plurality of buffers includes a transistor having a size corresponding to a load of a circuit connected to an output end of a corresponding buffer.
US09666125B2 Organic light-emitting diode circuit and driving method thereof
An organic light-emitting diode circuit and a driving method thereof are disclosed herein. The organic light-emitting diode circuit includes a storage unit, a transistor, a coupling capacitor, a compensation unit, an input unit, a switch unit, and an organic light-emitting diode. The transistor is configured to be driven by a voltage stored in the storage unit so that a second end of the transistor generates a driving current. The coupling capacitor changes a voltage of the second end of the transistor. The compensation unit changes the voltage level at the second end of the transistor according to a first scan signal. The input unit transmits a data voltage to the storage unit according to a second scan signal. The switch unit is turned on according to a light-emitting signal so that the driving current is transmitted to the organic light-emitting diode through the switch unit.
US09666121B2 Display control apparatus and method
Provided is a display control apparatus including: a display control unit configured to distribute brightness information to a plurality of display devices in accordance with external light amount information from a sensor; and a plurality of drive units configured to drive the plurality of display devices on a basis of the brightness information distributed by the display control unit.
US09666119B2 Systems and methods for controlling current in display devices
The present disclosure relates generally systems and methods for controlling current provided to display devices. A method for controlling the current may include receiving drive current values associated with subpixels in a display and receiving information that corresponds to an application type being rendered on the display and/or an indication of image data being rendered on the display. The method may then include reducing at least some of the drive current values based at least in part on the application type. Alternatively, the method may include reducing the at least a portion of the image data corresponding to the at least some of the drive current values has substantially similar luminance and color values. The method may then include supplying the subpixels with drive currents that correspond to the drive current values.
US09666116B2 Image display device and driving method thereof
An image display device includes a plurality of pixels, a pixel detection unit configured to detect first pixels having same R, G, and B gray scale values for a predetermined time among the plurality of pixels, a gray scale value calculation unit configured to calculate average gray scale values of the first pixels and average gray scale values of corresponding R, G and B of second pixels in a predetermined area around the first pixels, a data correction unit configured to correct the R, G and B gray scale values of the first pixels, using the calculated average gray scale values of the first and second pixels, and a data driver configured to correct the image data with the corrected R, G and B gray scale values of the first pixels, and to supply the corrected image data to each pixel of the plurality of pixels.
US09666113B2 Display, image processing unit, and display method for improving image quality
A display includes: a gain calculation section obtaining, according to an area of a high luminance region in a frame image, a first gain for each pixel in the region; a determination section determining, based on first luminance information for each pixel in the high luminance region and the first gain, second luminance information for each pixel in the high luminance region; and a display section performing display based on the second luminance information.
US09666109B2 Projector
A projector includes, a projecting unit that converts image data into light and projects the light at a predetermined angle of view, a projecting direction changing unit that changes the projecting direction of the projecting unit from a first projecting direction to a second projecting direction, a projection angle derivation unit that derives a projection angle between the first projecting direction and a projecting direction after changed, and an image cutting out unit that generates cut-out image data that a part of a region of an image of the inputted image data is cut out based on the angle of view and the projection angle as image data to be projected, when the projecting unit projects the image of the inputted image data stored on the storage unit across the first projecting direction and the second projecting direction.
US09666105B2 Sign construction with modular wire harness arrangements and methods of using same for backside to frontside power and data distribution schemes
A large format billboard type electronic sign having an anchored mounting structure, comprises at least one structural frame configured to be mounted to from a front side surface of the anchored mounting structure, and the at least one structural frame defines a plurality of structural bay members configured in adjacent columns for receiving and removably supporting therein a corresponding plurality of weatherized display modules; and at least one preformed wiring harness for routing low voltage power within the plurality of structural bay members, wherein the at least one preformed wiring harness is provided with at least one power introduction node to facilitate providing separate power branches for distributing power between adjacent columns of the structural bay members and at least one structural bay locator node to facilitate providing a low voltage power branch to at least an individual one of said plurality of structural bay members.
US09666104B2 Display panel, display method and display device
The present disclosure provides a display panel including a plurality of pixels, each of which includes at least one sub-pixel. Each sub-pixel includes a color reflection box and a control unit configured to control a color to be displayed by the color reflection box. The control unit is configured to, in the presence of ambient light, control a position of a light-entering surface of a shielding member in the corresponding color reflection box relative to a light-entering surface of a case in accordance with a display image at a corresponding position, so as to enable the color reflection box to display a color of the light-entering surface of the shielding member or a color of a colored material.
US09666103B2 Conduit identification system
An identifier for a conduit includes a substrate having a pair of apertures. The substrate further contains a frangible portion encompassing one of the apertures and having a shape that corresponds to an opening left in the substrate after removal of the frangible portion. The identifier enables the shape of the frangible portion to be correlated with the shape of the opening left in the substrate after the frangible portion is separated from the substrate.
US09666101B2 Multi-user medical robotic system for collaboration or training in minimally invasive surgical procedures
A multi-user medical robotic system for collaboration or training in minimally invasive surgical procedures includes first and second master input devices, a first slave robotic mechanism, and at least one processor configured to generate a first slave command for the first slave robotic mechanism by switchably using one or both of a first command indicative of manipulation of the first master input device by a first user and a second command indicative of manipulation of the second master input device by a second user. To facilitate the collaboration or training, both first and second users communicate with each other through an audio system and see the minimally invasive surgery site on first and second displays respectively viewable by the first and second users.
US09666099B2 Driver control assistance sensor and method
An arrangement for training a vehicle driver or improving driving ability having a sensor located in a position beneath a motor vehicle brake pedal. A warning indicator is connected to the sensor to provide a signal when the sensor detects that a driver's heel is not in contact with a floor of the vehicle during braking.
US09666095B2 Depth-related help functions for a wheel loader training simulator
Methods and systems for training an operator. One system includes a computing device including a processing unit and computer-readable medium. The computer-readable medium stores a training simulator application that is configured to receive an operating command from the operator, generate a simulated working environment and a simulated wheel loader having a simulated bucket, and generate an indicator providing depth-related information to an operator relating to a position of at least a portion of the simulated wheel loader with respect to a point-of-reference within the simulated working environment. The training simulator application is further configured to output the simulated working environment and the indicator for display to the operator, and automatically modify the indicator based on a position of the simulated wheel loader with respect to the point-of-reference.
US09666092B2 Vehicle comparison system
A system for comparing energy usage of different vehicle platforms is provided. The system may include a processor to execute routines stored in a memory device. Further, in one embodiment the routines include routines configured to receive selection of a driving style by a user and to select a virtual test drive based on the received selection. Also, the routines may include routines configured to output the selected virtual test drive and to output a comparison of multiple vehicles having different characteristics based on the selected virtual test drive. Other systems, methods, and manufactures are also disclosed.
US09666089B2 Automated creation and maintenance of video-based documentation
A computer system for creation and maintenance of video-based training documentation. Universal identifiers are created and associated with user interface elements for delimiting videos and audios. Test scripts are created based on matching the universal identifiers to task instructions. Videos are created based on test scripts where the universal identifiers are marked on the videos. Audios are created based on the universal identifiers and the task instructions, where the universal identifiers are marked on the audios. The audios and the videos are combined based on synchronizing the universal identifiers.
US09666088B2 Video-based teacher assistance
A video-based teaching aid system and method. Video images are recorded of at least some of a plurality of people in a classroom setting by use of a video camera arrangement. Expressions of the people in the video images are identified by use of an expression recognition module configured to receive the video images from the video camera arrangement. The identified expressions of the people in the video images are correlated with at least one of an event or an outcome of an event occurring in a classroom setting by use of a correlation module. The results of the correlating are outputted by an output device.
US09666086B2 Method and apparatus for teaching power distribution
A method and apparatus for teaching power distribution with an educational board game includes providing a game board that includes a power station location, power pole locations, and a target building location. A power pole indicator is placed at a power pole location and a power line indicator is connected from the power station location to the power pole indicator during the player's turn. Additional power pole indicators are positioned at additional power pole locations during the player's subsequent turns and the power line indicator is connected from the power station location to the target building location via the power pole indicator and the additional power pole indicators.
US09666083B2 Method for inserting a segment of flight plan in a flight plan
The invention relates to a method for inserting a segment (Tins) of flight plan into an initial flight plan (Pini) of an aircraft, performed by a flight management system (FMS) of the said aircraft, the initial flight plan (Pini) comprising an ordered series of initial legs (Sini), the said fixed initial legs being indexed with an index i that varies from 1 to n, the method comprising the steps involving: identifying (110), using a first iterative calculation on the index i, in the segment to be inserted (Tins), the fixed legs to be inserted that have a position identical to the position of the leg of index i Sini(i)), the said legs thus determined being referred to as occurrences of the leg of index i, the said occurrences (O1, O2) being ordered by rank k varying from 1 to m, as a function of their position in the segment that is to be inserted (Tins), and searching, among the identified occurrences, for the occurrence of lowest index i and lowest rank k (Oi0(k0)) that has a type and attribute values identical to the segment of index i, referred to as equivalent point, when the said equivalent point exists, inserting the segment that is to be inserted (Tins) from the said equivalent point, otherwise, inserting the segment that is to be inserted (Tins) from the identified occurrence of lowest index i and lowest rank k (Oi1(k1)) referred to as a pseudo equivalent point, when the said pseudo equivalent point exists.
US09666082B2 Method and system for guidance of an aircraft
A method of flight management and guidance of an aircraft executed by a flight management system FMS comprises the steps of: generating a reference trajectory, generating a short-term trajectory, periodically transmitting the short-term trajectory, generating a long-term trajectory, formatting the segments of the long-term trajectory, periodically transmitting the long-term trajectory, storing the long-term trajectory transmitted, testing the validity of the FMS sub-assembly, when the FMS sub-assembly is valid: identifying, by the autonomous guidance module, the active segment of the short-term trajectory, generating, by the autonomous guidance module, a first flight guidance order on the basis of the active segment of the short-term trajectory; when the FMS sub-assembly is not valid: identifying, by the autonomous guidance module, the active segment of the stored trajectory, generating, by the autonomous guidance module, a second flight guidance order on the basis of the active segment of the stored trajectory.
US09666074B2 Method and system for vehicle parking
A request to identify a parking spot is received. A response to the request, including an identification of at least one available parking spot, is provided. A parking spot selected from the response is identified. Data relating to the selected spot are collected. A user profile based on the collected data is updated.
US09666073B1 Innovated smart parking assistance system and information system
An innovated SMART Parking System, PRIN System and an Information System are provided. The PRIN System is able to manage multiple parking lots without range limitation, and deeply monitor the individual parking space status and also driveway status at each parking lot upon the control devices deployed. By the bi-directional communication, the control devices are able to be managed and changed the control methodology for dynamic parking service support. Besides, the Information System can provide the real-time parking service information for either remote or local access to assist the quick parking without spending too much driving and searching time for parking. Therefore, the PRIN System and Information System facilitates the problem solving of traffic jam and difficult parking within the city effectively, and significantly reduce the social cost, vehicle emission and carbon monoxide to improve the air we breathe and city environment we care.
US09666069B2 Autonomous vehicle handling and performance adjustment
A vehicle includes an autonomous driving sensor configured to detect a road condition and output at least one road condition signal representing the road condition, an autonomous mode controller configured to control the vehicle according to the at least one road condition signal, and a communication module configured to broadcast the road condition signal.
US09666066B2 Unexpectedness prediction sensitivity determination apparatus
An unexpectedness prediction sensitivity determining apparatus determines a standard driving operation level of a driver when turning to the right or left at an intersection for each intersection based on intersection travel information received from plural vehicles. Subsequently, the unexpectedness prediction sensitivity determining apparatus determines the unexpectedness prediction sensitivity of the driver when turning to the right or left at the intersection based on the intersection travel information associated with the intersections where determined standard driving operation levels of the drivers are identical to one another.
US09666061B2 System for monitoring caregivers and equipment
A hospital monitoring system for monitoring hospital personnel, a plurality of patient locations for patients, and associated devices is configured to control the associated devices based on the presence of hospital personnel or alarms.
US09666060B2 Alternative billing modes for security and automation applications
Techniques for facilitating one or more operating modes for monitoring of an intelligent home system are disclosed. The techniques facilitate detecting an adverse condition in a building, generating an alert based on the detection, sending a notification about the alert to a user (e.g., to a mobile device), awaiting a user response, and determining whether to send the alert to a central monitoring system to facilitate notification of an appropriate responder for the adverse condition. Determining whether to send the alert to the central monitoring system may be based on an affirmative command from the user or a failure to receive any command from the user. The user may be billed for the service of notifying an appropriate responder provided by central monitoring system regularly, intermittently when the user is away from the building, or on a per-alert basis.
US09666051B2 Method and a device for detecting icing at an air inlet of a turboshaft engine
A method of detecting that an aircraft is flying in icing conditions. A processor unit determines a real power developed by the turboshaft engine and a theoretical power that the engine can develop in theory, the theoretical power being determined using a theoretical model supplying a power as a function at least of a speed of rotation of a gas generator of the engine. The processor unit determines a difference between the real power and the theoretical power. The processor unit generates a warning to indicate the presence of icing conditions when the power difference is greater than a predetermined power threshold for a length of time longer than a time threshold, and when a temperature outside the aircraft lies between a low temperature threshold and a high temperature threshold.
US09666050B2 Forest fire early-warning system and method based on infrared thermal imaging technology
A forest fire early-warning system based on infrared thermal imaging technology includes an infrared camera erected in a forest to capture infrared thermal images of an area being monitored. The camera includes a frontal temperature detection and alarm module for calculating the alarm temperature value by using a temperature monitoring mathematical model, and for transmitting an excessive temperature alarm signal when there are abnormalities in said area. A video conversion device connected to the infrared camera converts an infrared thermal image analog signal outputted by the camera into an infrared digital signal, and receives from the camera said alarm signal and converts same into a digital signal. A monitoring computer generates and transmits an infrared camera control signal, and processes the infrared digital signal to ascertain the location in the monitoring area that triggered the infrared camera alarm.
US09666045B2 Safety control for product dispensers
Techniques are described for processing sensor data associated with product dispensers at an establishment. The system is configured to monitor the location of product dispensers at an establishment and the system detects an alarm event related to the monitoring system based on the monitoring.
US09666035B2 Security apparatus for an automated teller machine
A method and associated security apparatus for providing security to an automatic teller machine (ATM) having a cash capture device in a presenter area of the ATM. The cash capture device is detected by a proximity detector in the security apparatus in the ATM. A detecting signal is generated by the proximity detector in response to the cash capture device being detected. The detecting signal is received by control circuitry in the security apparatus and in response, the control circuitry causes a dispensing shutter of the ATM to remain in an open position. Each proximity detector is electrically connected to the control circuitry. The dispensing shutter in the open position is configured, in an absence of the cash capture device in the ATM, to dispense paper currency processed and stored in the presenter area of the ATM. security apparatus includes the proximity detector and the control circuitry.
US09666033B2 Electronic slot machine
An electronic slot machine, having a display for displaying a plurality of symbols arrayed in at least three vertical columns of symbols, and at least three horizontal rows of symbols where game play is initiated by selecting a sequence for sequentially spinning selected columns and rows up to three total. The resulting display of symbols are analyzed to determine whether the array of symbols constitute a winning combination. Additional game playing occurs when the player selects a new sequence of rows and columns for spinning to achieve a new set of symbols for analysis to determine a winning combination.
US09666029B1 Ad serving offers and new game promotions outside the game module with business intelligence based on portfolio of games
An online gaming system providing dynamic delivery of advertisements to users of an online game. The system may dynamically select advertisement for delivery based on one or more user parameters which characterize the user's activity with the online game. The system may comprise one or more processors configured to execute computer program modules. The system may include a game module configured to execute an instance of an online game and to implement the instance of the online game to facilitate participation of users in the online game. The system may include a user monitor module configured to monitor user activity parameters. The system may include a potential offer module configured to manage multiple incentive offers which are available for delivery to the users of the online game. The system may include an offer determination module configured to select incentive offers to be delivered to the users of the online game from the multiple incentive offers based on the monitored activity parameters of the users.
US09666020B2 Wagering game with a secondary reel having oversized single-evaluation symbols
A gaming system includes one or more input devices, one or more display devices, and one or more processors, and one or more memory devices storing instructions that cause the gaming system to receive an input indicative of a wager. The instructions further cause the gaming system to display a wagering game having an array of symbol positions positioned on a plurality of primary reels and at least one secondary reel overlaying two or more adjacent primary reels, the secondary reel including at least one oversized standard symbol, the oversized symbol overlaying symbol positions on at least two of the two or more adjacent primary reels. The instructions further cause the gaming system to spin the two or more adjacent primary reels and the secondary reel such that the two or more adjacent primary reels and the secondary reel appear to spin as a single reel.
US09666019B1 Determining paylines in a slot game based on player characters
A system and method for determining paylines in a slot game based on player characters are disclosed. A given player character may correspond to distinctive paylines along which symbols in a pull outcome may be assessed for rewards, for gameplays to be implemented in a game space, and/or any for other types of results provided by a slot game. In some examples, the number of the paylines corresponding to the given player character may correlate with various aspects regarding the given player character such as, without limitation, a class, a level, a race, a number of experience points, one or more skills, virtual items, and/or any other aspects regarding the given player character. In some examples, the combinations of symbols appearing on active paylines in a pull outcome may trigger one or more gameplays for implementation in a game space associated with the slot game.
US09666018B1 In-game building that receives stat boosts from troops
A system and method for garrisoning virtual units in virtual structures such that the attributes of the virtual structure are modified to reflect the garrisoning of the virtual unit inside the virtual structure.
US09666016B1 System and method for conducting casino style game utilizing a pair of spinning tops
A casino style system and method involving the use of a pair of spinning tops to generate random outcomes. A dealer's top and player's top are spun simultaneously before which players are able to place wagers on a series of colors (e.g., red, green, blue and yellow) and/or symbols (e.g., wild jokers) depicted on different facets of the tops and win awards responsive to random outcomes generated by said tops once toppling over. The tops are adapted to land such that a single facet is facing upwards identifying a color/symbol. Players may be able to place combo outcome wagers on specific combinations of random outcomes generated by the tops. A calibration/balance device is used to check and maintain the randomness of the tops.
US09666013B2 Cloud-based vending
In a general aspect, a computer-implemented method can include receiving, at a computing device, a beacon signal including a vending device identifier and sending, to a cloud-based vending service, the vending device identifier. The method can further include receiving, from the cloud-based vending service, an indication of at least one product available for purchase from the vending device and receiving, at the computing device, an indication of a selected product of the at least one product available for purchase. The method can also include sending, to the cloud based service, a request to purchase the selected product and receiving, from the cloud-based vending service, a purchase token for the selected product. The method can still further include sending, to the vending device, the purchase token and receiving, from the vending device, an acknowledgment that the purchase token has been used to purchase the selected product.
US09666006B2 Wireless radio frequency switch controller
A wireless radio frequency switch controller may be capable of being retrofit on to any existing parent system such as a thermostat, security system, garage door, and the like. The switch controller may have an external housing, a contact penetrating clip, a processor capable of being connected to a network, and a computer readable storage medium storing one or more programs for execution by the processor. The bottom of the contact penetrating clip preferably has at least one cutting surface. The cutting surface being capable of cutting an insulative covering for an electrical wire, once the contact penetrating clip is secured to the switch controller. The switch controller requires no batteries and harvests/stores energy from the parent system's existing wiring. The switch controller may be capable of being paired with a wireless receiver/transceiver by which the operation of the switch controller and subsequently the parent system may be manipulated.
US09666004B2 Electronic latch release backup system for a motor vehicle door
A latch release backup system for a latch assembly of a motor-vehicle door is provided with a key cylinder configured to receive a vehicle key and which is rotatably mounted to the motor-vehicle door, and a mechanical coupling arrangement mounted within the motor-vehicle door and operable to convert a rotation of the key cylinder into actuation of an actuation group of the latch assembly for causing latch release. The key cylinder defines an electrical interface socket designed to receive the vehicle key. An electronic control unit is mounted within the motor-vehicle door and is electrically connected to the electrical interface socket to receive identification information (Id) from the vehicle key when plugged into the electrical interface socket. The mechanical coupling arrangement is normally disengaged from the actuation group of the latch assembly, and the electronic control unit is configured to control selective engagement of the mechanical coupling arrangement to the actuation group of the latch assembly based on the identification information (Id) received from the vehicle key.
US09666002B2 Method for operating a vehicle barrier
In a method for operating a vehicle barrier (1) having a barrier column (2), a barrier arm (4) and a drive mechanism for pivoting the barrier arm (4) between a blocking position and an open position, a camera (7) is used for vehicle recognition, for the license plate recognition, for recognizing a following vehicle and for monitoring for vandalism, and the images thereof are evaluated by an electronic evaluation logic that is coupled to control of the vehicle barrier (1).
US09666001B2 Virtual gantry detection in a GNSS system
Method and system for detecting passages by vehicle at a virtual gantry controlled by a GNSS system comprising an OBU in every vehicle to be surveyed by the system, said OBU receiving signals from satellites to consistently and frequently estimate positions for the vehicle, the method comprising the steps of: defining a virtual gantry in terms of a number of ordered passage lines across a road; determining intersection points from the intersection between the GNSS trace and the passage line; calculating a value representing probability of a true passage at that passage line; for each vehicle for which intersection points have been determined for at least two different passage lines, calculating a total probability value based on the individually calculated probability values; concluding of a true passage by the vehicle in question only if the total probability value is exceeding a predefined minimum value.
US09665995B2 Method and system for performing crash analysis of one or more vehicles
A method and system for crash analysis of one or more vehicles involved in a crash is disclosed. The method may comprise capturing data samples such as a plurality of GPS samples and a plurality of acceleration samples. The method may further comprise generating a trajectory. Moreover, the method may comprise segmenting the trajectory into a macro level segment and further into a micro level segment. The method may further comprise computing at least one macro level score based on the plurality of acceleration samples and the GPS samples. Based on the at least one macro level score, the method may be configured to compute a crash responsibility score for ascertaining crash responsibility.
US09665991B2 Tolling using mobile device
In one aspect, a tolling system is operable to perform operations, which may include: receiving, over a network and from a mobile device application operating on a mobile processing device, an identifier and road usage data collected by the mobile device application; identifying a profile based on the identifier; accessing a toll pricing model applicable to an entity associated with the identified profile; and determining a tolling charge incurred by the entity based on the road usage data collected by the mobile device application, the identified profile, and the accessed toll pricing model. In another aspect, a mobile device application is operable to perform operations that may include: collecting road usage data; communicating, over a network to a tolling system, the collected road usage data and an identifier; and receiving, from the tolling system, tolling charge data computed based on the communicated road usage data.
US09665985B2 Remote expert system
A remote expert application identifies a manipulation of virtual objects displayed in a first wearable device. The virtual objects are rendered based a physical object viewed with a second wearable device. A manipulation of the virtual objects is received from the first wearable device. A visualization of the manipulation of the virtual objects is generated for a display of the second wearable device. The visualization of the manipulation of the virtual objects is communicated to the second wearable device.
US09665982B2 Information processing apparatus, information processing method, and recording medium
There is provided an information processing apparatus including an image acquisition part configured to acquire an image captured by an imaging part, and a display controller configured to cause a virtual object to be displayed in accordance with a recognition result of a real object shown in the image. The display controller controls the virtual object on a basis of a size of the real object in a real space.
US09665978B2 Consistent tessellation via topology-aware surface tracking
Consistent tessellation via topology-aware surface tracking is provided in which a series of meshes is approximated by taking one or more meshes from the series and calculating a transformation field to transform the keyframe mesh into each mesh of the series, and substituting the transformed keyframe meshes for the original meshes. The keyframe mesh may be selected advisedly based upon a scoring metric. An error measurement on the transformed keyframe exceeding tolerance or threshold may suggest another keyframe be selected for one or more frames in the series. The sequence of frames may be divided into a number of subsequences to permit parallel processing, including two or more recursive levels of keyframe substitution. The transformed keyframe meshes achieve more consistent tessellation of the object across the series.
US09665975B2 Shader program execution techniques for use in graphics processing
This disclosure describes techniques for executing shader programs in a graphics processing unit (GPU). In some examples, the techniques for executing shader programs may include executing, with a shader unit of a graphics processor, a shader program that performs vertex shader processing and that generates multiple output vertices for each input vertex that is received by the shader program. In further examples, the techniques for executing shader programs may include executing a merged vertex/geometry shader program using a non-replicated mode of execution. The non-replicated mode of execution may involve assigning each of a plurality of primitives to one merged vertex/geometry shader program instance per primitive and causing each of the instances to output a plurality of vertices. In additional examples, the techniques for executing shader programs may include techniques for selecting one of a non-replicated mode and a replicated mode for executing a merged vertex/geometry shader program.
US09665974B2 Methods and systems of joint path importance sampling
Methods and systems of joint path importance sampling are provided to construct light paths in participating media. The product of anisotropic phase functions and geometric terms across a sequence of path vertices are considered. A connection subpath is determined to join a light source subpath with a light receiver subpath with multiple intermediate vertices while considering the product of phase functions and geometry terms. A joint probability density function (“PDF”) may be factorized unidirectional or bidirectional. The joint PDF may be factorized into a product of multiple conditional PDFs, each of which corresponds to a sampling routine. Analytic importance sampling may be performed for isotropic scattering, whereas tabulated importance sampling may be performed for anisotropic scattering.
US09665970B2 Variable-sized concurrent grouping for multiprocessing
Aspects include, for example, a method for interpreting information in a computer program, or profiling such a program to estimate a group size for instances of that program (program module, or portion thereof). Such a method can be used in a system that supports collecting outputs of executing instances, where those outputs can specify new program instances. Scheduling of new instances (or allocation of resources for executing such instances) can be deferred. A trigger to begin scheduling (or allocation) for a collection of instances uses a target group size for that program. Thus, different programs can have different group sizes, which can be set explicitly, or based on profiling. The profiling can occur during one or more of pre-execution and during execution. The group size estimate can be an input into an algorithm that also accounts for system state during execution.
US09665967B2 Disparity map generation including reliability estimation
A better basis for a further processing such as virtual view rendering, in form of a disparity map is achieved. To this end, the disparity map generation is done in two separate steps, namely the generation of two depth/disparity map estimates based on two different pairs of views of the scene in a manner independent from each other, with then comparing both depth/disparity map estimates so as to obtain a reliability measure for one or both of the depth/disparity map estimates.
US09665964B2 Image processing apparatus and image processing method
To display images by suitably superimposing a graphics image on a high-dynamic-range image in an easily visible manner.A dynamic range converter (311) converts a SDR graphics image to an HDR graphics image based on metadata. An image combiner (312) combines the graphics image of which the dynamic range has been converted to HDR with HDR content. A dynamic range converter (313) performs display mapping on the HDR content combined with the graphics image based on metadata.
US09665962B2 Image distractor detection and processng
Image distractor detection and processing techniques are described. In one or more implementations, a digital medium environment is configured for image distractor detection that includes detecting one or more locations within the image automatically and without user intervention by the one or more computing devices that include one or more distractors that are likely to be considered by a user as distracting from content within the image. The detection includes forming a plurality of segments from the image by the one or more computing devices and calculating a score for each of the plurality of segments that is indicative of a relative likelihood that a respective said segment is considered a distractor within the image. The calculation is performed using a distractor model trained using machine learning as applied to a plurality images having ground truth distractor locations.
US09665951B2 Unified compression/decompression graphics architecture
A unified compression/decompression architecture is disclosed for reducing memory bandwidth requirements in 3D graphics processing applications. The techniques described erase several distinctions between a texture (compressed once, and decompressed many times), and buffers (compressed and decompressed repeatedly during rendering of an image). An exemplary method for processing graphics data according to one or more embodiments of the invention thus begins with the updating of one or more tiles of a first image array, which are then compressed, using a real-time buffer compression algorithm, to obtain compressed image array tiles. The compressed image array tiles are stored for subsequent use as a texture. During real-time rendering of a second image array, the compressed image array tiles are retrieved and decompressed using a decompression algorithm corresponding to the buffer compression algorithm. The decompressed image array tiles are then applied as a texture to one or more primitives in the second image array.
US09665950B2 X-ray imaging system and image processing device
An X-ray imaging system includes an X-ray imaging device and an image processing device including a reconstruction unit and an estimation unit. The X-ray imaging device uses a Talbot or Talbot-Lau interferometer including gratings disposed in a line. The X-ray imaging device obtains sets of moire fringe images by fringe scanning multiple times between which arrangement of the gratings is changed. In the fringe scanning, one of the gratings is moved relatively to the remaining grating. The reconstruction unit generates, on the basis of the sets, a reconstructed image which is a differential phase image, an X-ray absorption image and/or a small-angle scattering image. The estimation unit estimates, on the basis of the reconstructed image, a relative position of the moved grating from a reference position of the grating at each imaging in the fringe scanning.
US09665948B2 Saturation compensation method
A saturation compensation method is provided. The method includes the steps of: retrieving an input image; performing at least one first image process on the input image to generate a first image; calculating saturation corresponding to each pixel in the input image; and performing a saturation compensation process on the first image according to the input image and the saturation to generate an output image.
US09665945B2 Techniques for image segmentation
Techniques for image segmentation can include receiving image data of an image including a background and a face of a person in a foreground, and determining a respective a priori probability of a head-shoulder foreground pixel appearing per pixel of the plurality of pixels, according to a positioning result of a plurality of exterior contour points of the face. The techniques can also include selecting foreground and background pixels of the plurality of pixels, according to at least the a priori probabilities, and determining respective color likelihood probabilities of the foreground and the background, according to color feature vectors of the selected pixels. The techniques can also include determining respective posteriori probabilities of at least part of the foreground and at least part of the background, according to the a priori probabilities and the respective color likelihood probabilities. The techniques can also include performing segmentation on the plurality of pixels, according to the respective posteriori probabilities.
US09665944B2 Image processing apparatus and non-transitory computer readable recording medium storing an image processing program with improved duplication of characters against a background image
In an image processing apparatus, a character recognizing unit identifies a character image in a document image. A font matching unit determines a character code and a font type corresponding to the identified character image. A fore-and-background setting unit sets the document image as a background image and sets a standard character image based on the determined character code and the determined font type. A background image correcting unit (a) deletes a deletion area in the background image, the deletion area taking a same position as the character image or the standard character image, (b) interpolates a differential area between the character image and the standard character image in a specific neighborhood area that contacts with the deletion area on the basis of the background image, and (c) interpolates the deletion area on the basis of the back ground image.
US09665943B2 Histogram-based image segmentation
Systems, apparatuses, and/or methods may provide for segmenting an image by generating a histogram of its pixel values, dividing the histogram into class intervals, and then iteratively computing new, shifted weighted means and shifted class interval boundaries for the class intervals until a predetermined level of convergence to a limit is obtained. The pixels may then be updated to a last weighted mean for class intervals to which they belong, providing segmentation. Similarly, any data may be segmented to provide computational efficiency.
US09665942B2 Object detection and tracking system
Methods and apparatuses for analyzing a sequence of images for an object are disclosed herein. In a general embodiment, the method identifies a region of interest in the sequence of images. The object is likely to move within the region of interest. The method divides the region of interest in the sequence of images into sections and calculates signal-to-noise ratios for a section in the sections. A signal-to-noise ratio for the section is calculated using the section in the image, a prior section in a prior image to the image, and a subsequent section in a subsequent image to the image. The signal-to-noise ratios are for potential velocities of the object in the section. The method also selects a velocity from the potential velocities for the object in the section using a potential velocity in the potential velocities having a highest signal-to-noise ratio in the signal-to-noise ratios.
US09665940B2 Light-microscopy method for locating point objects
A light-microscopy method for locating point objects in a sample arranged in an object space includes imaging the sample onto a detector by an imaging optical unit having a depth of field of predetermined axial extent along an optical axis in the object space, onto which the detector is imaged. The point objects in the sample are located within the depth of field. The first sample image generated by the imaging of the sample onto the detector is evaluated. For locating a respective first point object in a direction of the optical axis, a parameter of a first light spot of one or more light spots of the first sample image representing the first point object is determined, and a rough axial z position related to the first point object is assigned to the parameter based on predetermined association information.
US09665937B2 Incremental global non-rigid alignment of three-dimensional scans
Techniques are provided for incrementally aligning multiple scans of a three-dimensional subject. This can be accomplished by establishing an updated aligned set of scans as each new scan is sequentially processed and aligned with the existing scans. In such embodiments the pairwise and global alignment processes are effectively combined into a single collective alignment process. This collective alignment converges to an optimal alignment faster than the sequential pairwise alignment process that existing solutions use. The collective alignment enforces pairwise alignment between the individual scans in the aligned set of scans. This is because each scan comprising the aligned set can be aligned to the next incremental scan if any scan included in the aligned set can be aligned to the next incremental scan. The pairwise alignment between the scans comprising the aligned set is thus a known function.
US09665935B2 Image processing device and program
An object of the present invention is to provide an image processing technology capable of perceiving a motion of the shape of a target area. An image processing device (3) according to the present invention includes: a dynamic image acquiring unit (110) that acquires a dynamic image; a boundary line extracting means (130) that acquires a plurality of target area boundary lines by extracting boundary lines of a target area; a displacement correcting means (140) that acquires a predetermined number of displacement-corrected boundary lines in which a removal-required component is removed by calculating a displacement amount, which is the removal-required component, using a base boundary line as a displacement base for one or more of target area boundary lines other than the base boundary line among the plurality of target area boundary lines by using pixels corresponding to the plurality of target area boundary lines and correcting a predetermined number of the target area boundary lines other than the base boundary line by using the displacement amount after the calculation of the displacement amount; and a display means (34) that displays displacement-corrected boundary line information for display based on the predetermined number of displacement-corrected boundary lines.
US09665934B2 Apparatus for detecting faults in video frames of video sequence
A fault detection circuit for detecting faults in a video sequence includes a multiple input signature register (MISR) with a linear feedback shift register (LFSR) that receives pixel data for pixels in a frame region for video frames of a video sequence and receives a read signal to read the pixel data and shift the MISR; a multiple signature storage buffer (MSSB) that stores frame signatures; and a signature comparator that compares current and reference frame signatures to determine if a fault condition exists in the video sequence. The MISR holds a frame signature for the frame region of the video frame while receiving a frame end signal. The MSSB stores a current frame signature held by the MISR after receiving the frame end signal. The MSSB also stores a reference frame signature. A display processing circuit includes the fault detection circuit. An integrated circuit includes the display processing circuit.
US09665933B2 Method and apparatus for inspecting containers, such as bottles or similar containers
A method and apparatus for inspecting containers, such as bottles or similar containers. The abstract of the disclosure is submitted herewith as required by 37 C.F.R. §1.72(b). As stated in 37 C.F.R. §1.72(b): A brief abstract of the technical disclosure in the specification must commence on a separate sheet, preferably following the claims, under the heading “Abstract of the Disclosure.” The purpose of the abstract is to enable the Patent and Trademark Office and the public generally to determine quickly from a cursory inspection the nature and gist of the technical disclosure. The abstract shall not be used for interpreting the scope of the claims. Therefore, any statements made relating to the abstract are not intended to limit the claims in any manner and should not be interpreted as limiting the claims in any manner.
US09665924B2 Prioritized requesting of mapping layers
A mapping system disclosed herein includes a requestor that transmits requests for different layer sets of mapping data for a digital map to one or more data sources across a network according to a predefined order. According to one implementation, the mapping system also processes and/or renders the different layer sets to a display according to the predefined order.
US09665920B1 Simultaneous execution of compute and graphics applications
One embodiment of the present invention sets forth a technique for distributing graphics commands and atomic commands to a color processing unit (CROP) in an efficient manner. The interleaving mechanism determines, at each clock cycle, which graphics command(s) or atomic command(s) is transmitted to the CROP based on different factors. First, the interleaving mechanism ensures that atomic commands or graphics commands associated with a multi-transaction command stream are processed together. Second, the interleaving mechanism selects consecutive graphics commands for transmission to the CROP that optimize the use of different memory caches. Third, the interleaving mechanism prioritizes atomic commands over graphics commands. At each clock cycle, the graphics command(s) or the atomic command(s) selected by the interleaving mechanism are transmitted to the CROP for processing.
US09665914B2 Social campaign network and method for dynamic content delivery in same
An engine, system and method for a domain social network that interconnects Internet users with at least domains owned by or of interest to those Internet users, and that may obtain and/or forward obtained dynamic data regarding those domains automatically, such as by web service or email service. The dynamic data may be used to filter and protect content and data of the respective domains, to protect users by identifying low quality web pages or malicious software or pages, to isolate or improve search results regarding the domain, and/or to improve Internet-based transaction flow, such as the creation of advertising.
US09665912B1 Insurance claim capitation and predictive payment modeling
A claim-based capitation model is proposed for handling vehicle repair insurance claims. Rather than determining a detailed estimate of the expected actual cost of repair, the estimate may be determined using a simpler model. For example, the insurance company and a repair facility may agree to following a predictive payment model in which the insurance company pays a fixed predicted capitated amount of money for each repair claim, regardless of the amount of repair work that will be needed. Alternatively, the insurance company may pre-pay a fixed capitated amount for a predicted number of future insurance claims.
US09665911B2 System and method to document and display business requirements for computer data entry
An embodiment provides a real-time or dynamic collaborative computer data collection form prototype builder. An embodiment integrates several concepts in order to streamline the computer data collection form development process. In an embodiment a dataset is used to collect data entry form requirements and attributes about the user interface which are used by a program to render a computer data collection form. Change implementation is facilitated by permitting changes in the underlying data set to be reflected in the computer data collection form, e.g., as re-rendered by the system.
US09665910B2 System and method for providing customized safety feedback
The present invention relates generally to systems and methods for monitoring driving behavior and providing feedback to the driver. The systems evaluate driving behavior and relay feedback to the driver in a fashion that is customized to take into account individual characteristics and demographic characteristics of the driver.
US09665904B2 Order entry system and order entry method
There is provided an order entry system including: a first microphone that picks up speech regarding order details of a first speaker; a second microphone that picks up speech regarding the order details of a second speaker for checking the order details of the first speaker; a speech recognizer that recognizes the speech regarding the order details of the first speaker which is picked up by the first microphone and the speech regarding the order details of the second speaker which is picked up by the second microphone; and an order data output that displays on a display, a display screen of order data regarding the order details of the first speaker, including a first speech recognition result of the speech regarding the order details of the first speaker and a second speech recognition result of the speech regarding the order details of the second speaker.
US09665898B2 Executing multiple transactions using trigger inputs
Merchandise content is aggregated from numerous merchant sources and presented on computing devices of individual users. Users are able to purchase select individual merchandise items by performing a simplified action, such as a screen tap on a touchscreen device. When the user performs the action, a series of actions are performed programmatically and/or automatically on behalf of the user to initiate and complete the transaction for the selected merchandise item from the merchant source.
US09665893B2 Customizable state machine and state aggregation technique for processing collaborative and transactional business objects
A computer-implemented state machine is provided for processing business objects representing collaborations between business entities. At least one business object represents a collaboration between business entities. A number of graphs represented in computer-readable media each correspond to a particular collaborating business entity. The graphs are generated using text files, at least a first text file including state information for the business object, at least a second text file including action information for the business object, and at least a third text file including transition information for the business object. A computer-implemented method is provided for aggregating state information associated with a composite business object representing at least one collaboration between business entities. The method includes retrieving the state information for the composite business object from a computer-readable medium and determining a state for the composite business object based on an assigned priority level for a state in a hierarchy of states associated with the composite business object, each state in the hierarchy of states having a corresponding assigned priority level.
US09665886B2 Method and apparatus for interactive audience participation at a live entertainment event
The present invention relates to an interactive system enabling audience participation at a live event taking place in a venue. The system includes use of an interactive device that presents a promotional message (that is displayed on an electronic display) to an audience member, wherein said audience member is capable of responding to said message by entering feedback into said interactive device. Said interactive device having the capability to transmit messages to another audience member. Said feedback is transmitted to a central processor, where said feedback is stored as audience data and subsequently processed into results.
US09665884B2 Electronic periodical advertisement
An electronic periodical advertisement including a number of time dependent offers is generated, e.g., using a computing device. The offers are organized into a number of modules. A default set of the modules is presented to a user. The default set of modules is edited to generate a user-defined set of modules. A user-defined electronic periodical advertisement including the user-defined set of modules is presented to the user.
US09665883B2 Apparatus and method for bringing offline data online while protecting consumer privacy
A method and system for bringing together online and offline advertising uses anonymous links that are associated with consumer data. The anonymous links allow processing without personally identifiable information (PII) in a secure environment. Data is matched using the anonymous links, and further using identifiers that are encrypted for use in connection with individual match distribution partners. The method and system allows a marketer to utilize offline data to precisely target advertisements without the use of PII, and to perform analytics concerning the use of the online advertisements to more precisely determine the effectiveness of multichannel marketing efforts.
US09665882B2 System and method for evaluating search queries to identify titles for content production
Systems and methods are provided to select potential titles for online content using search query logs from web search service providers. A plurality of search queries are collected from one or more web search service providers. A lifetime value is determined for each of the search queries. Potential titles are then selected from the plurality of search queries using selection criteria including the lifetime value of the search queries. The potential titles can then be provided to content developers who develop online content based on the potential titles.
US09665878B2 Method and system for upgrading a previously purchased media asset
Systems, graphical user interfaces and methods for upgrading from one or more digital media assets to a set of digital media assets over a network are described. A potential purchaser can be notified of available upgrade opportunities that are available for purchase. The potential purchaser can elect to pursue an upgrade opportunity so as to purchase a set of digital media assets. Upon upgrading to the set of digital media assets, the digital media assets within the set of digital media assets are made available to the purchaser. According to one aspect, a graphical user interface facilitates presenting and requesting upgrade opportunities. According to another aspect, equivalency rules and/or eligibility rules can be used to control which sets of digital media assets are available for upgrade by respective potential purchasers.
US09665877B2 Reverse couponing
Embodiments of the invention are directed to systems, methods and computer program products for reverse couponing. An exemplary apparatus is configured to determine user information and account information associated with a user; adjust offer information associated with an offer based on the user information and the account information, wherein the offer enables the user to receive at least one of a discount or a rebate on a purchase from a merchant; and transmit the adjusted offer to the user.
US09665875B2 Automated software tools for improving sales
A sales application is described that includes multiple automated sales tools that can be combined to help improve sales within a sales team. A deal finder sales tool is described to help identify sales opportunities. A deal playbook sales tool is also described to help structure the sales opportunity into a sales play by recommending products to sale in conjunction and also constructing a sales team. An influencer sales tool is also described to help identify business relationships that can be utilized to influence members of the sales team.
US09665868B2 One-time use password systems and methods
According to the invention, a method of using a one-time password for a transaction between a user and a merchant is disclosed. The method may include generating the one-time password. The method may also include authenticating the user by the authentication server in response to a request from the user to use the one-time password. The method may further include authorizing the use of the one-time password for the transaction in response to authenticating the user by the authentication server. The method may moreover include using the one-time password in combination with an account number to settle the transaction between the user and the merchant. The method may additionally include sending a message to the authentication server originating from the merchant, wherein the message comprises the one-time password, and wherein the message requests a determination whether the one-time password is authorized for use in the transaction. The method may also include sending a message to the merchant originating from the authentication server, wherein the message includes a determination whether the transaction should be approved in response to the authentication server determining whether the one-time password is authorized for use in the transaction.
US09665864B2 Method and device for conducting trusted remote payment transactions
A method, device, and system for conducting trusted payment transactions including establishing a trust relationship between a first mobile computing device and a second mobile computing device. The first mobile computing device may initiate a payment transaction with a point-of-sale device, communicate with the second mobile communication device to retrieve payment information from the second mobile communication device, and complete the payment transaction with the point-of-sale device using the payment information. The second mobile computing device is configured to verify the user and identity of the first mobile computing device prior to providing the payment information. Communications between the mobile computing devices may be encrypted using pre-determined encryption techniques.
US09665860B2 Software application framework for network-connected devices
A facility for provisioning and managing registered applications is described. Registered applications can be downloaded to a mobile device from an application provisioning server. When the download is complete, the mobile device may begin execution of the registered application. However, at least portions of the registered application cannot be executed by the mobile device without first passing control to an application provisioning server via a network connection. Upon receiving temporary control of the registered application, the application provisioning server can perform tasks such as license verification and other tasks before turning control of the application back to the mobile device.
US09665859B2 Method for future payment transactions
A method for the online modification, submission and approval processing of a future payment request to afford a user the ability to renegotiate established loan agreement debt terms in which network communications are established between a user, such as a debtor, and a computing device, such as a server or server arrangement, is presented. The method comprises receiving information, at the computing device, regarding the loan agreement debt terms, presenting received information to a debtor, providing an interactive environment enabling a debtor to modify existing terms, submitting modified terms, processing data from the available information using a rules based engine, and processing a future payment request based on at least one decision made by the rules based engine. While online, the user/debtor may engage in revising a rejected future payment request in an attempt to reach a satisfactory renegotiation of debt terms.
US09665853B2 Deferred aircraft maintenance impact assessment apparatus, system, and method
Described herein is an apparatus that includes a minimum equipment list (MEL) data module and an impact assessment module. The MEL data module determines at least one operational limitation associated with deferred maintenance on a vehicle. The impact assessment module determines an operational impact associated with the deferred maintenance based on the at least one operational limitation.
US09665850B2 Synchronized conversation-centric message list and message reading pane
Technologies are described herein for a user interface uniting two primary components, a list view and a reading pane, within a message reading application. Technologies are also described for synchronizing status and parameters between the two primary user interface components. In particular, a user interface for reading messages can represent all components of a conversation with both a list view for presenting a message map, and a reading pane for presenting a content view. The list view can present a list of messages grouped by conversation. The reading pane window can contain smaller windows or frames. Each of the smaller windows or frames can contain a message within a given conversation. Synchronization provided between the list view and a reading pane can allow message selection in one of the user interface components to cause display and selection of the corresponding message in the other user interface component.
US09665849B2 Employing dependency graph in software build projects
A mechanism for employing dependency graph in software build projects is disclosed. A method of implementation of the invention includes receiving a first build script file associated with a software project, the first build script file identifying a plurality of project dependencies associated with the software project. The method also includes parsing the first build script file to generate a project dependency graph corresponding to the first build script file. The project dependency graph includes a plurality of vertices representing to the plurality of software project dependencies and further includes a plurality of edges representing relationships between the plurality of the software project dependencies. The method also includes determining a build order of the plurality of software project dependencies using the project dependency graph.
US09665842B2 Supply chain management anomaly detection
An integrated supply chain management with anomaly detection. An order schedule has one or more orders, each of which has a production requirement and a due date. An asset schedule has asset commitments associating assets with orders. Each asset has equipment specifications, including an asset class and one or more operational thresholds. The computer system identifies an asset of a class corresponding to a production requirement of an order and modifies the asset schedule to commit the asset to the order prior to the due date of the order. The computer system receives sensor input for the asset and determines whether an anomaly exists. If so, the computer system commits a second asset to the order.
US09665841B2 Cross-platform application framework
One set of instructions is generated in part by compiling application-specific source code. When natively executed on a platform provided by a device, the set of instructions provides an application. Another set of instructions is generated in part by compiling the same business logic source code. When natively executed on another platform provided by another device, the other set of instructions provides the same application. The business logic source code is substantially free of code specific to any platform. Moreover, the business logic source code defines substantially all application-specific functionality of the application.
US09665838B2 Messaging architecture and system for electronic management of resources
A system for managing resources used by an appliance includes a messaging architecture that uses resource profiles and function identifiers that represent a meaningful context related to the resource profiles so that the production or consumption of a resource can be managed by electronic messages using the message architecture.
US09665834B2 System for managing risk in employee travel
A system for managing risk in employee travel may display a world risk map having countries color coded or otherwise indicating a risk level associated with each of the countries. The countries may be assigned to geographic groupings, such as continents, and the countries of the geographic grouping may change to a uniform color or other indication when the cursor is disposed within the boundaries of one of the countries of the geographic grouping. Clicking on the geographic grouping may cause the world risk map may cause the display to zoom in on an enlarged geographic group map with the countries displayed with their risk level indication. Clicking on one of the countries may cause a country information page to be displayed.