最新美国发明专利
Document Document Title
US09531227B2 Stator structure for rotary electric machine
In a stator constituting a rotary electric machine, a U-shaped first and second divided conductors are disposed at slots. The pitch of a pair of straight parts of the first divided conductor is set larger than that of a pair of straight parts of the second divided conductor. The second divided conductor is disposed on the inner side of the first divided conductor, more specifically, on the stator core side.
US09531226B2 Rotor of internal permanent magnet synchronous motor and internal permanent magnet sycnronous motor
A rotor of an internal permanent magnet synchronous motor including a rotor core, a plurality of slots formed in the rotor core, and a plurality of permanent magnets housed in the plurality of slots. Each of the slots includes a holding part formed between a first outside diameter surface and a first inside diameter surface to hold each of the permanent magnets, and an opening part formed at both sides of the holding part and formed by a second outside diameter surface, a second inside diameter surface and a connecting surface connecting them. The second outside diameter surface is formed to a curved shape so that a distance to an outer circumferential surface of the rotor core in the diametrical direction gradually becomes smaller from both ends of the second outside diameter surface to an intermediate part in the circumferential direction.
US09531224B2 Generator spring bar enhancement for core support system
A generator including a frame (56); first and second frame rings (13) extending radially inwardly from an inside surface of the frame (56); a core (54) within the frame (56); key bars (100) spaced apart circumferentially and extending axially spanning a distance between the first and second frame rings (75A and 75B), the key bars coupled to the core; laminated spring bars (60) spaced apart circumferentially and extending axially to span a distance between the first and second frame rings, a first spring bar end (112) supported by the first frame ring (75A), a second opposing spring bar end (111) supported by the second frame ring (75B), each spring bar coupled to a key bar; wherein the laminated spring bar further includes spring bar subcomponents (60A and 60B) and couplers (98/99) for coupling the spring bar subcomponents.
US09531221B2 Locking structure for stator core
A locking structure for a stator core that locks the stator core having a circular outer circumference into an inner circumference of a cylindrical housing includes a first cut-out formed in an outer circumference of the stator core and a second cut-out formed in an inner circumference of the housing. The locking structure also includes a key interposed between the first and second cut-outs.
US09531220B2 Motor and washing machine having the same
A motor having a structure capable of achieving an enhancement in durability and a washing machine, to which the motor is applied. The motor includes a stator including a plurality of stator cores arranged in a circumferential direction, and coils respectively wound around the stator cores, and a rotor rotatably arranged inside or outside the stator. The rotor includes a plurality of rotor cores arranged in a circumferential direction of the rotor, a plurality of magnets each disposed between neighboring ones of the rotor cores, a molded body having a bridge to support the plurality of rotor cores and the plurality of magnets, and a coupler including coupling ribs outwardly extending from an outer circumferential surface of the bridge in a radial direction of the rotor, and coupling grooves formed at inner ends of the rotor cores supported by the bridge, to receive the coupling ribs, respectively.
US09531207B2 Holster for supporting and charging the wireless headset of handheld devices
A holster for use with a handheld device and a peripheral device is disclosed herein. The holster provides a mating structure for holding a peripheral device so that a mobile device charges the peripheral device. The holster removes the inconvenience of having to charge a peripheral off a battery charger at work or home by permitting the peripheral to charge off the handheld device. The holster can be used with any handheld device and peripheral device, such as a cellular phone and a wireless headset.
US09531205B2 Alarm system for power supply
An alarm system for power supply includes a power supply unit, an electronic device, a control unit, and a switch unit. The power supply unit includes a battery. The battery outputs a power supply voltage. The power supply receives a standby DC voltage, and outputs a first voltage level signal according to the standby DC voltage and the power supply voltage. The electronic device outputs a second voltage level signal. The control unit receives the first voltage level signal and the second voltage level signal, and outputs a control signal in accordance. The switch unit receives the control signal, and sounds alert when there is no electric charge in the battery.
US09531201B2 Mobile terminal and controlling method thereof
A mobile terminal including a battery; a wireless communication unit configured to provide wireless communication; a memory configured to store at least one user battery charging pattern previously used for charging the battery; and a controller configured to start a charging of the battery, estimate a battery charging stop time based on the stored user battery charging pattern, and control the charging speed of the battery to complete charging of the battery before the estimated battery charging stop time.
US09531200B2 Battery conditioning apparatus
The present invention relates to a battery conditioning apparatus for conditioning a battery. The apparatus includes a pulse generator circuit for generating pulses to be applied to the battery. A loading circuit is provided for loading the battery. The apparatus also includes a controller for controlling the pulse generator circuit and loading circuit to concurrently apply the pulses to and load the battery.
US09531199B2 Underwater charging station
A submersible power supply apparatus provides the ability to provide power for recharging batteries used to operate underwater vehicles, manned and unmanned. A battery charging station apparatus containing at least one modular reserve battery magazine with a plurality of compartments is provided. A plurality of reserve battery modules may be respectively provided in the plurality of compartments, each of the plurality of reserve battery modules being configured to provide power when a reserve battery provided therein is activated.
US09531197B2 Non-contact power transmission apparatus
A non-contact power transmission apparatus accurately determines the kind of object that is placed on the charging deck of the non-contact power transmission apparatus, and, only when a non-contact power receiving apparatus is placed on the power transmission apparatus, allows power transmission and data communication to take place, thereby accurately determining the state of the receiver side and efficiently controlling the transmission of power. In the power transmission apparatus, the power supplied to the non-contact power receiving apparatus is measured, and the output power of the wireless power signal output from two different cores is controlled, thereby allowing the charging operation to be stably conducted even if the non-contact power receiving apparatus is moved anywhere on the power transmission apparatus. The power transmission apparatus improves both the reliability of operation of the non-contact charging system, and the competitiveness of related products, such as portable terminals, battery packs and the like.
US09531194B2 Systems and methods for zero-delay wakeup for power gated asynchronous pipelines
A device including a pipeline having a number of groups of pipeline stages. Each group has at least one pipeline stage, a gated power supply power net or a gated ground power net, the gated power supply power net and the gated ground power net having components that allow gating power supply and ground to that group of pipeline stages. The device also has a number of control components, each control component controlling the gating of power supply or ground. Each group of pipeline stages controls the gating of power supply and ground of a subsequent group of pipeline stages. Each one group of pipeline stages being selected such that a forward propagation delay from a preceding group of pipeline stages to that one group is at least equal to a time required for activating gated power supply or ground in that one group. Methods of implementation are also discussed.
US09531192B2 Power providing apparatus for use with multiple electricity sources
A power providing apparatus includes a first input port for connection to a first electricity source, a second input port for connection to a second electricity source, an output port, a first current control component connected between the first input port and the output port, and a second current control component connected between the second input port and the output port. Based on voltages associated with the first electricity source and the second electricity source, each of the first and the second current control components makes or breaks a current path from a respective one of the first and second input ports to the output port.
US09531187B2 Overvoltage protection device
An overvoltage protection device capable of protecting a power supply line and including in parallel a break-over diode, a controlled switch, and a circuit for controlling the switch.
US09531158B2 Laser light source
A laser light source, comprising a semiconductor layer sequence on a substrate and having an active region and a radiation coupling out area having first and second partial regions and a filter structure. The active region generates coherent first electromagnetic radiation and incoherent second electromagnetic radiation, the coherent first electromagnetic radiation is emitted by the first partial region along an emission direction, the incoherent second electromagnetic radiation is emitted by the first partial region and by the second partial region. The filter structure at least partly attenuates the incoherent second electromagnetic radiation emitted by the active region along the emission direction. The filter structure has at least one filter element arranged on an area of the semiconductor layer sequence which has an extension direction parallel to the emission direction and which is remote from the substrate.
US09531156B2 Endoscopic light source
A light source assembly includes multiple light emitters having output that are focused and mixed onto a optical fiber leading to an endoscope or other device. The emitters can be LEDs or solid state lasers that emit different colors. A driver circuit controls the relative output intensities of the light emitters so as to produce a desired light spectrum. A driver circuit includes a buck topology connected to a controller that provides current mode control. Pulse width modulation of the buck current is provided by a semiconductor switch across a solid state laser. A second order filter, formed by the an external inductor and the output capacitance of the buck topology, minimizes AC current ripple to the laser.
US09531154B2 Lift-off method
In an optical device wafer, an optical device layer is formed over a front surface of an epitaxy substrate with the intermediary of a buffer layer composed of a Ga compound containing Ga. After a transfer substrate is joined to the optical device layer of the optical device wafer, a separation layer is formed at a boundary surface between the epitaxy substrate and the buffer layer by performing irradiation with a pulsed laser beam having such a wavelength as to be transmitted through the epitaxy substrate and be absorbed by the buffer layer from a back surface side of the epitaxy substrate. Thereafter, an ultrasonic horn that oscillates ultrasonic vibration is brought into contact with an outer circumferential part of the epitaxy substrate to vibrate the epitaxy substrate, and the epitaxy substrate is separated from the transfer substrate to transfer the optical device layer to the transfer substrate.
US09531152B2 Waveguide laser
A laser includes a wavelength selecting element 14 that selectively reflects laser beams with wavelengths λ=λ0, λ1, λ2, . . . , λn (n≧1) of different laser oscillation modes from among fundamental oscillation wavelengths of laser beams passing through a wavelength conversion element 13, and the wavelength conversion element 13 that converts the laser beams with the wavelengths λ=λ0, λ1, λ2, . . . , λn (n≧1) of different laser oscillation modes reflected by the wavelength selecting element 14 to harmonics. When using a material with a wide gain band as a laser medium 121 of a solid-state laser element 12, a waveguide laser is implemented capable of carrying out high-efficiency wavelength conversion at a plurality of wavelengths within the gain band.
US09531151B2 Method for generating a burst mode by means of switching a Pockels cell
Method for generating a series of laser pulses with a laser assembly, the laser assembly at least having two reflecting members, a laser medium and an electro-optical modulator are disclosed. The laser assembly operates in a light amplifying mode and runs a pulse extraction sequence. The pulse extraction sequence is run by applying a defined voltage change with reference to the amplification voltage, wherein changing of the voltage is adjusted such that at least one intermediate switching state is generated on side of the electro-optical modulator, the intermediate switching state providing a particular change of polarization of the amplified laser radiation by the electro-optical modulator, such that a final switching state is generated on side of the electro-optical modulator by applying a final extraction voltage at the end of the time period.
US09531150B2 Method and system for parity-time symmetric optics and nonreciprocal light transmission
A method and system for optical systems based on parity-time symmetry and its breaking, and for nonreciprocal light transmission in a parity-time symmetric micro-resonator system are provided. The system includes an optical assembly that includes a first dissipative optical system and a second optical system coupled in energy transfer communication with the first optical system. The second optical system is configured to receive a continuous flow of energy from an external source and to transfer energy to the first optical system through the couple wherein the energy transferred to the first optical system from the second optical system is approximately equal to the energy dissipated in the first optical system, where the energy transferred to the first optical system from the second optical system is selectable using at least one of an amount of couple between the first optical system and the second optical system and a gain of the second optical system.
US09531140B2 Coaxial protective device
A protective device for transmitting electromagnetic signals includes an inner conductor that extends coaxially within an outer conductor. To compensate for dimensional tolerances without compromising performance, inner conductor is constructed to include a center pin with a conical end, a plunger pin slidably disposed within an axial bore in the center pin, the plunger pin including a conical end located outside the center pin, and a resilient, expandable, conductive band coaxially mounted onto the conical ends of the center and plunger pins. A gas discharge tube is conductively coupled between the inner and outer conductors to discharge transient voltages transmitted along the inner conductor. To minimize disturbance to the transmission line, the width of the gas discharge tube in the region of contact with the inner conductor is preferably equal to the diameter of the inner conductor. Additionally, the gas discharge tube is preferably greater in length than in width.
US09531132B2 Connector having shielding structure with shield shell and shield cover
A connector has a shielding structure configured by: a shield shell, which has in the front end a tubular shielding portion that surrounds, accommodates, and fixes a resin housing, in the rear end, a barrel portion that crimps and fixes a sheath of a cable, and, between the shielding portion and the barrel portion, an opening portion that is upwardly opened; and a shield cover, which is attached from the upper side to the opening portion of the shield shell. Stoppers that limit rearward movement of the resin housing by causing a plate surface to be butted against a rear end surface of the resin housing that is fixed at the normal position in the shielding portion are disposed in the shield cover.
US09531131B2 Power receiving connector, charging system and communication system
Provided a power receiving connector and a charging system that, during a communication such as inband communication wherein a communication signal is superposed in a control wire incorporated in a charging cable connecting a vehicle and a feed device, can reduce the mutual effect resulting from electromagnetic waves caused by the communication signal transmitted within the vehicle and a device in the vehicle. A power receiving connector to be placed as a vehicle-mounted feeding port is formed by integrating connection terminals internal wirings, a superposition separation element, and a capacitor with a housing as a replaceable unit.
US09531126B2 Electrical receptacle with locking feature
A ganged electrical receptacle unit with locking feature includes a plurality of receptacles and a lock housing. The electrical receptacles are ganged together. The lock housing extends from a front of the receptacles and includes a pair of opposed side supports, a pair of torsion bars, each extending between the opposed side supports, a lock tab extending from each torsion bar toward the receptacle, and a release tab extending from each torsion bar away from the receptacle. A plug may be inserted into the lock housing causing temporary deflection of the lock tabs until the plug is seated in, and electrically connected with, the receptacle, at which point the lock tabs return to their undeflected positions and retain the plug in the receptacle. The release tabs may be depressed to release the lock tabs from the plug, thereby permitting the withdrawal of the plug from the lock housing.
US09531124B2 Electrical plug removal device
An electrical socket having an electrical plug removal device for allowing a user to more easily remove an electrical plug from an electrical socket. The electrical socket resembles a traditional electrical socket having openings into which the prongs of an electrical plug can be inserted. A switch is provided adjacent to the electrical socket, wherein the switch can be actuated in order to release the electrical plug from the electrical socket. In a preferred embodiment, the switch is operably connected to an ejecting device that includes one or more levers positioned within the openings of the electrical socket, wherein the levers are adapted to press against the prongs in order to eject the electrical plug from the socket. The levers can be electrically or mechanically operated depending upon the embodiment.
US09531121B1 Electrical connector system
An electrical connector system includes a connector and a header. The header includes a substantially T-shaped member having a proximal portion substantially rectangular in shape having a first width and a distal portion substantially rectangular in shape having a second width greater than the first width. A first and a second end portion of the distal portions are substantially T-shaped viewed end on. The first and the second end portions include a plurality of guides and shoulders. The connector includes a substantially rectangular member having a proximal portion having a first thickness and a distal portion having a second thickness less than the first thickness on a bottom side of the substantially rectangular member. The proximal portion includes first and second proximal feet and first and second distal feet. Each foot includes a foot retention shoulder and one or more guides.
US09531117B1 Electrical connector structure
An electrical connector structure includes a heat transfer enclosure; a base having an upper and a lower insertion slot and disposed in the enclosure; a horizontal intermediate heat transfer member separating the enclosure into an upper and a lower insertion channel, and having an upper and a lower opening formed thereon; a heat transfer element disposed in the horizontal intermediate heat transfer member, and having an upper and a lower heat transfer surface with a first air passage located therebetween; an upper heat transfer sheet having upper heat transfer spring fingers and disposed in the upper opening and connected to the upper heat transfer surface; and a lower heat transfer sheet having lower heat transfer spring fingers and disposed in the lower opening and connected to the lower heat transfer surface. With these arrangements, the lower insertion channel of the electrical connector structure can have a reduced temperature.
US09531114B2 Waterproof apparatus for cables and cable interfaces
Waterproof apparatus for cables and cable interfaces are provided herein. An exemplary apparatus includes a coupler body that includes a first end configured to releaseably couple with a connector bulkhead and a second end having an opening that is sized to receive a sealing gland, a cavity for receiving the sealing gland, the sealing gland comprising an outer peripheral surface configured to sealingly engage with an inner surface of the cavity, the sealing gland comprising an aperture that is configured to receive a cable.
US09531110B2 Collective connecting structure, guide frame, circuit body holding state guide frame, and collective connecting method
A guide frame is used to collectively connect circuit body side connectors to device side connectors. The guide frame includes circuit body holding parts for holding a circuit body and connector pressing parts that abut on the circuit body side connectors. Each of the circuit body holding parts includes a circuit body placement surface and a projection projecting from the circuit body placement surface. Each of the connector pressing parts includes an elastic part having elasticity in a connector connection direction and a pressing side abutting part.
US09531107B1 Tamper resistant power tap
A power tap including a body having an electrical plug receiving portion, an electrical receptacle portion on the body, a current transmitter connecting the electrical plug receiving portion and the electrical receptacle, and a cavity in the electrical plug receiving portion. The electrical plug receiving portion may further include a cover for opening and closing access to the cavity.
US09531102B2 Electrical power connector and a terminal assembly
An electrical power connector and a terminal assembly are disclosed. The electrical power connector includes a base and a terminal assembly. The terminal assembly includes two conductive terminals, two reinforcing terminals and at least one detection terminal. L-shaped pressing portions of the two reinforcing terminals together clamp arc protruding parts of the two conductive terminals. Meanwhile, the detection terminal can detect an insertion state of a butt connector to timely determine forming a power loop circuit. The terminal assembly of the present invention has characteristics of high electrical conductivity, high elasticity and high security.
US09531097B2 Electrical connector
An electrical connector for mating with a mating connector includes an insulating body and multiple terminals. The insulating body has a base, a tongue protruding forward from the base, and multiple terminal slots run from the tongue backward and through the base. The terminals are disposed in the terminal slots respectively. Each of the terminals has a retaining portion retained at the base, a contact portion extending forward from one end of the retaining portion to the tongue, and an urging portion disposed between the retaining portion and the contact portion. The urging portion is higher than an upper surface of the tongue. When the electrical connector mates with the mating connector, the mating connector presses against the urging portion downward, such that the contact portion electrically contacts the mating connector.
US09531092B2 Terminal and connection structure using terminal
A terminal includes a body portion formed in a major arc cylindrical shape in which a gap is formed between two edges in the circumferential direction or an overlapping cylindrical shape in which the two edges in the circumferential direction overlap each other, such that a cylindrical space is formed inside the body portion, and locking portions disposed on at least one side out of the back side and the front side in the insertion direction of the body portion and having base pieces that extend from the body portion toward the back side in the insertion direction or the front side in the insertion direction and locking pieces that are provided on the base pieces. The body portion has at least one projecting portion projecting toward the outside. A connection structure includes the terminal, a connected object and a mounting member. It is possible to cause the terminal to which the connected object is attached to stand on its own relative to the mounting member, and to ensure the thickness of a solder layer between the terminal with the connected object and a through hole.
US09531090B2 Coaxial cable connectors with conductor retaining members
Coaxial cables and coaxial cable connectors are disclosed. In one embodiment, a connector includes a body portion having a first end and a second end and defining a bore, a contact member having a circumferential portion and at least one protruding member, an inner sleeve, a rotatable coupling nut, and a conductor retaining member. The at least one protruding member protrudes from the circumferential portion toward the second end of the body portion and within the bore. The rotatable coupling nut is rotatably coupled to the inner sleeve and electrically coupled to the contact member. The conductor retaining member is centrally disposed within the inner sleeve, and is configured to receive an inner conductor of the co-axial cable such that the inner conductor is free to pass through the conductor retaining member in a first direction, and restricted from passing through the conductor retaining member in a second direction.
US09531089B2 Terminal connection structure
A terminal connection structure is proposed in which a bolt tightening terminal is set on a terminal mounting portion and is fastened with a connecting bolt that is tightened to a nut of the terminal mounting portion. The terminal mounting portion is provided with a displacement limiting portion. If the bolt tightening terminal, set on a terminal mounting portion, is disposed in a proper mounting position in which a bolt insertion hole and a threaded hole are aligned on the same center axis, the bolt tightening terminal is adapted not to interfere with the displacement limiting portion. If the bolt tightening terminal is displaced from the proper mounting position, the bolt tightening terminal is adapted to interfere with the displacement limiting portion to limit the displacement from the proper mounting position.
US09531087B2 MM wave antenna array integrated with cellular antenna
Wireless electronic devices may include a millimeter Wave (mmW) antenna array integrated with a cellular antenna. The devices may also include a package or module on the cellular antenna that integrates the mmW antenna array and an mmW circuit. The devices may also include a grounding element that includes an mmW antenna control and a power trace.
US09531083B2 Supply network for a group antenna
A group antenna has at least two transducers disposed offset from one another. A network is provided to supply the transducers. The network comprises coaxial cables running between a distributor and/or summation circuit and the access, connection, and/or supply points of the associated transducer. The network comprises at least two different types of coaxial cable characterized by different phase velocities.
US09531078B2 Wireless communication apparatus
There is provided a wireless communication apparatus that includes (a) a printed circuit board, (b) a radio frequency circuit installed on the printed circuit board, and (c) an antenna element that is integrated onto the printed circuit board and electrically coupled to the radio frequency circuit via a printed conductor.
US09531074B2 Planar inverted F antenna with improved feeding line connection
A planar inverted F antenna has a ground conductive plate and a main conductive plate that are short-circuited by a short circuit member. The main conductive plate connects to a feeding line for feeding power to the antenna and includes opposite side ends, a base extending from one side end to a prescribed position in the direction toward the other side end, and a slit extending from the other side end of the main conductive plate up to the prescribed position to form a microstrip line that is connected to the feeding line and at least one excitation conductive plate spaced apart from the microstrip line. The prescribed position includes a feeding point to which power is supplied from the feeding line via the microstrip line having a width such that an input impedance of the antenna at the feeding point and a characteristic impedance become Z.
US09531068B2 Efficient loop antenna system and method
An antenna including a conductive loop having a first top surface portion, the conductive loop having a first edge portion interrupted by a gap defining a feed point, a conductive strip having a second top surface, the conductive loop lying in a plane defined by the second top surface, the conductive strip having a second edge portion extending between first and second opposing distal ends, the second edge portion being spaced from the first edge portion, and the second edge portion extending along the first edge portion at a substantially constant distance from the first edge portion, and wherein the conductive strip is electrically isolated from the conductive loop and is structurally configured and positioned relative to the conductive loop to adjust an input impedance of the conductive loop.
US09531066B2 Antenna pattern frame and electronic device including the same
There is provided an antenna pattern frame including: a radiator including an antenna pattern part transmitting and receiving signals and a connection terminal part electrically connecting the antenna pattern part and a circuit board to each other; and a radiator frame provided by performing injection molding on the radiator while allowing the antenna pattern part to be exposed to one surface thereof and allowing the connection terminal part to be exposed to the other surface thereof, wherein the antenna pattern part is provided with a support part protruding outwardly from the antenna pattern part and bent in a direction toward the radiator frame to be disposed inwardly of the radiator frame.
US09531065B2 Tunable serpentine antenna assembly
An antenna assembly is mountable to a craft. The craft has a power source. The antenna assembly includes a base securable to the craft. A monopole post extends out from the base. A plurality of voltage lines extend through the base and the monopole post. The antenna assembly also includes a plurality of capacitors operatively connected to the monopole post. Each of the capacitors is electrically connected to each of the plurality of voltage lines. The plurality of capacitors extend through serpentine paths distributing electrical charge across the plurality of capacitors to vary reactance properties of the antenna assembly.
US09531058B2 Loosely-coupled radio antenna apparatus and methods
A multiband internal antenna apparatus and methods of tuning and utilizing the same. In one embodiment, the antenna configuration is used within a handheld mobile device (e.g., cellular telephone or smartphone). The device enclosure is fabricated from a conductive material and has two parts: the main portion, housing the device electronics and ground plane, and the antenna cap, which substantially envelops a directly fed radiator structure of the antenna. Electromagnetic coupling of the cap portion to the device feed effects formation of a parasitic antenna radiator in a lower frequency band. The cap portion is separated from the main portion by a narrow gap, extending along circumference of the device, and is grounded at a location selected to cause desired resonance and to widen antenna bandwidth. In one implementation, a second parasitic radiator is disposed proximate the directly feed radiator to further expand antenna frequency bands of operation.
US09531053B2 Directional coupler and wireless communication device
A directional coupler including a main line having an input terminal and an output terminal, and a sub-line having a coupling terminal and an isolation terminal, the main line, the sub-line, the input terminal, the output terminal, the coupling terminal and the isolation terminal being disposed within a laminate, wherein the main line and the sub-line extend in a loop shape in parallel with and spaced apart from each other by a gap such that electromagnetic coupling is generated therebetween and such that the main line is positioned outside the sub-line on a coupling layer, the input terminal, the output terminal, the coupling terminal and the isolation terminal are disposed outside the main line, and the main line is interposed between the output terminal and the sub-line.
US09531046B2 Battery pack
A battery pack has a casing, electric fans, battery temperature thermistors and a battery management unit. The casing accommodates the battery cell stacks. The electric fans generate an air circulation in the inside chamber of the casing. The thermistors detect a temperature of the battery cells. At least one of the thermistors is arranged in each of the battery cell stack to detect a temperature of a battery cell arranged at a specific location in a battery cell stacking direction. At least one of the thermistors arranged in one battery cell stack in a pair of the battery cell stacks selected from all of the battery cell stacks detects a temperature of the battery cell arranged at a different location in the battery cell stacking direction from a location of any battery cell arranged in the other battery cell stack in the pair of the battery cell stacks.
US09531043B2 Electrochemical cell unit for a secondary battery
The present invention relates to an electric cell unit for a secondary battery as well as to such a secondary battery module. The electric cell unit comprises: a first electric cell (12) enclosed by a first casing (13), a second electric cell (14) enclosed a second casing (15), wherein at least one of first and second casings (13, 15) comprises a recessed portion (16, 18) extending along a side edge (11) thereof to form a receptacle (30), which is adapted to receive at least one thermal transfer element (28).
US09531042B2 Battery target temperature methods and systems
Methods and systems for determining a target temperature and/or adjusting a temperature associated with a battery, such as a vehicle battery. In some implementations of such methods, a temperature-scaled battery capacity of at least a portion of a battery may be determined at a measured temperature. The temperature-scaled battery capacity may be compared with a capacity threshold and, upon determining that the temperature-scaled battery capacity is below the capacity threshold, a target battery temperature for the at least a portion of the battery may be determined and/or set.
US09531038B2 System and method of cell block voltage analytics to improve balancing effectiveness and identify self-discharge rate
A battery management unit includes a cell balancing module to perform cell balancing between a cells in a battery cell stack, and a controller operable to determine, during a first charge cycle, that the first cell has reached an over-voltage threshold before the second cell, to determine, during a discharge cycle, that the first cell has reached an under-voltage threshold before the second cell, to identify the first cell as having a lower capacity than the second cell based upon the determination that the first cell reached the over-voltage threshold before the second cell and upon the determination that the first cell reached the under-voltage threshold before the second cell, and to prevent, during another charge cycle, the cell balancing module from performing cell balancing on the first cell based upon the first cell being identified as having the lower capacity than the second cell.
US09531035B2 Lithium battery, method for manufacturing a lithium battery, integrated circuit and method of manufacturing an integrated circuit
A lithium battery includes a cathode, an anode integrally formed within a silicon substrate, wherein a surface portion of the silicon substrate is patterned to form a plurality of sub-structures, and an electrolyte.
US09531032B2 Battery case for secondary battery
Disclosed herein is a battery case including a receiving part having an electrode assembly mounted therein, wherein the receiving part, which is formed by deforming a sheet type base material, is configured to have a stair-like structure in which at least one corner and/or surface forming a shape of the receiving part is deformed.
US09531028B2 Redox flow battery
A redox flow battery charged and discharged by supply of a positive electrode electrolyte stored in a positive electrode tank and a negative electrode electrolyte stored in a negative electrode tank to a battery element, in which the positive electrode electrolyte contains a Mn ion as a positive electrode active material, and the positive electrode tank includes a positive electrode charging pipe opening to a position close to a liquid level of the positive electrode electrolyte in the positive electrode tank, and a positive electrode discharging pipe opening to a position close to the bottom of the positive electrode tank. This redox flow battery can include a stirring mechanism for stirring the electrolytes in the tanks, and can include a connection pipe connecting the positive electrode tank to the negative electrode tank.
US09531025B2 Membrane-electrode assembly, manufacture method thereof, and solid polymer fuel cell
A membrane-electrode assembly including an electrolyte membrane (1), a pair of catalyst layers (3, 3) facing each other sandwiching the electrolyte membrane (1), and a pair of gas diffusion layers facing each other sandwiching the electrolyte membrane (1) and the pair of catalyst layers (3, 3), wherein at least one of the pair of catalyst layers (3, 3) includes unwoven cloth (6A) including fiber-like structures (6) each having proton conduction performance, and wherein a portion of the unwoven cloth is buried in the electrolyte membrane (1) adjacent to the catalyst layer (3) including the unwoven cloth (6A).
US09531024B2 Distributed hydrogen extraction system
A hydrogen extraction system is provided. The extraction system can comprise a compressor for compressing a gas mixture comprising hydrogen and a desulfurization unit for receiving the compressed gas mixture. The system can also comprise a hydrogen-extraction device for receiving a reduced-sulfur gas mixture and a hydrogen storage device for receiving an extracted hydrogen gas. A method of extracting hydrogen from a gas mixture comprising natural gas and hydrogen, and a method of determining an energy price are also provided.
US09531019B2 Fuel cell system and method for controlling the same
Disclosed is a fuel cell system and a method for controlling the fuel cell system. In the method, an external air temperature and a fuel cell temperature are monitored. When a vehicle having the fuel cell system mounted therein is keyed on, a shut-off duration of the fuel cell system, a maximum external air temperature for the shut-off duration and a maximum fuel cell temperature for the shut-off duration are calculated. A gas composition of a fuel cell at a key-on time is estimated using the shut-off duration, the maximum external air temperature and the maximum fuel cell temperature. An ignition condition of the fuel cell system is set based on the estimated gas composition. Ignition of the fuel cell system is performed based on the set ignition condition.
US09531013B2 Fuel cell system with interconnect
The present invention includes a fuel cell system having a plurality of adjacent electrochemical cells formed of an anode layer, a cathode layer spaced apart from the anode layer, and an electrolyte layer disposed between the anode layer and the cathode layer. The fuel cell system also includes at least one interconnect, the interconnect being structured to conduct free electrons between adjacent electrochemical cells. Each interconnect includes a primary conductor embedded within the electrolyte layer and structured to conduct the free electrons.
US09531007B2 Production apparatus and production method for electric storage material
A production apparatus for an electric storage material includes a dissolution device that dissolves a thickener in a solvent by applying vibration to the solvent, and a kneading device that kneads a solution of the thickener having an adjusted viscosity and an active substance. The thickener is dissolved in the solvent, and a powder of the active substance and the like are dispersed and kneaded in the solution of the thickener having the adjusted viscosity. Thus, kneading can be performed in a short time, and damage to the active substance can be suppressed.
US09531000B2 Battery cell, battery cell module, method for producing a battery cell module, battery and motor vehicle
A battery cell has at least one terminal configured to electrically connect the battery cell. The at least one terminal has at least two connection devices. Each of the at least two connection devices is configured to electrically connect the at least one terminal to one cell connector.
US09530998B2 High voltage battery for vehicle
A high voltage battery for a vehicle includes a first plate, a second plate, and a third plate coupled to be folded with each other and have cell insertion spaces formed therebetween. A bus bar includes a first lead which is inserted into a side boundary of the first plate and the second plate to contact a tab of a cell, a second lead which is inserted into a side boundary of the second plate and the third plate to contact a tab of another cell, and a connector which connects the lead to the second lead.
US09530995B2 Battery module
This battery module comprises a secondary battery, a battery holder, a cover member and a pair of extended parts. The secondary battery comprises an electrode assembly, a case and an open valve. The cover member has a main body that faces the open valve. The pair of extended parts are provided between the case and the main body of the cover member. The open valve is positioned between the pair of extended parts. The case, the main body of the cover member and the pair of extended parts form a flow path for a gas that is discharged from the open valve. The battery holder has a lock projection that is locked to the main body of the cover member.
US09530986B2 Laminated substrate, light-emitting device, and method for producing light-emitting device
A light-emitting device includes a transparent substrate, a light-emitting element arranged on or above one main surface of the transparent substrate, and a porous layer arranged on or above the other main surface of the transparent substrate, the porous layer being an organic material layer having a plurality of pores. Inner surfaces of some pores among the plurality of pores may be exposed at a main surface of the porous layer opposite to a side on which the transparent substrate lies. A gas may be present in the pores the inner surfaces of which are exposed.
US09530983B2 Sintering method and display device packaging method using the same
A sintering method includes defining a closed pattern having at least one arcuate section. A substance is applied on a substrate along the closed pattern and is sintered along the closed pattern in a first rectilinear direction. The sintering is finished in a second rectilinear direction along the closed pattern. A display device packaging method includes defining a closed pattern having at least one arcuate section. Frit is applied on a substrate of a display device along the closed pattern. A cover plate is provided on the substrate. The frit is sintered along the closed pattern. The sintering is finished in a second rectilinear direction. Then, the cover plate and the substrate of the display device are packaged.
US09530978B2 Hollow white composite quantum dot preparation method, display panel and display device
The embodiments of the invention disclose a hollow white composite quantum dot preparation method, a display panel and a display device. In the preparation method, unicolor quantum dots of different colors are prepared into corresponding unicolor quantum dot emulsions through an emulsion polymerization technique, dissolved silicon dioxide nano particles are used as a seed solution, the individual unicolor quantum dot emulsions are dropped in the seed solution in sequence, such that the surfaces of the silicon dioxide nano particles are coated with the unicolor quantum dots in the individual unicolor quantum dot emulsions in sequence according to the dropping order so as to obtain white composite quantum dots, and finally, the silicon dioxide nano particles in the white composite quantum dots are removed to obtain hollow white composite quantum dots. The hollow white composite quantum dot particles obtained by the preparation method are controllable in particle size and uniform in size, and the problems of low quantum efficiency, poor stability of quantum dots, and the like are solved; besides, the color gamut of the hollow white composite quantum dots can be adjusted, so that the applicability is high, and the application range is wide; in addition, the preparation method is simple, and a batch production is facilitated.
US09530975B2 Method of making an organic thin film transistor
In one aspect, organic thin film transistors are described herein. In some embodiments, an organic thin film transistor comprises a source terminal, a drain terminal and a gate terminal; a dielectric layer positioned between the gate terminal and the source and drain terminals; and a vibrationally-assisted drop-cast organic film comprising small molecule semiconductor in electrical communication with the source terminal and drain terminal, wherein the transistor has a carrier mobility (μeff) of at least about 1 cm2/V·s.
US09530974B2 Copper complexes for optoelectronic applications
The invention relates to an optoelectronic component having a copper(I) complex of the formula: wherein X is independently selected from Cl, Br and I; N*∩E or E∩N* is a bidentate ligand connected to a first Cu atom via an N atom and connected to a second Cu atom via an E group, or a monodentate ligand connected to a Cu atom via an E group, wherein E is R2As or R2P, wherein R is selected from alkyl, aryl, alkoxy, and phenoxy; N* is a part of an aromatic group comprising an imine functional group, wherein the aromatic group is selected from pyridyl, pyrimidyl, pyridazinyl, triazinyl, oxazolyl, thiazolyl, imidazolyl, and fused N-heteroaromatics, and wherein the imine functional group comprises the N atom double bonded to a carbon atom of the aromatic group; and ∩ is a carbon atom, which is likewise part of the aromatic group, connected to the N atom of said aromatic group and also connected to the E group via the As or P atom of the E group.
US09530970B2 Benzimidazole compound, organic photoelectric device including the same, and display element including the same
A benzimidazole compound, an organic photoelectric device, and a display element, the benzimidazole compound being represented by the following Chemical Formula 1:
US09530969B2 Material for organic electroluminescence device and organic electroluminescence device
An organic electroluminescence device employing a specific biscarbazole derivative having a cyano group as a first host and a compound having both a carbazole structure and a nitrogen-containing aromatic heteroring as a second host. The organic electroluminescence device has a prolonged lifetime.
US09530967B2 Heterocyclic compound and organic light-emitting diode including the same
A heterocyclic compound includes a compound represented by Formula 1.
US09530966B2 Polymer compound and light emitting device using the same
A polymer compound comprising a constituent unit represented by the formula (1′) and a constituent unit having a mono-valent cross-linkable group: wherein R1′ to R4′ represent an alkyl group, an alkoxy group, an aryl group, an aryloxy group, a mono-valent heterocyclic group, R5 to R10 represent a hydrogen atom, an alkyl group, an alkoxy group, an aryl group, an aryloxy group, a mono-valent heterocyclic group, RA and RB represent a hydrogen atom, an alkyl group, an aryl group, a mono-valent heterocyclic group, and Ar1 and Ar2 represent an arylene group, a di-valent heterocyclic group.
US09530962B2 Patterning method for OLEDs
Methods of fabricating a device having laterally patterned first and second sub-devices, such as subpixels of an OLED, are provided. Exemplary methods may include depositing via organic vapor jet printing (OVJP) a first organic layer of the first sub-device and a first organic layer of the second sub-device. The first organic layer of the first sub-device and the first organic layer of the second sub-device are both the same type of layer, but have different thicknesses. The type of layer is selected from an ETL, an HTL, an HIL, a spacer and a capping layer.
US09530959B2 Magnetic tunnel junctions
A method of forming a magnetic electrode of a magnetic tunnel junction comprises forming non-magnetic MgO-comprising material over conductive material of the magnetic electrode being formed. An amorphous metal is formed over the MgO-comprising material. Amorphous magnetic electrode material comprising Co and Fe is formed over the amorphous metal. The amorphous magnetic electrode material is devoid of B. Non-magnetic tunnel insulator material comprising MgO is formed directly against the amorphous magnetic electrode material. The tunnel insulator material is devoid of B. After forming the tunnel insulator material, the amorphous Co and Fe-comprising magnetic electrode material is annealed at a temperature of at least about 250° C. to form crystalline Co and Fe-comprising magnetic electrode material from an MgO-comprising surface of the tunnel insulator material. The crystalline Co and Fe-comprising magnetic electrode material is devoid of B. Other method and non-method embodiments are disclosed.
US09530957B2 Magnetic sensor
A magnetic sensor includes magnetoresistive elements and a soft magnetic body. The magnetoresistive elements have multi layers including a magnetic layer and a nonmagnetic layer on a substrate, and exert a magnetoresistance effect. The soft magnetic body is electrically disconnected with the magnetoresistive elements, and converts a vertical magnetic field component from the outside into a magnetic field component in a horizontal direction so as to provide the magnetoresistive elements with the horizontally converted magnetic field component. The magnetoresistive elements have a pinned magnetic layer having a fixed magnetization direction and a free magnetic layer having a variable magnetization direction. The free magnetic layer is stacked on the pinned magnetic layer with a nonmagnetic layer interposed between the free magnetic layer and the pinned magnetic layer. The magnetization directions of the pinned magnetic layers of the magnetoresistive elements are the same direction. The magnetoresistive elements form a bridge circuit.
US09530954B2 Piezoelectric element
A piezoelectric element is a laminated type piezoelectric element including a plurality of piezoelectric layers laminated on each other; and an internal electrode layer disposed between adjacent piezoelectric layers. In the piezoelectric element, coating layers are disposed on a side surface of the piezoelectric element so as to cover at least an effective portion of the internal electrode layer that is exposed at the side surface. The coating layers contiguously extend from the side surface of the piezoelectric element to at least one of upper and lower surfaces of the piezoelectric element. A step is formed at the at least one of upper and lower surface of the piezoelectric element by the coating layers formed at an edge region.
US09530953B2 Vibration-type actuator, image pickup apparatus, and stage
A vibration-type actuator includes a supporting mechanism functioning such that a reaction force from a base against a pressing force from a driven member to an elastic member is dispersed to a vibrating portion and a supported portion of the elastic member. The supported portion is supported by the base with a vibration-isolating member interposed therebetween.
US09530952B2 Powder metallurgical production of a thermoelectric component
The invention relates to a method for producing a thermoelectric component or at least a semifinished version thereof, in which at least one thermoelectric active material in dry powder form is introduced into at least some of the holes of a perforated template. It addresses the problem of specifying a method which can be conducted in a particularly economically viable manner. The problem is solved by virtue of the active material remaining in the holes of the template, and the template filled with active material becoming a constituent of the thermoelectric component produced.
US09530947B2 Lens and light emitting module for surface illumination
A light emitting module includes a circuit board, light emitting elements disposed on the circuit board, each light emitting element including light emitting diode chips and a wavelength conversion layer coated on the light emitting diode chips, and a lens disposed on the light emitting elements and configured to diffuse light emitted from the light emitting elements. The lens includes a concave part having a light incident surface and an upper surface through which the light incident on the lens is emitted, and at least one of the light incident surface and the upper surface includes sections disposed at least 15° from a central axis and sequentially connected in a first direction.
US09530944B2 High color-saturation lighting devices with enhanced long wavelength illumination
A lighting device including a blue solid state emitter, at least one yellow-green or green lumiphoric material, and at least one red or red-orange solid state emitter provides high color saturation, preferably in combination with a high R9-prime (modified R9) color rendering value, with such condition(s) being obtainable with at least one of (i) a red emitter peak wavelength of at least 630 nm, (ii) a green lumiphoric material having a narrow peak wavelength, and (iii) a blue shifted green color point within a specified region of a 1931 CIE chromaticity diagram, and obtainable without requiring a notch filtering material. Aggregate emissions may have a CCT in a range of from 2000K to 5000K.
US09530940B2 Light-emitting device with high light extraction
A light-emitting device, comprises a light-emitting stacked layer comprising a first conductivity type semiconductor layer; a light-emitting layer formed on the first conductivity type semiconductor layer; and a second conductivity type semiconductor layer formed on the light-emitting layer and comprising a first plurality of cavities; a first planarization layer formed on a first part of the second conductivity type semiconductor layer; a first transparent conductive oxide layer formed on the first planarization layer and on a second part of the second conductivity type semiconductor layer, the first transparent conductive oxide layer including a first portion in contact with the first planarization layer and including a second portion in contact with the upper surface of the second conductivity type semiconductor layer; a first electrode formed on the first portion; and a first reflective metal layer formed between the first transparent conductive oxide layer and the first electrode.
US09530938B2 Semiconductor light-emitting device and method of forming electrode
A semiconductor light-emitting device having an electrode that can be manufactured by a simple method and is unlikely to deteriorate, and a method for forming the electrode are provided. The semiconductor light-emitting device according to the present invention has a semiconductor layered structure having a light-emitting layer that emits light by supplying electric power and an electrode formed on the semiconductor layered structure. The electrode has a reflection layer that reflects light exiting from the light-emitting layer, a barrier layer formed on the upper side and side surface of the reflection layer, and a pad layer formed only on the top surface of the barrier layer.
US09530936B2 Light emitting diode having vertical topology and method of making the same
An LED having vertical topology and a method of making the same is capable of improving a luminous efficiency and reliability, and is also capable of achieving mass productivity. The method includes forming a semiconductor layer on a substrate; forming a first electrode on the semiconductor layer; forming a supporting layer on the first electrode; generating an acoustic stress wave at the interface between the substrate and semiconductor layer, thereby separating the substrate from the semiconductor layer; and forming a second electrode on the semiconductor layer exposed by the separation of the substrate.
US09530933B2 GaN base light-emitting diode and manufacturing method therefor using mechanical post-processing
Disclosed are GaN based light emitting devices and methods of manufacturing the same using post-mechanical treatment. The GaN based light emitting device includes first and second electrodes, and a flexible substrate which are sequentially stacked, an n-type GaN layer, an activation layer, and a p-type GaN layer interposed between the first and second electrodes and forming a core-shell structure, and a buried layer interposed between the flexible substrate and the first electrode, wherein the first electrode and the core-shell structure are buried in the buried layer.
US09530929B2 Lift-off method
A lift-off method transfers an optical device layer in an optical device wafer to a transfer substrate. The optical device layer is formed on the front side of an epitaxy substrate through a buffer layer. A composite substrate is formed by bonding the transfer substrate through a bonding agent to the front side of the optical device layer, thereby forming a composite substrate. The buffer layer is broken up by applying a laser beam having a wavelength transmissive to the epitaxy substrate and absorptive to the buffer layer from the back side of the epitaxy substrate to the buffer layer after performing the composite substrate forming step, thereby breaking the buffer layer. An optical device layer is transferred by peeling off the epitaxy substrate from the optical device layer after performing the buffer layer breaking step, thereby transferring the optical device layer to the transfer substrate.
US09530921B2 Multi-junction solar cell
A multi-junction solar cell comprising a high-crystalline silicon solar cell and a high-crystalline germanium solar cell. The high-crystalline silicon solar including a first p-doped layer and a n+ layer and the high-crystalline germanium solar cell including a second p layer and a heavily doped layer. The multi-junction solar cell can also be comprised of a heavily doped silicon layer on a non-light receiving back surface of the high-crystalline germanium solar cell and a tunnel junction between the high-crystalline silicon solar cell and the high-crystalline germanium solar cell.
US09530920B2 Photoelectric conversion device
A photoelectric conversion device which is a semiconductor device comprising a first conductive layer having a first conductivity type; a second conductive layer formed on the first conductive layer and having a second conductivity type; and a photosensitizing layer formed between the first conductive layer and the second conductive layer, wherein charge carriers generated by photoelectric conversion in the photosensitizing layer are freely movable to at least one of the first conductive layer and the second conductive layer.
US09530919B2 Solar cell module
A solar cell module includes a solar cell string including solar cells disposed in an arrangement direction and at least two wiring members provided to extend along the arrangement direction in order to electrically connect the solar cells. The at least two wiring members include a first wiring member disposed at a first position where a distance between the solar cells adjacent to each other is short and a second wiring member disposed at a second position where the distance between the solar cells adjacent to each other is long. The respective first and second wiring members include bent portions between the solar cells. Between edge portions of the solar cells facing each other, the first wiring member has a slope whose maximum value is larger than the maximum value of a slope of the second wiring member.
US09530916B2 Corrugated panel mounting bracket
A mounting bracket (210) for a corrugated panel (202) is disclosed. The mounting bracket (210) includes an upper wall (216) in the form of an at least substantially flat surface for supporting various types of attachments. This upper wall (216) is disposed above and spaced from a panel valley engagement section (232) for engaging a panel valley (208) of the corrugated panel (202). A panel crown engagement section (224) is positioned on each side of the panel valley engagement section (232) for engaging different panel crowns (204) of a corrugated panel (202). An attachment may be secured relative to the mounting bracket (210) utilizing a mounting hole (218) on the bracket upper wall (216).
US09530909B2 Photodiode and ultraviolet sensor
A p-type semiconductor layer containing a solid solution of NiO and ZnO as a principal component is joined to an n-type semiconductor layer containing ZnO as a principal component, and the p-type semiconductor layer contains a rare earth element R. The content of the rare earth element R is preferably 0.001 to 1 mole with respect to 100 moles of the principal component. Further, Y, La, Ce, Pr, Nd, Sm, Eu, Gd, Tb, Dy, Ho, Er, Tm and Yb can be used as the rare earth element, for example. An internal electrode 4 is preferably principally composed of a composite oxide containing the rare earth element R and Ni. Thereby, photoelectric conversion efficiency can be improved, and ultraviolet light can be directly detected as a photocurrent without externally disposing a power source circuit.
US09530906B2 Methods to introduce sub-micrometer, symmetry-breaking surface corrugation to silicon substrates to increase light trapping
Provided is a method for fabricating a nanopatterned surface. The method includes forming a mask on a substrate, patterning the substrate to include a plurality of symmetry-breaking surface corrugations, and removing the mask. The mask includes a pattern defined by mask material portions that cover first surface portions of the substrate and a plurality of mask space portions that expose second surface portions of the substrate, wherein the plurality of mask space portions are arranged in a lattice arrangement having a row and column, and the row is not oriented parallel to a [110] direction of the substrate. The patterning the substrate includes anisotropically removing portions of the substrate exposed by the plurality of spaces.
US09530904B2 High temerature, hermetically sealed, triaxial mount for a light sensitive element
A sensor assembly for a flame sensor apparatus includes a photodiode that generates a current. The sensor assembly includes a seal assembly supporting the photodiode. The seal assembly includes an inner conductor defining an inner conductor end. The inner conductor includes an inner conductor surface disposed at the inner conductor end. The photodiode is attached to the inner conductor end of the inner conductor and to a middle conductor end of a middle conductor. The photodiode is electrically connected to the inner conductor surface. The seal assembly is triaxial so as to protect the current generated by the photodiode. The seal assembly withstands temperatures up to or greater than about 325° C. The seal assembly forms a hermetic barrier that, with the photodiode supported within a sealed volume, limits the passage of materials/gases through the seal assembly.
US09530903B2 Solar cell manufacturing method, solar cell module manufacturing method, and solar cell module
This solar cell module (10) is manufactured by connecting in series with a wiring material (15) multiple solar cells including at least two types of solar cells (11A, 11B) having different electrode structures, and covering the same with a first protective member (12) and a second protective member (13). This solar cell is manufactured by producing a photoelectric conversion unit, measuring characteristic values of the photoelectric conversion unit, selecting electrode structure on the basis of said characteristic values, and forming an electrode on the photoelectric conversion unit.
US09530893B2 Semiconductor device, measurement apparatus, and measurement method of relative permittivity
The field of an oxide semiconductor has been attracted attention in recent years. Therefore, the correlation between electric characteristics of a transistor including an oxide semiconductor layer and physical properties of the oxide semiconductor layer has not been clear yet. Thus, a first object is to improve electric characteristics of the transistor by control of physical properties of the oxide semiconductor layer. A semiconductor device including at least a gate electrode, an oxide semiconductor layer, and a gate insulating layer sandwiched between the gate electrode and the oxide semiconductor layer, where the oxide semiconductor layer has the relative permittivity of equal to or higher than 13 (or equal to or higher than 14), is provided.
US09530892B2 Semiconductor device and method for manufacturing the same
A semiconductor device includes a transistor including a gate electrode over a substrate, a gate insulating film covering the gate electrode, a multilayer film overlapping with the gate electrode with the gate insulating film provided therebetween, and a pair of electrodes in contact with the multilayer film, and an oxide insulating film covering the transistor. The multilayer film includes an oxide semiconductor film and an oxide film containing In or Ga, the oxide insulating film contains more oxygen than that in the stoichiometric composition, and in the transistor, by a bias-temperature stress test, threshold voltage does not change or the amount of the change in a positive direction or a negative direction is less than or equal to 1.0 V, preferably less than or equal to 0.5 V.
US09530890B1 Parasitic capacitance reduction
A method of making a semiconductor device includes forming a gate on a substrate; removing an end portion of the gate to form a recess at an end of the gate; depositing a low-k material in the recess such that an air gap is formed in the low-k material; removing a portion of the low-k material; depositing an insulating material on the low-k material that was recessed to form a bilayer insulating stack; and forming a source/drain contact on an active area positioned on the substrate and alongside the gate.
US09530887B1 Fin-type field effect transistor device and manufacturing method thereof
A fin-type field effect transistor device including a substrate, a gate stack structure, spacers and source and drain regions is described. The spacers includes first and second spacers and a first height of the first spacer is larger than a second height of the second spacer. A dielectric layer disposed on the gate stack structure includes a contact opening exposing the source and drain regions, the first and second spacers and a portion of the gate stack structure. A sheath structure is disposed within the contact opening and the sheath structure is in contact with the first and second spacers and the exposed portion of the gate stack structure without covering the source and drain regions. A metal connector is disposed within the sheath structure and connected to the source and drain regions.
US09530882B1 Trench MOSFET with shielded gate and diffused drift region
A trench MOSFET with diffused drift region and closed cell layout having shielded gate is disclosed, wherein closed gate trenches surrounding a deep trench in each unit cell and the shielded gate disposed in the deep trench. Trenched source-body contacts are formed between the closed gate trenches and the deep trench. The deep trench has square, rectangular, circle or hexagon shape.
US09530878B2 III-N material structure for gate-recessed transistors
III-N transistors with recessed gates. An epitaxial stack includes a doped III-N source/drain layer and a III-N etch stop layer disposed between a the source/drain layer and a III-N channel layer. An etch process, e.g., utilizing photochemical oxidation, selectively etches the source/drain layer over the etch stop layer. A gate electrode is disposed over the etch stop layer to form a recessed-gate III-N HEMT. At least a portion of the etch stop layer may be oxidized with a gate electrode over the oxidized etch stop layer for a recessed gate III-N MOS-HEMT including a III-N oxide. A high-k dielectric may be formed over the oxidized etch stop layer with a gate electrode over the high-k dielectric to form a recessed gate III-N MOS-HEMT having a composite gate dielectric stack.
US09530876B2 Strained semiconductor nanowire
At least one semiconductor nanowire laterally abutted by a pair of semiconductor pad portions is formed over an insulator layer. Portions of the insulator layer are etched from underneath the at least one semiconductor nanowire such that the at least one semiconductor nanowire is suspended. A temporary fill material is deposited over the at least one semiconductor nanowire, and is planarized to physically expose top surfaces of the pair of semiconductor pad portions. Trenches are formed within the pair of semiconductor pad portions, and are filled with stress-generating materials. The temporary fill material is subsequently removed. The at least one semiconductor nanowire is strained along the lengthwise direction with a tensile strain or a compressive strain.
US09530864B2 Junction overlap control in a semiconductor device using a sacrificial spacer layer
Approaches for providing junction overlap control in a semiconductor device are provided. Specifically, at least one approach includes: providing a gate over a substrate; forming a set of junction extensions in a channel region adjacent the gate; forming a set of spacer layers along each of a set of sidewalls of the gate; removing the gate between the set of spacer layers to form an opening; removing, from within the opening, an exposed sacrificial spacer layer of the set of spacer layers, the exposed sacrificial spacer layer defining a junction extension overlap linear distance from the set of sidewalls of the gate; and forming a replacement gate electrode within the opening. This results in a highly scaled advanced transistor having precisely defined junction profiles and well-controlled gate overlap geometry achieved using extremely abrupt junctions whose surface position is defined using the set of spacer layers.
US09530860B2 III-V MOSFETs with halo-doped bottom barrier layer
Techniques for controlling short channel effects in III-V MOSFETs through the use of a halo-doped bottom (III-V) barrier layer are provided. In one aspect, a method of forming a MOSFET device is provided. The method includes the steps of: forming a III-V barrier layer on a substrate; forming a III-V channel layer on a side of the III-V barrier layer opposite the substrate, wherein the III-V barrier layer is configured to confine charge carriers in the MOSFET device to the III-V channel layer; forming a gate stack on a side of the III-V channel layer opposite the III-V barrier layer; and forming halo implants in the III-V barrier layer on opposite sides of the gate stack. A MOSFET device is also provided.
US09530858B2 Nitride semiconductor device and method of manufacturing the same
Disclosed are an npn-type bipolar transistor as a nitride semiconductor device having good characteristics, and a method of manufacturing the same. A so-called pn epitaxial substrate has a structure wherein an n-type collector layer and a p-type base layer of a three-layer structure are provided over a substrate. The three-layer structure includes first (lower layer side), second, and third (upper layer side) p-type base layers which differ in thickness and p-type impurity concentration. In a partial region inside the second p-type base layer located as an intermediate layer in the p-type base layer of the three-layer structure, an n-type emitter region is formed by ion implantation.
US09530849B2 Transistor having dual work function buried gate electrode and method for fabricating the same
A transistor having a source region and a drain region which are separately formed in a substrate, a trench which is defined in the substrate between the source region and the drain region, and a gate electrode which is formed in the trench. The gate electrode includes a first electrode buried over a bottom of the trench; a second electrode formed over the first electrode; and a liner electrode having an interface part which is positioned between the first electrode and the second electrode and a side part, which is positioned on sidewalls of the second electrode and overlaps with the source region and the drain region.
US09530833B2 Semiconductor structure including capacitors having different capacitor dielectrics and method for the formation thereof
An illustrative method disclosed herein includes providing a semiconductor structure. The semiconductor structure includes a first interlayer dielectric provided over a semiconductor substrate. A first electrode of a first capacitor is formed over the first interlayer dielectric. A layer of first dielectric material is deposited over the first electrode of the first capacitor and the first interlayer dielectric. A layer of electrically conductive material is deposited over the layer of first dielectric material. A second electrode of the first capacitor and a first electrode of the second capacitor are formed from the layer of electrically conductive material. After the formation of the second electrode of the first capacitor and the first electrode of the second capacitor, a layer of second dielectric material is deposited and a second electrode of the second capacitor is formed over the layer of second dielectric material.
US09530826B2 Organic light emitting display device and method of fabricating the same
The present disclosure relates to an organic light emitting display device including a substrate having an outer part and a display part, a driving thin film transistor on each of a plurality of pixel regions within the display part of the substrate, a pixel electrode on each pixel region of the display part, an organic light emitting unit on each pixel region of the display part to emit light, a common electrode on the organic light emitting unit and a bank layer to apply a signal to the organic light emitting layer, and a first passivation layer, an organic insulating layer and a second passivation layer on the outer part and the display part, wherein the first passivation layer and the second passivation layer are removed from the outermost region of the outer part, so that the substrate is exposed to the outside.
US09530817B2 Back side illumination photodiode of high quantum efficiency
A back side illumination photodiode includes a light-receiving back side surface of a semiconductor material substrate. An area of the light-receiving back side surface includes a recess. The recess is filled with a material having an optical index that is lower than an optical index of the semiconductor material substrate. Both the substrate and the filling material are transparent to an operating wavelength of the photodiode. The recess may be formed to have a ring shape.
US09530814B2 Method and apparatus for reducing crosstalk in CMOS image sensor
A CMOS image sensor and a method of manufacturing the same are provided. The CMOS image sensor includes a semiconductor substrate having a front side and a back side, at least two pixels disposed in the first side, a shallow trench isolation disposed in the front side between the at least two pixels, and a crosstalk reduction element disposed in the back side at a location above the shallow trench isolation. The crosstalk reduction element reduces optical and electrical crosstalk and improves the image quality of the CMOS image sensor.
US09530810B2 Photoelectric conversion device
To provide a photoelectric conversion device which prevents a reset time from being made long when a large quantity of light is entered. There is provided a photoelectric conversion device equipped with a photodiode which causes a photoelectric current corresponding to a quantity of incident light to flow, a reset circuit which charges a parasitic capacitance of the photodiode to a reset voltage, a voltage limit circuit which prevents the voltage of the parasitic capacitance of the photodiode from being lower than a prescribed voltage, and an output circuit which outputs the voltage of the parasitic capacitance of the photodiode.
US09530809B2 Layered structure, thin film transistor array, and method of manufacturing the same
A layered structure includes a first electrode layer on an insulating substrate, a first insulating film on the first electrode layer, a second electrode layer on the first insulating film, a second insulating film on the second electrode layer, and a third electrode layer on the second insulating film. The first electrode layer, an opening of the first insulating film, the second electrode layer, an opening of the second insulating film, and the third electrode layer have a stack structure that causes the first electrode layer and the second electrode layer to be connected. The third electrode layer relays or reinforces, through the opening of the second insulating film, a connection between the first electrode layer and the second electrode layer formed on the first insulating film.
US09530808B2 TFT array substrate, manufacturing method thereof, and display device
A method of manufacturing a TFT array substrate and a TFT array substrate and a display device are provided. During a pattern of a gate layer (2), a pattern of the gate insulating layer (3) and a pattern of the active layer are made, a gate layer (2) material, a gate insulating layer (3) material and an active layer material are deposited successively. The gate layer (2), the gate insulating layer (3) and the active layer are made through one patterning process. At least one mask process is saved and the process complexity is reduced.
US09530807B2 Thin film transistor array substrate, manufacturing method thereof, and display device
A thin film transistor (TFT) array substrate, a manufacturing method thereof and a display device are provided. The manufacturing method comprises: forming a first passivation layer (8) on a substrate (1), and forming a board wiring PAD-region via hole (11) in the first passivation layer (8) above the board wiring PAD region (11) through a first patterning process; forming a second passivation layer (16) on the substrate (1) formed with the board wiring PAD-region via hole (11), and forming a pixel-region via hole (15) in the first passivation layer (8) and the second passivation layer (16) above the display electrode (7) through a second patterning process in such a way that the pixel-region via hole (15) has a top-size smaller than its bottom-size; and applying a transparent conductive layer on the substrate (1) formed with the pixel-region via hole (15) to form a second display electrode.
US09530805B2 Backplane for display apparatus and method of manufacturing the backplane
A backplane for a display apparatus includes a substrate including a display area and a non-display area; a first transistor formed on the display area; and a second transistor formed on the non-display area, wherein a first active layer includes a first channel area, a first source area disposed on one side of the first channel area, a first drain area disposed on the other side of the first channel area, and a low-density doped area and a halo doped area that are adjacent to both ends of the first gate electrode, and the second active layer includes a second channel area, a second source area disposed on one side of the second channel area, and a second drain area disposed on the other side of the second channel area.
US09530799B2 Polysilicon thin film transistor and manufacturing method thereof, array substrate
A polysilicon thin film transistor, a manufacturing method thereof, an array substrate involve display technology field, and can repair the boundary defect and the defect state in polysilicon, suppress the hot carrier effect and make the characteristics of TFTs more stable. The polysilicon thin film transistor includes a gate electrode, a source electrode, a drain electrode and an active layer, the active layer comprises at least a channel area, first doped regions, second doped regions and heavily doped regions, and the first doped regions are disposed on two sides of the channel area, the second doped regions are disposed on sides of the first doped regions away from the channel area; the heavily doped regions are disposed on sides of the second doped regions opposed to the first doped regions; and dosage of ions in the heavily doped regions lies between that in the first doped regions and that in the second doped regions.
US09530795B2 Methods for cell boundary encroachment and semiconductor devices implementing the same
A semiconductor device includes a plurality of cells. Each of the cells has a respective outer cell boundary defined to circumscribe the cell in an orthogonal manner. Also, each of the cells includes circuitry for performing one or more logic functions. This circuitry includes a plurality of conductive features defined in one or more levels of the cell. One or more of the conductive features in at least one level of a given cell is an encroaching feature positioned to encroach by an encroachment distance into an exclusion zone. The exclusion zone occupies an area within the cell defined by an exclusion distance extending perpendicularly inward into the given cell from a first segment of the outer cell boundary. The exclusion distance is based on a design rule distance representing a minimum separation distance required between conductive features in adjacently placed cells on the semiconductor device.
US09530789B2 Semiconductor memory device and method of fabricating the same
Semiconductor memory devices and methods of fabricating the same are provided. A semiconductor memory device includes stack gate structures that are spaced apart from each other in a first direction horizontal to a substrate. Each of the stack gate structures includes insulating layers and gate electrodes alternately and repeatedly stacked on the substrate. Vertical channel structures penetrate the stack gate structures. A source plug line is provided between the stack gate structures. The source plug line is in contact with the substrate and extends in a second direction intersecting the first direction. The substrate being in contact with the source plug line includes a plurality of protruding regions formed along the second direction. Each of the protruding regions has a first width, and the protruding regions are spaced apart from each other by a first distance greater than the first width.
US09530786B2 Memory device and method for fabricating the same
Provided is a memory device, including a plurality of gate pillar structures and a plurality of dielectric pillars. The gate pillar structures and the dielectric pillars are arranged alternately and separately along a first direction, and are arranged alternately and contact each other along a second direction. In addition, the gate pillar structures and the dielectric pillars are embedded in a stack layer along a third direction, thereby dividing the stack layer into a plurality of stack structures. A sidewall of each of the dielectric pillars in the second direction and a sidewall of the adjacent gate pillar structure in the second direction are not coplanar.
US09530782B2 Nonvolatile semiconductor memory device comprising memory gate and peripheral gate having different thicknesses
A nonvolatile semiconductor memory device includes a semiconductor substrate, a memory element including a first gate electrode having a first thickness disposed on a first insulation film on the semiconductor substrate, and a first peripheral element other than a memory element including a second gate electrode having a second thickness disposed on a second insulation film on the semiconductor substrate. The first gate electrode and second gate electrode comprise a plurality of film layers, and the configuration of the film layers are different as between the first gate electrode of the memory element and the second gate electrode of the peripheral element, and the first thickness is different from the second thickness.
US09530781B2 Three dimensional NAND memory having improved connection between source line and in-hole channel material as well as reduced damage to in-hole layers
A fabrication process is provided for a 3D stacked non-volatile memory device which provides a source contact to a bottom of a memory hole in a stack without exposing a programmable material lining of an interior sidewall of the memory hole and without exposing a channel forming region also lining an interior of the memory hole to an energetic and potentially damaging etch environment. The stack includes alternating control gate layers and dielectric layers on a substrate, and the memory hole is etched through the stack before lining an interior sidewall thereof with the programmable material and then with the channel forming material. The process avoids a need to energetically etch down through the memory hole to open up a source contact hole near the bottom of the channel forming material by instead etching upwardly from beneath the memory hole.
US09530780B2 Memory bit cell for reduced layout area
An approach for providing SRAM bit cells with miniaturized bit cells, without local interconnection layers, with improved lithographic printability, and enabling methodology are disclosed. Embodiments include providing first color structures, in a M1 layer, including a first word line, a first bit line, a second bit line, a first ground line, a second ground line, a second latch line or a combination thereof, wherein the first color structures include side edges longer than tip edges; providing second color structures, in the M1 layer, including a second word line, a first power line, a second power line, a first latch line or a combination thereof, wherein the second color structures include side edges longer than tip edges; and forming a bit cell including the first color structures and the second color structures, wherein adjacent tip edges include a first color structure tip edge and a second color structure tip edge.
US09530779B2 Semiconductor device and method for fabricating the same
A method for fabricating semiconductor device is disclosed. The method includes the steps of: providing a substrate having at least one fin-shaped structure thereon, wherein the fin-shaped structure comprises a top portion and a bottom portion; removing part of the bottom portion of the fin-shaped structure; forming an epitaxial layer on the substrate to surround the bottom portion of the fin-shaped structure; transforming the bottom portion of the fin-shaped structure into the epitaxial layer; and removing part of the epitaxial layer.
US09530775B2 Methods of forming different FinFET devices having different fin heights and an integrated circuit product containing such devices
One illustrative method disclosed herein includes forming a plurality of trenches in a plurality of active regions of a substrate that defines at least a first plurality of fins and a second plurality of fins for first and second FinFET devices, respectively, forming liner materials adjacent to the first and second plurality of fins, wherein the liner materials adjacent the first fins and the second fins have a different thickness. The method also includes removing insulating material to expose portions of the liner materials, performing an etching process to remove portions of the liner materials so as to expose at least one fin in the first plurality of fins to a first height and at least one of the second plurality of fins to a second height that is different from the first height.
US09530773B2 Systems and methods for integrating bootstrap circuit elements in power transistors and other devices
Embodiments relate to bootstrap circuits integrated with at least one other device, such as a power transistor or other semiconductor device. In embodiments, the bootstrap circuit can comprise a bootstrap capacitor and a bootstrap diode, or the bootstrap circuit can comprise a bootstrap capacitor and a bootstrap transistor. The bootstrap capacitor comprises a semiconductor-based capacitor, as opposed to an electrolytic, ceramic or other capacitor, in embodiments. The integration of the bootstrap circuit with another circuit or device, such as a power transistor device in one embodiment, is at a silicon-level in embodiments, rather than as a module-like system-in-package of conventional approaches. In other words, the combination of the bootstrap circuit elements and power transistor or other device forms a system-on-silicon, or an integrated circuit, in embodiments, and additionally can be arranged in a single package.
US09530771B2 Feedback and impedance circuits, devices and methods for broadband radio-frequency amplifiers
Feedback and impedance circuits, devices and methods for broadband radio-frequency (RF) amplifiers. An RF amplifier architecture can include an amplifier having a first field-effect transistor (FET) and a second FET arranged in a cascode configuration. The gate of the first FET can be configured to receive an RF signal, the drain of the first FET can be coupled to the source of the second FET, and the drain of the second FET can be configured to output an amplified RF signal. The RF amplifier architecture can further include a first feedback circuit implemented between the drain of the second FET and the gate of the second FET to provide gain control, and a second feedback circuit implemented between the drain of the second FET and the gate of the first FET to provide an increase in a frequency range having a desirable range of gain.
US09530770B2 Integrated circuits with resistor structures formed from gate metal and methods for fabricating same
Integrated circuits having resistor structures formed from gate metal and methods for fabricating such integrated circuits are provided. In an embodiment, a method for fabricating an integrated circuit includes providing a semiconductor substrate with a resistor area and a transistor area. The method deposits a gate metal over the resistor area and the transistor area of the semiconductor substrate, and the gate metal forms a gate metal layer in the resistor area. The method includes etching the gate metal to form a resistor structure from the gate metal layer in the resistor area. Further, the method includes forming contacts to the resistor structure in the resistor area.
US09530769B2 Semiconductor device with electro-static discharge protection device above semiconductor device area
A semiconductor device includes a semiconductor substrate on which a semiconductor device is formed; first and second pads; a first insulating film which is formed above the semiconductor substrate; a plurality of wiring lines which are embedded in ditches provided in the first insulating film; a second insulating film provided to cover the first insulating film and the plurality of wiring lines; a semiconductor layer formed on the second insulating film; a source electrode connected with the semiconductor layer; and a drain electrode connected with the semiconductor layer. The plurality of wiring lines includes a gate electrode provided in a position which is opposite to the semiconductor layer. The semiconductor layer, the source electrode, the drain electrode and the gate electrode configure an ESD protection device to discharge a current by ESD surge from the first pad to the second pad.
US09530766B2 Semiconductor device
A transistor (2) is provided on a semiconductor substrate (8). A temperature detection diode (4) for monitoring temperature of an upper surface of the semiconductor substrate (8) is provided on the semiconductor substrate (8). An external electrode (7) is connected in common to an emitter (E) of the transistor (2) and a cathode (K) of the temperature detection diode (4). Therefore, an external electrode for the cathode (K) of the temperature detection diode (4) can be removed, and thus the device can be reduced in size and improved in terms of ease of assembly.
US09530763B2 Monolithic integration of CMOS and non-silicon devices
A method includes attaching a partially processed CMOS wafer to a second wafer to produce a combined wafer. The second wafer comprises a first region including a material different from silicon. The method also includes forming devices in the first region or in a second region of the combined wafer having a material different from silicon.
US09530759B2 3D package with through substrate vias
A package, comprising a substrate having electrical devices disposed at a first side of the substrate, vias extending from the first side of the substrate to a second side of the substrate opposite the first side and metallization layers disposed on the first side of the substrate. Contact pads are disposed over the first metallization layers and a protection layer is disposed over the contact pads. Post-passivation interconnects are disposed over the protection layer and extend to the contact pads through openings in the protection layer. Connectors are disposed on the PPIs and a molding compound extends over the PPIs and around the connectors.
US09530758B2 3D integrated circuit package with through-mold first level interconnects
3D integrated circuit packages with through-mold first level interconnects and methods to form such packages are described. For example, a semiconductor package includes a substrate. A bottom semiconductor die has an active side with a surface area. The bottom semiconductor die is coupled to the substrate with the active side distal from the substrate. A top semiconductor die has an active side with a surface area larger than the surface area of the bottom semiconductor die. The top semiconductor die is coupled to the substrate with the active side proximate to the substrate. The active side of the bottom semiconductor die is facing and conductively coupled to the active side of the top semiconductor die. The top semiconductor die is conductively coupled to the substrate by first level interconnects that bypass the bottom semiconductor die.
US09530757B2 Single mask package apparatus
Disclosed herein is a single mask package apparatus on a device comprising a first substrate having a land disposed on a first surface, a stud disposed on the land and a protective layer disposed over the first surface of the first substrate and around the stud. The protective layer may optionally have a thickness of at least 3 μm. A PPI may be disposed over the protective layer and in electrical contact with the stud, with a first portion of the PPI extending laterally from the stud. An interconnect may be disposed on and in electrical contact with the first portion of the PPI, and a second substrate mounted on the interconnect. A molding compound may be disposed over the PPI and around the interconnect. The stud may be a substantially solid material having a cylindrical cross section and may optionally be wirebonded to the land.
US09530755B2 Semiconductor packages
Provided is a semiconductor package including a substrate, a first semiconductor chip disposed on the substrate to have a rectangular shape with long and short sides, and a second semiconductor chip disposed on the first semiconductor chip to have a rectangular shape with long and short sides. Centers of the first and second semiconductor chips may be located at substantially the same position as that of the substrate, and the long side of the first semiconductor chip may be substantially parallel to a diagonal line of the substrate. Further, the long side of the second semiconductor chip may be not parallel to that of the first semiconductor chip.
US09530753B2 Integrated circuit packaging system with chip stacking and method of manufacture thereof
A method of manufacture of an integrated circuit packaging system includes: providing a first substrate; mounting an integrated circuit structure on the first substrate; mounting a second substrate on the integrated circuit structure; coupling a vertical chip to the first substrate and to the second substrate; and forming a package body for encapsulating the integrated circuit structure, the vertical chip, and a portion of the second substrate.
US09530751B2 Die bonder and bonding method
A die bonder and a bonding method are provided that are capable of surely mounting a die on an intermediate stage and surely picking up the die from the intermediate stage and thus, are high in reliability. The die bonder is provided with the intermediate stage for mounting thereon the die picked up by the pickup head from a die supply unit. A mounting portion of the intermediate stage is provided with an uneven pattern including a plurality of mounting support protrusions having contact surfaces that flush contact the back surface of the die for supporting the die not to slip out of place, and a plurality of recesses formed between the mounting support protrusions.
US09530749B2 Coupling of side surface contacts to a circuit platform
An apparatus relates generally to a microelectromechanical system component. In such an apparatus, the microelectromechanical system component has a lower surface, an upper surface, first side surfaces, and second side surfaces. Surface area of the first side surfaces is greater than surface area of the second side surfaces. The microelectromechanical system component has a plurality of wire bond wires attached to and extending away from a first side surface of the first side surfaces. The wire bond wires are self-supporting and cantilevered with respect to the first side surface of the first side surfaces.
US09530748B2 Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices
Packaged microelectronic devices and methods for manufacturing packaged microelectronic devices are disclosed herein. In one embodiment, a packaged microelectronic device can include a support member, a first die attached to the support member, and a second die attached to the first die in a stacked configuration. The device can also include an attachment feature between the first and second dies. The attachment feature can be composed of a dielectric adhesive material. The attachment feature includes (a) a single, unitary structure covering at least approximately all of the back side of the second die, and (b) a plurality of interconnect structures electrically coupled to internal active features of both the first die and the second die.
US09530747B2 Solder in cavity interconnection structures
The present disclosure relates to the field of fabricating microelectronic packages, wherein cavities are formed in a dielectric layer deposited on a first substrate to maintain separation between soldered interconnections. In one embodiment, the cavities may have sloped sidewalls. In another embodiment, a solder paste may be deposited in the cavities and upon heating solder structures may be formed. In other embodiments, the solder structures may be placed in the cavities or may be formed on a second substrate to which the first substrate may be connected. In still other embodiments, solder structures may be formed on both the first substrate and a second substrate. The solder structures may be used to form solder interconnects by contact and reflow with either contact lands or solder structures on a second substrate.
US09530745B2 Electronic apparatus and method for fabricating the same
An electronic apparatus includes a first electronic part with a first terminal, a second electronic part with a second terminal opposite the first terminal, and a joining portion which joins the first terminal and the second terminal. The joining portion contains a pole-like compound extending in a direction in which the first terminal and the second terminal are opposite to each other. The joining portion contains the pole-like compound, so the strength of the joining portion is improved. When the first terminal and the second terminal are joined, the temperature of one of the first electronic part and the second electronic part is made higher than that of the other. A joining material is cooled and solidified in this state. By doing so, the pole-like compound is formed.
US09530741B2 Semiconductor packages having residual stress layers and methods of fabricating the same
A semiconductor package is provided. The semiconductor includes a lower package and an upper package stacked on the lower package. The lower package includes a package substrate, a semiconductor chip, a mold layer and a residential stress layer. The package substrate has upper and lower surfaces. The semiconductor chip is disposed on the upper surface of the package substrate. The mold layer encapsulates the semiconductor chip. The residual stress layer is disposed on the semiconductor chip. The residual stress layer includes a plastically deformed surface. The residual stress layer has a residual stress to counterbalance warpage of the lower package.
US09530740B2 3D interconnect structure comprising through-silicon vias combined with fine pitch backside metal redistribution lines fabricated using a dual damascene type approach
A 3D interconnect structure and method of manufacture are described in which a through-silicon vias (TSVs) and metal redistribution layers (RDLs) are formed using a dual damascene type process flow. A silicon nitride or silicon carbide passivation layer may be provided between the thinned device wafer back side and the RDLs to provide a hermetic barrier and etch stop layer during the process flow.
US09530736B2 Semiconductor device and formation thereof
A semiconductor device and method of formation are provided. The semiconductor device comprises a metal plug in a first opening over a substrate, the metal plug is over a silicide layer, and the silicide layer is over a metal oxide layer. The metal oxide layer has an oxygen gradient, such that a percentage of oxygen increases from a top surface of the metal oxide layer to a bottom surface of the metal oxide layer. The metal oxide layer unpins the Fermi level of the interface between the metal plug and the substrate, which is exhibited by a lowered Schottky barrier height (SBH) and increased oxygen vacancy states between the V.B. and the C.B. of the metal oxide layer, which decreases the intrinsic resistivity between the metal plug and the substrate as compared to a semiconductor device that lacks such a metal oxide layer.
US09530729B2 Semiconductor devices including insulating extension patterns between adjacent landing pads and methods of fabricating the same
A semiconductor memory device includes a plurality of pattern structures respectively including a bit line and insulating spacers on sidewalls thereof protruding from a substrate. A plurality of insulating extension patterns are provided on opposing sidewalls of the pattern structures, and respectively extend from upper portions of the opposing sidewalls toward the substrate along the insulating spacers such that lower portions of the opposing sidewalls are free of the extension patterns. A plurality of buried contact patterns are provided on the substrate between the lower portions of the opposing sidewalls of adjacent pattern structures. Related fabrication methods are also discussed.
US09530725B2 Wiring substrate and semiconductor package
A wiring substrate includes a core layer including a plate-like body and linear conductors, a first wiring layer formed on a first surface of the plate-like body, and an insulating layer formed on the first surface. A gap between the adjacent linear conductors is smaller than a diameter of each linear conductor. The linear conductors include a first linear conductor disposed in a position overlapping with the first wiring layer and conducting to the first wiring layer and a second linear conductor disposed in a position not overlapping with the first wiring layer. An end surface of the first linear conductor on the side of the first surface is approximately flush with the first surface. An end surface of the second linear conductor on the side of the first surface is in a position more depressed than the first surface to form a hole. The insulating layer is filled in the hole.
US09530723B2 Semiconductor device and manufacturing method thereof
On the assumption that a pair of hanging parts is provided in a lead frame and a clip includes a main body part and a pair of extension parts, the pair of the extension parts is mounted and supported on the pair of the hanging parts. Accordingly, the clip is mounted on a lead (one point) and the pair of the hanging parts (two points), and the clip is supported by the three points.
US09530721B2 Semiconductor device
A semiconductor device includes first and second semiconductor chips, a plurality of leads, a plurality of wires, and a sealing body sealing those components. A first pad electrode, a second pad electrode, and an internal wiring electrically connected to the first and second electrode pads are formed on a main surface of the first semiconductor chip. A third pad electrode of the second semiconductor chip is electrically connected to the first electrode pad of the first semiconductor chip via a first wire, and the second electrode pad of the first semiconductor chip is electrically connected to a first lead via a second wire. A distance between the first lead and the first semiconductor chip is smaller than a distance between the first lead and the second semiconductor chip. The first electrode pad, the second electrode pad and the internal wiring are not connected to any circuit formed in the first semiconductor chip.
US09530719B2 Direct die solder of gallium arsenide integrated circuit dies and methods of manufacturing gallium arsenide wafers
Electronic devices, and methods of manufacturing the electronic devices, utilizing direct die soldering of GaAs integrated circuit dies. In some embodiments, the GaAs integrated circuit die can have a footprint approximately the same size as a die attach pad. Further, the GaAs integrated circuit die can self-align with the die attach pad after reflow of any solder layer used to attach the die.
US09530718B2 DBF film as a thermal interface material
A die backside film including a matrix material; and an amount of filler particles to render the die backside film thermally conductive, wherein a thermal conductivity of the amount of filler particles is greater than a thermal conductivity of silica particles. A method including introducing a die backside film on a backside surface of a die, the die backside film including a matrix material including an elastomer an amount of filler particles to render the die backside film thermally conductive, wherein a thermal conductivity of the amount of filler particles is greater than a thermal conductivity of silica particles; and disposing the die in a package.
US09530713B2 Cooler-integrated semiconductor module
A cooler-integrated semiconductor module, includes an insulating substrate; a circuit layer disposed on a front surface of the insulating substrate; a semiconductor element electrically connected to the circuit layer; a metal layer provided on a back surface of the insulating substrate; a sealing resin covering the insulating substrate, the circuit layer, the semiconductor element, and a portion of the metal layer; a cooler disposed on a lower surface side of the metal layer; a plating layer disposed on at least a surface of the sealing resin facing the cooler; and a joining member connecting the plating layer and the cooler.
US09530710B2 Passivation structure of fin field effect transistor
A FinFET comprises a substrate comprising a major surface; a fin structure protruding from the major surface comprising a lower fin portion comprising a first semiconductor material having a first lattice constant; an upper fin portion comprising a second semiconductor material having a second lattice constant greater than the first lattice constant; a middle fin portion comprising a third semiconductor material having a third lattice constant between the first lattice constant and the second lattice constant; and a passivation structure surrounding the fin structure comprising a lower passivation portion surrounding the lower fin portion comprising a first oxynitride of the first semiconductor material; an upper passivation portion surrounding the upper fin portion comprising a second oxynitride of the second semiconductor material; and a middle passivation portion surrounding the middle fin portion comprising a third oxynitride of the third semiconductor material.
US09530707B2 Semiconductor module
A semiconductor module includes a printed circuit board having an insulating plate, first and fourth wiring layers disposed on a principal surface of the insulating plate, second and third wiring layers disposed on another surface opposite to the principal surface, a first via disposed in the insulating plate and electrically and mechanically connected to the first and third wiring layers, and a second via disposed in the insulating plate and electrically and mechanically connected to the second and fourth wiring layers; a first insulating substrate disposed with a first circuit plate; a second insulating substrate disposed with a second circuit plate; a first semiconductor chip; a second semiconductor chip; a first heat release member fixed between the third wiring layer and the third circuit plate; and a second heat release member fixed between the fourth wiring layer and the first circuit plate.
US09530703B2 Method for manufacturing silicon carbide semiconductor device
Provided is a method for manufacturing a silicon carbide semiconductor device capable of preventing an increase in a cost of manufacturing one chip while favorably maintaining forward characteristics of the semiconductor device including (a) inspecting the characteristics of the forward conduction of body diodes as element structures; (b) classifying the body diode and the body diode as either a first group suitable for forward conduction or a second group unsuitable for forward conduction on the basis of an inspection result; and (c) manufacturing a silicon carbide semiconductor MOSFET that requires forward conduction using the body diode classified into the first group or manufacturing a silicon carbide semiconductor MOSFET that does not need forward conduction using the body diode classified into the second group.
US09530702B2 Method for measuring recombination lifetime of silicon substrate
Provided is a method of measuring a recombination lifetime of a silicon substrate, which is capable of evaluating metal contamination and crystal defects in a silicon substrate manufacturing process and a device manufacturing process with high accuracy. The method includes: measuring a recombination lifetime of a silicon substrate after subjecting a surface of the silicon substrate to chemical passivation processing; and performing ultraviolet protection processing of protecting at least the silicon substrate from ultraviolet rays during a period from the chemical passivation processing to a time when the measurement of the recombination lifetime is completed.
US09530700B1 Method of fabricating vertical field effect transistors with protective fin liner during bottom spacer recess etch
A method of fabricating a vertical field effect transistor comprising that includes forming openings through a spacer material to provide fin structure openings to a first semiconductor material, and forming an inner spacer liner on sidewalls of the fin structure openings. A channel semiconductor material is epitaxially formed on a surface of the first semiconductor material filling at least a portion of the fin structure openings. The spacer material is recessed with an etch that is selective to the inner spacer liner to form a first spacer. The inner spacer liner is removed selectively to the channel semiconductor material. A gate structure on the channel semiconductor material, and a second semiconductor material is formed in contact with the channel semiconductor material.
US09530699B2 Semiconductor device including gate channel having adjusted threshold voltage
A semiconductor device includes at least one first semiconductor fin formed on an nFET region of a semiconductor device and at least one second semiconductor fin formed on a pFET region. The at least one first semiconductor fin has an nFET channel region interposed between a pair of nFET source/drain regions. The at least one second semiconductor fin has a pFET channel region interposed between a pair of pFET source/drain regions. The an epitaxial liner is formed on only the pFET channel region of the at least one second semiconductor fin such that a first threshold voltage of the nFET channel region is different than a second threshold voltage of the pFET channel.
US09530698B1 Method and structure for forming FinFET CMOS with dual doped STI regions
A method of making a semiconductor device includes forming a first fin of a first transistor in a substrate; forming a second fin of a second transistor in the substrate; disposing a first doped oxide layer including a first dopant onto the first fin and the second fin, the first dopant being an n-type dopant or a p-type dopant; disposing a mask over the first fin and removing the first doped oxide layer from the second fin; removing the mask and disposing a second doped oxide layer onto the first doped oxide layer over the first doped oxide layer covering the first fin and directly onto the second fin, the second doped oxide layer including an n-type dopant or a p-type dopant that is different than the first dopant; and annealing to drive in the first dopant into a portion of the first fin and the second dopant into a portion of the second fin.
US09530697B1 Semiconductor memory device and method for manufacturing same
According to one embodiment, a semiconductor memory device includes a substrate, a stacked body, a semiconductor film, a memory film, an interconnect portion, and first and second insulating films. The first and second insulating films are provided on the interconnect portion. The interconnect portion includes first and second interconnect portions. The first interconnect portion is provided on the substrate. A width of a cross-section of the second interconnect portion decreases with increased distance from the substrate. The first insulating film is provided on side surfaces of the first and second interconnect portions. The second insulating film includes first to third portions. The first portion is provided on an upper surface of the interconnect portion. The first insulating film is provided between the second portion and the side surface of the second interconnect portion. The third portion extends in a second direction crossing the stacking direction and the first direction.
US09530696B1 Method of fabricating semiconductor device
A method of fabricating a semiconductor device is provided. A plurality of sacrificial gates and a plurality of sacrificial gate dielectric layers thereunder are formed on a substrate. An interlayer dielectric layer is filled between the sacrificial gates. A protective layer is formed on the interlayer dielectric layer. The sacrificial gates and the sacrificial gate dielectric layers are removed to form an opening, wherein the interlayer dielectric layer is protected by the protective layer from recessing. A stacked gate structure is formed in the opening, wherein the protective layer is removed.
US09530690B2 Metal pad structure over TSV to reduce shorting of upper metal layer
Various embodiments of mechanisms for forming a slotted metal pad over a TSV in substrate are provided. The dielectric structures in the slotted metal pad reduce dishing effect during planarization of the slotted metal pad. As a result, the risk of having metal stringers in upper metal level(s) caused by the dishing effect is greatly reduced.
US09530689B2 Methods for fabricating integrated circuits using multi-patterning processes
Methods for fabricating integrated circuits are provided. One method includes decomposing a master pattern layout for a semiconductor device layer that includes a target metal line with a target interconnecting via/contact into a first sub-pattern and a second sub-pattern. The target metal line is decomposed into a first line feature pattern that is part of the first sub-pattern and a second line feature pattern that is part of the second sub-pattern such that the first and second line feature patterns have overlapping portions defining a stitch that corresponds to the target interconnecting via/contact. A first photomask is generated that corresponds to the first sub-pattern. A second photomask is generated that corresponds to the second sub-pattern.
US09530683B2 Forming source/drain zones with a dielectric plug over an isolation region between active regions
An embodiment includes forming an isolation region between first and second active regions in a semiconductor, forming an opening between the first and second active regions by removing a portion of the isolation region, and forming a dielectric plug within the opening so that the dielectric plug is between the first and second active regions and so that a portion of the dielectric plug extends below upper surfaces of the first and second active regions. The dielectric plug may be formed of a dielectric material having a lower removal rate than a dielectric material of the isolation region for a particular isotropic removal chemistry.
US09530680B2 Method of fabricating semiconductor package, semiconductor chip supporting carrier and chip mounting device
In fabricating semiconductor packages, a first supporting unit is supported by a supporting substrate with one surface of an adhesive sheet directed upward, the first supporting unit being constituted by attaching the adhesive sheet having an adhesive layer as the one surface thereof and a non-adhesive layer as the other surface thereof to a frame member; semiconductor chips are mounted on the one surface of the adhesive sheet; on the adhesive sheet, a resin portion containing the semiconductor chips is formed by resin-sealing the semiconductor chips; the first supporting unit is removed from the second supporting unit; the resin portion is stripped from the adhesive sheet; external connection members are formed at the semiconductor chips contained in the resin portion; and portions between the respective semiconductor chips contained in the resin portion are cut to obtain individual semiconductor packages.
US09530678B2 Substrate carrier system for moving substrates in a vertical oven and method for processing substrates
A substrate carrier system for moving substrates in a vertical oven and a method for processing substrates are disclosed. In some embodiments, a method for oxidizing material or depositing material includes carrying a plurality of substrates by a substrate carrier and inserting the substrate carrier into a vertical oven, wherein the plurality of substrates are held by the substrate carrier in predefined positions, wherein an angle measured between a main surface of a substrate of the plurality of substrates at one of the predefined positions and a vertical direction is less than 20 degrees. The method further includes oxidizing a material on the plurality of substrates or depositing a material onto the plurality of substrates.
US09530675B2 Wafer handling station including cassette members with lateral wafer confining brackets and associated methods
A wafer handling station includes a housing defining a chamber, and a wafer cassette assembly positionable in the chamber. The wafer cassette assembly includes a vertical support, and cassette members carried by the vertical support in spaced relation. Each cassette member includes a base coupled to the vertical support, wafer contact pads on an upper surface of the base and configured to support a wafer thereon, and a pair of wafer brackets carried by the base and configured to engage respective edges of the wafer to laterally confine the wafer.
US09530674B2 Method and system for three-dimensional (3D) structure fill
Embodiments include methods and systems of 3D structure fill. In one embodiment, a method of filling a trench in a wafer includes performing directional plasma treatment with an ion beam at an angle with respect to a sidewall of the trench to form a treated portion of the sidewall and an untreated bottom of the trench. A material is deposited in the trench. The deposition rate of the material on the treated portion of the sidewall is different than a second deposition rate on the untreated bottom of the trench. In one embodiment, a method includes depositing a material on the wafer, filling a bottom of the trench and forming a layer on a sidewall of the trench and a top surface adjacent to the trench. The method includes etching the layer with an ion beam at an angle with respect to the sidewall.
US09530672B2 Production method for a semiconductor device
A method for producing a semiconductor device includes providing a semiconductor substrate having a first conductivity type; implanting protons through a rear surface of the semiconductor substrate of the first conductivity type; and forming a first semiconductor region of the first conductivity type in the semiconductor substrate by performing an annealing process in an annealing furnace in a hydrogen atmosphere having a volume concentration of hydrogen that is equal to or greater than 0.5% and less than 4.65%, the first semiconductor region having a higher impurity concentration than that of the semiconductor substrate after the implantation step. The method reduces crystal defects in the generation of donors during proton implantation and improves the rate of change into a donor.
US09530669B1 Method of making a semiconductor device having a semiconductor material on a relaxed semiconductor including replacing a strained, selective etchable material, with a low density dielectric in a cavity
A semiconductor device comprising a substrate having a region protruding from the substrate surface; a relaxed semiconductor disposed on the region; an additional semiconductor disposed on the relaxed semiconductor; and low density dielectric disposed next to and at least partially underneath the relaxed semiconductor and adjacent to the protruding region of the substrate.
US09530668B2 Thin-film pattern array and production method therefor
Disclosed are: a thin-film pattern array able to minimize level differences between thin films; and a production method therefor. The thin-film pattern array comprises: a lower thin-film pattern which is positioned on a substrate; an upper thin-film pattern which is positioned on the upper edge of the lower thin-film pattern; and a level-difference attenuating pattern which is positioned between the lower thin-film pattern and the upper thin-film pattern, and has a gentle taper angle so as to be able to reduce the level difference between the lower thin-film pattern and the upper thin-film pattern.
US09530666B2 Plasma etching method and plasma etching apparatus
A plasma etching method includes a first process and a second process. In the first process, a hole is formed in a processing target film formed on a substrate accommodated within a processing chamber by performing an etching process of etching the processing target film. In the second process, a removing process, a deposition process and an extending process are repeatedly performed. In the removing process, a reaction product adhering to an inlet portion of the hole which is formed through the etching process is removed. In the deposition process, a deposit is deposited on a sidewall of the hole from which the reaction product is removed through the removing process. In the extending process, the hole, in which the deposit is deposited on the sidewall thereof through the deposition process, is deeply etched by performing the etching process.
US09530665B2 Protective trench layer and gate spacer in finFET devices
Forming a field effect transistor device includes forming first and second semiconductor fins on a semiconductor substrate. The first and second semiconductor fins are separated by a trench region. The trench region has a first sidewall corresponding to a sidewall of the first semiconductor fin and a second sidewall corresponding to a sidewall of the second semiconductor fin. A gate stack is arranged over respective channel regions of the first and semiconductor fins. A first sidewall of the gate stack corresponds to a third sidewall of the trench region. A protective layer is formed only on a bottom portion of the trench region and along the first sidewall of the gate stack. The protective layer along the first sidewall of the gate stack defines a gate spacer.
US09530661B2 Method of modifying epitaxial growth shape on source drain area of transistor
Methods for forming semiconductor devices, such as FinFETs, are provided. An epitaxial film is formed over a semiconductor fin, and the epitaxial film includes a top surface having two facets. A cap layer is deposited on the top surface, and portions of the epitaxial film in a lateral direction are removed. Having a smaller lateral dimension prevents the epitaxial film from merging with an adjacent epitaxial film and creates a gap between the epitaxial film and the adjacent epitaxial film.
US09530660B2 Multiple directed self-assembly patterning process
Disclosed is a method of forming a target pattern for a semiconductor device using multiple directed self-assembly (DSA) patterning processes. The method includes receiving a substrate and forming a guide pattern over the substrate by performing a process that includes a first DSA process. The method further includes performing a second DSA process over the substrate using the guide pattern. In an embodiment, the first DSA process controls the first pitch of a dense pattern in a first direction and the second DSA process controls the second pitch of the dense pattern in a second direction.
US09530659B2 Structure for preventing buried oxide gouging during planar and FinFET Processing on SOI
A structure for manufacturing a semiconductor device without damaging the insulator layer during creation of fin field effect transistor (FinFET) devices includes an insulator layer; an active semiconductor layer; and an etch stop layer including material resistant to those processes the etch stop layer is exposed to during creation of a FinFET having fins formed from the active semiconductor layer, such that the etch stop layer and the insulator layer are not damaged during creation of the FinFET; wherein, the etch stop layer is between the insulator layer and the active semiconductor layer.
US09530657B2 Method of processing substrate and substrate processing apparatus
A method of processing a substrate using a substrate processing apparatus that has an electrostatic chuck including an insulating member inside which an electrode is included and provides a plasma process to a substrate mounted on the electrostatic chuck includes a first process of supplying a heat transfer gas having a second gas pressure to a back surface of the substrate while eliminating electric charges in the substrate using plasma of a process gas having a first gas pressure.
US09530651B2 Replacement metal gate finFET
A field effect transistor device includes a fin including a semiconductor material arranged on an insulator layer, the fin including a channel region, a hardmask layer arranged partially over the channel region of the fin, a gate stack arranged over the hardmask layer and over the channel region of the fin, a metallic alloy layer arranged on a first portion of the hardmask layer, the metallic alloy layer arranged adjacent to the gate stack, and a first spacer arranged adjacent to the gate stack and over the metallic alloy layer.
US09530649B2 Semiconductor electronic devices and methods of manufacture thereof
A method of manufacturing an electronic device comprises: providing a layer of semiconductor material comprising a first portion, a second portion, and a third portion, the third portion connecting the first portion to the second portion and providing a semiconductive channel for electrical current flow between the first and second portions; providing a gate terminal arranged with respect to said third portion such that a voltage may be applied to the gate terminal to control an electrical conductivity of said channel; and processing at least one of the first and second portions so as to have an electrical conductivity greater than an electrical conductivity of the channel when no voltage is applied to the gate terminal. In certain embodiments, the processing comprises exposing at least one of the first and second portions to electromagnetic radiation. The first and second portions may be laser annealed to increase their conductivities.
US09530646B2 Method of forming a semiconductor structure
A method of forming a semiconductor structure includes following steps. First of all, a patterned hard mask layer having a plurality of mandrel patterns is provided. Next, a plurality of first mandrels is formed on a substrate through the patterned hard mask. Following these, at least one sidewall image transferring (SIT) process is performed. Finally, a plurality of fins is formed in the substrate, wherein each of the fins has a predetermined critical dimension (CD), and each of the mandrel patterns has a CD being 5-8 times greater than the predetermined CD.
US09530643B2 Selective epitaxy using epitaxy-prevention layers
A method for forming an epitaxial structure includes providing a two-dimensional material on a crystal semiconductor material and opening up portions of the two-dimensional material to expose the crystal semiconductor material. A structure is epitaxially grown in the portions opened up in the crystal semiconductor material such that the epitaxial growth is selective to the exposed crystal semiconductor material relative to the two-dimensional material.
US09530639B2 Method of preparing ZnO nanowire and ZnO nanowire prepared thereby
A method of preparing a ZnO nanowire, and a ZnO nanowire prepared by the method are provided. The method of preparing a ZnO nanowire includes: preparing a zinc chalcogenide solution by dissolving zinc chalcogenide in a solvent; applying the zinc chalcogenide solution onto a substrate; drying the zinc chalcogenide solution applied onto the substrate; and annealing the substrate in the presence of oxygen after the drying the zinc chalcogenide solution.
US09530636B2 Light source with nanostructured antireflection layer
A laser-sustained plasma light source includes a plasma cell configured to contain a volume of gas. The plasma cell is configured to receive illumination from a pump laser in order to generate plasma within the volume of gas. The plasma emits broadband radiation. The plasma cell includes one or more transparent portions being at least partially transparent to at least a portion of illumination from the pump laser and at least a portion of the broadband radiation emitted by the plasma. The plasma cell also includes one or more nanostructured layers disposed on one or more surfaces of the one or more transparent portions of the plasma cell. The one or more nanostructure layers form a region of refractive index control across an interface between the one or more transparent portions of the plasma cell and an atmosphere.
US09530632B2 Ion detection system and method
A detection system and a method for detecting ions which have been separated in a time-of-flight (TOF) mass analyzer, comprising an amplifying arrangement for converting ions into packets of secondary particles and amplifying the packets of secondary particles, wherein the amplifying arrangement is arranged so that each packet of secondary particles produces at least a first output and a second output separated in time and so that during the delay between producing the first and second output the first output produced by a packet of secondary particles is used for modulating the second output produced by the same packet. An increased dynamic range of detection and protection of the detection system against intense ion pulses is thereby provided.
US09530625B2 Method for attachment of an electrode into an inductively-coupled plasma
An inductively coupled plasma charged particle source for focused ion beam systems includes a plasma reaction chamber with a removably attached source electrode. A fastening mechanism connects the source electrode with the plasma reaction chamber and allows for a heat-conductive, vacuum seal to form. With a removable source electrode, improved serviceability and reuse of the plasma source tube are now possible.
US09530620B2 Dual control modes
Systems and methods for using variables based on a state associated with a plasma system. A method includes determining whether the state associated with the plasma system is a first state or a second state and determining a first variable upon determining that the state is the first state. The first variable is determined based on a measurement at a communication medium. The method further includes determining a second variable upon determining that the state is the second state. The second variable is determined based on a measurement at the communication medium. The method includes determining whether the second variable exceeds a first threshold, providing an instruction to reduce power supplied to a plasma chamber upon determining that the second variable exceeds the first threshold, and providing an instruction to increase power supplied to the plasma chamber upon determining that the second variable is below the first threshold.
US09530615B2 Techniques for improving the performance and extending the lifetime of an ion source
A system and method of improving the performance and extending the lifetime of an ion source is disclosed. The ion source includes an ion source chamber, a suppression electrode and a ground electrode. In the processing mode, the ion source chamber may be biased to a first positive voltage, while the suppression electrode is biased to a negative voltage to attract positive ions from within the chamber through an aperture and toward the workpiece. In the cleaning mode, the ion source chamber may be grounded, while the suppression electrode is biased using a power supply having a high current capability. The voltage applied to the suppression electrode creates a plasma between the suppression electrode and the ion source chamber, and between the suppression electrode and the ground electrode.
US09530614B2 Charged particle beam device and arithmetic device
It is possible to determine an optimal parasitic aberration adjustment amount even when the relationship of the parasitic aberration adjustment amount with respect to the field intensity of multiple poles changes nonlinearly. To this end, in the present invention, an aberration correction amount is computed by measuring an aberration coefficient of an optical unit of a charged particle beam device, and at the same time, the present value of a power supply control value applied to an aberration corrector is measured. Then, the parasitic aberration adjustment amount for suppressing the amount of a parasitic aberration generated in the aberration corrector is computed on the basis of the aberration correction amount and the present value of the power supply control value.
US09530613B2 Focusing a charged particle system
A charged particle beam focusing apparatus includes a charged particle beam generator configured to project simultaneously at least one non-astigmatic charged particle beam and at least one astigmatic charged particle beam onto locations on a surface of a specimen, thereby causing released electrons to be emitted from the locations. The apparatus also includes an imaging detector configured to receive the released electrons from the locations and to form images of the locations from the released electrons. A processor analyzes the image produced by the at least one astigmatic charged particle beam and in response thereto adjusts a focus of the at least one non-astigmatic charged particle beam.
US09530609B2 X-ray apparatus
An x-ray apparatus includes an x-ray emitter having an x-ray tube, a rotary anode disposed in the x-ray tube, and a drive for the rotary anode. The drive includes a reluctance motor having a stator disposed outside the x-ray tube and a rotor disposed inside the x-ray tube. The rotor is mechanically connected to the rotary anode.
US09530606B2 Ion source and method for making same
An articles includes: an ion source configured to provide a first ion beam that has a first brightness; and a cooler configured to receive the first ion beam and to produce a second ion beam from the first ion beam, the second ion beam including a second brightness that is greater than the first brightness. A process for cooling includes receiving a first ion beam that includes a first brightness in a cooler, and the cooler includes a first mirror and a second mirror disposed opposingly to the first mirror; receiving a first laser beam in the cooler; receiving a second laser beam in the cooler; transmitting the first laser beam and the second laser beam through the first ion beam to decrease an emittance of the first ion beam; reflecting the first laser beam from the first mirror and the second laser beam from the second mirror; and transmitting, after being reflected, the first laser beam and the second laser beam through the first ion beam to cool the first ion beam and to decrease the emittance of the first ion beam to produce a second ion beam that includes a second brightness that is greater than the first brightness.
US09530600B2 Microelectronic switch and active matrix organic light emitting display device
The embodiments of the present invention discloses a microelectronic switch comprising: a gate electrode; a source electrode; a drain electrode; a first electrostatic electrode; a cantilever with two working positions of an open position and a close position; a connecting portion arranged at the cantilever; a second electrostatic electrode arranged at the cantilever, the second electrostatic electrode is electrically connected with the gate electrode and is arranged opposite to the first electrostatic electrode; an insulating dielectric layer arranged between the first electrostatic electrode and the second electrostatic electrode; the cantilever is located at one working position of the two working positions when the voltage applied by the gate electrode to the second electrostatic electrode is less than a preset threshold, the cantilever is switched to the other working position of the two working positions when said voltage is greater than the preset threshold.
US09530597B2 Relay drive device
A relay switch has a coil such that a predetermined voltage is imposed on one end thereof and the other end is grounded with a resistor therebetween, and when the voltage of the coil is at least a predetermined value, the relay switch is turned on and a power source is supplied to an electronic apparatus. A transistor causes the voltage of the coil to be at least the predetermined value by means of drawing in the current flowing through the coil and causing the current to flow to the ground without passing through the resistor when starting the supply of the power source, and after the start of supply of the power source, gradually decreases the amount drawn in of the current flowing through the coil, causing a decrease in a manner so that the voltage of the coil does not fall below the predetermined value.
US09530590B2 Luminous keyboard
A luminous keyboard includes plural bottom-emitting type illumination elements, a sensing module, plural keys, and a light-transmissible supporting plate. As a key is moved toward the sensing module, the sensing module generates a corresponding non-contact key signal. Each bottom-emitting type illumination element is aligned with the corresponding key, and disposed under the corresponding key. The light-transmissible supporting plate is arranged between the plural bottom-emitting type illumination elements and the plural keys. After the light beam provided by each bottom-emitting type illumination element is transmitted through the light-transmissible supporting plate, the light beam is projected to the corresponding key.
US09530588B2 Circuit breaking arrangement
A circuit breaking arrangement is disclosed, which is adapted to be coupled to a transmission line arranged to carry direct current for controllably effecting discontinuation of flow of direct current in the transmission line. The circuit breaking arrangement includes a current interrupter unit adapted to, when actuated, interrupt current in the transmission line and a first resonance circuit and at least a second resonance circuit. Each of the first and the at least a second resonance circuit is adapted to, upon actuation of the current interrupter unit and when the respective resonance circuit is activated, generate a resonance current superposing current of any arc generated in the current interrupter unit after actuation thereof. At least during a predefined period immediately after actuation of the current interrupter unit a resonance current that has been generated by the first resonance circuit flows into the current interrupter unit from a different direction than a resonance current generated by the second resonance circuit would have, or vice versa.
US09530587B2 Switch device
A switch device may have a restriction member provided between a support portion and a fixed contact point portion of a polar board for restricting movement of a movable piece to the polar board. The restriction member may have a set height from the polar board such that the restriction member abuts on the movable where the fixed contact point reaches a predetermined height from the polar board due to wear. The movable piece may be supported by the support portion to be displaceable in the longitudinal direction such that when one side of the movable piece makes contact with the first fixed contact point, in a case where the restriction member makes contact with the movable piece, the movable piece may be displaced in the longitudinal direction on a basis of the contact position with the restriction member to be disconnected from the first fixed contact point.
US09530581B2 Changing the state of a switch through the application of power
A switch includes a spring. The switch further includes a collapsing element. The spring has a first state in which it is being held in tension by a restraining element and a second state in which it is not being held in tension because the restraining element has failed. The collapsing element is situated such that when sufficient power is applied to the collapsing element heat from the collapsing element will cause the restraining element to fail. The switch further includes a first contact coupled to the spring. The switch further includes a second contact coupled to the spring. The first contact and the second contact are separate from each other when the spring is in the first state. The first contact and the second contact are electrically connected to each other when the spring is in the second state.
US09530578B2 Electrical switching apparatus and transmission assembly therefor
A transmission assembly is for an electrical switching apparatus. The electrical switching apparatus includes a housing, a mount, at least one charging mechanism, and a pair of separable contacts. The transmission assembly has a drive assembly and a transfer assembly. The drive assembly includes a rotary driving member, a stored energy mechanism, and a linear driving member partially extending into the stored energy mechanism and being coupled to the rotary driving member. The transfer assembly cooperates with the drive assembly and the separable contacts and includes a sliding transfer component. The transmission assembly moves between a LOADED OPEN position, an UNLOADED CLOSED position, a LOADED CLOSED position, and an UNLOADED OPEN position. When the transmission assembly moves from the LOADED OPEN position to the UNLOADED CLOSED position, the linear driving member drives the sliding transfer component in a generally linear direction, thereby closing the separable contacts.
US09530575B2 Transfer switch for sequentially derived system
A transfer switch configured to transfer connection of each power conductor and neutral conductor of a load between two power supplies. The transfer switch includes a switch member configured to transfer each of the connections in tandem. The transfer switch disconnects each power conductor prior to disconnecting the neutral conductor of the first supply when disconnecting the load from either power supply and connects the neutral connector prior to connecting each power conductor when connecting the load to either power supply.
US09530574B1 Super dielectric materials
A class of materials is provided that has dielectric constants greater than 105. The super dielectric materials (SDM) can be generated readily from common, inexpensive materials. Various embodiments include a porous, electrically insulating material, such as high surface area powders of silica or titantia, mixed with a liquid containing a high concentration of ionic species. In some embodiments, high surface area alumina powders, loaded to the incipient wetness point with a solution of boric acid dissolved in water, have dielectric constants greater than 4*108.
US09530570B2 Manufacturing method of solid-state dye-sensitized solar cells and electrolyte filling device used therefor
The present description is directed to a manufacturing method of solid-state dye-sensitized solar cells and a solid-state electrolyte filling device used in the manufacturing method. The present invention provides a manufacturing method of dye-sensitized solar cells that fills the solid-state electrolyte more uniformly with enhanced efficiency to secure higher light-to-energy conversion efficiency.
US09530565B2 Electronic component
An electronic component has dimensions (length×width×thickness) of about 0.6 mm to about 1.0 mm×about 0.3 mm to about 0.5 mm×about 0.07 mm to about 0.15 mm. An area of a triangle defined by a first hypothetical straight line being in contact with the top of a portion of an outer electrode positioned on a first main surface at a center in the width direction and extending in the length direction, a second hypothetical straight line being in contact with the top of a portion of the outer electrode positioned on the first end surface at the center in the width direction and extending in the thickness direction, and a third hypothetical straight line being in contact with the outer electrode at the center in the width direction and being inclined at about 45° with respect to the first and second hypothetical straight lines is about 450 μm2 or larger.
US09530564B2 Dielectric ceramic and multilayer ceramic capacitor
A dielectric ceramic that contains Al and Si, as well as a barium titanate-based compound having a perovskite type crystal structure as a primary component. The total molar amount of Al and Si is 2 to 4 parts by mole with respect to 100 parts by mole of Ti, and the content ratio of Al with respect to the total molar amount is 0.2 or less (excluding 0) on the molar ratio basis. The dielectric ceramic may also contain at least one specific rare earth element Re, such as Gd, Tb, or Dy.
US09530562B2 Dielectric ceramic composition and dielectric device
To provide a dielectric ceramic composition having a high dielectric constant, i.e., 3,000 or more, at elevated temperatures at or above 150° C. and having a practically sufficient relative dielectric constant at an applied DC electric field of 2 V/μm, and to provide a dielectric device including such a dielectric ceramic composition, a dielectric ceramic composition is a composite oxide represented by formula (1): {[(BisNat)a(BiuKv)bBac]1-dNad}xTi1-dNbdO3  (1) where a, b, c, d, s, t, u, v, and x are numbers satisfying the following conditions: 0.20≦a<0.95 0.00(0.80−a)/2 a+b+c=1 0.02≦d<0.10 0.90≦s+u≦1.00 0.45≦t≦0.50 0.45≦v≦0.50 0.95≦x≦1.05.
US09530560B2 Ceramic electronic component with low equivalent series resistance and method for manufacturing the same
External electrodes, electrically connected to exposed portions of internal electrodes, are arranged on end surfaces of a ceramic main body of a laminated ceramic capacitor. Alloy layers of a metal contained in internal electrodes, and a metal contained in external electrodes, are arranged at the boundaries between external electrodes, and the ceramic main body and internal electrodes. Plating layers are provided on surfaces of external electrodes. A ceramic electronic component having a reduced ESR is thus provided.
US09530554B2 Multilayer coil component
Disclosed herein is a multilayer coil component including a copper-nickel mixture for an internal electrode, in which a nickel content in the internal electrode is adjusted to thereby optimize the area ratio of nickel to copper while the copper-nickel mixture is used for a material for the internal electrode of the multilayer coil component, thereby preventing deterioration in characteristics of the multilayer coil component, so that ferrite characteristics of the multilayer coil component, such as, impedance (Z), inductance (L), and the like, can be improved.
US09530552B1 Magnetic circuit switching device with single-sided attraction
A magnetic circuit switching device with single-sided attraction includes a housing with a first side and a second side individually arranged at either side, where the first side has an attraction surface to attract an iron core; a permanent magnet having a first type magnetic pole and a second type magnetic pole individually arranged at inner and outer side with opposite properties; a nonconductive axial tube for the iron core to engage, having an opening at the right side extending to the second side of the housing; and a spring providing elastic force for the iron core to displace. With a magnetic path alteration function and the elastic force from the spring, the structure is able to keep the iron core in a pre-determined position. Therefore the iron core has a wider stretching range for operation, increasing the possibilities of wider application and ensuring in-time adjusting in case of deviation and wear and tear of the device. Also, the present invention requires less power for operation, thus achieving an energy-saving effect.
US09530551B2 Solenoid actuator
A short travel solenoid actuator (44) is disclosed which comprises at least one pole piece (47, 48), an armature (51), an electromagnet coil (46) arranged, in response to energization, to actuate the armature between first and second positions. A permanent magnet (52) is positioned and orientated so as to latch the armature in the first and second positions when the armature is in the first and second positions respectively. A spring (53) is arranged to bias the armature.
US09530550B2 Remote control kit
A remote control kit includes a magnetic holder and a remote control, wherein the magnetic holder includes a magnet and a non-slip member which covers the magnet. The remote control includes a case and a ferromagnetic member therein. The magnetic holder is fixed on a wall where the remote control is ready to be placed. The ferromagnetic member of the remote control is made of a material selected form the group consisting of iron, cobalt, and nickel, and therefore the remote control can be attached onto the magnetic holder via magnetic force.
US09530545B2 Device comprising a thermal fuse and a resistor
The present invention discloses a device comprising a thermal fuse, a resistor and a protective casing. The protective casing provides housing for the thermal fuse and the resistor and increases the anti-explosion properties and insulating and voltage-withstanding properties at the same time. The thermal fuse and the resistor can be used as a basic unit and be directly installed into a switch-mode power supply. It is capable of replacing the existing simple wirewound resistor or the wirewound resistor with an external contact type thermal fuse, and realizing the functions of general impedance, over-current fuse protection, surge protection, anti-explosion and over-temperature protection in case of overloading.
US09530544B2 Shielded electrical conductor furcation assembly
A furcation assembly for electrical conductors of an electro-optical cable with electrical conductors and optical conductors has an inner tube surrounded by a metallic shield layer and a polymer jacket surrounding the metallic shield layer. The inner tube may have a circular or a generally ovaloid cross section inner diameter. A transition housing may be applied over an interconnection between the metallic shield layer and a metallic shield of the electro-optical cable. A pull strand may be provided in the inner tube inner diameter, for ease of insertion of the electrical conductors and/or additional water proofing characteristics.
US09530538B2 Wire harness manufacturing method and wire harness
A wire harness includes plural cables, a first sheet and a second sheet. The first sheet includes a base sheet, and a self-adhesive layer formed on a whole of only first surface of the base sheet. The first sheet is wound on the plural cables so that a non-self-adhesive layer formed on a second surface, opposite to the first surface, of the first sheet is located inside. The second sheet includes a base sheet and a self-adhesive layer formed on a whole of only first surface of the base sheet. The second sheet is wound on the first sheet so that the self-adhesive layer of the first surface of the second sheet is located inside.
US09530532B2 Hybrid conductor with circumferential conducting layers
A conducting medium or high voltage cable can include at least one conductor surrounded by an insulating layer. One or more layers of conducting wires can surround the insulating layers, and the layers of conducting wires themselves can be separated by insulating layers. The centrally disposed conductor and surrounding circumferential conducting layers can include copper, aluminum, or a combination of both. The central conductor can range between about 1000 kcmil to about 4000 kcmil cross-sectional area, and the surrounding layers of conducting wires can be at least about 250 kcmil.
US09530531B2 Process for producing highly conducting and transparent films from graphene oxide-metal nanowire hybrid materials
A process for producing a transparent conductive film, comprising (a) providing a graphene oxide gel; (b) dispersing metal nanowires in the graphene oxide gel to form a suspension; (c) dispensing and depositing the suspension onto a substrate; and (d) removing the liquid medium to form the film. The film is composed of metal nanowires and graphene oxide with a metal nanowire-to-graphene oxide weight ratio from 1/99 to 99/1, wherein the metal nanowires contain no surface-borne metal oxide or metal compound and the film exhibits an optical transparence no less than 80% and sheet resistance no higher than 300 ohm/square. This film can be used as a transparent conductive electrode in an electro-optic device, such as a photovoltaic or solar cell, light-emitting diode, photo-detector, touch screen, electro-wetting display, liquid crystal display, plasma display, LED display, a TV screen, a computer screen, or a mobile phone screen.
US09530529B2 Radioisotope battery and manufacturing method thereof
This invention relates to a radioisotope battery and a method of manufacturing the same, wherein manufacturing the radioisotope battery and shielding radiation emitted from the radioisotope Ni-63 from the outside are achieved simultaneously. This radioisotope battery includes a semiconductor layer, a seed layer formed on the semiconductor layer, a radioisotope layer formed on the seed layer, and a radiation shielding layer formed on the radioisotope layer and for shielding radiation of the radioisotope layer form the outside.
US09530517B2 Read disturb detection in open blocks
A storage device with a memory may include read disturb detection for open blocks. An open or partially programmed block may develop read disturb errors from reading of the programmed portion of the open block. The detection of any read disturb effects may be necessary for continued programming of the open block and may include verifying that wordlines in the unprogrammed portion of the open block are in the erase state. A modified erase verify operation for the open block is used in which programmed wordlines are subject to a higher erase verify read voltage, while the unprogrammed wordlines are subject to an erase verify bias voltage.
US09530513B1 Methods and apparatus to read memory cells based on clock pulse counts
A disclosed example sense programmed states of memory cells includes starting a counter at a time of activating a plurality of memory cells. Binary values are obtained based on sense amplifiers in circuit with the memory cells in response to the counter reaching a trigger count value. A programmed state of the memory cells is determined based on the binary values.
US09530511B1 Operating method of memory device
An operating method of a memory device includes providing the memory device and performing an erase operation. The memory device includes a substrate, a gate dielectric layer formed on the substrate, a gate conductive layer formed on the gate dielectric layer, a charge trapping layer, a charge blocking layer, a source region, and a drain region. The charge trapping layer has a vertical portion formed on a sidewall of the gate conductive layer and a horizontal portion formed between the substrate and the gate conductive layer. The charge blocking layer is formed between the substrate and the charge trapping layer. The source and drain regions are formed in the substrate and located at two sides of the gate conductive layer respectively. Performing the erase operation includes applying an erase voltage to the gate conductive layer for inducing a BBHH injection and a FN hole tunneling.
US09530509B2 Data programming method, memory storage device and memory control circuit unit
A data programming method, a memory storage device and a memory control circuit unit are provided. The method includes: receiving first data and programming the first data into a first lower physical programming unit; receiving second data; in response to the second data to be programmed into a first upper physical programming unit corresponding to the first lower physical programming unit, performing a first data obtaining operation which does not include reading the first lower physical programming unit by using a default read voltage; and programming the second data into the first upper physical programming unit according to the third data obtained through the first data obtaining operation.
US09530508B2 Memory device and method for operating the same
A memory device and a method for operating the same are provided. The memory device includes a substrate, a plurality of word lines, and a plurality of dummy word lines. The word lines and the dummy word lines are located on the substrate. At least one side of each dummy word line is adjacent to the word line. At least one word line and at least one dummy word line form a group. The method for operating the memory device includes the following. At least one group is selected, and the group is operated. A first operational voltage is applied to the word line of the group. A second operational voltage is applied to the dummy word line of the group.
US09530505B1 EEPROM memory cell gate control signal generating circuit
An EEPROM memory cell gate control signal generating circuit, which includes a high-voltage row decoding circuit and a plurality of word selection circuits; the output of the high-voltage row decoding circuit is divided into two routes, which output a first total wordline voltage used for providing the erasing positive voltage and a second total wordline voltage used for providing the erasing negative voltage, respectively; besides, the two-route voltages are inputted into the individual word selection circuits respectively, which avoids the influence of the erasing positive voltage on the grid oxide layer of an NMOS transistor and the influence of the erasing negative voltage on a PMOS transistor, and can save the MOS transistor used for isolating the grid oxide layer.
US09530496B2 Method for programming switching element
In order to realize a switching element that is highly reliable and can be highly integrated, in a method for programming a switching element of the present invention, programming of the switching element is performed by increasing or decreasing a resistance value R of a resistive-change film by applying a first pulse voltage to a first electrode or a second electrode, a measurement of the resistance value R is performed, verification in which it is determined whether or not the measured resistance value R is equal to a desired value is performed, and reprogramming of the switching element is performed by applying a second pulse voltage whose polarity is the same as that of the first pulse voltage to the same electrode to which the first pulse voltage is applied on the basis of the resistance value R when the resistance value R is not equal to the desired value.
US09530492B2 NAND array hiarchical BL structures for multiple-WL and All-BL simultaneous erase, erase-verify, program, program-verify, and read operations
Several 2D and 3D HiNAND flash memory arrays with 1-level or 2-level broken BL-hierarchical structures are provided for Multiple Whole-WL and All-BL simultaneous operations in Dispersed Blocks. The global bit line (GBL) is divided to multiple 1 (top)-level broken metal2 GBLs plus optional lower-level broken metal1 local bit lines (LBLs). A preferred Vinhibit supply higher than Vdd can be selectively supplied via horizontal metal0 power line LBLps to charge selected broken GBLs/LBLs which can also be selectively discharged via a String source line. Charge-sharing technique for precharging and discharging of broken GBL/LBL capacitors for NAND cell data sensing is used in Read and Verify operations with reduced power consumption and latency. Recall technique to restore the desired Program Data stored in the broken GBL/LBL capacitors is used for Multiple-WL and All-BL Program and Program-Verify operation with reduced program current for highest program yield superior P/E cycles.
US09530487B2 Method of writing memory with regulated ground nodes
A method of writing data to an accessed memory cell of an accessed column of an accessed section of a memory array includes, electrically coupling a first voltage source of at least three voltage sources to a column internal ground node of the accessed column; and electrically coupling the first voltage source of the at least three voltage sources to a column internal ground node of an un-accessed column of an un-accessed segment. The memory array has at least one segment. Each memory cell has an internal ground node. The at least one segment has at least one section, and each section has at least one column and at least one row. Each column has at least three switches and a column internal ground node capable of being electrically coupled to at least three voltage sources through a corresponding one of the at least three switches.
US09530486B1 Adaptive technique for adjusting signal development across bit lines for read operation robustness in memory circuits
In one embodiment, a memory array has a pair of bit lines for each column of 1-bit SRAM cells and a word line for each row of cells, where, during a memory read operation, the bit value stored in each cell is detectable by sensing a voltage difference developed between the corresponding bit line pair. A first signal-development circuit is coupled to one bit line to accelerate draining that bit line of charge if a first bit value is stored in the cell, and a second signal-development circuit is coupled to the other bit line to accelerate draining that other bit line of charge if a second, different bit value is stored in the cell. Pulldown devices are provided to ensure that the signal-development circuit operate properly during the pre-charge and voltage difference development phases of the memory read operation, which is now faster due to the signal-development circuits.
US09530484B1 Semiconductor apparatus and semiconductor system including the same
A semiconductor apparatus includes a plurality of unit memory blocks and a plurality of sense amplifier arrays configured to be shared with two or more unit memory blocks among the plurality of unit memory blocks, and amplify data of the unit memory blocks. When a unit memory block corresponding to an external address and a unit memory block corresponding to a refresh address among the plurality of unit memory blocks are coupled in common to one of the plurality of sense simplifier arrays, the semiconductor apparatus stores the refresh address and executes a normal operation command corresponding to the external address.
US09530483B2 System and method for retaining dram data when reprogramming reconfigurable devices with DRAM memory controllers incorporating a data maintenance block colocated with a memory module or subsystem
A system and method for retaining dynamic random access memory (DRAM) data when reprogramming reconfigurable devices with DRAM memory controllers such as field programmable gate arrays (FPGAs). The DRAM memory controller is utilized in concert with a data maintenance block collocated with the DRAM memory and coupled to an I2C interface of the reconfigurable device, wherein the FPGA drives the majority of the DRAM input/output (I/O) and the data maintenance block drives the self-refresh command inputs. Even though the FPGA reconfigures and the majority of the DRAM inputs are tri-stated, the data maintenance block provides stable input levels on the self-refresh command inputs.
US09530481B2 Ferroelectric random access memory with plate line drive circuit
A ferroelectric random access memory includes a memory cell matrix constituted by a plurality of 1T1C type memory cells. Each of the plurality of memory cells is connected to a j bit line and one pair of k word lines and k plate lines. A plate line drive circuit selectively applies one of a first potential and a second potential having a higher potential level than the first potential to one plate line of the k plate lines. An equalizing circuit performs an equalizing process in which the first potential is applied to each of the j bit lines. The plate line drive circuit applies a third potential having a potential level between the first and second potentials to the one plate line, before starting the equalizing process by the equalizing circuit.
US09530474B2 Semiconductor integrated circuit including semiconductor memory apparatus including a plurality of banks
A semiconductor memory apparatus includes: a memory cell area including a plurality of banks each having a plurality of octet banks corresponding to a first group and a plurality of octet banks corresponding to a second group; and a control unit configured to generate a plurality of control signals to input a data signal to any one octet bank of the first group and any one octet bank of the second group with a predetermined margin.
US09530471B1 Semiconductor memory apparatus
A semiconductor memory apparatus may include a driving voltage-applying unit and a sub-word line-driving unit. The driving voltage-applying unit may be configured to generate a driving voltage in response to an active signal, a word line-enabling signal and a sub-word line selection signal. The sub-word line-driving unit may be configured to drive a sub-word line as a voltage level of the driving voltage in response to a main word line and the sub-word line selection signal.
US09530470B2 Method and apparatus for pre-charging data lines in a memory cell array
Memories, pre-charge circuits, and methods for pre-charging memory are described. One such method includes providing a voltage to a data line and adjusting the voltage provided to the data line based at least in part on a voltage difference between a target voltage and a voltage of the data line being pre-charged. An example pre-charge circuit includes a voltage generator configured to generate an output voltage having a magnitude based at least in part on a reference voltage and a feedback signal, first and second drivers, and a voltage detector. The voltage detector is configured to determine a voltage difference between the reference voltage and a sample voltage of a data line coupled to the second driver and generate the feedback signal based at least in part on the difference.
US09530466B1 System and method for memory access dynamic mode switching
Systems, methods, and other embodiments associated with providing dynamic switching between memory access modes are described. According to one embodiment, an apparatus includes first memory and second memory. The apparatus also includes a memory control logic configured to facilitate memory access of the first memory and the second memory using either a first memory access mode or a second memory access mode. The first memory access mode is configured to facilitate memory access of both the first memory and the second memory. The second memory access mode is configured to facilitate memory access of one of the first memory or the second memory. The memory control logic is configured to dynamically switch between the first memory access mode and the second memory access mode, without having to remap memory or reboot the system, in accordance with a region-based memory address mapping technique.
US09530463B1 Memory device and method thereof
A first input of a sense amplifier is connected to a first bitline, a second input of the sense amplifier is connected to a second bitline, a third input of the sense amplifier is coupled to a third bitline. The sense amplifier provides at an output an indicator of a storage state of a memory cell connected to the first bitline based upon information provided to the sense amplifier via the first, second, and third bitlines.
US09530461B2 Architectures and techniques for providing low-power storage mechanisms
Techniques to utilize a very low power state with a memory subsystem that includes one or more non-volatile memory devices and a volatile memory system. A memory controller is coupled with the one or more non-volatile memory devices and the volatile memory system. The memory controller comprising at least an embedded control agent and memory locations to store state information. The memory controller to selectively enable and disable the one or more non-volatile memory devices. The memory controller transfers the state information to the volatile memory system prior to entering a low power state. Control circuitry is coupled with the memory controller. The control circuitry to selectively enable and disable operation of the memory controller.
US09530460B2 Array structure of single-ploy nonvolatile memory
An array structure of a single-poly nonvolatile memory includes a first and a second MTP sections, a first and a second OTP sections. The first MTP is connected to a first word line, a first source line, a first erase line and a plurality of bit lines. The second MTP section is connected to a second word line, a second source line and shares the first erase line and the plurality of bit lines with the first MTP section. The first OTP section is connected to a third word line and shares the first source line and the plurality of bit lines with the first MTP section. The second OTP section is connected to a fourth word line, a third source line, and shares the plurality of bit lines with the first MTP section, the second MTP section and the third OTP section.
US09530459B2 Semiconductor memory device including a repeater circuit on main data lines
A semiconductor memory disclosed in this disclosure includes first and second memory cell arrays, a first main data line that transfers the read data read from the first memory cell array, a second main data line that transfers the read data read from the second memory cell array, a main amplifier coupled to the second main data line, and a repeater circuit coupled to the first main data line and the second main data line.
US09530458B2 Stub minimization using duplicate sets of signal terminals
A microelectronic structure has active elements defining a storage array, and address inputs for receipt of address information specifying locations within the storage array. The structure has a first surface and can have terminals exposed at the first surface. The terminals may include first terminals and the structure may be configured to transfer address information received at the first terminals to the address inputs. Each first terminal can have a signal assignment which includes one or more of the address inputs. The first terminals are disposed on first and second opposite sides of a theoretical plane normal to the first surface, wherein the signal assignments of the first terminals disposed on the first side are a mirror image of the signal assignments of the first terminals disposed on the second side of the theoretical plane.
US09530457B2 Data processing device
A microcomputer provided on a rectangular semiconductor board has memory interface circuits. The memory interface circuits are separately disposed in such positions as to extend along the peripheries of the semiconductor board on both sides from one corner as a reference position. In this case, limitations to size reduction imposed on the semiconductor board can be reduced compared with a semiconductor board having memory interface circuits only on one side. Respective partial circuits on each of the separated memory interface circuits have equal data units associated with data and data strobe signals. Thus, the microcomputer has simplified line design on a mother board and on a module board.
US09530456B2 Data processing system having data reproduction independent of data processing
A processing unit performs a method including controlling a reading-out of data from a first storage medium at a predetermined read-out data rate to produce inputted data, and controlling a compression of the inputted data to produce first compressed data of a first compressed format. The method includes controlling a storage of the first compressed data in a second storage medium at a faster writing data rate than the predetermined read-out data rate, controlling a reading-out of second compressed data of a second compressed format from the second storage medium, and controlling a decompression of the second compressed data to produce decompressed data. The method also includes controlling simultaneously the storage of the first compressed data in the second storage medium, the reading-out of the second compressed data from the second storage medium, and audibly reproducing the decompressed data. The first compressed format is different from the second compressed format.
US09530454B2 Systems and methods for real-time pixel switching
Systems and accompanying methods are provided for real-time pixel switching in video. A video having first and second portions is provided and is presented to a user, with the first video portion being initially visible to the user and the second video portion not initially visible to the user. During presentation of the video, a user interaction with the first video portion is received, and a selected region of the second video portion is identified based thereon, where the selected region defines a subset of pixels from the second video portion. The selected region is then overlaid on the first video portion, and playback of the second video portion and the first video portion is synchronized.
US09530448B1 Tray braking device
The tray braking device includes a tray, a tray motor, a sliding plate and a buffer structure. The tray is used for carrying a disc. The tray motor is used for driving the tray to a finish position from a first position. The sliding plate is disposed on a base. The buffer structure is disposed between the sliding plate and the base. When the tray moves to a second position from the first position, the tray moves at a first speed, and the second position is positioned between the first position and the finish position. When the tray moves towards the finish position from the second position, the tray drives the sliding plate to move, such that the buffer structure leans between the sliding plate and the base and generates deformation, making the tray move at a second speed slower than the first speed.
US09530446B2 Information recording apparatus, information recording method, information reproducing apparatus, and information reproducing method
An information recording apparatus for an optical information disk includes a recording position determining unit that determines a recording position on the optical information disk; and a recording and reproducing unit that performs recording and reproduction on the optical information disk. The recording position determining unit determines recording positions for all or some areas of the optical information disk, and the recording and reproducing unit records data at the recording positions on the optical information disk determined by the recording position determining unit.
US09530445B1 Perpendicular heat-assisted magnetic recording (HAMR) medium with a perovskite oxide intermediate layer
A heat-assisted magnetic recording medium has a heat-sink layer, a chemically-ordered FePt alloy magnetic layer and a perovskite oxide intermediate layer between the heat-sink layer and the magnetic layer. The perovskite oxide intermediate layer may function as both a seed layer for the magnetic layer and a thermal barrier layer, as just a seed layer for the magnetic layer, or as just a thermal barrier layer. The intermediate layer is formed of a material selected from a ABO3 perovskite oxide (where A is selected from one or more of Ba, Sr and Ca and B is selected from one or more of Zr, Ce, Hf, Sn, Ir, and Nb), and a A2REBO6 rare earth double perovskite oxide (where RE is a rare earth element, A is selected from Ba, Sr and Ca, and B is selected from Nb and Ta).
US09530444B2 Magnetic recording medium
An aspect of the present invention relates to a magnetic recording medium, which comprises a magnetic layer comprising ferromagnetic powder and binder on a nonmagnetic support, wherein the ferromagnetic powder is ferromagnetic hexagonal ferrite powder comprising 3 to 12 weight percent of Al, based on Al2O3 conversion, relative to 100 weight percent of a total weight of the powder, the magnetic layer further comprises abrasive, and a maximum plan view surface area of the abrasive as determined for a 4.3 μm×6.3 μm rectangular region of the magnetic layer by a scanning electron microscope is less than 0.06 percent relative to 100 percent of a total surface area of the region.
US09530443B1 Method for fabricating a magnetic recording device having a high aspect ratio structure
A method provides a magnetic write apparatus on a substrate. A mask is provided on a substrate. The mask has a trench therein. The trench has a top, a bottom and a plurality of sidewalls extending between the top and the bottom of the trench. The top of the trench is wider than the bottom. A protective layer is provided in the trench. The protective layer extends from the top of the trench along a first portion of the plurality of sidewalls such that the bottom of the trench and a second portion of the plurality of sidewalls are free of the protective layer. The structure is provided in a remaining portion of the trench.
US09530440B1 Compensating for loss of current through shorted tunneling magnetoresistance sensors
Embodiments of the present invention provide methods, systems, and computer program products for compensating for loss of current through shorted tunneling magnetoresistance (TMR) sensors. In one embodiment, for a magnetic head having multiple TMR read sensors, a first voltage limit is set for most parts and a second voltage limit is set for all of the parts. A number of TMR read sensors which are allowed to function between the first and the second voltage limits is determined using a probability algorithm, which determines the probability that the application of the second voltage limit will result in a dielectric breakdown within an expected lifetime of a drive is below a threshold value. For the number of TMR read sensors which are allowed to function at voltages between the first and second voltage limits, a determined subset of those sensors are then allowed to function at the second voltage limit.
US09530439B2 Disk drive head suspension tail with stiffened edge alignment features
A head gimbal assembly for a disk drive includes a flexure tail terminal region having flexure bond pads in electrical communication with the head. Each of the flexure bond pads includes a widened region of a corresponding one of a plurality of electrical traces in a conductive layer, and a discontinuous bond pad backing island in a structural layer that overlaps the widened region. The flexure tail terminal region also includes a plurality of discontinuous edge stiffener islands in the structural layer that do not overlap the widened region of any flexure bond pad, and that are disposed no more than 50 microns from one of the two opposing longitudinal outer edges of the flexure tail terminal region. At least one of the plurality of discontinuous bond pad backing islands is disposed no more than 50 microns from one of the two opposing longitudinal outer edges.
US09530438B1 Storage device with adaptive voltage generation system
Apparatus and method for generating supply voltages in a data storage device. In some embodiments, the apparatus includes a data transducer adjacent a rotatable magnetic recording medium, the data transducer having a write coil and an electromagnetic source for thermally assisted recording by the write coil. A preamplifier/driver circuit (preamp) has a write driver adapted to supply write currents to the write coil and a source driver adapted to supply source voltage to the electromagnetic source. A voltage regulation circuit applies a first positive supply voltage to the write driver and a different, second positive supply voltage to the source driver.
US09530435B2 Voiced sound interval classification device, voiced sound interval classification method and voiced sound interval classification program
The voiced sound interval classification device comprises a vector calculation unit which calculates, from a power spectrum time series of voice signals, a multidimensional vector series as a vector series of a power spectrum having as many dimensions as the number of microphones, a difference calculation unit which calculates, with respect to each time of the multidimensional vector series, a vector of a difference between the time and the preceding time, a sound source direction estimation unit which estimates, as a sound source direction, a main component of the differential vector, and a voiced sound interval determination unit which determines whether each sound source direction is in a voiced sound interval or a voiceless sound interval by using a predetermined voiced sound index indicative of a likelihood of a voiced sound interval of the voice signal applied at each time.
US09530433B2 Voice activity detection for noise-canceling bioacoustic sensor
A low overhead voice activity detection technique for a noise-canceling bioacoustic sensor consumes, as inputs, signals generated by a body microphone and an environment microphone and produces, as an output based on these inputs, an indication of whether voice activity is present. The technique applies a novel dual ANC configuration that produces, in addition to the normal noise reduction function, a signal composed of environmental sounds with body sounds attenuated and a signal composed of body sounds projected into the acoustic environment, primarily speech sounds. The technique then applies to these derived signals an algorithm based on the scientific observation that speech intensity, within limits, rises and falls to match environmental sound intensity to provide voice activity detection.
US09530432B2 Method for determining the presence of a wanted signal component
This invention provides a method for determining, in a speech dialog system issuing speech prompts, a score value as an indicator for the presence of a wanted signal component in an input signal stemming from a microphone, comprising the steps of: using a first likelihood function to determine a first likelihood value for the presence of the wanted signal component in the input signal, using a second likelihood function to determine a second likelihood value for the presence of a noise signal component in the input signal, and determining a score value based on the first and the second likelihood values, wherein the first likelihood function is based on a predetermined reference wanted signal, and the second likelihood function is based on a predetermined reference noise signal.
US09530431B2 Device method, and computer program product for calculating score representing correctness of voice
According to an embodiment, a voice processor includes a presenting unit to present text to an operator; a voice acquisition unit to acquire a voice of the operator reading aloud the text; an identifying unit to identify output intervals of phonemes included in the voice; a determination unit to determine whether each of time lengths of the output intervals is normal; a frequency acquisition unit to acquire frequency values respectively representing occurrence frequencies of contexts, respectively corresponding to the phonemes, the context including the phoneme and another phoneme adjacent to at least one side of the phoneme; and a score calculator to calculate a score representing correctness of the voice on the basis of the determination results of the time lengths of the output intervals and the frequency values of the contexts acquired respectively corresponding to the phonemes.
US09530428B2 Echo cancellation device
An echo cancellation device includes: a full-band echo canceller that generates a pseudo-echo signal; a downsample processor that downsamples a received signal and extracts a low-band component delayed by a delay amount D1; a delay controller that delays the low-band component by a delay amount D2; a delay controller that delays an output signal of the delay controller by a delay amount D3; a low-band echo canceller that generates a pseudo-echo signal delayed by a delay amount D1+D2; and an upsample processor that upsamples the low-band pseudo-echo signal to generate a full-band pseudo-echo signal delayed by the delay amount 2D1+D2. The delay controllers control the delay amounts D2 and D3 such that a tap length LA satisfies a condition of LA≧2D1+D2=D2+D3, the tap length LA indicating a response time of the adaptive filter in the full-band echo canceller.
US09530423B2 Speech encoding by determining a quantization gain based on inverse of a pitch correlation
A method, system and program for encoding and decoding speech according to a source-filter model whereby speech is modelled to comprise a source signal filtered by a time-varying filter. The method comprises: receiving a speech signal comprising successive frames. For each of a plurality of frames of the speech signal: adding a predetermined noise signal generated by a quantization gain multiplied by 0.5 times an inverse of a pitch correlation to the speech signal to generate a simulated signal, determining linear predictive coding coefficients based on the simulated signal frame, and determining a linear predictive coding residual signal based on the linear predictive coding coefficients and one of the speech signal and the simulated signal. Then forming an encoded signal representing said speech signal, based on the linear predictive coding coefficients and the linear predictive coding residual signal.
US09530420B2 Method and apparatus for allocating bits of audio signal
A method and an apparatus for allocating bits of an audio signal. The method includes dividing a frequency band of an audio signal into multiple sub-bands, and quantizing a sub-band normalization factor of each sub-band; classifying the multiple sub-bands into multiple groups, and acquiring a sum of intra-group sub-band normalization factors of each group; performing initial inter-group bit allocation to determine the initial number of bits of each group; performing secondary inter-group bit allocation to allocate coding bits of the audio signal to at least one group; and allocating the bits of the audio signal to sub-bands in the group. The present invention can, by means of grouping, ensure relatively stable allocation in a previous frame and a next frame and reduce an impact of global allocation on local discontinuity in a case of low and medium bit rates.
US09530418B2 Image display apparatus and method of controlling the same
Provided are an image display apparatus and a method of controlling the same. The image display apparatus enabling voice recognition includes: a first voice inputter which receives a user-side audio signal; an audio outputter which outputs an audio signal processed by the image display apparatus; a first voice recognizer which recognizes the user-side audio signal received through the first voice inputter; and a controller which decreases a volume of the audio signal output through the audio outputter to a predetermined level if a voice recognition start command is received.
US09530416B2 System and method for managing models for embedded speech and language processing
Disclosed herein are systems, methods, and computer-readable storage devices for fetching speech processing models based on context changes in advance of speech requests using the speech processing models. An example local device configured to practice the method, having a local speech processor, and having access to remote speech models, detects a change in context. The change in context can be based on geographical location, language translation, speech in a different language, user language settings, installing or removing an app, and so forth. The local device can determine a speech processing model that is likely to be needed based on the change in context, and that is not stored on the local device. Independently of an explicit request to process speech, the local device can retrieve, from a remote server, the speech processing model for use on the mobile device.
US09530413B2 Socket and voice-recognition method using same
A socket includes a voice-receiver, a processing module coupled to the voice-receiver, a converting member coupled to the processing module, and a switching member coupled to the converting member. The switching member is configured to couple to a supply member and a load. The voice-receiver is configured to receive a voice instruction. The processing module is configured to recognize the voice instruction and to output a control signal according the voice instruction. The converting member is configured to convert the control signal to a switching signal. The switching member is configured to be switched on or be switched off according to the switching signal. The supply member is configured to supply power to the load after the switching member is be switched on and not to supply power to the load after the switching member is be switched off. A voice-recognition method is also provided.
US09530411B2 Dynamically extending the speech prompts of a multimodal application
A prompt generation engine operates to dynamically extend prompts of a multimodal application. The prompt generation engine receives a media file having a metadata container. The prompt generation engine operates on a multimodal device that supports a voice mode and a non-voice mode for interacting with the multimodal device. The prompt generation engine retrieves from the metadata container a speech prompt related to content stored in the media file for inclusion in the multimodal application. The prompt generation engine modifies the multimodal application to include the speech prompt.
US09530410B1 Multi-mode guard for voice commands
Embodiments may be implemented by a computing device, such as a head-mountable display, in order to use a single guard phrase to enable different voice commands in different interface modes. An example device includes an audio sensor and a computing system configured to analyze audio data captured by the audio sensor to detect speech that includes a predefined guard phrase, and to operate in a plurality of different interface modes comprising at least a first and a second interface mode. During operation in the first interface mode, the computing system may initially disable one or more first-mode speech commands, and respond to detection of the guard phrase by enabling the one or more first-mode speech commands. During operation in the second interface mode, the computing system may initially disable a second-mode speech command, and to respond to the guard phrase by enabling the second-mode speech command.
US09530408B2 Acoustic environment recognizer for optimal speech processing
A system for providing an acoustic environment recognizer for optimal speech processing is disclosed. In particular, the system may utilize metadata obtained from various acoustic environments to assist in suppressing ambient noise interfering with a desired audio signal. In order to do so, the system may receive an audio stream including an audio signal associated with a user and including ambient noise obtained from an acoustic environment of the user. The system may obtain first metadata associated with the ambient noise, and may determine if the first metadata corresponds to second metadata in a profile for the acoustic environment. If the first metadata corresponds to the second metadata, the system may select a processing scheme for suppressing the ambient noise from the audio stream, and process the audio stream using the processing scheme. Once the audio stream is processed, the system may provide the audio stream to a destination.
US09530402B2 Methods and systems for adapting a speech system based on user characteristics
Methods and systems are provided for adapting a speech system. In one example a method includes: logging speech data from the speech system; detecting a user characteristic from the speech data; and selectively updating a language model based on the user characteristic.
US09530401B2 Apparatus and method for reporting speech recognition failures
Provided are an apparatus and method for reporting speech recognition failures. The method includes detecting pure speech data from input speech data and outputting the detected pure speech data, determining at least one speech recognition failure for the pure speech data, and ascertaining speech recognition failure reasons from a check result for the speech recognition failures and outputting the ascertained speech recognition failure reasons.
US09530397B2 Light efficient acoustically transmissive front projection screens
A front projection screen is provided having a first portion of material and a second portion of material. The first and second portions of material may have an undercut edge profile, and the first and second portions of material may be perforated, such that the perforations allow the first and second portions of material to be at least somewhat acoustically transmissive while substantially maintaining optical efficiency from the front side of the front projection screen. Such optical efficiency has particular utility in stereoscopic projection applications utilizing polarized encoded light.
US09530395B2 Modular music synthesizer
A modular music synthesizer is implemented in a hybrid design incorporating both hardware implementation and software implementation. A plurality of hexagonal-shaped modules are assembled and connected by the user-artist to configure a visual presentation of synthesizer signal generation and signal processing functions. The synthesizer visually replicates hardware functionality by incorporating user controls on many of the modules that are connected to enclosed (embedded) circuit boards. These circuit boards communicate with a system CPU (computer processing unit) that operates softsynth software resident within the CPU to drive audio output. The configuration of the softsynth is determined by the physical arrangement of hardware hexagonal modules that represent the functionality of software modules. The hardware modules provide user interface elements corresponding to parameters of their softsynth counterparts.
US09530393B1 Ergonomic instrument strap
An ergonomic instrument strap designed to eliminate pressure points on a user's shoulder, neck, and back, and wear points on the strap. Unique curves in a portion of the strap draw the downward force out toward user's arm while shifting the strap off a user's shoulder blade, reducing fatigue on neck, back, and shoulder muscles. A wider portion over the shoulder helps to distribute force over wider area, reducing stress load on any one point. Additional layers of cloth and padding help to prevent strong downward forces, increasing comfort for the user. May be left orientation, right orientation, or reversible. Strap may include end pieces. Strap end pieces contain pockets with opening facing the user's body to allow the user to quickly recover if a pick is lost. Side opening prevents pick falling into pocket and becoming irretrievable. Strap may contain zero, one, or two end pieces.
US09530390B1 Pillow practice pad for drummers
A two-part pillow practice pad assembly is provided as an aid to practicing the drums and improving drumming technique. In an embodiment, the two-part pillow practice pad assembly may have a resilient, non-rebounding upper pillow section, and a lower, weighted pillow section. The weighted lower pillow section prevents the pillow practice pad assembly from moving or migrating during use. In an embodiment, the upper and lower pillows are detachably fastened together.
US09530384B2 Display device that compensates for changes in driving frequency and drive method thereof
In a display device that can use a low frequency drive method, in the case of low frequency drive, in a data correction unit (23) of a display control circuit (200), a pixel grayscale value is set such that the differential value between the potential difference between the pixel electrode and the common electrode when a voltage of positive polarity is applied and the potential difference between the pixel electrode and the common electrode when a voltage of negative polarity is applied becomes larger than during normal drive. With this, a correction amount (shift amount) is made larger during low frequency drive than during normal drive, whereby flickers and ghosting during low frequency drive are prevented.
US09530383B2 Display apparatus and driving method thereof
A display device includes: a display panel comprising a plurality of pixels coupled to a plurality of gate lines and a plurality of data lines, respectively; a gate driver configured to drive the plurality of gate lines; a data driver configured to drive the plurality of data lines; and a timing controller configured to control the gate driver and the data driver and to provide the data driver with a data signal generated by compressing an image signal received from an external device, wherein the timing controller is configured to compress the image signal according to a first compression scheme and a second compression scheme to generate a first compression signal and a second compression signal, respectively, and wherein the timing controller is configured to select whichever one, from among the first compression signal and the second compression signal, that has a relatively narrower bit width as the data signal.
US09530382B2 Light management for image and data control
A light control and display technology applicable to light redirection and projection with the capacity, in a number of embodiments modified for particular applications, to produce managed light, including advanced images. Applications include miniature to very large scale video displays, optical data processing, 3-dimensional imaging, and lens-less vision enhancement for poor night-driving vision, cataracts and macular degeneration.
US09530376B2 Driving device and driving method of liquid crystal display device and liquid crystal display device
The present disclosure relates to a driving device and a driving method of a liquid crystal display device and a liquid crystal display device. The liquid crystal display device comprises a display panel. The driving method comprising following steps of: displaying a current image by driving the display panel in a current reverse driving mode; detecting a variation value of a common voltage of the display panel during a prescribed period of time, and determining whether the variation value of the common voltage is greater than a prescribed threshold voltage variation; and in case that the variation value of the common voltage is greater than the prescribed threshold voltage variation, determining an occurrence of an image flickering and changing the current reverse driving mode. According to the present disclosure, the flickering of the liquid crystal display device can be reduced.
US09530374B2 Display device
A display device includes: a display panel including a plurality of gate lines on a substrate, a plurality of data lines crossing the gate lines, and a plurality of pixels, each of the pixels being coupled to one of the gate lines and to one of the data lines; a data driver configured to output data signals through a plurality of channel terminals; and a line selector configured to transmit the data signals to a plurality of data line blocks, each of the data line blocks including a plurality of data lines, wherein the line selector includes a plurality of thin-film transistors, and at least two of the thin-film transistors have different sizes.
US09530371B2 GOA circuit for tablet display and display device
The present invention relates to a GOA circuit for tablet display and a display device. The GOA circuit comprises cascaded plurality of GOA units, the GOA unit comprises a pull-up control part 400 and a transfer part 500; the transfer part 500 comprises a first thin film transistor T22, the gate thereof is connected with the gate signal point Q(n), the drain and the source are respectively input the clock signal CK(n) and output the turn-on signal ST(n); the pull-up control part comprises: a second thin film transistor T11, the gate thereof is input the turn-on signal ST(n−2), the drain and the source are respectively connected with the horizontal scan line G(n−2) and the gate signal point Q(n); a third tin film transistor T12, the gate thereof is connected with the horizontal scan line G(n−1), the drain and the source are respectively connected with the horizontal scan line G(n−1) and the gate signal point Q(n). The present invention also provides a related display device. The present invention can improve the stability of the GOA circuit and the related display device in high temperature.
US09530370B2 Shift register unit and driving method thereof, gate driving circuit and display device
The present disclosure relates to a field of display technology. Provided are a shift register unit and a driving method thereof, a gate driving circuit and a display device. The shift register unit includes an input module, a pull-up module, a pull-down control module and a pull-down module. The turn-on duty ratio of transistors in the shift register unit may be reduced, and the power consumption of the display device product may be reduced.
US09530365B2 Method for controlling signal value on gate line, gate driving circuit and display device
The disclosure relates to a method for controlling signal values on gate lines, a gate driving circuit and a display device. The method comprises: for each of gate lines in the valid display area, in a first frame in any two adjacent frames of image, connecting a gate connecting line in a first layer to a gate line by a first strobe unit and applying a first signal value to the gate line; in a second frame, connecting a gate connecting line in a second layer to the gate line by a second strobe unit and applying a second signal value to the gate line. It may address the issue of H-line Mura due to different impedances of wires in the gate layer and the S/D layer.
US09530364B2 Liquid crystal display
A liquid crystal display includes a first substrate, a gate line and a data line on the first substrate, a plurality of display pixels arranged in a row direction and a column direction of a matrix, on the first substrate, each display pixel including a pixel electrode and a common electrode on the first substrate and overlapping each other, and an insulating film between the pixel and common electrodes, a plurality of non-display dummy pixels at an edge of the matrix of display pixels; and a first common voltage line outside the matrix of display pixels and extending in the row direction.
US09530359B2 Method of driving backlight unit and display device having the backlight unit
According to an exemplary embodiment, a display device includes a backlight unit and a display panel. The backlight unit comprises a single light emitting diode string with a plurality of light emitting diodes that are connected to each other in series and configured to emit light. The backlight unit also comprises a detector configured to generate a first voltage and a second voltage with respect to an output voltage for driving the single light emitting diode string, sample the first voltage at a predetermined time interval to generate a sample voltage, and compare a level of the sample voltage with a level of the second voltage to generate a compared result. The display panel is configured to receive light from the backlight unit to display an image. The compared result determines whether the output voltage is applied to the light emitting diode string.
US09530358B2 Display device control based on integrated ambient light detection and lighting source characteristics
Systems and methods are provided for a display device including one or more methods for modifying the display brightness by automatically adapting to ambient lighting conditions.
US09530357B2 Gradation voltage generator and display driving apparatus
A gradation voltage generator for applying a gradation voltage according to gamma characteristics of a display panel includes a reference gamma selector that receives a maximum reference voltage, a minimum reference voltage, and a first reference voltage, and selects and outputs a maximum gamma voltage and a minimum gamma voltage from among voltages between the maximum reference voltage and the minimum reference voltage, wherein when the maximum reference voltage changes, the minimum gamma voltage is compensated by a difference the changed maximum reference voltage and the first reference voltage and a gamma curve controller that receives the maximum gamma voltage and the minimum gamma voltage, and generates and outputs a plurality of gradation voltages.
US09530353B2 Organic electroluminescent display device and method of driving the same
An organic electroluminescent display device includes an organic electroluminescent diode receiving a driving voltage and a first ground voltage; first and second driving thin film transistors for providing a driving current to the organic electroluminescent diode; a first switching thin film transistor receiving a data voltage and switched by an nth scan signal; a second switching thin film transistor switched by a current providing signal; a third switching thin film transistor receiving a second ground voltage and switched by a selection signal; a fourth switching thin film transistor disposed among an output terminal of the second switching thin film transistor; and a first capacitor disposed among the output terminal of the first switching thin film transistor, the gate terminal of the first driving thin film transistor and the gate terminal of the second driving thin film transistor.
US09530346B2 Organic light-emitting diode display and method of driving the same
An organic light-emitting diode (OLED) display and a method of driving the display are disclosed. In one aspect, the method includes receiving input image data, calculating a load value corresponding to a driving amount of the input image data, and calculating a luminance adjustment value for each of the pixels based at least in part on the load value and a voltage drop proportional value of each of the pixels. The voltage drop proportional value corresponds to a ratio of a voltage drop value to a maximum voltage drop value. The method also includes generating output image data based at least in part on the input image data and the luminance adjustment value and displaying an image corresponding to the output image data.
US09530343B2 Method for correcting gray-scale of display panel
The present disclosure relates to a gray-scale correction method of a display panel, comprising: selecting a plurality of measurement points and specifying a reference point; specifying a plurality of measurement gray-scales, and, under each measurement gray-scale, measuring actual gray-scale of each measurement point when the brightness thereof reaches a reference brightness, wherein the reference brightness is the brightness of the reference point; determining a gray-scale correction coefficient of each measurement point under each measurement gray-scale according to the corresponding relationship between the actual gray-scale and the measurement gray-scale, and establishing an original gray-scale correction coefficient table; extending the original gray-scale correction coefficient table to a gray-scale correction coefficient table of pixel points of the display panel under all gray-scales through linear interpolation algorithm; when a data voltage is to be applied to a pixel point under a gray-scale, searching the gray-scale correction coefficient corresponding to said gray-scale and said pixel point from the extended gray-scale correction coefficient table, correcting the value of said gray-scale accordingly, and driving the display panel according to the corrected gray-scale.
US09530339B2 Apparatus and method for inspecting an organic light-emitting display apparatus
A device for inspecting an organic light-emitting display apparatus includes a power supply unit, a power receiving unit, a wiring location sensing unit, and a control unit. The power supply unit applies an AC signal to each of wirings arranged in the organic light-emitting display apparatus. The power receiving unit senses an electrical signal from each of the wirings. The wiring location sensing unit senses a location of each of the wirings. The control unit determines whether each of the wirings has a defect based on the sensed electrical signal and information pertaining to each wiring type of the wirings.
US09530337B2 Test method and test apparatus for transparent display device
Embodiments of the invention provide a test method and a test apparatus for a transparent display device. The test apparatus for the transparent display device comprises: an optical measuring device disposed on one side of the transparent display device to be tested, and a reference object disposed on the other side of the transparent display device to be tested. A brightness of the transparent display device to be tested is adjustable, and the optical measuring device measures a display effect of the reference object through the transparent display device to be tested which is set to different brightness.
US09530333B1 Real-time driver observation and scoring for driver's education
A method includes, during a driving session in which a student driver operates a vehicle, gathering driving skill data indicative of at least one of behavior of the student driver, acceleration of the vehicle, braking of the vehicle, or steering of the vehicle, and gathering comments from a driving instructor about the driving session. The method also includes generating a driving session report corresponding to the driving session. The driving session report includes at least one score based on the driving skill data, and the comments from the driving instructor about the driving session. Still further, the method includes causing the driving session report to be displayed on a display device.
US09530332B2 Systems and methods for managing the toilet training process of a child
Systems and methods for managing the toilet training process of a child are provided. In one aspect, a computer system for managing toilet training a person is provided. The computer system includes a memory device, a display device, and a processor in communication with the memory device and the display device. The processor is programmed to provide a first set of functionality accessible using the display device. The processor is also programmed to provide a set of enhanced functionality configured in a disabled status. The processor is further programmed to utilize the first set of functionality to identify completion of a toilet training milestone, and reconfigure the second set of enhanced functionality to an enabled status based on identifying completion of the toilet training milestone.
US09530327B2 System and method for managing continued attention to distance-learning content
Management of a user's continued attention to distance learning content using a general purpose computer having a central processing unit, an operating system configured to run multiple program applications concurrently, and a player suitable for presenting the distance learning content. A distance learning module comprises code executable on the central processing unit, as one of the multiple program applications. The distance learning module is operable to interrupt a presentation of the distance learning content at the player to the user in response to prescribed events concerning another one of the multiple program applications. A method executing on a computer that can concurrently run multiple applications identifies events concerning an application other than the distance learning application, processes the identified events so as to identify a prescribed event among the identified events, and interrupts the presentation of the distance learning content in response to the prescribed event.
US09530322B2 Contextual aid to flight management
A method implemented by computer for the management of the flight of an aircraft comprises the steps of receiving flight directives and flight information associated with these directives; determining a flight context of the aircraft; as a function of the context determined, selecting information from among that associated with the formulation of a directive and/or with a current flight directive and/or with a change of a flight directive; sensorially restoring the selected information. Various developments are described, notably links to documentary resources, the determination of anomalies, the use of predefined logic rules and configuration options. System aspects and software aspects are described.
US09530315B2 Method and device for establishing an alternate route in the event of a blocked roadway in a monitored region
A method and a device for establishing an alternate route in the event of a blocked roadway in a monitored region, in particular in an airport ramp. A vehicle is authorized to bypass the blocked roadway by a control center. Position data are repeatedly ascertained with respect to the vehicle by way of a position determining device. The data of the bypass route are ascertained from the position data by way of a computing device. The bypass route data are stored in a memory associated with the control center. Furthermore, authorization data which apply to the blocked roadway and which are stored in the memory are transmitted to the bypass route.
US09530311B2 Traffic information detection system and method thereof
A traffic information detection system and method. According to the traffic information detection method of the present invention, at least one loop coil on a road transmits a signal indicative of electric change induced in the loop coil by a vehicle, at least one loop detection device installed at the garden or escape zone of the road receives the signal transmitted from the loop coil and wirelessly transmits a signal indicative of whether or not a vehicle exists on a road, the velocity of and type of the vehicle, and a traffic signal controller wirelessly receives the signal transmitted from the loop detection device, thereby acquiring traffic information.
US09530310B2 Method and system for detecting and tracking a vehicle of interest utilizing a network of traffic image-capturing units
Methods and systems for detecting a vehicle of interest utilizing one or more traffic image-capturing units and a centralized server. A request from an authority to detect a vehicle of interest with respect to an incident can be verified based on particular criteria. One or more of the image-capturing units can be selected along with location information stored in a database in order to enable a search. A notification can be sent to the authority upon identification of the vehicle of interest by the image-capturing unit(s). An area or radius of search can be calculated to alert one or more other image-capturing units for use in tracking the vehicle of interest. Data regarding the vehicle of interest can then be transmitted to an incident management module to dynamically update details regarding detection of the vehicle of interest.
US09530309B2 Object detection system
In a projector or an optical receiver, a master device produces pieces of definition information that determines timings of detection processes in the device including its own device and transmits the pieces of definition information to the slave device. The master device simultaneously transmits commands to require operations of internal timers to be synchronized with each other to the other slave devices in response to elapse of a time corresponding to a period in which a circulating period of the detection processes of the sensors proceeds by a predetermined cycle. Each of the slave devices corrects the timer in response to the command, and determines a timing at which a detection process should be performed with reference to a time point for correction on the basis of the definition information matched with its own device to execute the detection process.
US09530307B2 System and method for transmitting sensor data from a rotating component of a turbomachine
A system for transmitting data from a rotating component of a turbomachine includes a plurality of thermal sensors coupled to corresponding rotatable components within the turbomachine where each thermal sensor generates a discrete analog signal indicative of temperature. A plurality of transmitter assemblies is coupled to an end of a rotor shaft of the turbomachine. The plurality of transmitter assemblies comprises a first transmitter assembly and a second transmitter assembly. The first transmitter assembly is configured to receive the discrete analog signals from the plurality of thermal sensors, multiplex the plurality of discrete analog signals into a single amplifier and an analog-to-digital converter to generate a single stream of digital data therefrom. The system also includes a slip ring assembly having a plurality of conductive rings where at least one of the conductive rings defines a digital signal path between the first transmitter assembly and a data acquisition system.
US09530304B2 Distributed sensor network
Distributed sensing is provided. A first node of a plurality of nodes receives a fire status message from a second node of the plurality of nodes. The fire status message indicates a determination by the second node that an environmental condition exceeds a predetermined threshold. Each node of the plurality of nodes is a computing device. The first node estimates an arrival time of a fire based, at least in part, on the fire status message and a geographic location of the second node. The arrival time is a time until the fire arrives at a predetermined geographic location.
US09530301B1 Electronic disk drive apparatus
An electronic apparatus includes a casing, a first sliding tray module, a second sliding tray module, a switch module and a main board. The first sliding tray module includes a first belt unit, a baffle is disposed on one end of the first belt unit. The switch module includes an elastic piece and a switch. The first sliding tray module and/or the second sliding tray module slide/slides in or out to make the elastic piece and the baffle touched or untouched. The switch generates a switch signal according to whether the elastic piece and the baffle being touched or untouched. While the elastic piece and the baffle are untouched, the main board is configured to generate a detecting time according to the switch signal, and while the detecting time is longer than a safe time, the main board generates a warning signal through the electronic apparatus.
US09530300B1 Hand-held radiation detector
A hand-held radiation detector that produces a voltage as a function of the amount of ionizing radiation is described. The hand-held radiation detector may be configured for measuring low levels of ionizing radiation including alpha radiation. A light alert feature may blink and/or a sound alert feature may produce a bird chirping sound at a frequency relative to the amount of radiation detected. The ionizing radiation detector may have an ion chamber comprising a first electrode chamber and a second electrode configured inside the first electrode chamber, and it may be an open type ion chamber allowing ambient air to enter the ion chamber. A sensitivity range selector may be used to increase or decrease the voltage range for detection. An input selector may be used to select the type of detection a user desires, such as consumables or radon gas for example.
US09530299B2 Methods and apparatuses for assisting a visually-impaired user
In one embodiment, a method for assisting a visually-impaired user is provided. The method includes determining, based upon an input from at least one sensor, a body position or posture of a user. The method also compares, using a processor, the determined body position to a plurality of body positions or postures to identify whether the determined body position or posture is acceptable. The method further includes providing a feedback signal indicating a change in body position or posture to assist the visually impaired user.
US09530295B2 Wireless access control system and methods for intelligent door lock system
A wireless access control system includes a mobile device for accessing a lock. A mobile device controller generates a signal configured to be transmitted to an intelligent lock system. The intelligent lock system includes a lock, a processor with a memory, one or more wireless communication devices coupled to a circuit and one or more motion transfer device coupled to a drive shaft, the lock receiving the signal, and enabling a change of a state of the lock between locked and unlocked. A geo-positioning system sensor determines a geographic location of the mobile device, the controller determines whether or not the geographic position is within a geo-fence for the lock.
US09530293B2 Wireless acoustic glass breakage detectors
An acoustic glass breakage detector including a pulsating current-powered microphone and operable for generating pulsed signal data corresponding to sound waves detected thereby, a sample and hold circuit operable for converting the pulsed signal data into a voltage level signal and storing the voltage level signal, a sound frequency band pass amplifier operable for ascertaining whether the voltage level signal corresponds to an explosion-like sound typical of an initial glass-breakage sound, a flex wave band pass amplifier operable for ascertaining whether the voltage level signal corresponds to a flex wave typical of an initial glass-breakage sound, and circuitry operable, responsive to ascertaining that the voltage level signal corresponds to an explosion-like sound typical of an initial glass-breakage event and that the voltage level signal corresponds to a flex wave typical of an initial glass-breakage sound, for ascertaining that the pulsed signal data is indicative of a glass-breakage event.
US09530287B2 Gaming system and method providing indication of notable symbols
The gaming device and method disclosed herein produces an indication of an appearance of a notable or designated symbol in a symbol display region while at least one reel is spinning. The indication continues while the notable symbol appears in the symbol display region and while the at least one reel is spinning. Different indications are produced for the different notable symbols when appearing in the symbol display region while the at least one reel is spinning.
US09530286B2 Reel device for a gaming machine
A gaming machine includes: a reel having an outer circumferential surface on which symbols are lined up; a reel driving mechanism which rotates the reel to rearrange the symbols; a magnet which is provided in the reel driving mechanism to change an external magnetic field in accordance with the rotation of the reel; a magnetic force detecting mechanism which detects a magnetic force of the external magnetic field so as to output a magnetic force detection signal; a reel setting unit by which the magnetic force detection signal and arrangement positions of the symbols are associated with one another; and a reel drive control unit which controls the reel driving mechanism so that the symbols are rearranged in a predetermined arrangement based on the magnetic force detection signal and the arrangement positions of the symbols.
US09530280B2 Electronic gaming device with card tournament functionality
Examples disclosed herein relate to systems and methods, which may receive wagers on one or more paylines. The systems and methods may utilize one or more tournament game structures. The systems and methods may utilize one or more power-up cards in the one or more tournament game structures.
US09530279B2 Three-card war game with wagers
A wagering playing card game is played by: a dealer providing a set of playing cards; the dealer accepting at least one wager at a player position on an underlying playing card game; the dealer providing a first subset of exactly three random playing cards from the set of playing cards to a player position and dealer position; the dealer evaluates each player hand against the dealer hand as follows: a) a player position hand having all three cards with a rank below a predetermined rank automatically loses; b) a highest rank card from each player hand and the dealer hand play a game of war as a first sub-game, with the highest rank winning; c) a second highest rank card from each player hand and the dealer hand play a game of war as a second sub-game, with the highest rank winning; d) any ties void a sub-game.
US09530277B2 Virtual ticket-in and ticket-out on a gaming machine
An electronic gaming machine includes a cabinet, a display mounted to the cabinet, a wireless interface for communicating with a portable electronic device, a network interface for communicating with a validation server, a bill validator coupled to a game controller configured to accept bills and printed ticket vouchers, and a removable cash box. The game controller includes a processor and a memory configured to control a wager-based game played on the EGM, redeem virtual ticket vouchers and printed ticket vouchers, receive an indication to transfer value to the EGM via a virtual ticket voucher, receive the virtual ticket voucher including a virtual ticket voucher validation number from the portable electronic device via the wireless interface, validate the virtual ticket voucher with the validation server via the network interface, deposit a credit amount associated with the virtual ticket voucher, and notify the validation server that the virtual ticket voucher is redeemed.
US09530275B2 Gambling game objectification and abstraction
Systems for configuring a gaming system include a plurality of real world controller modules, wherein each real world controller module is constructed to provide a gambling game; a game world controller, wherein the game world controller is constructed to: connect to a selected real world module; receive a conveyance of actions taken by a player, during the player's consumption of one or more elements of an entertainment game; trigger a commitment of a wager of real world credits in the selected real world controller module's gambling game; receive a gambling outcome of the wager of real world credits; increment in the entertainment game using the communications network, the one or more elements of the entertainment game when real world credits are won; and decrement in the entertainment game using the communications network, the one or more elements of the entertainment game when real world credit is lost.
US09530274B2 Device identification
The system provides the capability of identifying the presence and location of network devices. During start-up, a device sends its MAC address out on the network. A local switch collects MAC and IP addresses for the devices connected to it. Periodically, the switch transmits raw Ethernet frames, USB packets, or TCP packets containing tables of devices and associated MAC/IP addresses. When a device receives information about another device, the device may attempt communication with that device. First, a verification procedure is used to validate the devices. Subsequently, communication is possible between the devices.
US09530272B2 System and method for displaying multiple activities
A virtual activity space is provided to users. The virtual activity space, or instances of the virtual activity space, may be used to enable users to participate in an activity such as, e.g., a card game. A user may participate in multiple activities concurrently. One of these activities, the so-called primary activity, is more dominantly and/or prominently presented than the other activities, the so-called secondary activities. Navigating between concurrent activities is accomplished through an interface that is displayed at the periphery of a view of a virtual activity space. A selection of a secondary activity simultaneously causes the primary activity to become a secondary activity, and causes the selected activity to become the new and current primary activity.
US09530270B2 Conveying money items
An apparatus for conveying money items, which is configured to singulate money items during conveyance, sense characteristics of money items during conveyance and eject money items from a conveyor.
US09530268B1 ADA compliant coin recycling device
The present invention relates generally to an ADA compliant coin recycler device that is capable of sorting a mixed denomination of coins, storing the coins and dispensing the desired amount of coins in the desired denomination. Additionally, the ADA compliant coin recycler device of the present invention also comprises a coin elevator assembly attached to the outside of the housing, which receives coins from the coin recycler and elevates the coins to an accessible height above the ADA's Standards for Accessible Design minimum reach requirement.
US09530261B2 Method and device for triggering, using an RFID reader, a procedure for actuating a means for locking/unlocking the access doors of a motor vehicle
A method and device for triggering, via an RFID reader (5) endowed with a transmitting antenna (6), a procedure for actuating an element for locking/unlocking the access doors (2) of a motor vehicle (1). A coil (7) is arranged in the vicinity and in the field of action of the transmitting antenna (6), and: the RFID reader (5) is commanded so as to control the successive transmission of electromagnetic pulses of the same power, upon each pulse, a value representative of the electrical voltage at the terminals of the coil (7) is measured, and the procedure for actuating the locking/unlocking element is triggered in the event of a variation in the measured values greater than a determined value.
US09530255B2 System and method for communicating with an electronic control unit of a vehicle to determine if the vehicle is safe
A system and method for sending and receiving messages from an electronic control unit of a vehicle to determine if the vehicle is safe includes a processor, a display and a port. The port and display are in communication with the processor. The port is configured to communicate with the electronic control unit of the vehicle. The processor is configured to receive information from the electronic control unit of the vehicle. The information includes processing of at least one trouble code or other data from at least one subsystem of the vehicle. The processor is further configured to determine and display on the display device a safety state of the vehicle based on the received trouble codes or data from the subsystem of the vehicle.
US09530248B2 Model-based helmet design to reduce concussions
A system and method for designing a helmet to reduce mild traumatic brain injury sustained by a user during primary or secondary head impact include modeling a helmeted head including a head, brain, and helmet using a finite element computer model, the finite element computer model including material properties for the head, brain structures, and helmet and estimating at least intracranial pressure, brain strain and strain rate in response to an impact; and selecting at least one of a helmet cushion material and helmet shell material to limit at least one of intracranial pressure, brain strain and strain rate to a corresponding threshold for an associated impact.
US09530237B2 Interpolation circuitry and techniques for graphics processing
Techniques are disclosed relating to interpolation for texture mapping. In some embodiments, a graphics unit includes circuitry configured to map a texture to a screen space such that a set of multiple in the screen space falls between first and second adjacent texels of the texture in a first dimension. In some embodiments, the graphics unit also includes texture processing circuitry configured to perform different types of interpolation for pixels in the group of pixels. In these embodiments, this includes determining pixel attributes for first and second end groups of pixels in the set of pixels using a nearest-neighbor interpolation technique and attributes of the first and second texels respectively. In these embodiments, this also includes determining pixel attributes for an intermediate group of pixels in the set of pixels using a second, different interpolation technique and attributes of both the first and second texels.
US09530232B2 Augmented reality surface segmentation
Methods, systems, computer-readable media, and apparatuses for providing intuitive, functional, and convenient ways of enabling a user of a head-mounted display unit or another augmented reality enabled device to interact with various user interfaces and other features provided by such a unit or device are presented. In some embodiments, a computing device, such as a head-mounted display unit, may receive camera input of a scene. Subsequently, the computing device may identify at least one reference object in the scene, for example, based on detecting one or more rectangles in the received camera input. The computing device then may receive input that defines a surface segment relative to the at least one reference object. Thereafter, the computing device may render the surface segment.
US09530231B2 Method for generating masking image using general polygonal mask
A method for generating masking image using general polygonal mask includes receiving a pixel of a raw image and a polygon vertices array corresponding to a polygonal mask, determining whether the pixel is inside the polygonal mask, labeling the pixel to be a masked pixel if the pixel is inside the polygonal mask, or labeling the pixel to be a visible pixel if the pixel is outside the polygonal mask, and outputting the masked pixel or the visible pixel to generate the masking image.
US09530229B2 Data object visualization using graphs
A presentation engine presents facts in a UI having a graph. Through manipulation of the UI, an end-user can add or remove facts from the graph, and can sort the facts shown in the graph based on values that are shown, or not shown, in the graph. The presentation engine determines a graph type that best facilitates interpretation of the facts by the end-user and automatically creates a graph of that type. Possible graph types include bar graphs, scatter plots, timelines, and maps.
US09530226B2 Systems and methods for optimizing N dimensional volume data for transmission
A method and system for optimizing N dimensional volume data for transmission is disclosed. The device and method including organizing points based on XYZ location, into volumes, which are recursively divided by N into smaller volumes, where N is greater than 1, and decompressing each volume, by encoding a reference volume then encoding the remaining volumes as a distance from the reference cuboid or the most recently recorded cuboid.
US09530225B1 Point cloud data processing for scalable compression
A point cloud contains data points having coordinates that locate each data point in a coordinate system. Cell boundaries are defined in the point cloud and a unique index is assigned to each cell. The indexes of the cells are assigned to any of data point contained in a cell having the same index. The index data points can be accessed in a manner analogous to rasterized or gridded data while maintaining the arbitrary or random distribution associated with point clouds. The indexed point cloud can be further processed to achieve a scalable compression level, either losslessly by increasing redundancy in the point cloud data and/or by separating the point cloud data into relevancy bands, or by conventional lossy techniques, such as by exploiting the redundancies created in the point cloud data to represent the point cloud in a finite number of symbols.
US09530224B2 Intra prediction method of chrominance block using luminance sample, and apparatus using same
Disclosed are an intra prediction method of a chrominance block using a luminance sample and an apparatus using the same. An image decoding method comprises the steps of: calculating an intra prediction mode of a chrominance block on the basis of an LM mapping table when the chrominance block uses an LM; and generating a prediction block for the chrominance block on the basis of the calculated intra prediction mode of the chrominance block. When intra prediction mode information of chrominance blocks are decoded, mutually different tables are used depending on whether or not an LM is used, so that encoding and decoding can be performed without an unnecessary waste of bits.
US09530223B2 Image correction method and image correction device
An image correction method and an image correction device are provided. The image correction method includes the following steps: obtaining a gray level value of a pixel in an image and a frequency domain value of the gray level value; determining whether the frequency domain value is smaller than a first threshold; performing an adaptive gamma correction procedure on the gray level value according to the frequency domain value and outputting the result if the frequency domain value is smaller than the first threshold; outputting the gray level value directly if the frequency domain value is not smaller than the first threshold.
US09530216B2 Image processing apparatus and image processing method
The image processing apparatus performs region designation with respect to a displayed image. The image processing apparatus comprises a display unit configured to display an image constituted by a predetermined number of pixels, an input unit configured to receive a selection operation with respect to the image, a control unit, and a storage unit. The control unit generates a plurality of divided regions acquired by dividing the image in accordance with similarity calculated based on pixel values and pixel locations. Each time a divided region among the plurality of divided regions is selected according to the selection operation received by the input unit, the control unit stores identification information of the selected divided region in the storage unit in association with a selection order of selecting the divided region. The control unit displays the divided region corresponding to the stored identification information on the display unit in an identifiable manner.
US09530213B2 Single-sensor system for extracting depth information from image blur
Hardware and software methodology are described for three-dimensional imaging in connection with a single sensor. A plurality of images is captured at different degrees of focus without focus change of an objective lens between such images. Depth information is extracted by comparing image blur between the images captured on the single sensor.
US09530211B2 Display control apparatus, a method of controlling a display control apparatus and display apparatus
A method of controlling a display control apparatus in a display system includes causing a display unit to generate a first certain image indicating a first presentation image to be overlapped on a certain object in display on a display medium on the basis of the recognized certain object; determining a wiping area wiped by a wiper on the display medium on the basis of detected position after the first presentation image is displayed on the display medium; and causing the display unit to generate a second certain image indicating a second presentation image resulting from deletion of a portion corresponding to the wiping area in the first presentation image in the display on the display medium.
US09530202B2 Inspection apparatus and inspection method
An inspection apparatus includes an optical image acquisition unit to acquire an optical image of a photomask on which a plurality of figure patterns are formed, a first measurement unit to measure a first positional deviation amount in the horizontal direction at each position on the photomask accompanying deflection of the surface of the photomask generated by supporting the photomask using a support method which is used for acquiring the optical image, a second measurement unit to measure a second positional deviation amount of each of the plurality of figure patterns, by using the optical image, and a difference map generation unit to generate a difference map in which a difference value obtained by subtracting the first positional deviation amount from the second positional deviation amount is used as a map value, with respect to a region on the surface of the photomask.
US09530197B2 Digital signage for immersive views
Techniques for generating and superimposing digital signage onto an immersive view. In an exemplary embodiment, certain entities are occluded or otherwise unviewable in an immersive view of an environment. For such entities, digital signage may be generated and superimposed in a suitable area of the immersive view, and further indicating, e.g., directions to such entities from a viewing location, as well as other metadata, such as business name, website, etc. To determine whether a nearby entity is displayed in the immersive view, a planar layout storing geometrical data associated with entities in the vicinity may be loaded and processed.
US09530190B2 Image denoising method and image denoising apparatus
The present invention provides an image denoising method and an image denoising apparatus. The image denoising method includes performing preliminary denoising processing to an acquired image to be processed, so as to obtain a preliminarily denoised image; calculating a residual quantity corresponding to a central pixel of each unit area in the image to be processed according to numerical values of specific energy parameters to which the image to be processed and the preliminarily denoised image correspond, respectively; and using the residual quantity to calculate a weight matrix corresponding to each unit area, and performing non-local mean value calculation to the image to be processed according to the weight matrix, so as to realize the denoising processing of the image to be processed. The image denoising method is able to denoise effectively, and make a denoised image more visually natural.
US09530188B2 Image processing method, image processing system, and image processing program
The present invention relates to an illumination spectrum estimation method in which an illumination spectrum is calculated on the basis of weather information.
US09530187B2 Controlling element layout on a display
Some embodiments provide a method for displaying an electronic publication. The method receives a selection of a cover page displayed for an electronic publication. The method animates an opening of the cover page to a first content page of the electronic publication that appears as an opposite side of the cover page during the opening animation. While displaying a second content page of the electronic publication, the method receives input to close the electronic publication. The method animates a closing of the electronic publication in order to display the cover page. The second content page appears as an opposite side of the cover page during the closing animation.
US09530186B2 Real-time image processing for optimizing sub-images views
An image processor and method for processing a sub-image (100a) specified within a global image (100). The processor (DZC) and the method yield a modified sub-image (100m) with spatial frequencies of large scale structures suppressed or removed and the modified sub-image is adapted to the dynamic grey value range of a screen (110) on which said modified sub-image (100m) is to be displayed.
US09530181B2 Computer System for Continuous Oblique Panning
A computer system for continuously panning oblique images is disclosed. More particularly, the computer system uses a methodology whereby separate oblique images are presented in a manner that allows a user to maintain an understanding of the relationship of specific features between different oblique images when panning.
US09530177B2 Layer access method, data access device and layer access arrangement method
A data access method is provided. The data access method is applied for a data device access device to access data from N layers to display an image, where N is a positive integer. Each of the N layers includes a horizontal start point, a horizontal end point, a vertical start point and a vertical end point. The data access method includes: dividing the image into a plurality of regions according to the horizontal start points, the horizontal end points, the vertical start points and the vertical end points, wherein the regions respectively correspond to the N layers; and accessing data from the respective layers corresponding to the regions when displaying the image.
US09530174B2 Selective GPU throttling
A method and apparatus of a device that manages a thermal profile of a device by selectively throttling graphics processing unit operations of the device is described. In an exemplary embodiment, the device monitors the thermal profile of the device, where the device executes a plurality of processes that utilizes a graphics processing unit of the device. In addition, the plurality of processes include a high priority process and a low priority process. If the thermal profile of the device exceeds a thermal threshold, the device decreases a first GPU utilization for the low priority process and maintains a second GPU utilization for the high priority process. The device further executes the low priority process using the first GPU utilization with the GPU and executes the high priority process using the second GPU utilization with the GPU.
US09530173B2 Information processing device, imaging device, and information processing method
There is provided an information processing device including N first clock conversion units (N is an integer) that convert image data as parallel data into image data having a specific clock cycle, a serial conversion unit that converts N pieces of the converted image data into one-system serial data and outputs the converted data, a parallel conversion unit to which the converted image data is input and that converts the data into N pieces of parallel data having a predetermined number of bits, a synchronized data generation unit that generates synchronized data of the image data, and N second clock conversion units that reconvert the N pieces of converted image data to an original clock cycle from the specific clock cycle and set the clock cycle of the converted image data to be in a phase in synchronization with the synchronized data generated by the synchronized data generation unit.
US09530172B2 Encoding hidden information in spatial line frequencies
A method of encoding a hidden image in high frequency spatial frequencies of a line pattern of a host image. A set of host image spatial frequencies is generated based on a predefined mapping of a domain of a set of representative scalar values of the hidden image and a domain of the host image spatial frequencies. The line pattern of the host image is generated based on the set of host image spatial frequencies. The host image may be composed of tiles containing parallel line segments, with each tile encoding a corresponding one of the scalar values. The host image may be composed of a stochastic line pattern generated from a white noise image convolved with a space variable kernel based on the predefined domain mapping. The hidden image may be decoded algorithmically or optically in a single step.
US09530154B2 Advertising receptacle
A receptacle may include a container to receive trash and other items. The receptacle may also include a display area to provide advertisements to people located in the vicinity of the receptacle.
US09530149B2 Keyword-based services for mobile device messages
A software and/or hardware facility that identifies keywords in a message received by a mobile device and provides advertising and contextual services to the mobile device based on a keyword selection by a user. The facility analyzes a received message to identify keywords in the message. The keywords are identified based on user-specific information that is maintained on the mobile device. The message is displayed to the user with the identified keywords highlighted to the user. When the user selects a keyword, the facility identifies one or more advertisements that are targeted to a user in a manner that takes into account user-specific information. The facility also identifies one or more contexts that are related to the keyword. The facility displays the identified advertisements and contexts to the user. If the user selects an advertisement or context, relevant services are called to deliver responsive content to the user.
US09530145B2 Providing social impact information associated with identified products or businesses
Embodiments of the invention are directed to methods and apparatuses for capturing a real-time video stream using a mobile computing device, determining, using a computing device processor, which images from the real-time video stream are associated with goods and businesses consistent with a predetermined social impact, and presenting on a display of the real-time video stream, one or more indicators, each indicator being associated with an image determined to be consistent with a predetermined social impact.
US09530144B2 Content output device, content output method, content output program, and recording medium having content output program recorded thereon
An information providing device associates in advance and stores a characteristic element which is a candidate to be specified from an image, with content. Further, the information providing device is configured to specify a difference between characteristic elements by comparing a characteristic element specified from a currently acquired image with a characteristic element specified from an image acquired prior to (in the past) the image, and acquire content associated with the characteristic element related to the difference, and display the content on a display.
US09530139B2 Evaluation of voice communications
One-to-many comparisons of callers' words and/or voice prints with known words and/or voice prints to identify any substantial matches between them. When a customer communicates with a particular entity, such as a customer service center, the system makes a recording of the real-time call including both the customer's and agent's voices. The system segments the recording to extract different words, such as words of anger. The system may also segment at least a portion of the customer's voice to create a tone profile, and it formats the segmented words and tone profiles for network transmission to a server. The server compares the customer's words and/or tone profiles with multiple known words and/or tone profiles stored on a database to determine any substantial matches. The identification of any matches may be used for a variety of purposes, such as providing representative feedback or customer follow-up.
US09530135B2 Method, apparatus, and network system for displaying security identifier on page
The present disclosure discloses a method, an apparatus, and a network system for displaying a security identifier on a page. The method includes: receiving a display request for a numerical value transfer page, where the display request at least carries link information of the numerical value transfer page and a numerical value transfer object identifier of the numerical value transfer page, and the link information of the numerical value transfer page includes domain name information of a domain name to which the numerical value transfer page belongs; determining, according to a preset correspondence between a transfer object identifier and domain name information, whether the link information of the numerical value transfer page matches domain name information corresponding to the transfer object identifier; if yes, when displaying the numerical value transfer page, displaying a security identifier in a page function type identifier column on an interface of a client.
US09530134B2 Authentication on mobile device using two-dimensional code
A two-dimensional code generated from encrypted original authentication data can be displayed on an authentication device. The code is read and decrypted by an authentication application on a mobile device. This can generate and display a new two-dimensional code. The new code can contain additional information, and the new two-dimensional code is read by the two-dimensional code reading unit of an authentication device. It is then authenticated.
US09530130B2 Systems and methods for correction of information in card-not-present account-on-file transactions
In one aspect, a method for processing a card-not-present account-on-file transaction is provided. The transaction involves a cardholder using payment card information stored by a merchant. The method includes receiving an authorization request message for the transaction, the authorization request message received at a payment network from an acquirer associated with the merchant and receiving an authorization response message, the authorization response message received at the payment network from an issuer. The authorization response includes a denial indicator indicating that the transaction has been denied. The method further includes querying a database coupled to the payment network to determine whether the database includes updated payment card information for a payment card associated with the transaction. The method additionally includes transmitting the updated payment card information associated with the payment card account identifier associated with the transaction to the acquirer for the acquirer to communicate to the merchant.
US09530129B2 Secure authentication and payment system
The present invention provides a service for allowing secure financial transactions to be carried out, the service involving authenticating a user's identity and/or status as part of a financial transaction with another party and in the event that the user is authenticated arranging for the transaction to be completed without revealing the user's financial details and/or other personal details to that other party. Authentication data and transaction data may be communicated over any suitable communications channel(s). The invention provides a trusted authentication and payment environment that protects a user's financial details, but allows them to be securely authenticated and arranges for transactions to be fulfilled, while providing other parties with reassurance that transactions will be completed. In this way, fraud and theft due to misappropriation of financial details can be minimized.
US09530125B2 Method and system for secure mobile payment transactions
A method for facilitating the widespread use of the PIN-Debit payment method for Internet “eCommerce” and mobile payments sales which requires little or no change for the cardholders, merchants, debit networks and card issuers based primarily on the introduction of a layer of middleware and wherein the Debit Networks and Issuing Banks may customize the implementation of the services based on individual strategy and cardholder preferences.
US09530121B2 Vehicle service procedures
A method and apparatus for carrying out a set of vehicle inspections including, but not limited to, wheel alignment measurement, brake testing, tire tread depth measurement, tire pressure monitoring, vehicle battery testing, and a review of vehicle diagnostic trouble codes in an efficient manner using a multi-function vehicle service system and a single vehicle service bay or inspection lane. Results of the vehicle inspections are incorporated into customized reports generated for a customer or for a technician, and which may be utilized to obtain approval from the customer to conduct necessary repairs and/or provide beneficial vehicle services.
US09530119B1 System and methods for dynamically applying an electronic messaging budget to messaging activities within a business
A system and methods for establishing and enforcing an electronic messaging budget. In at least one embodiment, the inventive method involves identifying a set of users of an electronic message system. Next, an electronic message budget for the set of users is calculated or otherwise determined, and a portion of the budget is allocated to each user, group of users, department, or other suitable element, etc. In response to one of the users attempting to send an electronic message, a cost of the message is calculated and compared to that user's (or group's) available messaging budget. If the cost exceeds the budget, then the message may not be delivered or its delivery may be conditioned on some action of the user.
US09530114B2 Method and apparatus for operating, interfacing and/or managing for at least one optical characteristic system for container handlers in a container yard
Methods and several apparatus embodiments are disclosed operating Optical Characteristic Systems (OCS) in a container storage and/or transfer yard supporting the automated recognition of container codes displayed on various sides of the containers being stored and/or transferred. At least one processor may initiate an operational process by an OCS mounted on a container handler to create an operational result, select the operational process based upon an operational schedule and communicate with at least one OCS to receive an image of a container being handled by the container handler to at least partly create a container code estimate for a container inventory management system. A program system directing at least one computer implementing these operations, and may reside in computer readable memory, an installation package and/or a download server. The computer readable memory may or may not be accessibly coupled to the computer.
US09530112B2 Common conditions for past projects as evidence for success causes
A processor-implemented method, system, and/or computer program product identifies a cause of a level of success in multiple projects from a set of past projects. Multiple artifacts describe conditions associated with each project from a set of past projects, where a cause for a level of success in the past projects is initially unknown. Logic identifies a set of common artifacts in multiple projects from the set of past projects, where the set of common artifacts describes common conditions that are common to all of the multiple projects. Additional logic identifies a level of success experienced by each of the multiple projects. In response to a particular set of projects having a same level of success, common conditions identified by the set of common artifacts are identified as the cause for the same level of success experienced by all of the projects in the particular set of projects.
US09530110B2 Autonomic management of autonomous management systems
In general, the techniques of this invention are directed to autonomic management of autonomic management systems. In particular, the embodiments of this invention use a measure, analyze, and respond model to autonomically manage one or more autonomic management systems. By understanding specific state information of these autonomic management systems, embodiments of the invention may achieve target performance for the autonomic management systems through operations monitoring, analyzing current system state against target state, and modifying the configurations or resources of the autonomic management systems.
US09530109B2 Iterative pattern generation algorithm for plate design problems
A method to generate a plurality of groups each including at least one of a plurality of elements. The method includes selecting at least one candidate element from the plurality of elements as a candidate to be included in a group, determining whether or not to generate the group including the at least one candidate element selected in the selecting step, based on an element evaluation value associated with each of the at least one candidate element selected in the selecting step, provided that a determination is made to generate the group in the determining step, generating the group including the at least one candidate element selected in the selecting step, and weighting the element evaluation value of each of the at least one element according to how many times the each element is included in already-generated groups to reflect the weighted element evaluation value in next group generation.
US09530105B2 Managing entity organizational chart
Displaying organizational information of an entity includes storing data representing nodes associated with members of the entity in a database accessible by members of the entity. Data representing connections between the nodes that represent hierarchical relationships between the members is stored. An organizational chart comprising the nodes and connections is displayed on a presentation surface associated with a particular member of the entity. Input to create new nodes and connections is received from the particular member of the entity. When the new nodes are associated with a group that is associated with the particular member, the displayed nodes and connections are updated in response to the received input.
US09530104B1 Scalable bootstrap method for assessing the quality of machine learning algorithms over massive time series
Described is a system for assessing the quality of machine learning algorithms over massive time series. A set of random blocks of a time series data sample of size n is selected in parallel. Then, r resamples are generated, in parallel, by applying a bootstrapping method to each block in the set of random blocks to obtain a resample of size n, where r is not fixed. Errors are estimated on the r resamples, and a final accuracy estimate is produced by averaging the errors estimated on the r resamples.
US09530101B1 Method for calculating sensor performance of a sensor grid using dynamic path aggregation
A technique is provided for determining expected maximum probability of detection of targets moving through a sensor grid to maximize performance of the sensor grid by changing the sensor grid variables. Non-spatial variables from a plurality of sensors of the sensor grid are removed to provide that sensor performance of the plurality of sensors is a function of spatial variables. A selection is made for the desired description of flow of targets such as pedestrians through the sensor grid between restricted stochastic flow and unrestricted stochastic flow. The specific technique and related equations for determining expected maximum probability of detection for each sensor depends on whether restricted stochastic flow or unrestricted stochastic flow is selected.
US09530100B2 Reasoning engines
A reasoning engine is disclosed. Contemplated reasoning engines acquire data relating to one or more aspects of various environments. Inference engines within the reasoning engines review the acquire data, historical or current, to generate one or more hypotheses about how the aspects of the environments might be correlated, if at all. The reasoning engine can attempt to validate the hypotheses through controlling acquisition of the environment data.
US09530099B1 Access to network content
A method and system for improving access to network content are described. Aspects of the disclosure minimize the delay between a navigation event and a network response by prerendering the next navigation event. For example, the method and system may predict a likely next uniform resource locator during web browsing to preemptively request content from the network before the user selects the corresponding link on a web page. The methods and systems describe a variety of manners for prerendering content and managing and configuring prerendering operations.
US09530098B2 Method and computer program product for providing a response to a statement of a user
The present disclosure includes a method for providing a response to a statement of a user. The method includes receiving user input that comprises a portion of a user statement. The method also includes selecting, before receiving a whole user statement, an answerable statement response between an answerable statement, multiple answerable statements and a response to an answerable statement. The selecting is responsive to user input and to structured representations of answerable statements answerable by an answering entity. Further, the method includes sending to the user information representative of response to the user statement.
US09530097B2 Associative relevancy knowledge profiling architecture, system, method, and computer program product
Provided are architectures, system, methods, and computer program products that provide a user with the ability to define an association of data and/or information from known reference sets perceived by the user as relevant to a subject matter domain, thereby imparting and formalizing some of the user's knowledge about the domain. An associative relevancy knowledge profiler may also allow a user to create a profile by modifying or restricting the known reference sets and windowing the results from the association as a user might refine any other analysis algorithms. An associative relevancy knowledge profiler may also be used to define a user profile used by the user and others. A user profile may be usable in various manners depending upon, for example, rights management permissions and restrictions for a user.
US09530096B2 Automatic identification and use of alternate user contact information
Computer-implemented techniques for automatic identification and use of alternate user contact information can include identifying, at a server having one or more processors, a set of patterns from training electronic messages, each pattern indicating a pattern of contact information context. The techniques can include storing and utilizing, at the server, the set of patterns to obtain a set of alternate contact information for a target user. In response to a use of a specific alternate contact information for the target user by a source user at a computing device, the techniques can include providing, from the server to the computing device, a suggestion for the source user. Examples of the suggestion may include a virtual address for an electronic message or at a social network, a physical address for navigation, and a telephone number for calling or incoming caller identification.
US09530094B2 Jabba-type contextual tagger
Example methods, apparatuses, or articles of manufacture are disclosed that may be implemented, in whole or in part, using one or more computing devices to facilitate or otherwise support one or more processes or operations for a Jabba-type contextual tagger.
US09530089B2 Wearable device with overlapping ends coupled by magnets of a selected width, length and depth
A wearable device is provided with a wearable device structure. The wearable device has a first end and a second end, each with a plurality of magnets. The first and second ends are coupled by overlapping at least a portion of the first end magnets to at least a portion of the second end magnets. A size of the magnets is: (i) length, 0.5 mm to 30 mm; (ii), width, 0.5 mm to 30 mm; and (iii) thickness or depth, 0.5 mm to 10 mm. ID circuitry is provided at a surface or an interior of the wearable device.
US09530085B2 Information processing apparatus and data processing method for controlling an operation clock signal
An information processing apparatus includes a plurality of modules and a change processing portion. The modules are capable of executing data processing on data stored in a memory connected thereto via a bus. The change processing portion is configured to change a frequency of an operation clock signal to be supplied to each module, in accordance with either one of or both a number and types of the modules that execute the data processing in parallel, during execution of a specific data process of executing the data processing by each module at a preset execution timing.
US09530081B2 Similarity detecting apparatus and directional nearest neighbor detecting method
In order to detect similar data from a great deal of data at high speed, a similarity detecting apparatus includes a random number generating unit 3 which calculates random number data based on a parameter list, a table managing unit 5 which calculates a plurality of key calculation functions based on the random number data, calculates a plurality of tables based on input data, and calculates a candidate data list based on a query shown by a search condition, and a data processing unit 6 which calculates search result data from the candidacy data list to satisfy the condition shown a search condition. Each table is calculated for a value corresponding to a key to show a data list of data in which the data substituted into a key calculation function is equal to the key. A candidate data list contains a plurality of search data list and a search data list corresponding to the table shows the value corresponding to a query value obtained by substituting the query into the key calculation function.
US09530080B2 Systems and methods for configuring baby monitor cameras to provide uniform data sets for analysis and to provide an advantageous view point of babies
Systems and methods for monitoring babies with cameras using a centralized computation and storage center that allows using visual output signals for computer vision and machine learning analysis and high-level reasoning of baby movements. The system comprises a camera located at a predefined working point above a baby's crib, and one or more communication networks between components of the system including a web-based network for in-depth computer vision and machine learning analysis of the visual output signals by an analysis server.
US09530075B2 Presentation and organization of content
Embodiments are provided for organization and presentation of content. In some embodiments, a plurality of images and a plurality of similarity rules for image categorization are received. For each image in the plurality of images, that image and each remaining image from the plurality is compared by: applying each similarity rule to the image and a remaining image from the plurality to obtain a numeric result, and recording the numeric result for the pair of images in a numeric representation, the numeric representation embodying similarities. The numeric representation is used as a reference for clustering the plurality of images into clusters of similar images, and each image is stored with a marker denoting a cluster to which it has been assigned.
US09530074B2 Flame detection system and method
A hazard detection system measures a color and intensity of a portion of an image of a scene. The image is obtained using a known gain and/or exposure such that the image substantially lacks any saturation. A black body brightness temperature and the corresponding block body intensity are determined based on the measured color. A hazard condition, such the presence of a flame, can be detected using a comparison of the measured intensity and the computed intensity. The gain and/or exposure can be selected such that only the pixels of intensity greater than a certain threshold generally saturate in the captured image. Hazard conditions, such as smoke, can be detected using images in which selective saturation is permitted.
US09530065B2 Systems and methods for use at a vehicle including an eye tracking device
Systems and methods for a vehicle including an eye tracking device. The systems and methods use input from the eye tracking device. The systems and methods are configured to communicate with a driver based on input from the eye tracking device. For example, the systems and methods are configured to generate indicators on a display based on input from the eye tracking device.
US09530063B2 Lane-line recognition apparatus including a masking area setter to set a masking area ahead of a vehicle in an image captured by an image capture unit
An apparatus for recognizing a lane line. In the apparatus, when a three-dimensional object lies in the same lane as a subject vehicle and a distance between the three-dimensional object and the subject vehicle is small in an image acquired by an image capture unit, a masking area setter sets a masking area that is partially truncated at or near a lower end of the three-dimensional object in the image. A degree-of-belief calculator is configured to, for each of the edge points extracted by the edge-point extractor, calculate a degree of belief that the edge point is on the lane line. The degree of belief when the edge point is in the masking area is set less than the degree of belief when the edge point is outside the masking area. A lane-line recognizer is configured to recognize the lane line based on the degrees of belief calculated for the edge points.
US09530058B2 Visual-assist robots
In one embodiment, a visual-assist robot includes a housing defining a base portion, an imaging assembly, a motorized wheel assembly positioned at the lower surface of the base portion, a processor disposed within the housing and communicatively coupled to the imaging assembly and the motorized wheel assembly, and a non-transitory memory device disposed within the housing. The imaging assembly generates image data corresponding to an environment, and at least a portion of the imaging assembly is configured to be disposed above the upper surface of the base portion. The non-transitory memory device stores machine-readable instructions that cause the processor to provide a drive signal to the motorized wheel assembly such that the motorized wheel assembly moves the visual-assist robot to a desired location within the environment, determine objects from the image data received from the imaging assembly, and transmit message data for receipt by a user.
US09530057B2 Maintenance assistant system
A maintenance assistance system and method of operating are provided. The maintenance assistance system may include, but is not limited to, a camera, a speaker, a technician marker, a memory configured to store a location of a plurality of tags and a location of at least one component relative to at least one of the plurality of tags, and a processor communicatively coupled to the camera, the speaker and the memory, the processor configured to receive an indication of one of the components, determine a location of the technician marker relative to the location of the indicated component based upon data from the camera and the location of the indicated component relative to the at least one of the plurality of tags, and output position information to the speaker based upon the determined location of the technician marker relative to the location of the indicated component.
US09530051B2 Pupil detection device
There is provided a pupil tracking device including an active light source, an image sensor and a processing unit. The active light source emits light toward an eyeball alternatively in a first brightness value and a second brightness value. The image sensor captures a first brightness image corresponding to the first brightness value and a second brightness image corresponding to the second brightness value. The processing unit identifies a brightest region at corresponding positions of the first brightness image and the second brightness image as an active light image.
US09530049B2 Kinetic-based tool for biometric identification, verification, validation and profiling
A method for identifying an animal or human, including the steps of collecting and retaining an archive data set of measurements of two or more kinetic stylometrics of a first individual animal or human; collecting and retaining a test data set of measurements of the same two or more kinetic stylometrics of a test individual; and comparing archive and test data sets to determine similarity therefore, wherein similarity within any appropriate confidence interval confirms that the test individual and the first individual are the same. Using similar methods, social or other groups maybe kinetically stylometrically profiled for subsequent individual testing.
US09530045B2 Method, system and non-transitory computer storage medium for face detection
In a face detection method, preprocess an image, and extract corners from the preprocessed image. Then, filter and combine the corners to obtain a connected component for the corners. Extract a centroid from the connected component of the corners, and match the centroid with a facial template. Then, calculate a matching probability of the centroid with the facial template, and identify a region formed by centroids having a matching probability greater than or equal to a predetermined value as a candidate face region. With the method described above, the accuracy and efficiency of face detection can be improved. In addition, the present invention provides a face detection system and a computer storage medium.
US09530043B2 Cell analysis apparatus and method
A cell analysis apparatus may include: an image processing unit imaging cultured cell colonies to convert the imaged cell colonies into digital signals; an outline extracting unit extracting outlines of the cell colonies from image data obtained from the image processing unit; a size calculating unit calculating sizes of the cell colonies from the extracted outlines; and a selecting unit comparing the sizes of the cell colonies with a preset value to select grown cell colonies.
US09530041B2 Processing visible coding sequence, playing visible coding sequence
Embodiments of the present invention generally relate to data processing, and further the embodiments of the invention relate to a method of processing a visible coding sequence and a system thereof, a method of playing a visible coding sequence and a system thereof. The present invention creatively proposes a scheme of determining sampling rate with synchronized frames to realize effective processing of a visible coding sequence. The scheme of processing a visible coding sequence according to the present invention is helpful for visible coding synchronization on the capturing side, enabling the capturing side to determine appropriate sampling rate and sampling timing, and thus effectively acquire the visible coding sequence, which may not only reduce resource waste, but also acquire a complete visible coding sequence.
US09530039B2 Identifier eligibility
In various disclosed examples, an identifier is selected from a first set of identifiers, the selected identifier having a representation of at least two different characters. An indication of a difference between the representation of the selected identifier and representations of one or more identifiers from a second set of identifiers is calculated, and the selected identifier is determined to be an eligible identifier if the indication of the difference satisfies a threshold criteria.
US09530031B2 Position detection system
An electromagnetic wave propagation medium 1 extends in the propagation direction of an electromagnetic wave and has an electromagnetic wave propagation space sandwiched between conductors in the direction perpendicular to the electromagnetic wave propagation direction. A base unit 2 and multiple terminals 3 are placed on the electromagnetic wave propagation medium 1. When the position of a terminal 3 is detected, the base unit 2 transmits a position detection signal through the electromagnetic wave propagation medium 1 to the terminal 3. This position detection signal is attenuated more heavily during its propagation through the electromagnetic wave propagation medium 1 than a communication signal for use in normal communication is. The signal strength of the position detection signal drops as it moves away from the base unit 2. Hence the position of each terminal 3 can be detected based on the signal strength of the position detection signal received by each terminal 3.
US09530025B1 System, method and computer program product for controlling access to protected personal information
A computer-based system, method and computer program product for controlling access to protected personal information is disclosed. Protected personal information that is accessible by an information management application program is stored in a computer memory. In response to a request from an authenticated user for information, which includes protected personal information, information is displayed indicating that user has requested protected personal information, but the protected personal information is not displayed. In response to receiving user input requesting access to the protected personal information, a determination is made as to whether the user is authorized to access the requested protected personal information. If so, requested protected personal information is displayed to the user and information is stored relating to the user's access to protected personal information. Otherwise, requested protected personal information is not displayed to the user and information relating to the user's access to protected personal information is not stored.
US09530024B2 Recommendation system for protecting user privacy
One embodiment of the present invention sets forth a technique for providing application command recommendations to a privacy-sensitive client device. The technique includes receiving a command log from each general client device included in a plurality of general client devices and analyzing the command logs to generate a command recommendation file. The command recommendation file may indicate a relationship between one or more application commands executed by at least one of the general client devices and one or more application commands that are available for execution by the privacy-sensitive client device. The technique further includes transmitting the command recommendation file to the privacy-sensitive client device.
US09530019B1 Encapsulated simulation components
Systems and methods are provided for providing protected three-dimensional components for simulation. A three-dimensional component may be accessed, wherein the three-dimensional component includes one or more characteristics of the three-dimensional component, and wherein certain values of the characteristics of the three-dimensional components are variable via a parameter. An encapsulation command may be received for the three-dimensional component, wherein the encapsulation command includes an encryption setting, an access control setting, and an identification of which values of the characteristics of the three-dimensional component are variable via a parameter. An encapsulation of the three-dimensional component may be generated, wherein the encapsulation is encrypted based on the encryption setting and the access control setting, and wherein, when the three-dimensional component is encrypted, the three-dimensional component is inaccessible outside of an authorized program.
US09530018B2 Information processing apparatus, information processing system, and non-transitory computer readable medium for outputting encryption key on paper
An information processing apparatus includes a file acquiring unit, a generating unit, a data processing unit, and an output unit. The file acquiring unit acquires a file on the basis of an instruction from a user. The generating unit generates restriction information for restricting access to the file acquired by the file acquiring unit. The data processing unit associates the restriction information generated by the generating unit with the file acquired by the file acquiring unit. The output unit outputs the restriction information generated by the generating unit on a paper medium.
US09530017B2 Secure printing between printer and print client device
Systems and methods of operating a computing system may involve securely printing a print document sent from a client device to a target printer. In one example, the method may include verifying an operating environment of the target printer and generating a plurality of security keys to implement asymmetric encryption of the print document.
US09530016B1 Using source taint analysis to reduce false positives in an advanced persistent threat (APT) protection solution
In response to a local Advanced Persistent Threat (APT) agent identifying a potential data exfiltration attack, the binary identified in the attack is sent to a static analysis tool for further analysis. The agent also identifies a source and a sink involved in the potential data exfiltration. The static analysis tool decompiles the binary, and then runs the de-compiled code through a static analysis to identify data flows between the source and the sink, e.g., a data flow from the source that is the method used to read sensitive information, and a data flow to the sink that is the method used to write to the remote system. If there are such data flows, the activity reported by the agent is likely a true exfiltration attack. Based on this flow determination, the static analysis tool returns a response to the agent validating that the activity is an attack.
US09530015B2 System, method and computer program product for messaging in an on-demand database service
In accordance with embodiments, there are provided mechanisms and methods for messaging in an on-demand database service. These mechanisms and methods for messaging in an on-demand database service can enable embodiments to more flexibly message in on-demand database environments. The ability of embodiments to provide such feature may lead to enhanced messaging features which may be used for providing more effective ways of messaging in the context of on-demand databases.
US09530012B2 Processing extensible markup language security messages using delta parsing technology
Markup language security messages are processed. A template corresponding to a markup language security message is identified. The markup language security message is parsed for variable values using the template. A transition sequence is generated that represents the entire markup language security message. Each transition in the transition sequence is associated with a portion of the markup language security message. A lightweight data model of the markup language security message is populated using the transition sequence. The lightweight data model includes nodes for the variable values and a set of selected constant values.
US09530010B2 Energy usage data management
A method including receiving energy usage data representative of energy usage of a customer during a particular time period. The energy usage data is sign with a digital signature of a utility. The method includes receiving input of a customer effective to select a data block of the energy usage data. The method includes redacting the selected data block from the energy usage data in response to the input. The method includes calculating a hash value for the redacted data block using a per-customer key that is unique to the customer, an initialization vector, and a counter. The method includes replacing in the energy usage data the redacted data block with the calculated hash value corresponding to the redacted data block.
US09530009B2 Secure execution and update of application module code
A dynamic root of trust can be injected in an application module on a client device using a backend server and can be continuously monitored to ensure authenticity, integrity and confidentiality at load time, run time and update time of the application module. The dynamic root of trust can be updated directly from the backend server and can be used to establish a time bound trust chain for the other software modules loaded and executed as part of the application module.
US09530006B2 Method and system for performing a memory safety check of a program written in an unmanaged programming language
A method for performing a memory safety check of a program coded in an unmanaged programming language includes receiving an intermediate representation (IR) of the program and performing a static analysis pass of the IR to generate annotations including a safe pointer and an unsafe pointer. The method further includes removing, during a static analysis pass of the IR, the safe pointer from the annotations, inserting, into the IR using the annotations, a sandbox function call at the unsafe pointer to generate a modified IR, compiling the modified IR to generate an executable version of the program, executing, inside a sandbox framework, the executable version of the program, generating, during runtime and upon reaching the sandbox function call, a metadata entry and an enhanced pointer for atomicity, and comparing, during runtime and upon reaching a use of the unsafe pointer, the metadata entry with the enhanced pointer.
US09530004B2 Secure boot method, semiconductor device and recording medium
A secure boot method for a system, the system including a processor and a storage medium configured to store a program, a plurality of first partial hash values calculated based on a plurality of first partial programs into which the program is divided, and a first legitimate hash value which is a hash value calculated based on a plurality of first legitimate partial hash values, the plurality of first legitimate partial hash values being calculated based on a plurality of legitimate partial programs. The secure boot method includes calculating, a second calculated hash value based on the plurality of first partial hash values, and determining, whether or not the second calculated hash value matches the first legitimate hash value to continue the start-up processing of the system when the determination indicates match, and suspend the start-up processing of the system when the determination does not indicate match.
US09529998B2 Systems and methods for securing virtual machine computing environments
Systems and methods are provided for securing data in virtual machine computing environments. A request is received for a security operation from a first virtual machine operating in a host operating system of a first device. In response to receiving the request, a first security module executes the security operation, the first security module implemented in a kernel of the host operating system. The result of the security operation is provided to the first virtual machine.
US09529997B2 Centralized platform settings management for virtualized and multi OS systems
A processing device may include a first processor executing an operating system including a configurable setting and an isolated execution environment including a second processor communicatively coupled to the first processor, and a secure store coupled to the second processor to store a setting profile containing a copy of the configurable setting, in which the second processor is to, subsequent to establishing a trust relationship between the isolated execution environment and the operating system, synchronize the configurable setting with the setting profile.
US09529995B2 Auto discovery of virtual machines
A method and apparatus is disclosed herein for performing auto discovery of virtual machines. In one embodiment, the method includes monitoring, using an interface of the device, one or more packets being sent from one or more virtual machines, the one or more packets being sent determining, using a processor of the device, if one of the monitored packets includes a discovery packet from one virtual machine of the one or more virtual machines, wherein the discovery packet includes an address of a destination location; sending, using the interface of the device, a reply packet to the one virtual machine using an address in the discovery packet identified in the monitored packets, the reply packet including an Internet Protocol (IP) address of the device.
US09529993B2 Policy-driven approach to managing privileged/shared identity in an enterprise
Access to a privileged account is managed by first requiring authentication of a user logging into the account and then performing a policy evaluation to determine whether the identified user is allowed to log in using the privileged identity. Preferably, the authentication is a two factor authentication. The policy evaluation preferably enforces a policy, such as a role-based access control, and a context-based access control, a combination of such access controls, or the like. Thus, according to this approach, the entity is provided access to the privileged account if the user's identity is verified and a policy is met. In the alternative, the entity is denied access to the privileged account if either the authentication fails, or (assuming authentication does not fail) policy criteria for the user is not met.
US09529980B2 Deduplication of end user license agreements
In a computer-implemented method for deduplicating a plurality of instances of end user licensing agreements (EULAs), an end user licensing agreement (EULA) from a software bundle is accessed. Only a single instance of the EULA is displayed such that there is a deduplication of a plurality of instances of EULAs.
US09529979B2 Providing content items from alternate sources
Systems and methods for providing content items to users. A computer system may provide to a first user an indication of a plurality of available content items. The computer system may receive from the first user an indication of a first content item selected from the plurality of content items. The computer system may determine whether a content provider service associated with the computer system is authorized to stream the first content item to the first user. When the content provider service is not authorized to stream the first content item to the first user, the computer system may identify an alternate source for the first content item. The computer system may initiate playback of the first content item to the first user from the alternate source.
US09529976B2 Systems and methods for detecting infectious diseases
Systems, methods, and devices for detecting infections in a clinical sample are provided. Small-volume clinical samples obtained at a point-of-service (POS) location and may be tested at the POS location for multiple markers for multiple diseases, including upper and lower respiratory diseases. Samples may be tested for cytokines, or for inflammation indicators. Dilution of samples, or levels of detection, may be determined by the condition or past history of a subject. Test results may be obtained within a short amount of time after sample placement in a testing device, or within a short amount of time after being obtained from the subject. A prescription for treatment of a detected disorder may be provided, and may be filled, at the POS location. A bill may be automatically generated for the testing, or for the prescription, may be automatically sent to an insurance provider, and payment may be automatically obtained.
US09529972B2 Patient event indication
An indication that a patient event occurred may be used to evaluate the efficacy of at least one therapy program and/or adjust therapy delivery to the patient. In some examples, the patient event indication includes patient input that may be received via an event indication button of a programming device. In addition to or instead of the patient input, the patient event indication may be generated based on a physiological parameter of the patient. In some examples, therapy delivery may be adjusted by adjusting at least one therapy parameter value, switching therapy programs or therapy program groups or restarting a therapy cycle of a medical device. The patient input via an event indication button may also help evaluate whether a therapy system is useful for the patient.
US09529971B2 Method for the electronic authenticating of a handwritten signature, corresponding module and computer program
A method and apparatus are provided for electronically authenticating a handwritten signature of a user, entered on a writing surface via a writing instrument. The method includes acquiring, by the writing surface, at least one instant during the entering of the signature, of at least one piece of data representing the altitude z of the writing instrument relative to the writing surface, in an area of proximity to the writing surface; and authenticating the entered handwritten signature by taking account of at least the altitude z.
US09529970B2 Software and methods for dental treatment planning
Computer-implemented methods to plan, display and evaluate orthodontic treatment plans. A plurality of teeth in a representation on a computer display may be moved simultaneously in accordance with a mathematically defined pattern. Software tools available to generate the treatment path may include adjusting the smile teeth, moving teeth along a curve fit to points in the mandible, individually moving a tooth, cross sectioning to check for interference and simulations of occlusal points, highlighting teeth that have moved from their original position, making notations on the teeth, and generating and saving animation sequences of before and after treatment tooth positions.
US09529968B2 System and method of integrating mobile medical data into a database centric analytical process, and clinical workflow
The present invention provides a system and method of integrating mobile medical data into a database centric analytical process, and clinical workflow. This includes a method comprising: integrating smartphone and digital camera data into a clinical database management system comprising a database association and a clinical workflow based on a per dictum, including clinical session and procedural data and metadata, and generally involving shared communication of text data, and photographic and video/audio data sets associated with a patient file through a secured workflow series.
US09529967B2 Bioinformatics systems, apparatuses, and methods executed on an integrated circuit processing platform
A system, method and apparatus for executing a sequence analysis pipeline on genetic sequence data includes a structured ASIC formed of a set of hardwired digital logic circuits that are interconnected by physical electrical interconnects. One of the physical electrical interconnects forms an input to the structured ASIC connected with an electronic data source for receiving reads of genomic data. The hardwired digital logic circuits are arranged as a set of processing engines, each processing engine being formed of a subset of the hardwired digital logic circuits to perform one or more steps in the sequence analysis pipeline on the reads of genomic data. Each subset of the hardwired digital logic circuits is formed in a wired configuration to perform the one or more steps in the sequence analysis pipeline.
US09529964B2 Process for three-dimensional modeling and design of off-highway dump bodies
A method is provided for loading material into a dump body of a truck using a loading bucket whose volumetric capacity is approximately ⅓ or more than that of the dump body. The loading bucket is filled with an amount of earthen material and centered over the dump body. The bucket is then lowered to a position that: (1) substantially minimizes the clearance between the floor of the dump body and a swinging gate of the loading bucket in its freed position; (2) allows the swinging gate to clear the side walls of the dump body as it swings through an arc after it is freed, and (3) allows the material to be discharged substantially in the center of the dump body. After it is positioned, the swinging gate is then freed so as to release the material held in the bucket.
US09529963B1 Method and system for partitioning a verification testbench
A method of partitioning a verification test bench, the method comprising: receiving a source code of the verification test bench, the source code comprising reactive components for sending test traffic to a design under test (DUT) and for receiving test traffic from the DUT, the source code further comprising analytic components for verifying the test traffic between the reactive components and the DUT; identifying the analytic components in the source code; compiling the reactive components and the DUT into a first executable test bench that can be run in a regression to generate test traffic between the reactive components and the DUT; and compiling the analytic components into a second executable test bench that can be run separately from the first executable test bench in order to verify the test traffic.
US09529960B2 Photolithography patterning system using feature parameters
A method of providing a photolithography pattern can be provided by identifying at least one weak feature from among a plurality of features included in a photolithography pattern based on a feature parameter that is compared to a predetermined identification threshold value for the feature parameter. A first region of the weak feature can be classified as a first dosage region and a second region of the weak feature can be classified as a second dosage region. Related methods and apparatus are also disclosed.
US09529959B2 System and method for pattern correction in e-beam lithography
The present disclosure provides a method for pattern correction for electron-beam (e-beam) lithography. In accordance with some embodiments, the method includes splitting a plurality of patterns into a plurality of pattern types; performing model fittings to determine a plurality of models for the plurality of pattern types respectively; and performing a pattern correction to an integrated circuit (IC) layout using the plurality of models.
US09529953B2 Subthreshold standard cell library
A subthreshold standard cell library addresses the energy efficiency of electronic systems, thereby significantly reducing power consumption. Recent energy performance requirements are causing the next-generation system manufacturers to explore approaches to lower power consumption. Subthreshold operation has been examined and implemented in designing ultra-low power standard cell designs that operate beyond the normal modes of operation, with the potential for large energy savings. Operation of CMOS (Complementary Metal Oxide Semiconductor) transistors in the subthreshold regime, where the supply voltage used in operation is orders of magnitude below the normal operating voltage of typical transistors, has proven to be very beneficial for energy constrained systems as it enables minimum energy consumption in Application Specific Integrated Circuits (ASICs).
US09529950B1 Systems and methods for performing profile-based circuit optimization using high-level system modeling
Integrated circuits may be programmed using configuration data to implement desired custom logic circuits. The configuration data may be generated using a logic design system. The logic design system may include first and second compilers and an emulation engine. The first compiler may compile a computer program language description of the logic circuit to generate a hardware description language (HDL) description. The emulation engine may emulate performance of the logic circuit when loaded on a target device and may monitor the emulated performance to generate emulated profile data characterizing the emulated performance of the logic circuit. The first compiler may process the emulated profile data to identify optimizations to perform on the logic circuit and may compile an optimized HDL description. The second compiler may compile optimized configuration data using the optimized HDL. The design system may generate the optimized configuration data without performing multiple, time-consuming, HDL compilations.
US09529945B2 Robot simulation system which simulates takeout process of workpieces
A robot simulation system includes a first plane calculation part which calculates a group of first planes extending through focal points of two camera models and divide the fields of vision of the two camera models at equal intervals when capturing a measurement region, a second plane calculation part which calculates a group of second planes which intersect the first planes and extend along boundaries of light-dark contrast formed on the measurement region with stripe shaped patterns of light from the projector model, an intersecting line calculation part which calculates a plurality of intersecting lines between the first planes and the second planes, a three-dimensional information calculation part which calculates positions of intersecting points between the intersecting lines and surfaces of the workpiece models as three-dimensional information, and a position and posture calculation part which calculates positions and postures of the workpiece model based on the three-dimensional information.
US09529943B2 Sizing application for a toilet bowl trapping device
A method, an apparatus and a system for sizing a trapping device for trapping non-dispersing cloths and/or other materials in a toilet bowl and/or a hopper sink are disclosed. A computer device may be used to implement the method for sizing one or more trapping devices for installation at a facility, such as a medical institution. The computer device may be configured to determine a configuration of a trapway for each of one or more toilet bowls and/or hopper sinks at the facility. After determining the configuration, the computer device may determine a size of a trapping device corresponding to the determined configuration of each of the one or more trapways.
US09529942B1 Auto-optimizing out-of-core method and system for rendering of large engineering 3D CAD assemblies on handheld devices
A method for rendering data of a 3D CAD assembly includes a parsing step for creating an array storing the size and location of the data, a sorting step of sorting the array in decreasing order of the size of the data, a loading step of sequentially loading the data of as many parts as will fit into memory, a rendering process of sequentially rendering the data of the parts from memory, an update process executed concurrently with the rendering process of removing from memory the data of parts loaded earlier by the update process that have already been rendered in the current rendering pass and loading into memory data of parts yet to be rendered in the current rendering pass, and an auto-optimize process of removing, after each rendering pass, the data of a subset of the parts loaded into the available memory by the loading process.
US09529941B2 Conformal hand brace
A conformable hand brace includes a support surface for supporting palm portion of a patient's hand and an adjustable mechanism that allows the cross section of the brace to be adjusted. The brace can be adjusted to provide a close fit as the geometry of the hand changes. The inventive system allows the conformable hand brace to be designed automatically by a computer based upon anatomical measurements.
US09529937B2 Methods and apparatus for querying a relational data store using schema-less queries
The invention provides, in one aspect, a method of searching an RDF triples data store of the type in which the triples are maintained in accord with a first storage schema. The method includes inputting a first query specifying RDF triples that are to be identified in the data store. That first query assumes either (i) that the triples are stored in a schema-less manner (i.e., with no storage schema) or (ii) that the triples are maintained in accord with a second storage schema that differs from the first. The method further includes generating, from the first query, a second query that specifies those same RDF triples, yet, that reflects the first storage schema. That second query can be applied to the RDF triples data store in order to identify and/or retrieve the desired data.
US09529933B2 Dynamic assignment of business logic based on schema mapping metadata
Provided are techniques for dynamic assignment of business logic based on schema mapping metadata. A first transformation is performed using a simplified map and a structural transformation map that maps attributes between a source system and a target system to generate simplified map data that includes source attribute and target attribute pairs. A document that includes combined data is generated using the simplified map data and source system metadata containing contextual values of the source system. A second transformation is performed to generate transformed contextual metadata containing contextual values for the target system using a contextual metadata transformation map and the combined data.
US09529924B2 User interface providing localized search capabilities
A user interface is disclosed that operates in conjunction with a search engine browser to present localized information that pertains to specific areas of interest. As characters of a search query are being entered into the browser, they are provided to one or more servers that are associated with respective domains of information. If information within those domains corresponds to the search query being entered, an indication is provided to the user of those results, in addition to any input provided by the search engine browser. The user interface enables the user to access the results, even before the search is conducted, to quickly learn about items from the domains that may be of possible interest.
US09529923B1 Methods and apparatus for a distributed database within a network
In some embodiments, an apparatus includes an instance of a distributed database at a first compute device configured to be included within a set of compute devices that implement the distributed database. The apparatus also includes a processor configured to define a first event linked to a first set of events. The processor is configured to receive, from a second compute device from the set of compute devices, a signal representing a second event (1) defined by the second compute device and (2) linked to a second set of events. The processor is configured to identify an order associated with a third set of events based at least one a result of a protocol. The processor is configured to store in the instance of the distributed database the order associated with the third set of events.
US09529921B2 Content recommendation system
In various example embodiments, systems and methods to provide content recommendations are provided. Search parameters are received from a user. An attribute associated with the user is derived. Using the search parameters and the attribute, content from a database matching the attribute and the search parameters are determined. The matching content may be prioritized for presentation to the user.
US09529920B2 Automatic webpage characterization and search results annotation
A system and method for automatically analyzing and characterizing Internet search results and annotating a search results page according to specific characteristics of each webpage located at a URL corresponding to a search result. Such characteristics include the composition of each search results webpage as well as which search term elements are present in a webpage located at a URL corresponding to a search result out of those search term elements that were submitted to a search engine to produce the search results webpage. Further, search results are annotated to indicate which search term elements are present in a descendent webpage of a webpage located at a URL corresponding to a search result. Search results may also be optionally filtered according to specific characteristics of a webpage located at a search results URL such that certain categories of webpage are excluded from being referenced in the displayed search results.
US09529919B2 Traffic driver for suggesting stores
A system and method for providing a suggested store at or through which to purchase a product or service. When a user enters a query for a product or service into a user interface, the system may use the query as a search argument to search files to find one or more pictures illustrating information about a product or service represented by the query. The picture could illustrate where the queried product or service may be purchased. Auto-complete processes may also be used to process the query as it is being entered, to generate an auto-suggestion key word based on fewer than all the letters of the query, to use as a search argument for the search. Both the query and the auto-suggestion key word may be used as search arguments to find the relevant picture in a variety of search logic sequences to provide the picture to the user.
US09529918B2 System and methods thereof for downloading applications via a communication network
A method and system for downloading at least one application via a communication network are provided. The method comprises receiving an input search query from a user device; determining the search intent respective of the input search query, wherein the search intent indicates a topic of interest of a user of the user device; selecting, based on the search intent, at least one application from at least one applications central repository; creating a display segment over a display of the user device; displaying an icon corresponding to the at least one selected application in the display segment; establishing a direct communication link between the user device and a location hosting the at least one selected application in response to an input received from the user device; and downloading the application to the user device.
US09529916B1 Managing documents based on access context
Disclosed is a document management system where accessed documents can be stored in a document list along with information regarding the context in which the documents were accessed. The context can include information regarding the time and date the document was accessed and what applications were running when the document was accessed. Other context information can include whether the document was accessed during a calendar event or if the document was included in an attachment to an e-mail. When the current context of the computing device matches a previously recorded context, documents from the document list can be entered into a subset list and presented to the user.
US09529911B2 Building of a web corpus with the help of a reference web crawl
Computer-implemented method for building a web corpus (WCD) comprising the steps of: sending by a web crawler (WC) a query to a reference web crawl agent (RWCA), this query containing a least one identifier of a resource, receiving by the web crawler (WC) a response from the reference web crawl agent (RWCA); if this response does not contain the resource identified by the identifier, downloading by the web crawler (WC) the resource from the website (WS) corresponding to the identifier and adding the resource to the web corpus (WCD; and if this response contains the resource identified by the identifier, adding the resource to the web corpus (WCD).
US09529906B2 Low-latency audio networking
Low-latency audio networking is disclosed. In one embodiment, an example playback device includes a processor and memory having stored thereon instructions executable by the processor. The example instructions are to cause the first playback device to perform functions comprising: receiving audio information; selecting a first frequency channel of a first spectrum based on a threshold latency associated with the audio information; transmitting to the second playback device via a second frequency channel of a second spectrum, control information that identifies the first frequency channel of the first spectrum; and transmitting to the second playback device via the first frequency channel of the first spectrum, the audio information to be played by the second playback device.
US09529899B2 Visualizing motifs with visual structures
Visual structures are produced to represent corresponding motifs, where the motifs correspond to repeating patterns in an input data set, where sizes of the visual structures are based on values of a characteristic associated with the motifs, and where a first of the motifs is nested within a second of the motifs to represent a hierarchical relationship of the patterns represented by the first and second motifs. The visual structures of corresponding motifs are presented for display in a visualization screen, where the visualization screen depicts the data in the input data set with the visual structures overlapping parts of depicted data. Interactive input is received specifying modification of a region containing motifs, wherein the specified modification includes interactive distortion of the visual structures in the region to change a size of the visual structures in the region.
US09529892B2 Interactive navigation among visualizations
Various mechanisms are provided for navigating among visualizations of quantitative data. At least one relationship is defined among a plurality of visualizations. A virtual multi-faceted shape is constructed, having a plurality of surfaces, some or all of which may correspond to visualizations. Visualizations may be presented, for example, by projecting or texture mapping the visualizations on corresponding surfaces of the shape. In at least one embodiment, surfaces are spatially oriented with one another in a manner that represents a relationship between the corresponding two visualizations. The user can interact with the virtual shape, for example by causing it to rotate, zoom, move, or the like. Such interactions cause different visualizations to be displayed.
US09529890B2 System for decomposing events from managed infrastructures using a topology proximity engine, graph topologies, and k-means clustering
An event clustering system includes an extraction engine in communication with an infrastructure. The extraction engine receives data from the infrastructure and produces events. An alert engine receives the events and creates alerts mapped into a matrix, M. A sigalizer engine includes one or more of an NMF engine, a k-means clustering engine and a topology proximity engine. The sigalizer engine determines one or more common steps from events and produces clusters relating to the alerts and or events.
US09529885B1 Maintaining consistent point-in-time in asynchronous replication during virtual machine relocation
In one aspect, a method includes pausing write I/Os for a second virtual machine running at a second site, generating a snapshot of a first virtual machine running at a first site after pausing the write I/Os for the second virtual machine, generating a bookmark for the second virtual machine, resuming the write I/Os for the second virtual machine after generating the bookmark, rolling a journal for the second virtual machine to a point-in-time of the bookmark and generating, at the first site, a second snapshot of the second virtual volume for the point-in-time of the bookmark using the journal.
US09529880B2 Synchronizing a disaster-recovery system of a database
A method and associated systems for synchronizing a disaster-recovery system of a database. A processor identifies transactions that affect data blocks of a database and records each change in a vector form. For each block, the processor determines a more efficient way to communicate changes made to the block by a subset of the identified transactions. If fewer resources are needed to communicate an updated image of the entire changed block than would be needed to instead communicate a related set of change vectors that identify changes made to the block by the subset of transactions, then the processor communicates the updated image to the disaster-recovery system. Otherwise, the processor instead communicates the related change vectors to the disaster-recovery system. The processor repeats these determinations and communications for each block of the database that was changed by an identified transaction.
US09529876B2 Verification of transformed content
A computer manages methods for determining accurate document transformation by rendering the source document into a non-rasterized format, where the non-rasterized format is a rendered source document. The computer rendering the target document into a non-rasterized format, where the non-rasterized format is a rendered target document. The computer comparing one or more aspects of the rendered source document to corresponding one or more aspects of the rendered target document. The computer determining, based, at least in part, on the compared one or more aspects, whether or not the source document was accurately transformed to the target document.
US09529874B2 Verification of transformed content
A computer manages methods for determining accurate document transformation by rendering the source document into a non-rasterized format, where the non-rasterized format is a rendered source document. The computer rendering the target document into a non-rasterized format, where the non-rasterized format is a rendered target document. The computer comparing one or more aspects of the rendered source document to corresponding one or more aspects of the rendered target document. The computer determining, based, at least in part, on the compared one or more aspects, whether or not the source document was accurately transformed to the target document.
US09529873B2 Enhancing performance of extract, transform, and load (ETL) jobs
A computer receives one or more files having configuration information that includes data that defines a plurality of stages of an extract, transform, and load (ETL) job, wherein the plurality of stages comprise a read stage that is preceded by a write stage, and wherein the read stage reads data from a source location, and wherein the data that is read or a modified version of the data that is read is being written by the write stage that writes data to the source location. The computer replaces the read stage with a decompressor stage. The computer replaces the write stage with a compressor stage. The computer executes the decompressor stage and compressor stage on a field-programmable gate array that is programmatically customized with data compression and data decompression functionality to enhance the performance of the ETL job.
US09529871B2 Information management of mobile device data
A method and system for providing information management of mobile device data provides a user interface to permit a user of an information management system to define information management policies for the mobile device, receives definitions of the information management policies from the provided interface, and sends data from the mobile device to the information management system in accordance with the information management policies. In some examples, the system sends information identifying the user and the mobile device to the information management system, and/or sends the information management policies defined from the interface to the information management system.
US09529870B1 Methods for linking an electronic media work to perform an action
A method including the steps of: receiving, by a computer system including at least one computer, a first electronic media work uploaded from a first electronic device; extracting one or more features from the first electronic media work; linking the first electronic media work with a reference electronic media work identifier associated with a reference electronic media work to generate correlation information using an approximate nearest neighbor search; storing the correlation information; receiving, from a second electronic device, a query related to the first electronic media work; correlating the query with action information related to an action to be performed and associated with the reference electronic media work identifier based at least in part on the correlation information; generating machine-readable instructions based upon the action information; and providing to the second electronic device, the machine-readable instructions to be used in performing the action.
US09529858B2 Methods and systems for ranking items on a presentation area based on binary outcomes
A method includes accessing a number of cards from a database. The cards are ranked in the database based on a test conducted on a number of users. The cards are associated with one or more rule states. The one or more rule states provide binary outcomes of one or more rules. Each rule is identified using a code. The test is conducted by presenting different random sequences of the cards to different users and receiving inputs from the number of users. The method further includes receiving a request for a presentation area from a client device operated by a user. The presentation area is used for displaying the number of cards in an order, which is determined based on the test. The method includes providing the number of cards for display in the order within the presentation area on the client device of the user in response to the request.
US09529854B2 Providing location-based services in a distributed environment without direct control over the point of access
A method, system and computer program product for providing location-specific content to a personal computing device (PCD) connected to a distributed server network (such as the Internet) without requiring an access control gateway to provide such content. Location-specific (and user-specific) content/services are provided by a client-server architecture utilizing a location database and a location look-up utility of a location identifier and content retrieval (LICR) server. Specifically, a utility executing on the PCD provides PCD location parameters to the LICR server, which is equipped with a location look up engine/functionality and a location content retrieval engine/functionality (both within a LICR utility) that responds by providing location-specific and user-specific content to the PCD.
US09529852B1 Selecting a template for a content item
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for selecting a template for a content item. In one aspect, a method includes receiving a content item request that includes context data. A content item that is eligible to be presented in response to the content item request is identified. A determination is made that the content item includes a template variable that is resolved based on the context data. A template feed including a set of templates is identified based on the template variable. A template is selected from the template feed for the content item. The template can be selected based on the context data. The selected template is populated with content for the content item to create a formatted content item. The formatted content item is provided in response to the content item request.
US09529851B1 Server architecture for electronic data quality processing
In one embodiment, a server architecture is disclosed that provides for processing and analyzing data received from data furnishers to evaluate quality of the provided data. The system may format the data received from the data furnishers into standardized form. Based on configuration information and rules for the data furnishers and the provided data, the system may analyze the data set to calculate one or more data quality indicators.
US09529850B1 Data source joins
Database report generation technology for handling a single logical query that requires data that is physically located in two different sources. The system uses intelligent push-down joins, which move data from one source to the other and join data within that source. The system dynamically determines which direction to move data depending on how the data is used in a query.
US09529846B2 Data grid advisor
A system and method to generate an improved layout of a data grid in a database environment is provided. The data grid is a clustered in-memory database cache comprising one or more data fabrics, where each data fabric includes multiple in-memory database cache nodes. A data grid advisor capability can be used by application developers and database administrators to evaluate and design the data grid layout so as to optimize performance based on resource constraints and the needs of particular database applications.
US09529844B2 Method, program, and system for processing space-time database
A method, system, and a computer program product for querying a database. The system includes: a storage means; a processor communicatively coupled to the storage means; and a feature selection module communicatively coupled to the storage means and the processor, wherein the feature selection module is configured to perform the steps of a method including: storing a database in the storage means, the database including a time field; extracting data in a predetermined period from a current time from the database; sorting the data by the time field; buffering the sorted data in a main memory; receiving a query including time; and outputting the data buffered on the basis of the time field as a stream.
US09529843B2 Highly portable and dynamic user interface component to specify and perform simple to complex filtering on data using natural language-like user interface
Embodiments of the invention provide systems and methods for filtering a complex dataset. More specifically, embodiments of the present invention provide for using a filter implemented as a single, re-usable component of a user interface to specify and perform filtering on a complex dataset. For example, embodiments described herein can provide a consistent user interface for navigating and filtering the complex dataset that includes tree management. Embodiments also provide a single, reusable, componentized widget for declaring filters against the complex dataset. Additionally, or alternatively, embodiments described herein allow filters to be shared across portions of the dataset, e.g., across ledgers, across the dataset, e.g., across charts of accounts, applications, e.g., different financial applications, across pillars, etc.
US09529841B1 Methods and systems for electronically visualizing a life history
In an embodiment, a method of electronically visualizing a life history includes, using a processor, generating a first visual representation of a first life history as a function of a first set of multiple events that are defined by event data stored in a tangible storage medium. Each event is identified within the event data as being one of a positive life event and a negative life event. Within the event data, each event is associated with an age within the first life history.
US09529840B1 Real-time duplicate detection of videos in a massive video sharing system
Systems and methods for identifying duplicate media items in a media system are provided. In particular, media content can be uploaded to a serve. The media content can be fingerprinted. A digest is generated based on the fingerprint. The digest is indexed and potential matching media items are identified. Matches are determined from the potential matching media items.
US09529839B2 Applying limited-size hardware transactional memory to arbitrarily large data structure
A technique for applying hardware transaction memory to an arbitrarily large data structure is disclosed. A data updater traverses the data structure to locate an update point using a lockless synchronization technique that synchronizes the data updater with other updaters that may be concurrently updating the data structure. At the update point, the updater performs an update on the data structure using a hardware transactional memory transaction that operates at the update point.
US09529836B1 Managing disjoint-or trees
Methods, systems, and apparatus, including computer programs encoded on computer storage media, for managing disjoint-or trees. One of the methods includes determining that a disjoint-or tree occupies more memory than a maximum memory limit. One or more elements of the disjoint-or tree are selected for removal. If a particular leaf element selected for removal has a parent element with a status indicator of complete, data of the particular leaf element is added to a compound leaf element, the compound leaf element being a child element of the parent element and having data associated with the particular leaf element and one or more other sibling leaf elements. The particular leaf element is then removed from the disjoint-or tree without propagating changes associated with removing the particular leaf element to all the ancestors of the particular leaf element.
US09529833B2 Graph pruning in hipergraph
One embodiment of the present invention provides a system for graph pruning. During operation, the system identifies a connected component in a graph comprising one or more vertices. A respective vertex of the graph represent an element in a data set, an edge between two vertices represents a type and strength of relationship between the vertices. The system identifies a connected component to be smaller than a minimum graph traversal threshold associated with a query for the graph. This minimum graph traversal threshold indicates a minimum number of traversal steps needed for the query. The system then generates a second graph by pruning the connected component from the graph. This second graph is processed to extract information of interest from the data set.
US09529830B1 Data matching for column-oriented data tables
A computer-implemented method includes receiving a column-oriented table comprising data for a column family, wherein the data for the column family comprises column names and corresponding column values, receiving a set of anonymous column names for the column family, receiving a set of synonymous column names for the column family, determining a weighting for each column name that is not an anonymous column name based on the count or frequency of occurrence of the column name and the synonymous column names within the column-oriented table, and processing the column-oriented table with a probabilistic matching engine using the weighting for each column name. A corresponding computer program product and computer system are also disclosed herein.
US09529829B1 System and method to facilitate the use of processed data from a storage system to perform tasks
A system and method for facilitating the use of use processed data from a storage system to perform one or more tasks are disclosed. For example, the method can include identifying data, stored within a storage system, and needed to perform a task. Such data can be stored in a processed form, as a result of such data having been previously processed by the storage system. A determination is made to determine whether the identified data is stored in a processed form. If so, a subsequent determination is made to determine whether the data in the processed form is usable to perform the task. If the data in the processed form is usable to perform the task, a request is generated to request the data in the processed form. The processed data can then be used to perform the task.
US09529827B2 Change value database system and method
A method for constructing a change database reduces the footprint of a standard longitudinal data database and increases the manageability of the data for many applications. The change database concatenates representations of a time period for the change, the direction of the change, and the value of the change into a single string. The change database is constructed by creating foundation files from formatted historical data, constructing change files from these foundation files, and iteratively creating master files that encapsulate the change data.
US09529826B2 Methods and systems for use of a database of three-dimensional (3D) object data models for search queries
A server may receive a search query indicative of an object. The server may identify a 3D model from within a database of 3D object data models that corresponds to the object. The 3D model may be associated with information that pertains to the object. The server may determine an updated search query based on the information associated with the 3D model. The updated search query may be indicative of one or more of an environment of the object, an orientation of the object in the environment, a position of the object in the environment, or an identification of one or more other objects in the environment. The server may provide one or more search query results that include data pertaining to the object based on the updated search query.
US09529824B2 System and method for multi resolution and multi temporal image search
A system for modular image mining and search, comprising a plurality of image capture devices, a search engine, an indexing engine, a database, and user interface software. A plurality of image capture devices capture images and store them to a database. The indexing engine indexes images to create image data for each image with associated metadata and stores the information to the database. The interface software is used to request search queries via a search engine. The search engine accesses the image data to find images or parts of images that satisfy the search query.
US09529823B2 Geo-ontology extraction from entities with spatial and non-spatial attributes
Architecture that provides fully automatic generation of a geo-ontology and does not use pre-existing geo-ontologies or other location entity repositories (e.g., a licensed location). The architecture extracts the formal administrative structure of a geographical region of interest (e.g., country) (a geo-ontology of locations with attributes and relations) from a collection of entities with spatial attributes, extracts the informal administrative structure of a geographical region of interest (e.g., country) (informal administrative regions and names and informal neighborhoods and their attributes), and extracts location static rank features for all these entities (attributes used for ranking locations from the geo-ontology that appear in user queries).
US09529820B2 Automated content tracking and conversion
Source file information is associated with source file content in response to a copy operation of the source file content from a source file. An automated conversion of the source file content to a form compatible with a target file is performed based upon differences between the source file information and target file information in response to a paste operation.
US09529815B1 System and method to integrate backup and compliance systems
A method and system for validating data in a data backup system is provided. The method includes receiving, from a compliance system, compliance and internal standards information. The method includes storing the received compliance and internal standards information. The method includes monitoring one or more events. The method includes collecting data associated with the monitored one or more events. The method includes determining whether the collected data deviates from the compliance and internal standards information. The method includes sending a notification, warning, alert and/or other message with in backup system as well as to compliance system in case of deviation from the compliance and internal standards.
US09529814B1 Selective file system caching based upon a configurable cache map
Techniques for implementing selective file system caching are disclosed. In one particular embodiment, the techniques may be realized as a method including receiving an I/O request from an application such that the application provides a no-cache indication to a file system to implement a direct. I/O for the I/O request, comparing the I/O request and the no-cache indication with a configurable cache map such that the configurable cache map indicates a selective caching based on an I/O type and a file type, processing the I/O request to render a caching decision based on the comparison, and executing selective caching on the I/O request in accordance with the caching decision.
US09529809B2 Managing log data using a circular fixed size file
A request to write new data to a file is received. The file occupies a pre-determined size of storage space in a file-system. A determination is made whether an end location amount of space from an ending location value in an attribute up to the pre-determined size is insufficient to write the new data to the file. A second amount of space is computed. The first and the second amounts of space together are sufficient to write the new data. The second amount of space begins at a starting location value in a starting location attribute. The new data is written using the first and the second amounts of space. The ending location value is changed to indicate a location at the end of new data in the second amount of space. The starting location value is changed to indicate a location where existing data begins after new data.
US09529808B1 Efficient and flexible organization and management of file metadata
Storing data is disclosed, including: receiving a request to create a clone of a snapshot included in a first set of metadata associated with a source data; and generating a second set of metadata for the clone, wherein the second set of metadata associated with the clone includes, for at least some metadata values, a data associating with the second set of metadata one or more corresponding values in the first set of metadata associated with the source data.
US09529799B2 System and method for document driven actions
A system and method are disclosed for tracking documents in a computing environment, including documents stored locally on computing devices. A monitoring module stored on a computing device may determine that a user is trying to open a document stored locally on the computing device and communicate a signature associated with the document to a document tracking system. A document tracking system may compare the signature with a set of stored signatures to see if the document corresponds to a document already being tracked. If the document is not being tracked already, the document tracking system may upload the document into the system, send a link to a newer version or determine one or more actions to be performed on the document based on the signature.
US09529785B2 Detecting relationships between edits and acting on a subset of edits
Systems and methods are disclosed herein for detecting compounding and conflicting suggested edits in a collaborative document editing environment. A first edit and a second edit to an electronic document are received. A shared position of the first edit and the second edit in the electronic document is identified, and a compounding relationship or a conflicting relationship is determined based at least in part on the identification. The first edit, the second edit, and an indicator of the relationship are displayed to a user of the electronic document.
US09529783B2 Live previews for multitasking and state management
Invoked states of one or more activities invoked in a web application is detected. The web application is configured to display, in a foreground, a current activity on a client device. On the client device, display of a multitask preview interface that includes one or more live previews is caused. Each live preview of the one or more live previews corresponds to an invoked state of an activity of the one or more activities. The one or more live previews includes a particular live preview that corresponds to a particular invoked state of a particular activity of the one or more activities. Selection of the particular live preview is detected. In response to detecting selection of the particular live preview, the current activity displayed in the foreground of the web application is switched to the particular state of the particular activity.
US09529781B2 Apparatus and method for document format conversion
An apparatus and method for document format conversion. The apparatus includes a document parsing unit for parsing a fixed layout document to acquire path primitives of the document; a path grouping unit for dividing the path primitives into groups to generate path groups; a font file generating unit for acquiring path groups that are used to represent characters and generating font files corresponding to the path groups, wherein if there are two or more path groups representing the same character, only one font file is generated and associated with the multiple path groups representing the same character; a document generating unit for generating a converted document using all font files that have been generated. With the above, the problem of data redundancy in fixed layout documents is solved; further, the incorrect rending in reflowing processes may be solved to achieve better display effects.
US09529780B2 Displaying content on a mobile device
A method for facilitating the rendering of a web page on a mobile device includes providing an enhanced DOM tree for the web page that includes web page components and their display coordinates. A rule set is applied to the DOM tree, thereby selecting components for display on the mobile device. A mobile-device-specific version of the source code is generated based on the selected components.
US09529779B2 Detection and repositioning of pop-up dialogs
An embodiment of the invention provides a method where a file is displayed on a display screen of a mobile device; and, a pop-up is identified outside of the visible area on the display screen of the mobile device. The identification of the pop-up includes detecting a document object model change in the file, the presence of one or more non-active elements in the file, and/or a change in luminance in an area outside of the visible area on the display screen. A controller moves the pop-up to the visible area on the display screen, or the visible area on the display screen is moved to the pop-up.
US09529773B2 Systems and methods for enabling access to extensible remote storage over a network as local storage via a logical storage controller
A new approach is proposed that contemplates systems and methods to support elastic (extensible/flexible) storage access in real time by mapping a plurality of remote storage devices that are accessible over a network fabric as logical namespace(s) via a logical storage controller using a multitude of access mechanisms and storage network protocols. The logical storage controller exports and presents the remote storage devices to one or more VMs running on a host of the logical storage controller as the logical namespace(s), wherein these remote storage devices appear virtually as one or more logical volumes of a collection of logical blocks in the logical namespace(s) to the VMs. As a result, each of the VMs running on the host can access these remote storage devices to perform read/write operations as if they were local storage devices via the logical namespace(s).
US09529765B2 Integrated circuit (IC) with reconfigurable digital voltage regulator fabric
Described is an apparatus which comprises: a plurality of bridges which are operable to drive respective signals for one or more power supply rails; a plurality of controllers; and a main controller to couple one or more controllers from the plurality of controllers to one or more bridges from the plurality of bridges.
US09529758B1 Multiple port configuration
An method of configuring an electronic device having a plurality of serial ports, each of which is configurable to act in either a host port or a slave port mode, includes entering a port configuration state at the device, and, in this port configuration state detecting a trigger event and configuring each of the serial ports of the device in a defined one of its host port or slave port modes. The trigger event may be the proximity of one of the serial ports of the electronic device to a port of another external device in its slave mode. In response, the proximate serial port of the electronic device may assume its host port mode, and the remaining serial ports of said electronic device may assume the slave port mode.
US09529756B2 Method and terminal for starting universal serial USB state machine
A method and terminal for starting a USB state machine are provided in the present document. The method includes: connecting a USB voltage bus pin to a logic level; if detecting that a voltage of a charging voltage pin is greater than a threshold limit value, starting a charging state machine and the USB state machine. In the present document, the USB state machine is started through a signal for detecting plug-in and pull-out of a charger, which can not only trigger the start-up of the USB state machine, but also possess a function of satisfying overvoltage protection, thereby the charger and the USB are enabled to share one physical interface with the simplest and securest method under the premise of guaranteeing the reliability.
US09529755B2 Apparatus and method of recognizing external device in a communication system
An apparatus and a method are provided. The apparatus includes a connector to connect with an electronic device external to the apparatus, and a processor configured to identify a connection with the electronic device via the connector, receive, using a first communication scheme, a message from the electronic device based at least in part on the identifying, determine, based at least in part on the message, whether the electronic device supports a second communication scheme, and establish a communication link corresponding to the second communication scheme with the electronic device based at least in part on a determination that the electronic device supports the second communication scheme.
US09529752B2 Method and apparatus for communication between a vehicle based computing system and a remote application
A vehicle-based computing apparatus includes a computer processor in communication with persistent and non-persistent memory. The apparatus also includes a local wireless transceiver in communication with the computer processor and configured to communicate wirelessly with a wireless device located at the vehicle. The processor is operable to receive, through the wireless transceiver, a connection request sent from a nomadic wireless device, the connection request including at least a name of an application seeking to communicate with the processor. The processor is further operable to receive at least one secondary communication from the nomadic device, once the connection request has been processed. The secondary communication is at least one of a speak alert command, a display text command, a create phrase command, and a prompt and listen command.
US09529751B2 Requests and data handling in a bus architecture
Aspects relate to methods and systems for processing requests and sending data in a bus architecture. At least one master device is connected to at least two slave devices via a bus. An allocator allocates incoming requests from the master device to a target slave device. Incoming requests are buffered for the respective slave device. The master device sends a read request for a first slave device to the bus; the allocator generates a current-state indicator associated with the read request. The allocator generates a priority indicator associated with the read request. If the initial value of the current-state indicator equals the value of the priority indicator, the read request is processed; or if the initial value of the current-state indicator does not equal the value of priority indicator, the read request is deferred until a later time.
US09529750B2 Service processor (SP) initiated data transaction with bios utilizing interrupt
Certain aspects direct to systems and methods to perform service processor (SP) initiated data transaction with a host computer utilizing interrupts. In certain embodiments, the system includes a SP, which includes a processor, a non-volatile memory and a communication interface. The SP generates a first system management interface (SMI) message, and sends the first SMI message to the host computer to initiate a data transaction. The OS, in response to the first SMI message, execute a SMI handler in a system management random access memory (SMRAM) area at the CPU to enter a system management mode (SMM). The SMI handler then sends the notification to the SP via the communication interface. In response to receiving the notification from the SMI handler, the SP starts performing the data transaction with the host computer.
US09529749B2 Data bus inversion (DBI) encoding based on the speed of operation
A method for data transmission is described. A signaling speed of operation of an electronic device is determined. A data bus inversion algorithm is selected based on the signaling speed of operation. The selected data bus inversion algorithm is used to encode data. The encoded data and a data bus inversion flag are sent to a receiver over a transmission medium.
US09529747B2 Memory address generation for digital signal processing
Memory address generation for digital signal processing is described. In one example, a digital signal processing system-on-chip utilizes an on-chip memory space that is shared between functional blocks of the system. An on-chip DMA controller comprises an address generator that can generate sequences of read and write memory addresses for data items being transferred between the on-chip memory and a paged memory device, or internally within the system. The address generator is configurable and can generate non-linear sequences for the read and/or write addresses. This enables aspects of interleaving/deinterleaving operations to be performed as part of a data transfer between internal or paged memory. As a result, a dedicated memory for interleaving operations is not required. In further examples, the address generator can be configured to generate read and/or write addresses that take into account limitations of particular memory devices when performing interleaving, such as DRAM.
US09529746B2 Method for operating a communication system
A method for transmitting frames containing data between users of a ring-shaped communication system which has a master and at least one slave as users. Each user has at least one interrupt register, and one field of the at least one interrupt register is associated with an interrupt request and includes a value for an interrupt bit. An interrupt request which includes the interrupt bit is transmitted to the master by a slave in a frame designed as an empty frame. In addition, the empty frame has a toggle bit for all slaves which indicates the state of an interrupt request.
US09529743B2 Flexible PCIe routing
In some implementations, a riser card can be configured to connect to multiple PCIe connectors on a motherboard of a computing device. The riser card can be configured to route signals from an accessory installed in the riser to the CPU of the computing device through multiple PCIe connectors. The riser card can be configured to connect to a PCIe connector on the motherboard using cabling.
US09529740B1 Method for creation of a device driver for a peripheral device
A method and apparatus may be configured to create setup information, and perform the initialization and performance of an installation of a peripheral device of an electronic device. One example method may include storing a device identification (ID) of the peripheral device, extracting data and creating a data structure from existent setup information. The method may also include replacing a device ID in the data structure with the device ID of the peripheral device, and creating and storing a setup information file from content of the data structure. The method may also include creating and passing a request to at least one of a device driver of an interface of the peripheral device and a bus that initiates the installation of the peripheral device. The peripheral device may not be connected to the electronic device.
US09529735B2 Secure data encryption in shared storage using namespaces
A data storage device in a distributed computing system has physical block addresses that are each allocated to multiple namespaces. To access the data storage device, a host system issues a command to the data storage device that includes an access key and a virtual block address to be accessed. The data storage device converts the virtual block address to a physical block address of the data storage device using a mapping associated with the access key. Access to a physical data block associated with a particular namespace is granted only if an access key for that namespace is provided to the data storage device.
US09529728B2 Method for improving memory system performance in virtual machine systems
Updating contents of certain memory pages in a virtual machine system is deferred until they are needed. Specifically, certain page update operations are deferred until the page is accessed for a load or store operation. Each page within the virtual machine system includes associated metadata, which includes a page signature characterizing the contents of a corresponding page or a reference to a page with canonical contents, and a flag that indicates the page needs to be updated before being accessed. The metadata may also include a flag to indicate that a backing store of the memory page has contents of a known content class. When such a memory page is mapped to a shared page with contents of that known content class, a flag in the metadata to indicate that contents of the memory page needs to be updated is not set.
US09529727B2 Reconfigurable fetch pipeline
A particular method includes selecting between a first cache access mode and a second cache access mode based on a number of instructions stored at an issue queue, a number of active threads of an execution unit, or both. The method further includes performing a first cache access. When the first cache access mode is selected, performing the first cache access includes performing a tag access and performing a data array access after performing the tag access. When the second cache access mode is selected, performing the first cache access includes performing the tag access in parallel with the data array access.
US09529726B2 Memory device with page emulation mode
In some examples, a memory device is configured to load multiple pages of an internal page size into a cache in response to receiving an activate command and to write multiple pages of the internal page size into a memory array in response to receiving a precharge command. In some implementations, the memory array is arranged to store multiple pages of the internal page size in a single physical row.
US09529724B2 Layered architecture for hybrid controller
Approaches for implementing a controller for a hybrid memory that includes a main memory and a cache for the main memory are discussed. The controller comprises a hierarchy of abstraction layers, wherein each abstraction layer is configured to provide at least one component of a cache management structure. Each pair of abstraction layers utilizes processors communicating through an application programming interface (API). The controller is configured to receive incoming memory access requests from a host processor and to manage outgoing memory access requests routed to the cache using the plurality of abstraction layers.
US09529719B2 Dynamic multithreaded cache allocation
Apparatus and method embodiments for dynamically allocating cache space in a multi-threaded execution environment are disclosed. In some embodiments, a processor includes a cache shared by each of a plurality of processor cores and/or each of a plurality of threads executing on the processor. The processor further includes a cache allocation circuit configured to dynamically allocate space in the cache provided to each of the plurality of processor cores based on their respective usage patterns. The cache allocation unit may track cache usage by each of the processor cores/threads using subsets of usage bits and counters configured to update states of the usage bits. The cache allocation circuit may track the usage of cache space by the processor cores/threads and may allocate more space to those that exhibit more usage of the cache.
US09529717B2 Preserving an invalid global domain indication when installing a shared cache line in a cache
A technique for operating a memory system for a node includes interrogating, by a cache, an associated cache directory to determine whether a shared cache line to be installed in the cache is associated with an invalid global state in the cache. The invalid global state specifies that a version of the shared cache line has been intervened off-node. In response to the shared cache line being in the invalid global state the cache spawns a castout invalid global command for the shared cache line. The shared cache line is installed in the cache. A coherence state for the shared cache line is updated in the associated cache directory to indicate the shared cache line is shared.
US09529715B2 Hybrid hardware and software implementation of transactional memory access
Embodiments of the invention relate a hybrid hardware and software implementation of transactional memory accesses in a computer system. A processor including a transactional cache and a regular cache is utilized in a computer system that includes a policy manager to select one of a first mode (a hardware mode) or a second mode (a software mode) to implement transactional memory accesses. In the hardware mode the transactional cache is utilized to perform read and write memory operations and in the software mode the regular cache is utilized to perform read and write memory operations.
US09529712B2 Techniques for balancing accesses to memory having different memory types
Embodiments of the present technology are directed toward techniques for balancing memory accesses to different memory types.
US09529709B2 Apparatuses for managing and accessing flash memory module
A method for maintaining address mapping for a flash memory module is disclosed including: recording a first set of addresses corresponding to a first set of sequential logical addresses in a first section of a first addressing block; recording a second set of addresses corresponding to a second set of sequential logical addresses in a second section of the first addressing block; recording a third set of addresses corresponding to a third set of sequential logical addresses in a first section of a second addressing block; and recording a fourth set of addresses corresponding to a fourth set of sequential logical addresses in a second section of the second addressing block; wherein the second set of logical addresses is successive to the first set of logical addresses, and the third set of logical addresses is successive to the second set of logical addresses.
US09529707B2 Apparatus and method for reducing read-modify-write cycles by combining unaligned write commands
Write commands for a storage device specify write data with either a first data step size or a second data step size. In the former case, the storage device performs a read-modify-write (RMW) cycle which includes reading data with the second data step size. In the latter case, the storage device executes the command in a single write cycle. A command sorting unit sorts received commands into two groups, first commands and second commands, when storing them in a memory. First commands are write commands whose data boundaries do not match with the second data step size. Second commands include write commands whose data boundaries match with the second data step size. A command issuing unit converts first commands into a second command upon predetermined conditions. The command issuing unit issues the second commands to the storage device, in preference to the first commands.
US09529705B2 Nonvolatile memory system including nonvolatile memory device and memory controller that loads a mapping table on a sub-bitmap and method of operating the memory controller
A method of operating a memory controller controlling a nonvolatile memory device including a user area and a meta area is provided. The method includes selecting a source block among a plurality of memory blocks included in the user area, loading a mapping table stored in the meta area on the basis of a sub-bitmap of the selected source block, and generating a valid page layout constituted by valid pages among pages included in the source block on the basis of the loaded mapping table. The sub-bitmap includes information of a valid mapping table with respect to the selected source block.
US09529704B2 Graphical conversion between test program languages
A parser may be graphically modified without needing to directly alter the parser software and may be graphically modified to adjust for extensibility of the source test program language. The parser may be graphically modify to adjust for extensibility of the destination test program language and to translate a new text based test program language not inherently built into the parser.
US09529699B2 System and method for test data generation and optimization for data driven testing
A system, medium and method for automatically generating test data to be applied to test a target software code is disclosed. Input parameter data is received from a user via a displayed user interface, wherein the input parameter data is directed to a user selected data type, the data type being a Boolean, string, or integer. One or more preestablished stored testing algorithms is automatically selected based on the user selected data type and one or more values are applied to the selected one or more preestablished stored testing algorithms in accordance with the user selected data type. At least one set of test data from the one or more identified applicable testing algorithms is automatically generated, wherein the at least one set of test data generated from the identified testing algorithms can be used as inputs for testing the target software code.
US09529697B1 Coverage analysis for variable size signals
An embodiment can include one or more computer-readable media storing executable instructions that when executed on processing logic process variable signals. The media can store one or more instructions for receiving executable code that includes constructs with variable signals for processing the variable signals, and for performing a coverage measurement on the executable code based on information about one or more of the variable signals processed by the executable code. The media can store one or more instructions for producing a coverage result based on the coverage measurement, the coverage result identifying a degree of coverage for the executable code when the executable code processes the variable signals.
US09529695B2 Detecting race condition vulnerabilities in computer software applications
Testing computer software applications is performed by identifying first and second executable portions of the computer software application, where the portions are configured to access a data resource, and where at least one of the portions is configured to write to the data resource, instrumenting the computer software application by inserting one or more instrumentation instructions into one or both of the portions, where the instrumentation instruction is configured to cause execution of the portion being instrumented to be extended by a randomly-determined amount of time, and testing the computer software application in multiple iterations, where the computer software application is executed in multiple parallel execution threads, where the portions are independently executed at least partially in parallel in different threads, and where the computer software application is differently instrumented in each of the iterations.
US09529692B2 Memory management tools
The present technology monitors events that allocate and deallocate virtual memory regions in a device, wherein the events include system calls from user space. The system can generate a log of events, and based on the log of events, track regions of virtual memory allocated and deallocated via the events. The system can also record events with corresponding stack traces. Next, the system can group recorded events having matching stack traces to yield event groupings, and instrument functions in a compiled code associated with the process to determine retain counts of respective events associated with the functions. The system can then automatically pair at least one of a first portion of the events and a second portion of the respective events based on the event groupings and the retain counts of the respective events to yield paired events.
US09529691B2 Monitoring and correlating a binary process in a distributed business transaction
A dynamic monitoring process begins with configuring a start and end method to be monitored. The dynamic monitoring process may intercept both the start and end methods as and when the loader is initiated or at runtime to dynamically attach and detach the instrumentation. A loader may then be modified to call a library method upon detection of the start method. The library method may serve as a notification to the start of the method and causes a reflector to retrieve information from the incoming request. The incoming information may include data from which a business transaction name may be determined. The business transaction name is then associated with the monitoring of the particular request. When an exit call is detected, a call may be made to the library for a method which invokes a decorator. The decorator may insert business transaction name and other data into the outgoing call.
US09529689B2 Monitoring cloud computing environments
A monitoring system can provide monitoring services to users of cloud computing environment. The monitoring system can receive access information from users subscribing to the monitoring services. Once received, the monitoring system can access clouds utilizing the access information and monitor the computing processes instantiated in the clouds and associated with the user. The monitoring system can monitor the computing processes and collect information such as usage of cloud resources, number and type of computing processes instantiated, software programs utilized by the computing processes.
US09529686B1 Error protection for bus interconnect circuits
In an approach for detecting faults on a bus interconnect that connects a bus master circuit to bus slave circuits, application program code and fault detection program code are concurrently executed by a bus master circuit. The application program code initiates first bus transactions to the bus slave circuits, and the fault detection program code initiates second bus transactions to the bus slave circuits for detection of faults in data channels of the bus interconnect. An error code generator circuit generates error codes from addresses of the first and second bus transactions. The error codes are transmitted with the first and second bus transactions on address channels of the bus interconnect to addressed ones of the bus slave circuits. Respective error code checker circuits coupled between the bus interconnect and the bus slave circuits determine whether or not the addresses of the bus transactions are correct based on the error codes.
US09529680B2 Virtual resource-based backup
A device may receive a virtual image of a first state of a first virtual machine. Session information of the state of the first virtual machine may be synchronized with a second state of a second virtual machine. The second state of the second virtual machine may become active when the first virtual machine becomes unavailable. The device may identify that the first virtual machine is unavailable; and output, based on the identifying, the virtual image of the first state to a particular third virtual machine, to cause the particular third virtual machine to restore the first state of the first virtual machine. The second state of the second virtual machine may become inactive when the first state is restored to the third virtual machine.
US09529678B2 Apparatus and method for monitoring and auditing activity of a legacy environment
An apparatus and a method for monitoring and auditing activity of a legacy environment. The apparatus includes an analyzer and a mirror manager. The analyzer is operative to analyze intercepted packets conveyed by entities in a network and to generate analyzed data based on information associated with at least some of the packets. The analyzed data is indicative of sessions. The mirror manager is responsive to the analyzed data for generating data representative of mirror sessions, each mirror session corresponding to a session.
US09529674B2 Storage device management of unrecoverable logical block addresses for RAID data regeneration
A host processing system includes a processor, a RAID controller, and a data storage device coupled to the RAID controller and operable to detect first unrecoverable data at a first logical block address (LBA) of the data storage device, log the first LBA in an unrecoverable LBA table of the data storage device, provide the unrecoverable LBA table to the RAID controller, and in response to receiving a write to the first LBA, remove the first LBA from the unrecoverable LBA table.
US09529673B2 Memory device having adjustable refresh period and method of operating the same
A memory device includes a plurality of rows of memory cells, a refresh period determination unit, and a refresh control unit. The plurality of rows of memory cells includes a first row and one or more second rows. The refresh period determination unit is configured to set a refresh period according to read data from the first row. A refresh control unit is configured to control refreshing the one or more second rows based on the refresh period and to control obtaining the read data from the first row based on an adjustment interval.
US09529671B2 Error detection in stored data values
An apparatus has a plurality of storage units. A parity generator is configured to generate a parity value in dependence on the respective values stored in the plurality of storage units. The parity generator is configured such that determination of the parity value is independent of a read access to the data stored the plurality of storage units. A detector is configured to detect a change in value of the parity value.
US09529666B2 Decoding method, memory storage device and memory controlling circuit unit
A decoding method, a memory storage device and a memory controlling circuit are provided. The decoding method includes: sending a read command sequence configured to read the memory cells, so as to obtain a plurality of first verification bits; executing a first decoding procedure according to the first verification bits, and determining whether a first valid codeword is generated; if the first valid codeword is not generated, sending another read command sequence configured to obtain a plurality of second verification bits; calculating a total number of the memory cells conforming to a specific condition according to the second verification bits; obtaining a channel reliability message according to the total number; and executing a second decoding procedure according to the channel reliability message. Accordingly, a correcting ability of decoding may be improved.
US09529664B2 Using error correcting codes for parity purposes
Software that combines parity bits with error correcting codes (ECC) such that a subset of ECC bits is also used for parity purposes, by performing the following steps: (i) providing a first set of redundant bit(s) in a data block, where the first set of redundant bit(s) is adapted to detect and/or correct errors in the data block; (ii) providing, within the first set of redundant bit(s), a first sub-set of parity bit(s), where the first sub-set of parity bit(s) is adapted to provide single bit error detection for the data block; and (iii) determining, based, at least in part, on a first set of data read requirements, whether to use the first set of redundant bit(s) and/or the first sub-set of parity bit(s) to detect and/or correct potential errors while reading data on the data block.
US09529663B1 Detection and localization of failures in 3D NAND flash memory
A method includes, in a memory block, which includes at least a string of memory cells that is selectable using at least a select transistor, sensing a current flowing through the string. A failure in the memory block, which causes the string to conduct even when unselected using the select transistor, is detected based on the sensed current. A corrective action is initiated in response to the identified failure.
US09529662B1 Dynamic rule-based automatic crash dump analyzer
A method and system for dynamic rule-based automatic crash dump analysis are described. In an example, a dynamic rule-based crash dump analysis system retrieves debug symbol data, rules, and commands from a server over a network. The actions are executed based on the retrieved rules in order to automatically analyze a crash dump using a debugger and the debug symbol data. During the process of analyzing the crash dump, the system parses output from the debugger for further rule processing and creates a human-readable analysis file from the parsed output.
US09529659B2 Fault detection apparatus, a fault detection method and a program recording medium
A fault detection apparatus includes a storage unit which stores correlation destruction set information which includes one or more correlations between different types of performance values among a plurality of types of performance values of a system, and a comparison unit which detects a set of common correlations between said one or more correlations included in said correlation destruction set information and one or more correlations on each of which a correlation destruction is detected for inputted performance values.
US09529653B2 Processor register error correction management
Processor register protection management is disclosed. In embodiments, a method of processor register protection management can include determining a sensitive logical register for executable code generated by a compiler, generating an error-correction table identifying the sensitive logical register, and storing the error-correction table in a memory accessible by a processor. The processor can be configured to generate a duplicate register of the sensitive logical register identified by the error-correction table.
US09529650B2 Method and apparatus for accessing hardware resource
A method and an apparatus for accessing a hardware resource are provided. The method includes configuring permission for one or more privileged instructions that are used for hardware access such that when the privileged instructions are used by a user mode application program, the application program can access a hardware resource without trapping into a kernel, and executing the privileged instructions that are encapsulated in the privileged application programming interface (API) that is called at the code level by the application program , and a privileged instruction for direct access to a hardware resource is set and encapsulated into an API, which is deployed in user space in order to reduce system overheads for accessing the hardware resource and improve processing efficiency.
US09529647B2 System and method for controlling the sale and manufacture of equipment and the transition therebetween
A software and implementable system which provides bi-directional communication between engineering, through software add-ins, and other applications within an ERP system. Such a system provides efficiency enhancements and provides improved data flow and communication between engineering and others. While not required, the system is well suited for application in association with manufacturing of equipment, and in particular, manufacturing of custom equipment.
US09529645B2 Methods and apparatus to manage speculative execution of object locks by diverting the speculative execution of target code
Example methods and apparatus to manage object locks are disclosed. A disclosed example method includes intercepting a processor request to apply the lock on the object, identifying a performance history of the object based on a number of instances of contention, reducing computing resources of the processor by, when the number of instances is below a threshold value, generating a lock bypass for the object to cause speculative execution of target code within the object, and preventing speculative execution by applying the lock on the object when the number of instances is above the threshold value.
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