Document Document Title
US09472741B2 Semiconductor light-emitting device
A semiconductor light-emitting device includes a substrate; a first cladding layer formed on the substrate; a first guide layer formed on the first cladding layer; an active layer formed on the first guide layer; a second guide layer formed on the active layer; a contact layer formed on the second guide layer; a cladding electrode formed on the contact layer, and made of conductive metal oxide; and a pad electrode electrically coupled to the cladding electrode. The semiconductor light-emitting device includes a mesa structure including the contact layer. The cladding electrode has a greater width than the mesa structure. The cladding electrode covers an upper surface and side surfaces of the mesa structure, and is electrically coupled to the contact layer.
US09472738B2 Light emitting member having a wiring board with through hole exposing a light emitting semiconductor element with a light reflecting member covering a peripheral wall portion of the through hole
A light emitting device includes a heat dissipation board, a wiring board that is bonded and fixed to the heat dissipation board and formed with a through-hole, a semiconductor light emitting element that is mounted on a face of the heat dissipation board, the face being exposed through the through-hole of the wiring board, and a light reflecting member that covers a portion of an inner peripheral wall surface of the through-hole of the wiring board, the portion being squarely opposed to a side surface of the semiconductor light emitting element.
US09472737B2 Light emitting device and method of manufacturing same
A light-emitting device includes a substrate; a light-emitting element mounted on the substrate; a first light-transmissive member bonded to an upper surface of the light-emitting element via an adhesive; and a second light-transmissive member placed on an upper surface of the first light-transmissive member. In a plan view of the light-emitting device, a peripheral edge of a lower surface of the first light-transmissive member is positioned more inward than a peripheral edge of the upper surface of the light-emitting element. The adhesive extends from the upper surface of the light-emitting element to a lower surface of the second light-transmissive member, the adhesive covers a side surface of the first light-transmissive member, and the adhesive is separated from the substrate.
US09472735B2 Light-emitting device
A light-emitting device includes a package and at least one light-emitting element. The package includes a concave portion which has a bottom surface. The bottom surface includes sides, package distances between opposite sides among the sides, a longest package distance among the package distances, a lower side among the sides, and an upper side among the sides opposite to the lower side. The at least one light-emitting element is arranged on the bottom surface of the concave portion and has a polygonal shape viewed along a front direction. The polygonal shape has light-emitting element distances between vertexes of the polygonal shape and has a longest light-emitting element distance among the light-emitting element distances. The at least one light-emitting element is arranged such that a light-emitting element lateral line along the longest light-emitting element distance is substantially parallel to a package lateral line along the longest package distance.
US09472731B2 Phosphor-containing resin molded body, light emitting device, and resin pellet
A phosphor-containing resin molded body and a wavelength conversion member, in each of which one or more kinds of spherical phosphors represented by (AxByCz)3C5O12 (wherein A represents one or more rare earth elements selected from among Y, Gd and Lu; B represents one or more rare earth elements selected from among Ce, Nd and Tb; C represents Al and/or Ga; and x, y and z respectively represent positive numbers satisfying 0.002≦y≦0.2, 0
US09472730B2 Light emitting device
A light emitting device includes a light emitting element and a luminescent color conversion layer covering a light emitting surface of the light emitting element. The luminescent color conversion layer includes a transparent synthetic resin material and integrated particles provided inside the transparent synthetic resin material, each of the integrated particles being a mixture of phosphors and a dispersively binding material that are bonded to each other. The dispersively binding material has transparency and bondability to the phosphors. The luminescent color conversion layer is arranged such that primary light and secondary light are mixed to generate a mixed color light and such that the mixed-color light is emitted outside from the luminescent color conversion layer, the primary light being excitation light emitted by the light emitting element, and the secondary light being a portion of the primary light that has been is color-converted by an excitation of the phosphors.
US09472728B2 Light emitting device package and lighting apparatus including the package
A light emitting device package includes a package body, and a light emitting device chip provided on a chip mount area of the package body. A molding member is provided on the package body. The package body includes a central area having the chip mount area and a chip non-mount area adjacent to the chip mount area. An upper surface of the light emitting device chip is higher than an upper surface of the package body in the chip non-mount area and an upper surface of the package body in the peripheral area.
US09472726B2 Integrated LED light-emitting device and fabrication method thereof
An integrated LED light-emitting device includes: at least two mutually-isolated LED light-emitting epitaxial units having an upper and a lower surface, in which, the upper surface is a light-emitting surface; an electrode pad layer over the lower surface of the LED light-emitting epitaxial unit, with sufficient thickness for supporting the LED epitaxial unit and connecting to each LED light-emitting epitaxial unit to form a connection circuit plane with no height difference; and the electrode pad layer is divided into a P electrode region and an N electrode region. The LED light-emitting epitaxial units constitute a series, parallel or series-parallel circuit. Embodiments disclosed herein can effectively improve the problems of package welding, electrode shading and poor wiring stability.
US09472722B1 Light emitting device package and manufacturing method thereof
A light emitting device (LED) package and a manufacturing method thereof are provided. The LED package includes an LED including a first electrode pad and a second electrode pad disposed on one surface thereof; a bonding insulating pattern layer configured to expose the first electrode pad and the second electrode pad; a substrate including a via hole bored from a first surface to a second surface and a wiring metal layer formed on an inner surface of the via hole to extend to a part of the second surface; and a bonding metal pattern layer bonded to the wiring metal layer exposed through the via hole at the first surface of the substrate and also bonded to the first electrode pad and the second electrode pad.
US09472718B2 Semiconductor light-emitting element comprising an insulating reflection layer including plural opening portions
A semiconductor light-emitting element includes: a laminated semiconductor layer in which an n-type semiconductor layer, a light-emitting layer and a p-type semiconductor layer are laminated; a transparent conductive layer laminated on the p-type semiconductor layer of the laminated semiconductor layer and composed of a metal oxide having optical transparency to light emitted from the light-emitting layer; an insulating reflation layer laminated on the transparent conductive layer in which plural opening portions are provided to expose part of the transparent conductive layer; a metal reflection layer formed on the insulating reflection layer and inside the opening portions and composed of a metal containing aluminum; and a metal contact layer provided between the part of the transparent conductive layer exposed at the opening portion and the part of the metal reflection layer formed inside the opening portion, which contains an element selected from Group VIA and Group VIII of a periodic table.
US09472717B2 Methods for making water soluble quantum dots
A novel quantum dot containing two different metals at non-toxic levels which is capable of narrow bandwidth near infrared emissions at wavelengths of 600-1100 nm. The quantum dot is fabricated via an aqueous method which forms a structure having an inner region of one composition and an outer region of a different composition, wherein the inner region contains at least a first metal and the outer region contains at least a second metal. The quantum dots may be enabled for bioconjugation and may be used in a method for tissue imaging and analyte detection.
US09472713B2 Semiconductor light-emitting device
An embodiment has an emission layer, a first electrode having a reflective metal layer, an insulating layer, first and second conductivity type layers, and a second electrode. The insulating layer is provided on the first electrode and has an opening where a portion of the first electrode is provided. The first conductivity type layer is provided between the insulating layer and the emission layer and has bandgap energy larger than that of the emission layer. The second conductivity type layer is provided on the emission layer and has a current diffusion layer and a second contact layer. The second contact layer is not superimposed on the opening of the insulating layer, and a thickness of the current diffusion layer is larger than that of the first contact layer. The second electrode has a pad portion and a thin portion extends from the pad portion onto the second contact layer.
US09472704B2 Radiation detector and medical diagnostic system
A radiation detector is disclosed, including a plurality of detector elements arranged adjacent to one another in a planar manner. In an embodiment, for the purpose of radiation detection, a semiconductor layer with an upper side and a lower side is present, the semiconductor layer on one of the sides including an electrode embodied so as to extend across a number of detector elements and electrodes subdivided into individual electrodes being arranged on the other side of the semiconductor layer so that by applying voltage between the electrodes of the two sides, an electrical field is generatable and each individual electrode is assigned an effective volume so as to collect charge in the semiconductor layer. In an embodiment, the individual electrodes are alternately connected to at least two different voltage potentials. Furthermore, a medical diagnostic system is disclosed, including at least one such radiation detector.
US09472703B2 Monolithic integration of heterojunction solar cells
A method for fabricating a device with integrated photovoltaic cells includes supporting a semiconductor substrate on a first handle substrate and doping the semiconductor substrate to form doped alternating regions with opposite conductivity. A doped layer is formed over a first side the semiconductor substrate. A conductive material is patterned over the doped layer to form conductive islands such that the conductive islands are aligned with the alternating regions to define a plurality of photovoltaic cells connected in series on a monolithic structure.
US09472702B1 Photovoltaic cell with nano-patterned substrate
A photovoltaic solar cell comprises a nano-patterned substrate layer. A plurality of nano-windows are etched into an intermediate substrate layer to form the nano-patterned substrate layer. The nano-patterned substrate layer is positioned between an n-type semiconductor layer composed of an n-type semiconductor material and a p-type semiconductor layer composed of a p-type semiconductor material. Semiconductor material accumulates in the plurality of nano-windows, causing a plurality of heterojunctions to form between the n-type semiconductor layer and the p-type semiconductor layer.
US09472701B2 Systems and methods for wiring solar panel arrays
A solar power system may include a combiner module, one or more rows of solar panels connected to the combiner module, and one or more wiring circuits connecting the one or more rows of solar panels to the combiner module. Each circuit may include an inter-module wiring arrangement that connects individual solar panels to each other in series, and a return wiring arrangement that connects the inter-module wiring arrangement to the combiner module. Each inter-module wiring arrangement may be arranged such that at least some solar panels are wired to other solar panels in the same row in a substantially alternating manner, such that non-adjacent solar panels in the same row are wired directly in series to each other. This arrangement may reduce the total length of harness wires needed to connect the one or more panel rows to the combiner box, as compared with conventional wiring schemes.
US09472697B2 Photodetector with surface plasmon resonance
Methods and structures for providing single-color or multi-color photo-detectors leveraging plasmon resonance for performance benefits. In one example, a radiation detector includes a semiconductor absorber layer having a first electrical conductivity type and an energy bandgap responsive to radiation in a first spectral region, a semiconductor collector layer coupled to the absorber layer and having a second electrical conductivity type, and a plasmonic resonator coupled to the collector layer and having a periodic structure including a plurality of features arranged in a regularly repeating pattern.
US09472692B2 Process of fabrication of electronic devices and electronic device with a double encapsulation ring
An integrated circuit chip is mounted on top of a base wafer, and a protection wafer is mounted on top of the integrated circuit chip. An encapsulation block is formed around the integrated circuit chip and the protection wafer and on a peripheral part of the front face of the base wafer. The encapsulation block includes a first encapsulation ring arranged around the integrated circuit chip and the protection wafer, having an annular beading protruding with respect to the front face of the protection wafer and forming a peripheral groove (24) recessed with respect to this protruding annular beading. A second encapsulation ring of the encapsulation block fills the peripheral groove of the first encapsulation ring.
US09472691B2 Device for shunting current from photovoltaic circuit near the open circuit voltage and/or disconnecting solar module of a solar system
Devices for reducing the open circuit voltages of solar systems are described. In one embodiment, a solar system includes a string of a plurality of solar modules having an open circuit voltage. The solar system also includes a device for reducing the open circuit voltage of the string of the plurality of solar modules during an open circuit configuration.
US09472688B2 Semiconductor device
A semiconductor device according to the present invention includes a semiconductor layer, a trench formed selectively in an obverse surface portion of the semiconductor layer and defining a unit cell of predetermined shape in the obverse surface portion, a second conductivity type layer formed to conform to a portion or an entirety of an inner surface of the trench, an obverse surface layer of a first conductivity type formed so as to be exposed from an obverse surface of the semiconductor layer in the unit cell, a reverse surface layer of the first conductivity type formed so as to be exposed from a reverse surface of the semiconductor layer, a drift layer of the first conductivity type formed between the obverse surface layer and the reverse surface layer of the semiconductor layer and being of lower concentration than the obverse surface layer and the reverse surface layer, a first electrode contacting the obverse surface layer and forming an ohmic contact with the obverse surface layer, and a second electrode contacting the reverse surface layer and forming an ohmic contact with the reverse surface layer.
US09472686B2 Gate-tunable P-N heterojunction diode, and fabrication method and application of same
One aspect of the invention relates to a gate-tunable p-n heterojunction diode including a vertical stacked heterojunction of two ultrathin semiconductors. In one embodiment, single-layer molybdenum disulphide of an n-type semiconductor are stacked below semiconducting single-walled carbon nanotubes of a p-type semiconductor with each of them connected to a gold electrodes to form a p-n heterojunction. The electrical properties of the p-n heterojunction can be modulated by a gate voltage applied to a gate electrode and range from an insulator to a linear-response resistor to a highly rectifying diode. The gate tunability of the p-n heterojunction also allows spectral control over the photoresponse.
US09472681B2 Semiconductor device and method for manufacturing the same
The electrical characteristics of a transistor including an oxide semiconductor layer are varied by influence of an insulating film in contact with the oxide semiconductor layer, that is, by an interface state between the oxide semiconductor layer and the insulating film. A first oxide semiconductor layer S1, a second oxide semiconductor layer S2, and a third oxide semiconductor layer S3 are sequentially stacked, so that the oxide semiconductor layer through which carriers flow is separated from the gate insulating film containing silicon. The thickness of the first oxide semiconductor layer S1 is preferably smaller than those of the second oxide semiconductor layer S2 and the third oxide semiconductor layer S3, and is less than or equal to 10 nm, preferably less than or equal to 5 nm.
US09472677B2 Semiconductor device
A semiconductor device including an oxide semiconductor can have stable electric characteristics and high reliability. A transistor in which an oxide semiconductor layer containing indium, titanium, and zinc is used as a channel formation region and a semiconductor device including the transistor are provided. As a buffer layer in contact with the oxide semiconductor layer, a metal oxide layer containing an oxide of one or more elements selected from titanium, aluminum, gallium, zirconium, hafnium, and a rare earth element can be used.
US09472676B2 Semiconductor device and manufacturing method thereof
A semiconductor device having excellent electric characteristics and a method for manufacturing the semiconductor device are provided. A method for manufacturing a semiconductor device includes the steps of: forming a gate electrode; forming a gate insulating film to cover the gate electrode; forming an oxide semiconductor film over the gate insulating film; forming a hydrogen permeable film over the oxide semiconductor film; forming a hydrogen capture film over the hydrogen permeable film; performing heat treatment to release hydrogen from the oxide semiconductor film; forming a source electrode and a drain electrode to be in contact with a part of the oxide semiconductor film; and removing an exposed portion of the hydrogen capture film to form a channel protective film formed of the hydrogen permeable film. A semiconductor device manufactured by the above method is also provided.
US09472675B2 Method of manufacturing n-doped graphene and electrical component using NH4F, and graphene and electrical component thereby
This disclosure relates to a method of manufacturing n-doped graphene and an electrical component using ammonium fluoride (NH4F), and to graphene and an electrical component thereby. An example method of manufacturing n-doped graphene includes (a) preparing graphene and ammonium fluoride (NH4F); and (b) exposing the graphene to the ammonium fluoride (NH4F), wherein through (b), a fluorine layer is formed on part or all of upper and lower surfaces of a graphene layer, and ammonium ions are physisorbed to part or all of the upper and lower surfaces of the graphene layer or defects between carbon atoms of the graphene layer, thereby maintaining or further improving superior electrical properties of graphene including charge mobility while performing n-doping of graphene.
US09472665B2 MOS transistor and method for manufacturing MOS transistor
A novel MOS transistor, which includes a source region, a drain region, a channel region, an isolation region, a drift region, a gate dielectric layer, a gate electrode and a field plate, is provided. The gate electrode has a first portion and a second portion. The first portion of a first conductivity type is located over the channel region and has a width equal to or greater than a distance of the gate electrode overlapped with the channel region. The second portion is un-doped and located over the isolation region. Accordingly, the MOS transistor allows higher process freedom saves production cost, as well as improves reliability.
US09472664B1 Semiconductor device and manufacturing method thereof
The present disclosure provides a semiconductor device including a substrate, a gate structure, a channel layer, a first active region and a second active region. The gate structure is disposed in the substrate. The channel layer is sandwiched between the gate structure and the substrate. A material of the channel layer is selected from the group consisting of silicon-germanium epitaxial material, silicon-carbon epitaxial material, and a combination thereof. The first active region and the second active region are disposed in the substrate and respectively disposed at opposite sides of the gate structure. A method for manufacturing a semiconductor device is provided herein.
US09472661B1 Semiconductor structure
A semiconductor structure suitable for operating under a high voltage condition is provided. According to one aspect of the disclosure, the semiconductor structure includes a substrate, a gate, a source region, a drain region and a field-adjusting structure. The gate is disposed on the substrate. The source region and the drain region are disposed in the substrate and at opposite sides of the gate. The field-adjusting structure is disposed on the substrate at an outer side of one of the source region and the drain region. The field-adjusting structure comprises a first portion and a second portion. The second portion is disposed at an outer side of the first portion. The first portion is connected to the gate. The second portion is connected to the one of the source region and the drain region.
US09472660B2 Semiconductor device
A semiconductor device including: a first conductivity type n-type drift layer; a second conductivity type VLD region which is formed on a chip inner circumferential side of a termination structure region provided on one principal surface of the n-type drift layer and which is higher in concentration than the n-type drift layer; a second conductivity type first clip layer which is formed on a chip outer circumferential side of the VLD region so as to be separated from the VLD region and which is higher in concentration than the n-type drift layer; and a first conductivity type channel stopper layer which is formed on a chip outer circumferential side of the first clip layer so as to be separated from the first clip layer and which is higher in concentration than the n-type drift layer. Thus, it is possible to provide a semiconductor device having a stable and high breakdown voltage termination structure in which the length of a termination structure region is small as well as the immunity to the influence of external charge is high.
US09472657B2 Triode
A triode includes a semiconductor, a deep n-well, a p-well, an n+ doping region, and a p+ doping region. The deep n-well is disposed adjacent to the semiconductor substrate. The p-well is included in the deep n-well and serves as a collector region of the triode. The n+ doping region serves as a base region of the triode. The p+ doping region serves as an emitter region of the triode. The deep n-well is coupled to the n+ doping region.
US09472656B2 Semiconductor device and method for manufacturing the same
A semiconductor device including a minute transistor with a short channel length is provided. A gate insulating layer is formed over a gate electrode layer; an oxide semiconductor layer is formed over the gate insulating layer; a first conductive layer and a second conductive layer are formed over the oxide semiconductor layer; a conductive film is formed over the first conductive layer and the second conductive layer; a resist mask is formed over the conductive film by performing electron beam exposure; and then a third conductive layer and a fourth conductive layer are formed over and in contact with the first conductive layer and the second conductive layer, respectively, by selectively etching the conductive film.
US09472655B1 Method for producing a semiconductor device
An improvement is made in the reliability of a semiconductor device having a split gate type MONOS memory. An ONO film covering a control gate electrode, and a dummy memory electrode gates are formed, and then a diffusion region on a source-region-side of a memory to produced is formed across the dummy memory electrode gates. Subsequently, the dummy memory electrode gates is removed, and then a memory gate electrode is formed which is smaller in gate length than the dummy memory electrode gates. Thereafter, an extension region on the source-region-side of the memory is formed.
US09472654B2 Forming low parasitic trim gate last MOSFET
A method for making a fin MOSFET with substantially reduced parasitic capacitance and/or resistance is provided. The fin MOSFET includes: a patterned fin structure on a substrate, the substrate including a first semiconductor layer; an epitaxy layer covering the substrate and a first portion of the fin structure, the first portion of the fin structure being doped to be integrated with the epitaxy layer, wherein a source and drain region is formed in the epitaxy layer; a metal gate high-k structure covering a second portion of the fin structure; a nitride structure covering the metal gate high-k structure; an oxide spacer structure enclosing the metal gate high-k structure and the nitride structure; and a metal contact structure for the source and drain region.
US09472649B1 Fabrication method for multi-zoned and short channel thin film transistors
A method of fabricating a multi-zone, short gate length thin film transistor is provided. Gate metal and a plurality of layers are deposited on a substrate. The layers include a gate insulator, a first semiconductor, a second semiconductor, and source contact metal. An insulator is deposited on the plurality of layers partially overlapping the gate electrode and masking part of the plurality of layers. Portions of the source contact metal not masked by the insulator are removed and the first and second semiconductors are diffused with dopants via a plasma. Sidewalls of the insulator and source metal contact are covered with an insulating layer. Portions of the second semiconductor not masked are removed by etching for a length of time to create undercuts below the insulator and extending under the source contact metal. The undercuts are filled with an insulating material and an external metal contact layer is deposited.
US09472648B2 Semiconductor device, printing apparatus, and manufacturing method thereof
A manufacturing method of a semiconductor device including a DMOS transistor, an NMOS transistor and a PMOS transistor arranged on a semiconductor substrate, the DMOS transistor including a first impurity region and a second impurity region formed to be adjacent to each other, the first impurity region being of the same conductivity type as a drain region and a source region of the DMOS transistor, forming to enclose the drain region, and the second impurity region being of a conductivity type opposite to the first impurity region, forming to enclose the source region, the manufacturing method of the semiconductor device comprising forming the first impurity region and one of the NMOS transistor and the PMOS transistor, and forming the second impurity region and the other of the NMOS transistor and the PMOS transistor.
US09472644B2 Semiconductor device with air gap and method for fabricating the same
A method for fabricating a semiconductor device includes forming a gate structure over a substrate, forming a multi-layer sidewall spacer including a first sacrificial spacer which covers sidewalls of the gate structure and a second sacrificial spacer which is disposed on a sidewall of the first sacrificial spacer and recessed lower than an upper surface of the gate structure, forming an air gap having a narrower width top portion than a middle and a bottom portions, by removing the first and second sacrificial spacers, and forming a capping layer which caps the top portion of the air gap.
US09472641B2 Ambipolar synaptic devices
Device architectures based on trapping and de-trapping holes or electrons and/or recombination of both types of carriers are obtained by carrier trapping either in near-interface deep ambipolar states or in quantum wells/dots, either serving as ambipolar traps in semiconductor layers or in gate dielectric/barrier layers. In either case, the potential barrier for trapping is small and retention is provided by carrier confinement in the deep trap states and/or quantum wells/dots. The device architectures are usable as three terminal or two terminal devices.
US09472633B1 Transistor gate having an insulating layer support structure
Embodiments include but are not limited to apparatuses and systems including a microelectronic device including a gate, a source pad and a drain pad arranged such that the gate is separated from the source pad and the drain pad by air, and an insulating layer coupled with a portion of the gate such that at least a portion of the insulating layer is separated from the source pad and the drain pad by the air. Methods for making the same also are described.
US09472632B2 Semiconductor device
A semiconductor device is provided. The semiconductor device includes a semiconductor substrate, and a core device and a dummy device disposed on the semiconductor substrate. The core device includes a first gate disposed on the semiconductor substrate and a first stress layer disposed on opposing sides of the first gate. The dummy device includes a second gate disposed on the semiconductor substrate and a second stress layer disposed on opposing sides of the second gate.
US09472630B2 Deposit/etch for tapered oxide
A process for fabricating a tapered field plate dielectric for high-voltage semiconductor devices is disclosed. The process may include depositing a thin layer of oxide, depositing a polysilicon hard mask, depositing a resist layer and etching a trench area, performing deep silicon trench etch, and stripping the resist layer. The process may further include repeated steps of depositing a layer of oxide and anisotropic etching of the oxide to form a tapered wall within the trench. The process may further include depositing poly and performing further processing to form the semiconductor device.
US09472626B2 High performance III-nitride power device
A III-nitride semiconductor device which includes a barrier body between the gate electrode and the gate dielectric thereof.
US09472623B2 Nitride semiconductor element and nitride semiconductor package
A nitride semiconductor element capable of accommodating GaN electron transfer layers of a wide range of thickness, so as to allow greater freedom of device design, and a nitride semiconductor element package with excellent voltage tolerance performance and reliability. On a substrate, a buffer layer including an AlN layer, a first AlGaN layer (with an average Al component of 50%) and a second AlGaN layer (with an average Al component of 20%) is formed. On the buffer layer, an element action layer including a GaN electron transfer layer and an AlGaN electron supply layer is formed. Thus, an HEMT element is constituted.
US09472622B2 Semiconductor device and method for fabricating the same
A semiconductor device includes an emitter electrode and a first field plate disposed on one surface of a substrate and spaced apart from each other, a collector electrode disposed on the other surface of the substrate, a trench gate disposed in the substrate, a field diffusion junction disposed in the substrate, and a first contact connecting the trench gate and the first field plate. The first field plate has a first part extending toward the emitter electrode with respect to the first contact and having a first width, and a second part extending toward the field diffusion junction with respect to the first contact and having a second width. The second width is greater than the first width.
US09472616B2 Undercut insulating regions for silicon-on-insulator device
A method of making a silicon-on-insulator (SOI) semiconductor device includes etching an undercut isolation trench into an SOI substrate, the SOI substrate comprising a bottom substrate, a buried oxide (BOX) layer formed on the bottom substrate, and a top SOI layer formed on the BOX layer, wherein the undercut isolation trench extends through the top SOI layer and the BOX layer and into the bottom substrate such that a portion of the undercut isolation trench is located in the bottom substrate underneath the BOX layer. The undercut isolation trench is filled with an undercut fill comprising an insulating material to form an undercut isolation region. A field effect transistor (FET) device is formed on the top SOI layer adjacent to the undercut isolation region, wherein the undercut isolation region extends underneath a source/drain region of the FET.
US09472611B2 Semiconductor device and method of manufacturing the same
A semiconductor device includes: a semiconductor substrate; a base above the semiconductor substrate; a first conductive plug in the base; a memory cell region in the base; and a logic circuit region connected to the memory cell region, the logic circuit including a first capacitor. The first capacitor includes: a first bottom electrode, a part of a lower surface of the first bottom electrode being in contact with the first conductive plug; a first insulating film on the first bottom electrode; and a first top electrode on the first insulating film. The first top electrode is spaced apart from the first conductive plug in planar view.
US09472609B2 Methods of manufacturing polyresistors with selected TCR
Various embodiments provide computer program products and computer implemented methods. In some embodiments, aspects provide for a method of manufacturing a polysilicon resistor with a selected temperature coefficient of resistance (TCR), the method including selecting a sheet resistance for the polysilicon resistor, the selected sheet resistance being related to a selected film thickness of the polysilicon resistor, selecting a dose level for a grain size modulating species (GSMS) for modulating an average grain size of grains of the polysilicon resistor, selecting a thermal coefficient of resistance (TCR) for the polysilicon resistor, the TCR being related to a selected average grain size of the polysilicon and forming the polysilicon resistor on a substrate, the polysilicon resistor having the selected sheet resistance, the selected GSMS dose level and the selected TCR.
US09472608B2 Chip inductor
Disclosed herein is a chip inductor. The chip inductor according to the present invention includes a substrate on which a through-hole is formed, a conductive coil that is formed on the substrate, an upper resin composite magnetic layer that is filled to surround the conductive coil so that a core is formed on a center portion of the substrate, a lower resin composite magnetic layer that is formed on a bottom portion of the substrate, and an external electrode that is formed on both sides of the upper and lower resin composite magnetic layers.
US09472605B2 Organic light-emitting diode display with enhanced aperture ratio
An organic light-emitting diode display may have an array of pixels. Each pixel may have an organic light-emitting diode with an anode and cathode. The anodes may be formed from a patterned layer of metal. Thin-film transistor circuitry in the pixels may include transistors such as drive transistors and switching transistors. Data lines may supply data signals to the pixels and horizontal control lines may supply control signals to the gates of the transistors. A switching transistor may be coupled between a voltage initialization line and each anode. The voltage initialization lines and capacitor structures in the thin-film transistor circuitry may be formed using a layer of metal that is different than the layer of metal that forms the anodes.
US09472603B2 Package method of substrate and package structure
The present invention provides a package method of a substrate and a package structure. The method comprises: step 1, providing the substrate (1) and a package plate (3), and the package plate (3) comprises a spreading surface (31); step 2, forming at least one groove (311); step 3, spreading seal glue (50) to form the continuous frame (5), and a recess (51) is formed in the frame (5) corresponding to the groove (311); step 4, positioning underfill (70) inside an area surrounded by the frame (5); step 5, oppositely fitting the substrate (1) and the package plate (3), and an air outlet (20) is formed at a position of the recess (51) of the frame (5) between the substrate (1) and the package plate (3); step 6, extracting air between the substrate (1) and the package plate (3) through the air outlet (20); step 7, laminating the substrate (1) and the package plate (3); step 8, irradiating and solidifying the seal glue (50) and the underfill (70) with UV light.
US09472594B2 Light emitting diode chip
An LED chip for use in an LED chip array forming a continuous array of LEDs. The LED chip comprises an array of LEDs on a substrate. LEDs in a row of the array are longitudinally offset from corresponding LEDs in another row. Adjacent LEDs in each row of the array are separated by a longitudinal pitch. At least part of an end face of the substrate is angled with respect to a transverse axis of the LED chip such that the LED chip is positionable adjacent another LED chip to maintain the longitudinal pitch between adjacent LEDs on different chips.
US09472591B2 Semiconductor image pickup device
According to one embodiment, a semiconductor image pickup device includes a pixel area and a non-pixel area. The device includes a first photoelectric conversion element formed in the pixel area, a first transistor formed in the pixel area and connected to the first photoelectric conversion element, a second photoelectric conversion element formed in the non-pixel area, a second transistor formed in the non-pixel area and connected to the second photoelectric conversion element, a metal wire formed at least in the non-pixel area, a first cap layer formed on the metal wire to prevent diffusion of metal contained in the metal wire, and a dummy via wire formed in the non-pixel area and penetrating the first cap layer.
US09472589B2 Solid-state imaging device and electronic apparatus
An solid-state imaging device includes a pixel region formed on a semiconductor substrate, an effective pixel region and a shielded optical black region in the pixel region, a multilayer wiring layer formed on a surface of the side opposite to a light incident side of the semiconductor substrate, a supporting substrate bonded to a surface of the multilayer wiring layer side, and an antireflection structure that is formed on the bonding surface side of the supporting substrate.
US09472585B2 Semiconductor package, semiconductor device manufacturing method, and solid-state imaging device
A semiconductor package includes: a sheet-like thin plate on which a semiconductor chip is secured; and a substrate including a wiring layer, disposed on the thin plate to extend over a part of a region surrounding the region where the semiconductor chip is secured or over the entire surrounding region, wherein the semiconductor chip and the substrate are electrically connected.
US09472583B2 Method of manufacturing display apparatus using etching buffer layer
A method of manufacturing a display device including providing a substrate, forming a semiconductor layer on the substrate, forming a first insulating layer on the semiconductor layer, forming a metal layer on the first insulating layer, forming a second insulating layer on the metal layer, forming an etching buffer layer on the second insulating layer, forming a photosensitive film pattern on the etching buffer layer, and etching the etching buffer layer and the first and second insulating layers to expose the semiconductor layer.
US09472582B2 Thin film transistor array panel and manufacturing method thereof
A thin film transistor array panel includes an insulation substrate; a gate line and a data line on the insulation substrate; a first passivation layer on the gate line and the data line; an organic layer on the first passivation layer; a first electrode on the organic layer; a second passivation layer on the first electrode; and a second electrode on the second passivation layer. An edge of the organic layer is exposed by the first electrode.
US09472578B2 Display substrate and fabricating method thereof, display panel, and display device
The present invention provides a display substrate and a fabricating method thereof, a display panel, and a display device. The display substrate comprises a base substrate, gate lines and data lines formed on the base substrate, and at least one pixel unit defined by the gate lines and the date lines, wherein, each pixel unit comprises a thin film transistor and a pixel electrode, and in each pixel unit, a drain electrode of the thin film transistor is electrically connected with the pixel electrode by at least part of an edge region of at least one side of the drain electrode. The technical solution of the present invention can increase the number of contact points and/or contact area for connecting the pixel electrode and the drain electrode, and thus display quality is improved.
US09472577B2 Thin film transistor substrate, display apparatus having the same, and manufacturing method thereof
Each pixel of a thin film transistor substrate includes a base substrate including a pixel display area and a pixel non-display area surrounding the pixel display area, a gate electrode on the base substrate in the pixel non-display area, a first insulating layer which is on the base substrate in the pixel non-display area and covers the gate electrode, a semiconductor layer on the first insulating layer, of which a predetermined portion thereof overlaps the gate electrode, a source electrode and a drain electrode which are spaced apart from each other and on the semiconductor layer, a second insulating layer which is on the first insulating layer and the base substrate and covers the source electrode and the drain electrode, and a pixel electrode on the second insulating layer in the pixel display area.
US09472574B2 Ultrathin body (UTB) FinFET semiconductor structure
For fabrication of a semiconductor structure, there is set forth herein a method of fabricating a semiconductor structure, the method including forming a multilayer structure, the multilayer structure having a bulk substrate, a first layer defining an ultrathin body spaced apart from the bulk substrate, and a second layer above the first layer having material for defining a fin, and patterning the second layer to define a fin above the ultrathin body.
US09472571B2 Isolated semiconductor layer over buried isolation layer
An integrated circuit may be formed by forming an isolation recess in a single-crystal silicon-based substrate. Sidewall insulators are formed on sidewalls of the isolation recess. Thermal oxide is formed at a bottom surface of the isolation recess to provide a buried isolation layer, which does not extend up the sidewall insulators. A single-crystal silicon-based semiconductor layer is formed over the buried isolation layer and planarized to be substantially coplanar with the substrate adjacent to the isolation recess, thus forming an isolated semiconductor layer over the buried isolation layer. The isolated semiconductor layer is laterally separated from the substrate.
US09472567B2 Semiconductor device having three-dimensional structure and method of manufacturing the same
A semiconductor device includes a semiconductor pattern; conductive layers each including a first portion through which the semiconductor pattern passes and a second portion having a thickness greater than the first portion, wherein the first portion of each conductive layer includes a first barrier pattern surrounding the semiconductor pattern and a material pattern, which is formed in the first barrier pattern and has an etch selectivity with respect to the first barrier pattern, and the second portion of each conductive layer includes a conductive pattern; and contact plugs connected to the second portion of each of the conductive layers.
US09472566B1 Semiconductor device and method of manufacturing the same
A semiconductor device may include a substrate provided in a peripheral region, first and second insulation pillars formed in the substrate, and a gate electrode extending in a first direction from over the first insulation pillar to over the second insulation pillar, wherein the gate electrode includes first and second etch stop patterns, wherein the first etch stop pattern extends in the first direction from inside the gate electrode to over the first insulation pillar, and wherein the second etch stop pattern extends in the first direction from inside the gate electrode to over the second insulation pillar.
US09472560B2 Memory cell and an array of memory cells
A memory cell includes a first electrode and a second electrode. A select device and a programmable device are in series with each other between the first and second electrodes. The select device is proximate and electrically coupled to the first electrode. The programmable device is proximate and electrically coupled to the second electrode. The programmable device includes a radially inner electrode having radially outer sidewalls. Ferroelectric material is radially outward of the outer sidewalls of the inner electrode. A radially outer electrode is radially outward of the ferroelectric material. One of the outer electrode or the inner electrode is electrically coupled to the select device. The other of the outer electrode and the inner electrode is electrically coupled to the second electrode. Arrays of memory cells are disclosed.
US09472558B1 Semiconductor structures with stacked non-planar field effect transistors and methods of forming the structures
Disclosed are semiconductor structures and methods of forming them. The structures include field effect transistors (FETs) with different type conductivities in different levels, respectively, of the same fin, wherein the numbers of FETs in the different levels are different. Specifically, in a fin, a first semiconductor layer has source/drain and channel regions for a first and a second transistor and a second semiconductor layer has source/drain and channel regions for a third transistor with a different type conductivity than first and second transistors. A gate is on the top surface and sides of the first semiconductor layer at the channel region of the first transistor. Another gate has a lower portion on the sides of the first semiconductor layer at the channel region of the second transistor and an upper portion on the top surface and sides of the second semiconductor layer at the channel region of the third transistor.
US09472551B2 Vertical CMOS structure and method
A method for forming stacked, complementary transistors is disclosed. Selective deposition techniques are used to form a column having a lower portion that includes one type of semiconductor (e.g. germanium) and an upper portion of another type of semiconductor (e.g. indium arsenide. The lower portion of the column provides a channel region for a transistor of one type, while the upper column provides a channel region for a transistor of another type. This provides a complementary pair that occupies a minimum of integrated circuit surface area. The complementary transistors can be utilized in a variety of circuit configurations. Described are complementary transistors where the lower transistor is p-type and the upper transistor is n-type.
US09472549B2 Cascoded semiconductor devices
A cascoded power semiconductor circuit has a clamp circuit between the source and gate of a gallium nitride or silicon carbide FET to provide avalanche protection for the cascode MOSFET transistor.
US09472546B2 Cell-based IC layout system and cell-based IC layout method
A decoupling capacitor cell includes: a first decoupling capacitor formed by only a pMOS transistor; and a second decoupling capacitor formed by two metal layers. The decoupling capacitor cell is arranged in an unused region not occupied by basic cells in a cell-based IC and is connected to a power wiring and a ground wiring.
US09472544B2 Semiconductor device comprising electrostatic discharge protection structure
A semiconductor device comprises a semiconductor body having a first surface and a second surface opposite to the first surface. The semiconductor device further comprises a first isolation layer on the first surface of the semiconductor body, and an electrostatic discharge protection structure on the first isolation layer. The electrostatic discharge protection structure has a first terminal and a second terminal. The semiconductor device further comprises a heat dissipation structure, which has a first end in contact with the electrostatic discharge protection structure and a second end which is in direct contact to an electrically isolating region.
US09472540B2 Methods for making semiconductor device with sealing resin
Various embodiments of the present invention include a method for making a semiconductor device the method including disposing a first semiconductor chip on a first surface of a first substrate, the first substrate comprising a second surface opposing the first surface, depositing a first resin above the first semiconductor chip, disposing a built-in semiconductor device on the first resin. The built-in semiconductor device including a second substrate, a second semiconductor chip disposed on the second substrate, and a second resin that seals the second semiconductor chip. The method including depositing a third resin above the built-in semiconductor device and the first resin and covering a side surface of the first substrate and not extending beyond the second surface of the first substrate. According to an aspect of the present invention, it is possible to provide a high-quality semiconductor device fabrication method, in which downsizing and cost reduction can be realized.
US09472539B2 Semiconductor chip and a semiconductor package having a package on package (POP) structure including the semiconductor chip
A semiconductor chip including a substrate, a first data pad arranged on the substrate, and a first control/address pad arranged on the substrate, wherein the first data pad is arranged in an edge region of the substrate, and the first control/address pad is arranged in a center region of the substrate.
US09472538B2 Semiconductor device manufacturing method and semiconductor device
Fixing a semiconductor element to a substrate, electrically connecting signal and main terminals to the semiconductor element, a terminal aggregate includes a frame portion, the signal terminal, the main terminal, which has a larger width than the signal terminal, and a dummy terminal, and forming a to-be-encapsulated body in which the substrate, the semiconductor element, and the terminal aggregate are integrated, mounting the to-be-encapsulated body on a lower mold half such that a plurality of blocks formed in the lower mold half are meshed with the signal, main, and dummy terminals with no space left therebetween after the mounting, placing a bottom surface of an upper mold half on top surfaces of the plurality of blocks, and top surfaces of the signal, main, and dummy terminals to form a cavity for the substrate and the semiconductor element, and performing molding by injecting mold resin into the cavity are included.
US09472534B2 Method of arranging a multiplicity of LEDs in packaging units, and packaging unit including a multiplicity of LEDs
A method of arranging a multiplicity of LEDs in packaging units includes defining a desired range for at least one photometric measurement variable for each of the packaging units; selecting an LED from the multiplicity of LEDs not yet arranged in one of the packaging units; measuring the at least one photometric measurement variable for the selected LED; equipping one of the packaging units containing fewer than N−1 LEDs with the selected LED; storing a measured value and a position of the selected LED in the packaging unit in a memory; repeating until the packaging units are equipped with N−1 LEDs; repeating and calculating the average value of the photometric measurement variable, equipping a packaging unit for which the calculated average value of the variable lies in a defined range with the selected LED; and storing the measured value and the position of the selected LED.
US09472533B2 Semiconductor device and method of forming wire bondable fan-out EWLB package
A semiconductor device has a first semiconductor die and a first encapsulant deposited over the first semiconductor die. An interconnect structure is formed over the first semiconductor die and first encapsulant. A modular interconnect structure including a conductive via is disposed adjacent to the first semiconductor die. The first encapsulant is deposited over the modular interconnect structure. An opening is formed in the first encapsulant extending to the modular interconnect structure or to the interconnect structure. A second semiconductor die is disposed over the first semiconductor die. A bond wire is formed over the second semiconductor die and extends into the opening in the first encapsulant. A cap is formed over an active region of the second semiconductor die. A second encapsulant is deposited over the second semiconductor die and bond wire. Alternatively, a lid is formed over the second semiconductor die and bond wire.
US09472532B2 Leadframe area array packaging technology
Embodiments of the present invention are directed to leadframe area array packaging technology for fabricating an area array of I/O contacts. A manufactured package includes a polymer material substrate, an interconnect layer positioned on top of the polymer material substrate, a die coupled to the interconnect layer via wire bonds or conductive pillars, and a molding compound encapsulating the die, the interconnect layer and the wire bonds or conductive pillars. The polymer material is typically formed on a carrier before assembly and is not removed to act as the substrate of the manufactured package. The polymer material substrate has a plurality of through holes that exposes the interconnect layer at predetermined locations and enables solder ball mounting or solder printing directly to the interconnect layer. In some embodiments, the semiconductor package includes a relief channel in the polymer material substrate to improve the reliability performance of the manufactured package.
US09472531B2 Device packaging facility and method, and device processing apparatus utilizing phthalate
Provided are a device packing facility and method using phthalate and a device processing apparatus utilizing the phthalate. The device packaging facility includes a mounting unit providing phthalate between first and second devices to attach the first and second devices to each other, a processing unit thermally processing the first and second devices that are attached to each other to remove the phthalate and fix the first and second devices to each other, and a transfer unit transferring the first and second devices that are attached to each other from the mounting unit to the processing unit.
US09472525B2 Bump-on-trace structures with high assembly yield
A package includes first package component, which further includes a first metal trace at a surface of the first package component, with the first metal trace having a trace width measured in a direction perpendicular to a lengthwise direction of the first metal trace. The first package component further includes a second metal trace at the surface of the first package component. The first metal trace and the second metal trace are parallel to each other. A second package component is overlying the first package component, wherein the second package component includes a metal bump. A solder region bonds the metal bump to the first metal trace, wherein the solder region contacts a top surface and sidewalls of the first portion of the first metal trace. A ratio of a volume of the solder region to the trace width is between about 1,100 μm2 and about 1,300 μm2.
US09472523B2 Semiconductor structure and manufacturing method thereof
A semiconductor structure includes a conductive bump for disposing over a substrate and an elongated ferromagnetic member surrounded by the conductive bump, including a first end and a second end, and extending from the first end to the second end, the elongated ferromagnetic member is disposed substantially orthogonal to the substrate to dispose the conductive bump at a predetermined orientation and at a predetermined position of the substrate. Further, a method of manufacturing a semiconductor structure includes providing a substrate, forming a conductive trace within the substrate, applying an electric current passing through the conductive trace to generate an electromagnetic field and disposing a conductive bump including an elongated ferromagnetic member in a predetermined orientation and at a predetermined position above the substrate in response to the electromagnetic field generated by the conductive trace.
US09472522B2 Packaging devices and methods of manufacture thereof
Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a packaging device includes a contact pad disposed over a substrate, and a passivation layer disposed over the substrate and a first portion of the contact pad, a second portion of the contact pad being exposed. A post passivation interconnect (PPI) line is disposed over the passivation layer and is coupled to the second portion of the contact pad. A PPI pad is disposed over the passivation layer and is coupled to the PPI line. An insulating material is disposed over the PPI line, the PPI pad being exposed. The insulating material is spaced apart from an edge portion of the PPI pad by a predetermined distance.
US09472518B2 Semiconductor structures including carrier wafers and methods of using such semiconductor structures
A semiconductor structure comprising a carrier wafer and a device wafer. The carrier wafer comprises trenches sized and configured to receive conductive pillars of the device wafer. The carrier wafer and the device wafer are fusion bonded together and back side processing effected on the device wafer. The device wafer may be released from the carrier wafer by one or more of mechanically cleaving, thermally cleaving, and mechanically separating. Methods of forming the semiconductor structure including the carrier wafer and the device wafer are disclosed.
US09472516B2 Fan out package structure and methods of forming
An embodiment is a structure comprising a die having a pad on a surface and an encapsulant at least laterally encapsulating the die. The pad is exposed through the encapsulant. The structure further includes a first dielectric layer over the encapsulant and the die, a first conductive pattern over the first dielectric layer, and a second dielectric layer over the first conductive pattern and the first dielectric layer. The first dielectric layer and the second dielectric layer have a first opening to the pad of the die. The structure further includes a second conductive pattern over the second dielectric layer and in the first opening. The second conductive pattern adjoins a sidewall of the first dielectric layer in the first opening and a sidewall of the second dielectric layer in the first opening.
US09472515B2 Integrated circuit package
Embodiments of the present disclosure are directed towards a method of assembling an integrated circuit package. In embodiments the method may include providing a wafer having an unpatterned passivation layer to prevent corrosion of metal conductors embedded in the wafer. The method may further include laminating a dielectric material on the passivation layer to form a dielectric layer and selectively removing dielectric material to form voids in the dielectric layer. These voids may reveal portions of the passivation layer disposed over the metal conductors. The method may then involve removing the portions of the passivation layer to reveal the metal conductors. Other embodiments may be described and/or claimed.
US09472512B1 Integrated circuits with contacts through a buried oxide layer and methods of producing the same
Integrated circuits and methods of producing the same are provided. In an exemplary embodiment, an integrated circuit includes a substrate, where the substrate includes a buried oxide (BOX) layer positioned between a handle layer and a semiconductor layer. An electronic component overlies the buried oxide layer on a semiconductor layer side, and a gate line is electrically connected to the electronic component. A body line is also electrically connected to the electronic component. A first through BOX contact electrically connects the gate line with the handle layer, and a second through BOX contact electrically connects the body line with the handle layer.
US09472510B2 Semiconductor device and control system
To enhance the security of a semiconductor device, the semiconductor device has a regulator unit for generating an internal power supply voltage based on a power supply voltage supplied from outside, an internal circuit which operates on the internal power supply voltage, a current detection unit for monitoring a power supply current supplied to the internal circuit, and a control unit for controlling operation of the internal circuit. In the semiconductor device, when the current detection unit detects that the power supply current exceeds a predetermined threshold value, the control unit restricts the operation of the internal circuit.
US09472508B2 Interconnect arrangement with stress-reducing structure and method of fabricating the same
A semiconductor device structure and a method of fabricating the same are provided. The semiconductor structure includes a substrate and an interconnection structure formed over the substrate. The interconnection structure includes a first dielectric layer and a first stress-reducing structure formed in the first dielectric layer. The interconnection structure further includes a first conductive feature formed in the first dielectric layer, and the first conductive feature is surrounded by the first stress-reducing structure.
US09472507B2 Array substrate and organic light-emitting display including the same
An array substrate includes a substrate, a barrier layer disposed on the substrate, a buffer layer disposed on the barrier layer, a first insulating layer disposed on the buffer layer, a second insulating layer disposed on the first insulating layer, a plurality of wiring patterns disposed between the first insulating layer and the second insulating layer and/or on the second insulating layer. In addition, the wiring patterns are separated from each other, and extend toward a side of the substrate. The array substrate further includes a recess pattern disposed adjacent the wiring patterns and recessed from a top surface of the second insulating layer to expose at least part of a top surface of the substrate, and an organic insulating layer disposed on the second insulating layer and exposing at least part of a portion of the top surface of the substrate which is exposed by the recess pattern.
US09472500B2 Nonvolatile memory devices having single-layered gates
A nonvolatile memory device includes an active region extending in a first direction, a first single-layered gate intersecting the active region and extending in a second direction, a second single-layered gate intersecting the active region and extending in the second direction, and a selection gate intersecting the active region. The selection gate includes a first selection gate main line and a second selection gate main line that intersect the active region to be parallel with the first and second single-layered gates, a selection gate interconnection line that connects a first end of the first selection gate main line to a first end of the second selection gate main line, and a selection gate extension that extends from a portion of the selection gate interconnection line to be disposed between first ends of the first and second single-layered gates.
US09472495B2 Semiconductor device and method of manufacturing the same
Possible to form an opening having a sufficient opening diameter in a region sandwiched between a pair of bit lines and thereby provide a semiconductor device in which a high-quality contact using the opening is formed.The semiconductor device includes a first conductive layer, a first interlayer insulating film, a bit line, a first insulating film, a second interlayer insulating film, and a second conductive layer. The first insulating film that covers a side surface of the bit line has a portion perpendicular to a main surface of a semiconductor substrate in a region lower than a position lower than an uppermost portion of the first insulating film by a thickness, in a direction along the main surface of the semiconductor substrate, of the first insulating film that covers the side surface of the bit line at a lowermost portion of the bit line.
US09472493B1 High heat-dissipation chip package structure
A high heat-dissipation chip package structure for packaging the semiconductor chips is disclosed. A pre-attachment film is adhered on an upper surface of a heat-dissipation plate or a connection plate first and then it is packaged. After packaging, the pre-attachment film is torn off from the upper surface of the heat-dissipation plate or the connection plate. Finally, a metal layer is electroplated on the location of the upper surface of the heat-dissipation plate or the connection plate where the pre-attachment film is torn off so as to improve the fabricating and packaging quality of the semiconductor chips, reduce the cost of cleaning process, and improve the effects of heat dissipation and electrical conductivity.
US09472492B2 Semiconductor device with lead terminals having portions thereof extending obliquely
A semiconductor device in which a semiconductor chip, a lead frame and metal wires for electrically connecting the lead frame are sealed with sealing resin. The lead frame has a plurality of lead terminal portions, a supporting portion for supporting the semiconductor chip, and hanging lead portions supporting the supporting portion. Each of the lead terminal portions adjacent to the hanging lead portion is a chamfered lead terminal portion having, at its head, a chamfered portion formed substantially in parallel with the hanging lead portion so as to avoid interference with the hanging lead portion.
US09472490B1 IC structure with recessed solder bump area and methods of forming same
Embodiments of the present disclosure provide an integrated circuit (IC) structure with a recessed solder bump area, and methods of forming the same. An IC structure according to embodiments of the present disclosure can include: a semiconductor material, wherein an upper surface of the semiconductor material includes a non-recessed area and a recessed area laterally separated from each other, the recessed area of the upper surface being shaped to receive a solder bump therein; at least one first through-semiconductor via (TSV) positioned within the semiconductor material and including an upper surface protruding from the recessed area of the semiconductor material; and a metal layer formed over the recessed area and electrically connected to the at least one first TSV.
US09472489B2 Heat exchanger
An inner fin is provided in a fluid pipe for dividing a fluid passage for heating medium into multiple small fluid passages, so as to facilitate heat exchange between the heating medium and an electronic part. The inner fin is formed in a wave shape in a cross section perpendicular to a flow direction of the heating medium, wherein the inner fin has projecting portions alternately projecting in one direction and in the other direction. The inner fin is composed of multiple fin portions, wherein a fin pitch of a first fin portion is made to be smaller than a fin pitch of a second fin portion, which faces to the electronic part.
US09472487B2 Flexible electronic package integrated heat exchanger with cold plate and risers
In some embodiments, a semiconductor cooling apparatus includes a heat exchanger configured to thermally couple to a semiconductor element to transfer heat to coolant flowing through the heat exchanger. The apparatus also includes a flexible coolant supply manifold and a flexible coolant return manifold. The flexible coolant supply manifold and flexible coolant return manifold flex to conform to a height of the semiconductor element to apply a force to maintain the thermal coupling between the heat exchanger and the semiconductor element. The apparatus also includes a cold plate located under the semiconductor element, the cold plate configured to couple to the flexible coolant supply manifold via a first riser to provide coolant to the flexible coolant supply manifold and configured to couple to the flexible coolant return manifold via a second riser to exhaust returned coolant to the cold plate.
US09472485B2 Hybrid thermal interface material for IC packages with integrated heat spreader
Flip chip packages are described that include two or more thermal interface materials (TIMs). A die is mounted to a substrate by solder bumps. A first TIM is applied to the die, and has a first thermal resistance. A second TIM is applied to the die and/or the substrate, and has a second thermal resistance that is greater than the first thermal resistance. An open end of a heat spreader lid is mounted to the substrate such that the die is positioned in an enclosure formed by the heat spreader lid and substrate. The first TIM and the second TIM are each in contact with an inner surface of the heat spreader lid. A ring-shaped stiffener may surround the die and be connected between the substrate and heat spreader lid by the second TIM.
US09472482B2 Semiconductor device
A semiconductor device includes a substrate, a semiconductor element disposed on the substrate, a heat radiating plate disposed on the substrate and covering the semiconductor element, and a connection member connecting an upper surface of the semiconductor element and a lower surface of the heat radiating plate, wherein the connection member includes a first member being in contact with the upper surface of the semiconductor element and having a first melting point, a second member being in contact with the first member, having a larger area than the first member, and having a second melting point higher than the first melting point, and a third member interposed between the second member and the heat radiating plate, having an area smaller than the second member, and having a third melting point lower than the second melting point.
US09472480B2 Over-mold packaging for wide band-gap semiconductor devices
A transistor package includes a lead frame and a gallium nitride (GaN) transistor attached to the lead frame. The lead frame and the GaN transistor are surrounded by an over-mold with a glass transition temperature greater than about 135° C. and a flexural modulus less than about 20 GPa. Using an over-mold with a glass transition temperature greater than about 135° C. and a flexural modulus less than about 20 GPa allows the over-mold to handle the heat produced by the GaN transistor while preventing damage to the GaN transistor due to thermal expansion and/or contraction of the over-mold.
US09472479B2 Methods and apparatus for providing an interposer for interconnecting semiconductor chips
Methods and apparatus are provide for an interposer for interconnecting one or more semiconductor chips with an organic substrate in a semiconductor package, the interposer including: a first glass substrate having first and second opposing major surfaces, the first glass substrate having a first coefficient of thermal expansion (CTE1); a second glass substrate having first and second opposing major surfaces, the second glass substrate having a second coefficient of thermal expansion (CTE2); and an interface disposed between the first and second glass substrates and joining the second major surface of the first glass substrate to the first major surface of the second glass substrate, where CTE1 is less than CTE2, the first major surface of the first glass substrate operates to engage the one or more semiconductor chips, and the second major surface of the second glass substrate operates to engage the organic substrate.
US09472476B2 System and method for test structure on a wafer
System and method for test structure on a wafer. According to an embodiment, the present invention provides a test structure for testing an integrated circuit. For example, the test structure and the integrated circuit are manufactured on a same substrate material and the testing being conducted is in a temperature-controlled environment. The test structure includes a top structure positioned above the integrated circuit, the top structure including a first metal material, which includes a first electrical terminal and a second electrical terminal. The test structure also includes a bottom structure positioned below the integrated circuit, the bottom structure including a first silicon material. A first side structure is positioned between the top structure and the bottom structure and located next to a first side of the integrated circuit. A second side structure is positioned between the top structure and the bottom structure and located next to a second side of the integrated circuit.
US09472473B2 Method and device for testing a thin film transistor
A method and device for testing a thin film transistor (TFT) provided on an array substrate are provided in an embodiment. The method comprises determining periods and signal amplitudes in each period of the gate electrode test voltage signal and the source-drain-electrode test voltage signal corresponding to the TFT characteristics to be tested, wherein both the gate electrode test voltage signal and the source-drain-electrode test voltage signal are alternative current signals; according to the period and the signal amplitude in each period of the gate electrode test voltage signal and those of the source-drain-electrode test voltage signal, applying the gate electrode test voltage signal to a gate electrode of the TFT to be tested, and applying the source-drain-electrode test voltage signal across source and drain electrodes of the TFT; and obtaining the TFT output signals related to the TFT characteristics to be tested.
US09472472B2 Semiconductor device and method of manufacturing semiconductor device
A semiconductor device includes a first semiconductor substrate, a second semiconductor substrate, a first main surface side of the first semiconductor substrate and a first main surface side of the second semiconductor substrate being bonded to each other; and a warpage correction layer which is formed on at least one or more selected from the first main surface side of the first semiconductor substrate, the first main surface side of the second semiconductor substrate, a second main surface side of the first semiconductor substrate, and a second main surface side of the second semiconductor substrate.
US09472471B1 Hybrid orientation vertically stacked III-V and Ge gate-all-around CMOS
A method of CMOS construction may include stacked III-V nanowires and stacked Ge nanowires. The CMOS construction may include a hybrid orientation with surface SOI and a standard substrate.
US09472470B2 Methods of forming FinFET with wide unmerged source drain EPI
A method including forming fin spacers on opposite sidewalls of a semiconductor fin made from a semiconductor substrate, forming a dielectric layer in direct contact with the fin spacers such that a top surface of the fin and a top surface of the fin spacers remain exposed, recessing a portion of the fin between the fin spacers, removing the fin spacers to create an opening, and epitaxially growing an unmerged source drain region in the opening, where lateral growth of the unmerged source drain region is constrained on opposite sides by the dielectric layer.
US09472469B2 Back gate in select transistor for eDRAM
This disclosure relates to an eDRAM memory element comprising a first storage node, a bitline node for accessing the value stored in the storage node, and a select transistor, controlling access from the bitline node to the storage node, wherein the select transistor has a front gate and a back gate.
US09472467B2 Manufacturing method of semiconductor device
A method of forming a semiconductor device including a semiconductor substrate having a first surface and a second surface, and having a gallium nitride-containing layer provided on the first surface of the semiconductor substrate includes grinding, polishing, and etching the second surface of the semiconductor substrate of which a thickness is d1, and reducing the thickness of the semiconductor substrate to one-fifth or less of d1.
US09472466B2 Semiconductor device having reduced-damage active region and method of manufacturing the same
A semiconductor device according to example embodiments may include a substrate having an NMOS area and a PMOS area, isolation regions and well regions formed in the substrate, gate patterns formed on the substrate between the isolation regions, source/drain regions formed in the substrate between the gate patterns and the isolation regions, source/drain silicide regions formed in the source/drain regions, a tensile stress layer formed on the NMOS area, and a compressive stress layer formed on the PMOS area, wherein the tensile stress layer and compressive stress layer may overlap at a boundary region of the NMOS area and the PMOS area. The semiconductor devices according to example embodiments and methods of manufacturing the same may increase the stress effect on the active region while reducing or preventing surface damage to the active region.
US09472463B2 Patterning process for Fin implantation
After forming an organic planarization layer (OPL) atop a substrate which includes a plurality of semiconductor fins and a gate structure thereon, the OPL is recessed such that uppermost surfaces of remaining portions of the OPL are located below an uppermost surface of the gate structure but above top surfaces of the semiconductor fins. The remaining portions of the OPL are patterned to expose semiconductor fins in a pFinFET region for subsequent ion implantation. Portions of the OPL that remain on the semiconductor fins in an nFinFET region act as an implantation mask to shield the semiconductor fins in the nFinFET region from the ion implantation.
US09472462B2 Method of manufacturing 3D semiconductor integrated circuit device
A method of manufacturing a semiconductor integrated circuit device is provided. The method includes forming a plurality of pillars in a semiconductor substrate, forming an insulating layer between the plurality of pillars in such a manner that an upper region of each pillar protrudes, forming a silicide layer on an exposed surface of the pillar, and forming an insulating layer for planarization in a space between pillars.
US09472454B2 Tungsten film forming method
In a tungsten film forming method, a substrate having a recess is provided in a processing chamber, and a first tungsten film is formed on the substrate to fill the recess with a tungsten by simultaneously or alternately supplying WCl6 gas as a tungsten source and a reducing gas under a depressurized atmosphere of the processing chamber, and by reacting the WCl6 gas with the reducing gas while heating the substrate. Then, an opening is formed in the tungsten filled in the recess by supplying WCl6 gas into the processing chamber and etching an upper portion of the tungsten. Thereafter, a second tungsten film is formed on the substrate having the opening by simultaneously or alternately supplying the WCl6 gas and the reducing gas into the processing chamber, and by reacting the WCl6 gas with the reducing gas while heating the substrate.
US09472451B2 Technique for wafer-level processing of QFN packages
Semiconductor package device, such as wafer-level package semiconductor devices, are described that have pillars for providing electrical interconnectivity. In an implementation, the wafer-level package devices include an integrated circuit chip having at least one pillar formed over the integrated circuit chip. The pillar is configured to provide electrical interconnectivity with the integrated circuit chip. The wafer-level package device also includes an encapsulation structure configured to support the pillar.
US09472449B2 Semiconductor structure with inlaid capping layer and method of manufacturing the same
A method of fabricating a semiconductor structure includes forming a dielectric layer overlaying a substrate; forming a trench in the dielectric layer; forming a first barrier layer lining the trench; forming a conductive layer overlaying the first barrier layer; forming a second barrier layer overlaying the conductive layer; forming a metallic sacrificial layer to cover the second barrier layer and to fill the trench; and performing a polishing process to remove the materials above a bottom portion of the second barrier layer.
US09472448B2 Contact plug without seam hole and methods of forming the same
A method includes forming a metallic layer over a Metal-Oxide-Semiconductor (MOS) device, forming reverse memory posts over the metallic layer, and etching the metallic layer using the reverse memory posts as an etching mask. The remaining portions of the metallic layer include a gate contact plug and a source/drain contact plug. The reverse memory posts are then removed. After the gate contact plug and the source/drain contact plug are formed, an Inter-Level Dielectric (ILD) is formed to surround the gate contact plug and the source/drain contact plug.
US09472437B2 Debonding temporarily bonded semiconductor wafers
Described methods and apparatus provide a controlled perturbation to an adhesive bond between a device wafer and a carrier wafer. The controlled perturbation, which can be mechanical, chemical, thermal, or radiative, facilitates the separation of the two wafers without damaging the device wafer. The controlled perturbation initiates a crack either within the adhesive joining the two wafers, at an interface within the adhesive layer (such as between a release layer and the adhesive), or at a wafer/adhesive interface. The crack can then be propagated using any of the foregoing methods, or combinations thereof, used to initiate the crack.
US09472436B2 Multiple bonding layers for thin-wafer handling
Multiple bonding layer schemes that temporarily join semiconductor substrates are provided. In the inventive bonding scheme, at least one of the layers is directly in contact with the semiconductor substrate and at least two layers within the scheme are in direct contact with one another. The present invention provides several processing options as the different layers within the multilayer structure perform specific functions. More importantly, it will improve performance of the thin-wafer handling solution by providing higher thermal stability, greater compatibility with harsh backside processing steps, protection of bumps on the front side of the wafer by encapsulation, lower stress in the debonding step, and fewer defects on the front side.
US09472431B2 Thin wafer shipper
An improved wafer support mechanism in a wafer container useful for carrying a plurality of axially aligned thin mostly circular wafer substrates. The container includes a cassette that has a plurality of adjacently disposed teeth for receiving the substrates, wherein each rib member is continuous from the cassette open top to the cassette open bottom, a removable top cover portion, a removable bottom cover portion, a cushion assembly removably attached to the container top cover and another cushion assembly removably located in the container bottom cover and held in place by the weight of the wafer cassette. The top cushions are formed of individual segments having an extended lead-in feature at the end of each segment, spring sections in each segment and each segment has a V-shaped cross section to receive the wafer edge. The top and bottom cushions are installed in the top and bottom container covers respectively, and extend the wafer support to approximately the entire circumference of each wafer.
US09472423B2 Method for suppressing lattice defects in a semiconductor substrate
A method for suppressing the formation of leakage-promoting defects in a crystal lattice following dopant implantation in the lattice. The process provides a compressive layer of atoms, these atoms having a size greater than that of the lattice member atoms. The lattice is then annealed for a time sufficient for interstitial defect atoms to be emitted from the compressive layer, and in that manner energetically stable defects are formed in the lattice at a distance from the compressive layer.
US09472420B2 Composition for titanium nitride hard mask and etch residue removal
Aqueous compositions for stripping titanium nitride (TiN or TiNxOy) hard mask and removing etch residue are low pH aqueous composition comprising solvent, a weakly coordinating anion, amine, and at least two non-oxidizing trace metal ions. The aqueous compositions contain no non-ambient oxidizer, and are exposed to air. Bifluoride, or metal corrosion inhibitor may be added to the aqueous composition. Systems and processes use the aqueous compositions for stripping titanium nitride (TiN or TiNxOy) hard mask and removing titanium nitride (TiN or TiNxOy) etch residue.
US09472418B2 Method for forming a split-gate device
A method of forming a semiconductor device in an NVM region and in a logic region uses a semiconductor substrate and includes forming a gate region fill material over the NVM region and the logic region. The gate region fill material is patterned over the NVM region to leave a first patterned gate region fill material over the NVM region. An interlayer dielectric is formed around the first patterned gate region fill material. A first portion of the first patterned gate region fill material is removed to form a first opening and leaving a second portion of the first patterned gate region fill material. The first opening is laterally adjacent to the second portion. The first opening is filled with a charge storage layer and a conductive material that includes metal overlying the charge storage layer.
US09472417B2 Plasma-free metal etch
Methods of selectively etching metal-containing materials from the surface of a substrate are described. The etch selectively removes metal-containing materials relative to silicon-containing films such as silicon, polysilicon, silicon oxide, silicon germanium, silicon carbide, silicon carbon nitride and/or silicon nitride. The methods include exposing metal-containing materials to halogen containing species in a substrate processing region. No plasma excites the halogen-containing precursor either remotely or locally in embodiments.
US09472415B2 Directional chemical oxide etch technique
A method of forming a trench in an oxide layer; where the oxide layer is formed on top of a nitride layer. The trench is formed using an iterative etching technique until the nitride layer is exposed, each iterative etching step includes; using an isotropic etching technique to remove a portion of the oxide layer, the isotropic etching technique produces a byproduct that remains along a sidewall and a bottom of the trench, then using an anisotropic etching technique to remove the salt from the bottom of the trench, leaving salt on the sidewalls of the trench.
US09472411B1 Spalling using dissolvable release layer
A method of performing spalling of a semiconductor substrate in which a release layer is used between a handling substrate and a stressor layer. The release layer is removed using a liquid that does not damage the spalled semiconductor substrate.
US09472410B2 Pixelated capacitance controlled ESC
Implementations described herein provide a pixilated electrostatic chuck which enables both lateral and azimuthal tuning of the RF coupling between an electrostatic chuck and a substrate placed thereon. In one embodiment, the pixilated electrostatic chuck (ESC) may include a dielectric body having a workpiece support surface configured to accept a substrate thereon, one or more chucking electrodes disposed in the pixilated ESC, and a plurality of pixel electrodes. The plurality of pixel electrodes are switchable between a floating state and a grounded state, having variable capacitance to ground, or both. The pixel electrodes and the chucking electrodes form a circuit operable to electrostatically chuck the substrate to the workpiece support surface.
US09472407B2 Replacement metal gate FinFET
A method for fabricating a field effect transistor device includes depositing a hardmask over a semiconductor layer depositing a metallic alloy layer over the hardmask, defining a semiconductor fin, depositing a dummy gate stack material layer conformally on exposed portions of the fin, patterning a dummy gate stack by removing portions of the dummy gate stack material using an etching process that selectively removes exposed portions of the dummy gate stack without appreciably removing portions of the metallic alloy layer, removing exposed portions of the metallic alloy layer, forming spacers adjacent to the dummy gate stack, forming source and drain regions on exposed regions of the semiconductor fin, removing the dummy gate stack, removing exposed portions of the metallic alloy layer, and forming a gate stack conformally over exposed portions of the insulator layer and the semiconductor fin.
US09472403B2 Power semiconductor switch with plurality of trenches
A SiC JFET that includes a plurality of trenches formed in a SiC semiconductor body of one conductivity each trench having a region of another conductivity formed in the bottom and sidewalls thereof.
US09472401B2 Molybdenum disulfide film formation and transfer to a substrate
A method is provided for forming an unsupported MoS2 layer in an aqueous medium, the method comprising the steps of: providing an assembly of a Mo oxide layer on a Si substrate; annealing said assembly in presence of H2S at a temperature sufficient for forming a MoS2 layer; and contacting the annealed assembly with an aqueous medium. This unsupported MoS2 layer can then be transferred by dip-coating to another substrate such as a dielectric substrate.
US09472397B2 Method of manufacturing semiconductor device, substrate processing apparatus, and recording medium
A method of manufacturing a semiconductor device includes performing a cycle a predetermined number of times, the cycle including supplying a first precursor containing a specific element and a halogen group to form a first layer and supplying a second precursor containing the specific element and an amino group to modify the first layer into a second layer. A temperature of the substrate is set such that a ligand containing the amino group is separated from the specific element in the second precursor, the separated ligand reacts with the halogen group in the first layer to remove the halogen group from the first layer, the separated ligand is prevented from being bonded to the specific element in the first layer, and the specific element from which the ligand is separated in the second precursor is bonded to the specific element in the first layer.
US09472393B2 Method and apparatus for forming silicon oxide film
A silicon oxide film forming method includes: forming an amorphous silicon film, including: adsorbing an adsorbate containing silicon to a workpiece by supplying a source gas containing chlorine and silicon into a reaction chamber accommodating the workpiece, activating the source gas, and reacting the activated source gas with the workpiece; and removing chlorine contained in the adsorbate by supplying hydrogen gas into the reaction chamber and activating the hydrogen gas, and reacting the activated hydrogen gas with the adsorbate, wherein removing the chlorine is performed after adsorbing the adsorbate is performed, thereby forming the amorphous silicon film on the workpiece; and forming a silicon oxide film on the workpiece by supplying an oxidizing gas into the reaction chamber and oxidizing the amorphous silicon film, wherein forming the amorphous silicon film and forming the silicon oxide film are repeated in this order plural times.
US09472392B2 Step coverage dielectric
Silicon oxide is deposited with improved step coverage by first exposing a patterned substrate to a silicon-containing precursor and then to an oxygen-containing precursor or vice versa. Plasma excitation is used for both precursors. Exposing the precursors one-at-a-time avoids disproportionate deposition of silicon oxide near the opening of a high aspect ratio gap on a patterned substrate. The plasma-excited precursors exhibit a lower sticking coefficient and/or higher surface diffusion rate in regions already adsorbed and therefore end up depositing silicon oxide deep within the high aspect ratio gap to achieve the improvement in step coverage.
US09472391B2 Semiconductor device manufacturing method
A semiconductor device manufacturing method includes forming a thin film containing silicon, oxygen, carbon and a specified Group III or Group V element on a substrate by performing a cycle a predetermined number of times. The cycle includes: supplying a precursor gas containing silicon, carbon and a halogen element and having an Si—C bonding and a first catalytic gas to the substrate; supplying an oxidizing gas and a second catalytic gas to the substrate; and supplying a modifying gas containing the specified Group III or Group V element to the substrate.
US09472387B2 Systems and methods for identifying precursor ions from product ions using arbitrary transmission windowing
Ions are separated from a sample over time and filtered. The precursor ions produced at each step are fragmented. Resulting product ions are analyzed using a mass analyzer, producing a product ion spectrum for each step of the transmission window and a plurality of product ion spectra for the mass range for the each scan. The plurality of product ion spectra are received, producing a plurality of multi-scan product ion spectra. At least one product ion is selected from the plurality of multi-scan product ion spectra that is present at least two or more times in product ion spectra from each of two or more scans. A known separation profile of a precursor ion is fit to intensities from the at least one product ion in the plurality of multi-scan product ion spectra to reconstruct a separation profile of a precursor ion of the at least one product ion.
US09472385B2 RF power supply for a mass spectrometer
The present invention provides a radio frequency (RF) power supply in a mass spectrometer. The power supply provides an RF signal to electrodes of a storage device to create a trapping field. The RF field is usually collapsed prior to ion ejection. In an illustrative embodiment the RF power supply includes a RF signal supply; a coil arranged to receive the signal provided by the RF signal supply and to provide an output RF signal for supply to electrodes of an ion storage device; and a shunt including a switch operative to switch between a first open position and a second closed position in which the shunt shorts the coil output.
US09472384B2 Electronic device manufacturing method and sputtering method
An electronic device manufacturing method includes a first step of moving a substrate holder close to a first shield member and locating a first projecting portion formed on the first shield member and having a ring shape and a second projecting portion having a ring shape and formed on a second shield member installed on the surface of the substrate holder at the outer peripheral portion of a substrate at a position to engage with each other in a noncontact state, a second step of, after the first step, sputtering a target while maintaining the first projecting portion and the second projecting portion at the position to engage with each other in the noncontact state, and a third step of, after the second step, setting the first shield member in an open state and sputtering the target to perform deposition on the substrate.
US09472383B2 Copper or copper alloy target/copper alloy backing plate assembly
Provided is a copper or copper alloy target/copper alloy backing plate assembly in which the anti-eddy current characteristics and other characteristics required in a magnetron sputtering target are simultaneously pursued in a well balanced manner. This copper or copper alloy target/copper alloy backing plate assembly is used for magnetron sputtering, and the copper alloy backing plate is formed from low beryllium copper alloy or Cu—Ni—Si-based alloy. Further, with this copper or copper alloy target/copper alloy backing plate assembly, the copper alloy backing plate has electrical conductivity of 35 to 60% (IACS), and 0.2% proof stress of 400 to 850 MPa.
US09472379B2 Method of multiple zone symmetric gas injection for inductively coupled plasma
Implementations described herein inject feedstock gases into multiple zones of an inductively coupled plasma processing reactor with minimal or no effect on process skew. In one embodiment, an integrated gas and coil assembly is provided that includes an upper surface and a lower surface, a first RF field applicator coil bounded at the upper surface and the lower surface, a second RF field applicator coil circumscribed by the first RF field applicator coil and bounded at the upper surface and the lower surface and an RF shield disposed between the first and second RF field generator wherein the RF shield extends from the lower surface and past the upper surface. The RF shield may have at least one gas channel disposed therethrough.
US09472378B2 Multiple zone coil antenna with plural radial lobes
A low inductance coil antenna for a plasma reactor has multiple radial zones of plural conductor lobes extending radially from respective RF supply and ground rings.
US09472374B2 Testing assembly including a multiple degree of freedom stage
A multiple degree of freedom sample stage or testing assembly including a multiple degree of freedom sample stage. The multiple degree of freedom sample stage includes a plurality of stages including linear, and one or more of rotation or tilt stages configured to position a sample in a plurality of orientations for access or observation by multiple instruments in a clustered volume that confines movement of the multiple degree of freedom sample stage. The multiple degree of freedom sample stage includes one or more clamping assemblies to statically hold the sample in place throughout observation and with the application of force to the sample, for instance by a mechanical testing instrument. Further, the multiple degree of freedom sample stage includes one or more cross roller bearing assemblies that substantially eliminate mechanical tolerance between elements of one or more stages in directions orthogonal to a moving axis of the respective stages.
US09472370B2 Neutron generator having multiple extractors with independently selectable potentials
A radiation generator includes at least three extractor electrodes, with an ion source upstream of the at least three extractor electrodes to emit ions in a downstream direction toward the at least three extractor electrodes. There is a target downstream of the at least three extractor electrodes. The at least three extractor electrodes have independently selectable potentials so as to allow direction of an ion beam, formed from the ions, by the independently selectable potentials, toward different longitudinal and lateral regions of the target.
US09472368B2 Piezoelectronic switch device for RF applications
A piezoelectronic switch device for radio frequency (RF) applications includes a piezoelectric (PE) material layer and a piezoresistive (PR) material layer separated from one another by at least one electrode, wherein an electrical resistance of the PR material layer is dependent upon an applied voltage across the PE material layer by way of an applied pressure to the PR material layer by the PE material layer; and a conductive, high yield material (C-HYM) comprising a housing that surrounds the PE material layer, the PR material layer and the at least one electrode, the C-HYM configured to mechanically transmit a displacement of the PE material layer to the PR material layer such that applied voltage across the PE material layer causes an expansion thereof and an increase the applied pressure to the PR material layer, thereby causing a decrease in the electrical resistance of the PR material layer.
US09472363B2 Thermal protector
A thermal protector has superiority in current responsiveness or thermal responsiveness with a simple configuration that does not need a separate manufacturing step of incorporating a resistor. At a stage of press processing for cutting from an original material, a movable plate body part of a movable plate is partitioned into a narrow-width part and a wide-width part by a slim hole. The movable plate is assembled to a fixed conductor with columns of an insulator, a bimetal is assembled to the movable plate, the entire configuration is pressed down by a resinous block, and the entire fixing part is fixed by melting tips of the columns. The wide-width part serves as a normal movable plate, whereas the narrow-width part serves as a conductor in a normal state and as a resistor against an overcurrent.
US09472362B2 Switch
A rotation mechanism for a rotary switch and a method of operating a rotary switch are provided. The rotation mechanism includes a mechanism shaft for switching the switch between open and closed positions of the switch, a crank rotationally connected to the mechanism shaft, a spring connected to the crank, where the spring has a dead point between the open and closed positions of the switch, and a force transmission roll rotationally connected to the crank. The mechanism shaft, crank and force transmission roll have a common axis of rotation. There is a predetermined rotational free-play between the rotation of the mechanism shaft and the crank, and a predetermined rotational free-play between the rotation of the crank and the force transmission roll.
US09472360B2 Curable foam shims for buttons of electronic devices
Button assemblies using curable foam shims are disclosed. A button assembly may include a housing, a button positioned within the housing, and a curable foam shim positioned within the housing, the foam shim transformable between a compressible state having a first thickness, to a rigid state having a second thickness smaller than the first thickness. In this manner, the foam shim can be used to adaptively fill the interior of a button assembly by adapting to the dimensions of various components within the button assembly. In another example, a button assembly is formed using a foam shim by curing from a first state having a first thickness to a second state having a second thickness greater than the first thickness. In this manner, the foam shim can be used to adaptively fill the interior of a button assembly by adapting to the dimensions of various components within the button assembly.
US09472358B2 Assembling structure of electronic component and electrical junction box
An electronic component includes a rectangular parallelepiped main body portion and at least one terminal portion which is provided in the main body portion, wherein a housing member includes a first housing chamber which guides and accommodates the main body portion and a second housing chamber which accommodates and holds a terminal fitting, the first housing chamber is formed by surrounding with a frame-shaped wall portion uprightly raised from a bottom portion on every side, the second housing chamber is formed at an outside with the wall portion interposed therebetween, the terminal portion includes a base end and a fitting portion which extends from a protruding front end of the base end along a side surface of the main body portion while being separated from the side surface and is fitted to the terminal fitting.
US09472356B2 Tank-type vacuum circuit breaker
A tank-type vacuum circuit breaker includes: a pressure tank; an insulating frame that is detachably supported by a support member provided in the pressure tank using a coupling; a vacuum interrupter that is supported by the insulating frame and includes a stationary electrode and a moving electrode; a stationary-electrode side terminal that is connectably/disconnectably connected to a bushing-terminal side internal conductor; a moving-electrode side terminal that is connectably/disconnectably connected to a bushing-terminal side internal conductor; and an insulating rod, the inside end of which is detachably coupled to the moving electrode and the outside end of which is coupled to an opening/closing actuation mechanism that opens/closes the contacts of the stationary contact and moving contact. The vacuum interrupter, the stationary-electrode side terminal, the moving-electrode side terminal and the insulating frame are integrated into a unit, and the unit can be removed and mounted by disconnecting the connections and the couplings.
US09472353B2 Ultracapacitor with improved aging performance
An electric double layer capacitor comprises first and second electrodes, each comprising respective first and second carbon materials having distinct pore size distributions. A pore volume ratio of the first carbon material is greater than a pore volume ratio of the second carbon material. The pore volume ratio R is defined as R=V1/V, where V1 is a total volume of pores having a pore size of less than 1 nm, and V is a total volume of pores having a pore size greater than 1 nm.
US09472348B2 Method of producing conductive polymer particle dispersion, and method of producing electrolytic capacitor using said conductive polymer particle dispersion
A dispersion liquid including one of thiophene and derivatives thereof, a polyanion, and a solvent is prepared. Then, the dispersion liquid is mixed with an oxidizing agent so as to oxidatively polymerize the one of thiophene and derivatives thereof. During the oxidative polymerization, a temperature of the dispersion liquid is 35° C. or less and a dissolved oxygen concentration of the dispersion liquid is 7 ppm or less.
US09472344B2 Electronic component
An electronic component includes a multilayer capacitor and an interposer. The multilayer capacitor includes an element body and a pair of external electrodes. The interposer includes a substrate having first and second principal faces, a pair of first electrodes disposed on the first principal face, and a pair of second electrodes disposed on the second principal face so as to be separated from the pair of first electrodes in a first direction or in a second direction. Widths of the pair of external electrodes and the pair of first electrodes are smaller than a width of the element body. The element body has a first portion covered by the external electrode, and a pair of second portions located on both sides of the first portion. The pair of second portions are separated from the interposer and overlap the pair of second electrodes when viewed from a third direction.
US09472342B2 Leadless multi-layered ceramic capacitor stacks
A stacked MLCC capacitor is provided wherein the capacitor stack comprises multilayered ceramic capacitors wherein each multilayered ceramic capacitor comprises first electrodes and second electrodes in an alternating stack with a dielectric between each first electrode and each adjacent second electrode. The first electrodes terminate at a first side and the second electrodes second side. A first transient liquid phase sintering conductive layer is the first side and in electrical contact with each first electrode; and a second transient liquid phase sintering conductive layer is on the second side and in electrical contact with each second electrode.
US09472341B2 Method for manufacturing magnetic grain compact
A method for manufacturing a magnetic grain compact, includes: providing multiple metal grains constituted by soft magnetic alloy containing Fe, Si, and a metal element M that oxidizes more easily than Fe; compacting the metal grains; and forming oxide film formed on a surface of the metal grains, and forming first bonding parts where adjacent metal grains are directly contacted and bonded together, and second bonding parts where adjacent metal grains are bonded together via the oxide film formed around the entire surface of said adjacent metal grains other than the first bonding parts, by applying heat treatment to the compacted metal grains, thereby obtaining a magnetic grain compact.
US09472336B2 Power transmitting coil and wireless power transmitting apparatus
Disclosed herein are a power transmitting coil used to wirelessly transmit a power and a wireless power transmitting apparatus wirelessly transmitting a power using the power transmitting coil. The power transmitting coil includes at least one first coil mounted on a central portion of a core in which, when the power transmitting coil transmits a power, a current flows in a first direction; and at least one second coil disposed at an outer side of the first coil in which, when the power transmitting coil transmits a power, a current flows in a second direction opposite to the first direction. The wireless power transmitting apparatus wirelessly transmits the power using the power transmitting coil including the first coil and the second coil.
US09472334B2 Transformer
A transformer comprises first winding portions (101, 102) constituting a first foil winding and second winding portions (103, 104) constituting a second foil winding having a substantially same magnetic axis as the first foil winding. The first and second winding portions are interleaved in directions substantially perpendicular to the magnetic axis so as to reduce the leakage inductances of the first and second foil windings. The first winding portions are electrically interconnected so that at least one end-portion of each first winding portion is split to constitute two strips (105a, 105b) folded to mutually opposite directions substantially parallel with the magnetic axis, and ends of the strips of different first winding portions are interconnected to constitute connection bridges over a particular one of the second winding portions located between these first winding portions. The second winding portions are electrically interconnected in the corresponding way to constitute the second foil winding.
US09472329B2 High leakage transformers with tape wound cores
A high leakage inductance transformer core device, and method of forming same, that has a core made of tape wound material, at least one set of concentric primary and secondary windings, and at least one flux shunt between the primary and secondary windings which is also made of tape wound material. The transformer core and flux shunts are arranged so that the transformer has a low external magnetic field, and substantially no excess core losses due to principal core flux flowing from one part of the core structure to another through the broad surface of the core tape.
US09472326B2 Semiconductor ceramic composition and PTC thermistor
A semiconductor ceramic composition with small resistivity at room temperature and large temperature coefficient of resistance is provided; the composition is represented by formula, (Ba1-x-y-wBixAyREw)m(Ti1-zTMz)O3  (1), (wherein, A is at least one element from Na or K, RE is at least one element from the group consisting of Y, La, Ce, Pr, Nd, Sm, Gd, Dy and Er, TM is at least one element from the group consisting of V, Nb and Ta, and w, x, y, z (each in mol) and the mole ratio m of Ba site to Ti site satisfy the following in equations, 0.007≦x≦0.125  (2) x
US09472321B2 Cable comprising indicator material for detecting damage control
The invention relates to a cable with a sheath and an indication material that in case of damaging of the sheath at least partially escapes from the cable.
US09472318B2 Wire harness
Provided is a wire harness having a shielding structure that can achieve a required shielding effect while sufficiently meeting the requirements of weight reduction and cost reduction. The wire harness includes a wire group constituted by a plurality of wires and a retaining member that surrounds the wire group such that the wire group is retained in the form of a bundle, wherein the wire group is configured to include a first wire composed of a linear conductor that is located toward the center of the wire group, a tube-shaped wire sheathing that surrounds the first wire, and a second wire and a third wire that are composed of an opposing pair of split tube-shaped conductors that are insulated from each other with the first wire and the wire sheathing being interposed therebetween.
US09472312B2 Method for precipitating one or more solutes
The invention deals with a method for precipitating at least one solute in a reactor comprising: a) a step in which a first liquid phase comprising the solute and a second liquid phase comprising a solute precipitation reagent are brought into contact in co-current in a reactor, as a result of which an emulsion mix is obtained comprising precipitate particles in suspension, and a third liquid phase forming a dispersing phase for said emulsion mix; and b) a step in which the mix mentioned in step a) is fluidized by the third phase.
US09472311B2 Method for prediction of light water reactor fuel defects using a fuel condition index
A method to assess light water reactor fuel integrity is presented having the steps of granting access in a nuclear reactor fuel pool to at least one of a discharged fuel rod and a nuclear fuel assembly, calculating an operating flux for the fuel rod, measuring a thickness of CRUD on the fuel rod, measuring a thickness of oxide on the fuel rod, calculating a maximized flux for the at least one fuel rod for a position of the one fuel rod in a nuclear reactor, calculating a maximized deposit for the fuel rod, calculating a maximized oxide thickness for the fuel rod, calculating a fuel condition index of the fuel rod, comparing the fuel condition index to an index constant, and removing the fuel rod from operation when the fuel condition index is greater than the index constant.
US09472310B2 Coated nuclear reactor fuel particles
A method is described for producing nuclear fuel products, including the steps of receiving metallic or intermetallic uranium-based fuel particle cores, providing at least one physical vapour deposited coating layer surrounding the fuel particle core and embedding the nuclear fuel particles in a matrix so as to form a powder mixture of matrix material and coated fuel particles. The at least one physical vapour deposited coating layer may include inhibitors of inhibiting, stabilizing and/or reducing interaction between metallic and intermetallic uranium-based fuel particles cores and the matrix wherein the fuel particles typically may be embedded. The deposited coating layer may include neutron poisons.
US09472308B1 Semiconductor memory device and test method thereof
A semiconductor memory device includes: a normal cell region having normal cells; a redundancy cell region having first redundancy cells replaced with repair target cells of the normal cells and second redundancy cells which are not replaced with the repair target cells; a fuse unit suitable for programming repair information including replacement information and one of state information and a repair address of the repair target cells; a boot-up unit suitable for outputting the repair information programmed in the fuse unit, resetting the repair information in response to a test control signal, and outputting the reset repair information; an information update unit suitable for generating the test control signal; a test control unit suitable for generating a test address during a redundancy test operation; and a test unit suitable for selectively testing the second redundancy cells in response to the test address.
US09472304B2 Configuring signal-processing systems
A configurable signal-processing circuit may provide a plurality of selectable signal-processing operations. The configurable signal-processing circuit may have a configuration circuit that provides a configuration code that selects a first signal-processing operation from the plurality of selectable signal-processing operations based on a timing pattern for evaluating an input signal and outputting an output signal.
US09472302B2 Redundant fuse coding
In accordance with some embodiments, fuse information may be written into a fuse array in a way that provides sufficient redundancy, making it harder for malicious parties to attack the fuse array.
US09472299B2 Methods and systems for mitigating memory drift
A memory cell is read by measuring a parameter associated with the memory cell with a first resolution to determine a value stored in the memory cell. The parameter is also measured with a second resolution that is finer than the first resolution. The memory cell is reprogrammed to mitigate an offset between the parameter as measured with the second resolution and the parameter as measured with the first resolution.
US09472298B1 Dynamic read valley search in non-volatile memory
Determining dynamic read levels for memory cells is disclosed. A group of memory cells may be read at a pair of reference levels. Results of reading the group at the pair of reference levels are compared while the group is read at a different reference level. By comparing the results of reading the group at the pair of reference levels while reading the group at a different reference level, time is saved. Note that the reading and comparing can be repeated for other pairs of reference levels. The storage device may determine an adjusted read level based on the comparisons of the results for the different pairs of reference levels. The memory cells may be read at a set of reference levels. A voltage on a word line is not back down to ground between the reads in one aspect, which saves considerable time.
US09472293B2 Method for driving semiconductor device and semiconductor device
To read multilevel data from a memory cell having a transistor using silicon and a transistor using an oxide semiconductor, without switching a signal for reading the multilevel data in accordance with the number of the levels of the multilevel data. The potential of the bit line is precharged, the electrical charge of the bit line is discharged via a transistor for writing data, and the potential of the bit line which is changed by the discharging is read as multilevel data. With such a structure, the potential corresponding to data held in a gate of the transistor can be read by only one-time switching of a signal for reading data.
US09472290B2 Semiconductor device and method of erasing the same
A semiconductor device and a method of operating the same are provided. The method includes performing a multi-plane erase operation on selected planes; determining that the multi-plane erase operation has failed when a number of erase loops reaches a maximum number without successful completion of the multi-plane erase operation; determining whether there are passed planes amongst the selected planes; and performing a soft program operation on the passed planes.
US09472281B1 Non-volatile memory with adjustable cell bit shape
Embodiments of the present disclosure generally relate to non-volatile memory and, in particular, non-volatile memory with adjustable cell bit shapes. In one embodiment, an adjustable memory cell is provided. The memory cell generally includes a gate electrode, at least one recording layer and a channel layer. The channel layer generally is capable of supporting a depletion region and is disposed between the gate electrode and the at least one recording layer. In this embodiment, upon activating the gate, the channel layer may be depleted and current initially flowing through the channel may be steered through the at least one recording layer.
US09472277B2 Non-volatile memory device
According to one embodiment, a non-volatile memory device includes: first memory cell regions including first wirings extending in a first direction, second wirings extending in a second direction crossing the first direction, and first memory cells provided between the first wirings and the second wirings and being capable of changing resistance state; and second memory cell regions including third wirings extending in the first direction, fourth wirings extending in the second direction crossing the first direction, and second memory cells provided between the third wirings and the fourth wirings and being capable of changing resistance state, the second memory cell region having a smaller area than the first memory cell region in top view.
US09472275B2 Method of operating memory device using different read conditions
A memory device and a method of operating the memory device are provided for performing a read-retry operation. The method of operating the memory device includes starting a read-retry mode, reading data of multiple cell regions using different read conditions, and setting a final read condition for the cell regions according to results of data determination operations on data read from the cell regions.
US09472271B2 Method of programming a phase change memory and phase change memory device
A method for pre-programming a matrix of phase-change memory cells, including a phase-change material positioned between two conducting electrodes and able to be reversely electrically modified so as to vary the resistivity of the memory cell. A dielectric layer is provided with the memory cell having an original resistive state at the end of the memory cell production process. A pre-programming of the matrix is executed prior to mounting a component containing the matrix on a support. A breakdown voltage is applied to a selection of memory cells so that, for each one of the selected cells, the layer of the dielectric material breaks down to bring the cell from the original resistive state to a second resistive state.
US09472259B2 Semiconductor memory device with dummy memory mat and refresh operating method thereof
A semiconductor memory device includes a plurality of normal memory mats, one or more of which includes a redundancy word line, a dummy memory mat suitable for performing an operation with an edge memory mat as a pair during an active operation, wherein the edge memory mat is one among the plurality of normal memory mats disposed at an edge, and a refresh control section suitable for controlling refresh operations for the plurality of normal memory mats and the dummy memory mat, and restricting activation of the redundancy word line during a refresh operation for the edge memory mat.
US09472256B1 Magnetic memory having two transistors and two magnetic tunnel junctions per memory cell
Circuits and methods for driving generating multiple word line voltages used for writing to two-transistor two-magnetic tunnel junction (2T2MTJ) spin-torque magnetic random access memory (MRAM) cells. Some embodiments include auto-booting isolated word lines using common lines such as bit and source lines that are capacitively coupled to the word lines. Different memory architectures for 2T2MTJ memory arrays are also presented that include read/write circuits and word line drivers.
US09472252B2 Apparatuses and methods for improving retention performance of hierarchical digit lines
Apparatuses and methods for improving retention performance of hierarchical digit lines are disclosed herein. An example apparatus may include a first digit line portion and a second digit line portion. The apparatus may further include a first selector configured to selectively couple the first digit line portion to the second digit line portion based, at least in part, on a first control signal. The apparatus may further include a second selector configured to selectively couple the second digit line portion to a voltage based, at least in part, on a second control signal.
US09472250B1 Semiconductor device and operating method thereof
A semiconductor device including an input unit suitable for transferring external command signals provided from an external device to an internal device and a detection unit suitable for detecting a predetermined command signal among the external command signals, and restricting the transfer of the detected command signal.
US09472243B2 Systems and methods for stacked semiconductor memory devices
Systems and methods are provided for stacked semiconductor memory devices. The stacked semiconductor memory devices can include a nonvolatile memory controller, a number of nonvolatile memory dies arranged in a stacked configuration, and a package substrate. The memory controller and the memory dies can be coupled to each other with vias that extend through the package substrate. A vertical interconnect process may be used to electrically connect the nonvolatile memory dies to each other, as well as other system components. The memory controller may be flip-chip bonded to external circuitry, such as another semiconductor device or a printed circuit board.
US09472242B1 Hard disk drive enclosure base with feed through flexure design and accompanying flexure
A storage base having an interior side and an exterior side is described. The storage drive base includes a slotted aperature, a flexible circuit and a sealing-adhesive barrier. The slotted aperature passes through the storage drive base from the interior side to the exterior side. The flexible circuit has a first end and a second end. The first end of the flexible circuit is installed in the slotted aperture and aligned so that the first end extends along an interior surface of the storage drive base in a location proximal to the slotted aperture. The sealing-adhesive barrier is applied between edges of the slotted aperture and the flexible circuit to form a hermetic seal between the exterior side and the interior side of the storage drive base.
US09472235B2 Bulk data erase utilizing an encryption technique
A system and a computer program product are disclosed for eliminating access to data on removable storage media of a removable storage media cartridge. The system comprises a computer configured to send to a data storage drive a command to eliminate access to data on a removable storage media cartridge, and send to the data storage drive a command to shred at least one key in response to the command, where shredding the at least one key eliminates access to the data on the removable storage media cartridge. A determination to eliminate access to the data on the removable storage media cartridge is based on a number of read and/or write errors encountered for the removable storage media cartridge.
US09472231B2 Optical information recording medium and recording/reproducing device
An optical information recording medium has: a recording layer; a super-resolution functional layer; and a protective layer. Letting n be the refractive index of the protective layer with respect to a laser beam focused by a focusing optical system, λ, be the wavelength of the laser beam, and ds be the depth of recording marks, when the super-resolution functional layer is irradiated by the focused laser beam, it forms a focused light spot including central light that irradiates the recording marks and peripheral light that irradiates a region outside the central light. The optical information recording medium further satisfies either the condition that the central light has a positive phase difference with respect to the peripheral light and ds>λ/4n, or the condition that the central light has a negative phase difference with respect to the peripheral light and ds<λ/4n.
US09472229B1 Adaptive laser output control in a HAMR device
A current temperature of a data storage device having a heat assisted recording (HAMR) device is measured while in idle. A threshold laser diode power output of the HAMR device is calculated at the current temperature when there is a change between a previous temperature and the current temperature. A new laser diode current that produced the calculated threshold laser diode power output is applied to the HAMR device when there is a change between the currently applied laser diode current and the new laser diode current.
US09472227B2 Perpendicular magnetic recording media and methods for producing the same
[Problem] An object is to provide a perpendicular magnetic recording medium that can realize both improvement in crystal orientation and refinement of crystal grain size and can achieve a higher recording density and a higher SN ratio, and a method of manufacturing the same.[Solution] A perpendicular magnetic recording medium 100 of the present invention is a perpendicular magnetic recording medium 100 having a base plate 100, and a laminate film including a first ground layer 150a provided on the base plate 100, a second ground layer 150b provided on the first ground layer 150a, and a main recording layer 160 provided on the second ground layer 150b and containing a magnetic material having a granular structure, wherein the magnetic material which constitutes the main recording layer 160 contains a CoCrPt alloy, and a material which constitutes the second ground layer 150b contains an Ru—Co oxide alloy.
US09472224B2 Electrically removable heater for a thermally actuatable thermal asperity sensor
An apparatus comprising a writer, a reader, and a sensor configured to at least sense thermal asperities of a magnetic storage medium. The apparatus includes a writer heater configured to thermally actuate the writer, a reader heater configured to thermally actuate the reader, and a sensor heater configured to thermally actuate the sensor. The thermally actuated sensor is configured to detect thermal asperities arising from the magnetic storage medium during a topographical survey of the medium. The sensor heater is configured to be rendered inoperable subsequent to the survey in response to receiving a predetermined signal while the writer and the reader heaters remain operable.
US09472223B1 Media certification with different recording widths
Systems and methods are disclosed to perform media certification with different recording widths, in accordance with certain embodiments of the present disclosure. An apparatus may be configured to record data using at least two selectable recording widths. In some embodiments, the recording width may be controlled by adjusting a laser current supplied to a laser emitter of a heat assisted magnetic recording (HAMR) device. Certification data may be recorded to a storage medium at a selected recording width, with wider widths reducing testing time and narrower widths reducing wear on write heads. In some embodiments, an apparatus may be configured to record servo data using a first recording width to a storage medium, and record certification data using a second recording width. The drive may record servo data and certification during a first disc rotation, and may record servo data and read certification data during a second disc rotation.
US09472220B1 Dual waveguide near field transducer for heat assisted magnetic recording
A near field transducer (NFT) for heat assisted magnetic recording (HAMR) having a dual waveguide excitation system located adjacent to opposite sides of a plasmonic antenna. The light to one of the waveguides can be passed through a phase shifter so that its electric field is 180 degrees out of phase with that of the other waveguide. In this way, the energy from each of the waveguides can be delivered to the plasmonic antenna in an additive manner while heat-sinking schemes can be implemented in the orthogonal direction for greatly improving the optical efficiency and thermal stability of the NFT.
US09472219B1 Data storage device calibrating parameter for heat assisted magnetic recording
A data storage device is disclosed comprising a head actuated over a disk, wherein the head comprises a laser configured to heat the disk while writing data to the disk. A write power for the laser is calibrated, wherein the write power is applied to the laser while writing user data to the disk. A calibration power is applied to the laser for a first interval, wherein the calibration power is high enough to cause the head to contact the disk if applied for a second interval longer than the first interval. While applying the calibration power to the laser, test data is written to the disk during at least part of the first interval. The test data is read from the disk to generate a read signal, and a metric is generated based on the read signal.
US09472217B2 Magnetic write head characterization with nano-meter resolution using nitrogen vacancy color centers
A crystal film with one or more nitrogen vacancy centers is placed in close proximity to a recording head. A magnetic field or heat produced by the recording head as well as excitation illumination and an excitation field is applied to the crystal film. The magnetic field produced by the recording head, the heat produced by a thermal device on the recording head, and/or the excitation field may be varied. A confocal microscope or wide-field microscope optically detects a decrease in a spin dependent photoluminescence in response to the magnetic field or heat, excitation field and excitation illumination caused by electron spin resonance (ESR) of the at least one nitrogen vacancy center to measure Optically Detected Spin Resonance (ODMR). A characteristic of the recording head is determined using the ODMR.
US09472216B1 Differential dual free layer magnetic reader
A magnetic read apparatus has an air-bearing surface (ABS) and includes a differential read sensor, side bias structure(s) and rear magnetic bias structure(s). The differential read sensor includes first and second free layers and a nonmagnetic spacer layer between the first and second free layers in a down-track direction. The side bias structure(s) are adjacent to the first and second free layers in a cross-track direction perpendicular to the down-track direction. The side bias structure(s) magnetically bias the first and second free layers in the cross-track direction. The differential read sensor is between the ABS and the rear magnetic bias structure(s). The rear magnetic bias structure(s) provide a first magnetic bias for the first free layer in a first direction along a stripe height direction perpendicular to the ABS and provide a second magnetic bias for the second free layer in a second direction opposite to the first direction.
US09472214B1 Reader side shield
A magnetoresistive (MR) sensor shield shields against both down track and cross-track interference. The shield can be formed in a single deposition step. In one implementation of the disclosed technology, a “tail” portion of the shield is eliminated by including a non-magnetic material adjacent to opposite sides of a middle portion of the sensor stack.
US09472213B2 Magnetic recording head having protected reader sensors and near zero recessed write poles
An apparatus according to one embodiment includes a module having both read and write transducers positioned towards a media facing side of the module, wherein the read and write transducers are selected from a group consisting of piggyback read-write transducers, merged read-write transducers, interleaved read and write transducers, and an array of write transducers. The write transducers include write poles having media facing sides with negative, zero or near-zero recession from a plane extending along the media facing side of a substrate of the module. The read transducers each have at least one shield. A media facing side of the at least one shield is more recessed from the plane than the write poles.
US09472208B2 Method and device for voice activity detection
In accordance with an example embodiment of the present invention, disclosed is a method and an apparatus for voice activity detection (VAD). The VAD comprises creating a signal indicative of a primary VAD decision and determining hangover addition. The determination on hangover addition is made in dependence of a short term activity measure and/or a long term activity measure. A signal indicative of a final VAD decision is then created.
US09472204B2 Apparatus and method for eliminating noise, sound recognition apparatus using the apparatus and vehicle equipped with the sound recognition apparatus
An apparatus for eliminating noise includes: a gain acquisition unit that determines a gain and a correction value of the gain using a signal to noise ratio (SNR) of an input signal; and a gain application unit that acquires an output signal corresponding to the input signal using the determined gain and the determined correction value, wherein the output signal includes an input signal of which noise is eliminated and an input signal of which noise is not eliminated, and a proportion of the input signal of which noise is eliminated and a proportion of the input signal of which noise is not eliminated are determined according to the determined correction value.
US09472203B1 Clock synchronization for multichannel system
An acoustic echo cancellation (AEC) system that detects and compensates for differences in sample rates between the AEC system and a set of wireless speakers based on a search-based trial-and-error technique. The system individually determines a frequency offset for each microphone-speaker pair using an iterative process, determining an echo-return loss enhancement (ERLE) value for each offset that is tried, and selecting the frequency offset associated with the largest ERLE value.
US09472202B2 Method of and apparatus for evaluating intelligibility of a degraded speech signal
The present invention relates to a method of evaluating intelligibility of a degraded speech signal received from an audio transmission system conveying a reference speech signal. The method comprises sampling said signals into reference and degraded signal frames, and forming frame pairs by associating reference and degraded signal frames with each other. For each frame pair a difference function representing disturbance is provided, which is then compensated for specific disturbance types for providing a disturbance density function. Based on the density function of a plurality of frame pairs, an overall quality parameter is determined. The method provides for compensating the overall quality parameter for the effect that the assessment of intelligibility of CVC words is dominated by the intelligibility of consonants.
US09472201B1 Speaker localization by means of tactile input
A system can receive a gesture from a user and configure a microphone system based on the received gesture to be more sensitive in the direction of a user from a device. The gesture can detected by a sensor and can be a touch input, input from a camera and a depth sensor and the like. The microphone system can include a microphone that can be electronically or mechanically steerable, or both. Acoustic signals received from the direction of the user and from other directions can be used in conjunction with an automatic speech recognition system to detect and process a command from the user.
US09472196B1 Developer voice actions system
Methods, systems, and apparatus for receiving data identifying an application and a voice command trigger term, validating the received data, inducting the received data to generate an intent that specifies the application, the voice command trigger term, and one or more other voice command trigger terms that are determined based at least on the voice command trigger term, and storing the intent at a contextual intent database, wherein the contextual intent database comprises one or more other intents.
US09472193B2 Speech dialogue control method
A cloud server extracts voiceprint data from voice data of a user, and distinguishes the user. The cloud server identifies a task which the user instructs, from the voice data of the user. If contexts required to execute the task have not been amassed, the cloud server registers the distinguished user as a task owner, and notifies the user with a reply sentence to cause the user to speak the required context. If the voiceprint data of the voice data which the user has uttered matches the voiceprint data of the user A, and all required contexts are amassed, the cloud server causes a device to execute the task.
US09472189B2 Language processing method and integrated circuit
A parse unit parses an input sequence of token elements for an input string, wherein each token element contains a token and/or at least one corresponding token classifier. In a first mode the parse unit applies regular production rules on the token elements and on multi-token classifiers for phrases obtained from the token classifiers. If the first mode parsing does not result in a multi-token classifier encompassing all tokens of the input string, a control unit controls the parse unit to parse the input sequence in a second mode that applies both the regular and artificial production rules. A rule generator unit generates the artificial production rules based on the input sequence and/or intermediate results of the parsing. The parser unit provides a complete parse tree for ungrammatical sentences and a solution where the regular production rules do not cover the complete grammar of the respective natural language.
US09472187B2 Acoustic model training corpus selection
The present disclosure relates to training a speech recognition system. One example method includes receiving a collection of speech data items, wherein each speech data item corresponds to an utterance that was previously submitted for transcription by a production speech recognizer. The production speech recognizer uses initial production speech recognizer components in generating transcriptions of speech data items. A transcription for each speech data item is generated using an offline speech recognizer, and the offline speech recognizer components are configured to improve speech recognition accuracy in comparison with the initial production speech recognizer components. The updated production speech recognizer components are trained for the production speech recognizer using a selected subset of the transcriptions of the speech data items generated by the offline speech recognizer. An updated production speech recognizer component is provided to the production speech recognizer for use in transcribing subsequently received speech data items.
US09472186B1 Automated training of a user audio profile using transcribed medical record recordings
An automated system to build a user audio profile for a natural or continuous language speech to text dictation/transcription system is provided. The system uses previously recorded audio files that may have been already transcribed. The previously recorded audio file is split into a plurality of smaller audio files of about 15 seconds in length. The plurality of smaller audio files are matched to the transcribed text (e.g., small text files) or the smaller audio files are transcribed. All, some, or a selection of the small audio files and the small text files are linked as a training pair. The training pair may be edited in certain embodiments herein, both the text and the audio. The training pairs are submitted to the server to build the initial user audio profile.
US09472183B2 System and method for customized prompting
A method for providing an audible prompt to a user within a vehicle. The method includes retrieving one or more data files from a memory device. The data files define certain characteristics of an audio prompt. The method also includes creating the audio prompt from the data files and outputting the audio prompt as an audio signal.
US09472182B2 Voice font speaker and prosody interpolation
Multi-voice font interpolation is provided. A multi-voice font interpolation engine allows the production of computer generated speech with a wide variety of speaker characteristics and/or prosody by interpolating speaker characteristics and prosody from existing fonts. Using prediction models from multiple voice fonts, the multi-voice font interpolation engine predicts values for the parameters that influence speaker characteristics and/or prosody for the phoneme sequence obtained from the text to spoken. For each parameter, additional parameter values are generated by a weighted interpolation from the predicted values. Modifying an existing voice font with the interpolated parameters changes the style and/or emotion of the speech while retaining the base sound qualities of the original voice. The multi-voice font interpolation engine allows the speaker characteristics and/or prosody to be transplanted from one voice font to another or entirely new speaker characteristics and/or prosody to be generated for an existing voice font.
US09472180B2 Headset and a method for audio signal processing
A headset and a method configured to process audio signals from multiple microphones, comprising: a first pair of microphones (101,102) outputting a first pair of microphone signals and a second pair of microphones (103, 104) outputting a second pair of microphone signals; a first near-field beamformer (105) and a second near-field beamformer (106) each configured to receive a pair of microphone signals and adapt the spatial sensitivity of a respective pair of microphones as measured in a respective beamformed signal (XL; XR) output from a respective beamformer (105; 106); wherein the spatial sensitivity is adapted to suppress noise relative to a desired signal; a third beamformer (107) configured to dynamically combine the signals (XL; XR) output from the first beamformer (105) and the second beamformer (106) into a combined signal (XC); wherein the signals are combined such that signal energy in the combined signal is minimized while a desired signal is preserved; and a noise reduction unit (109) configured to process the combined signal (XC) from the third beamformer (107) and output the combined signal such that noise is reduced.
US09472176B2 Performance recording system, performance recording method, and musical instrument
A musical instrument includes: an operation section which is configured to accept a playing operation; a generation section which is configured to generate performance information representative of the accepted playing operation; a detection section which is configured to detect a portable terminal; and a control section which is configured to start, when the portable terminal is detected, processing of recording at least one of the performance information generated by the generation section and a video obtained by shooting a scene where the playing operation is performed, into at least one of the musical instrument and the portable terminal.
US09472175B2 Drum head and drum
A drum head includes a skin having an inner skin and an outer skin formed integrally with an outer edge of the inner skin. The inner skin has a plurality of openings arranged in a circumferential direction of the inner skin. An outline of each of the plurality of openings has an inner end portion in a radial direction of the skin in plan view, and the inner end portion protrudes and tapers inward in the radial direction.
US09472174B2 Drum pedal with interlocking features
Drum pedal assemblies are disclosed which can include one or more adjustment feature and/or interlocking feature. Adjustment features which can be included in embodiments of the invention can include spring tension adjustment features, pedal incline adjustment features, lever length adjustment features, and/or beater stem angle adjustment features. Drum pedal assemblies are also disclosed which can include slot-and-tab connections between assembly pieces, which can reduce or eliminate certain undesired pedal movements.
US09472167B2 Video capture through hardware
Activating a screen capture tool in a display adapter to capture information on a display. An operating system sends a command to the display adapter to initiate the capture of information from the graphical user interface of a display. The display adapter captures the information on the graphical user interface of the display. The information may be stored by the display adapter to a storage device that may be connected to the display adapter. The display is monitored for additional changes. Any changes that occur to the information on areas of the display may be captured and stored to the storage device. The operating system may enable the display adapter to retrieve the information stored in the storage device and/or play back the information retrieved to the display.
US09472165B2 Method and system for achieving moving synchronization in remote control and computer storage medium
The present disclosure relates to a method for achieving moving synchronization in remote control, which includes: obtaining a remote control instruction, and extracting a target speed and a remote moment from the remote control instruction; obtaining a local moving state of a controlled object, the local moving state including a local speed and a local moment of the controlled object; calculating a delay time according to the remote control moment and the local moment; and moving the controlled object according to the delay time, the target speed, the local speed and a preset synchronization time. In addition, also provided is a system for achieving moving synchronization in remote control and a computer storage medium. The aforementioned method and system for achieving moving synchronization in remote control and the computer storage medium enable the moving synchronization effect to be smoother.
US09472164B2 Display apparatus light emission control method and display apparatus
A method controls a display that includes a display portion, a scanner, and a driver. The display portion includes light emitting elements arranged in a matrix form. The scanner is connected to common lines each of which is connected to corresponding elements that are arranged in a corresponding row. The scanner applies a voltage to a selected common line. The driver is connected to driving lines each of which is connected to corresponding elements that are arranged in a corresponding column. The driver activates selected elements. The method controls the display whereby displaying an image in each cycle including frames. The voltage is applied to the selected one of the common lines in a lighting frame in which the light emitting elements are driven in one cycle. The scanner is prevented from applying the voltage in a non-lighting frame in which the elements are not driven in the one cycle.
US09472161B1 Customizing virtual assets
Customizing virtual assets is disclosed, including: transforming each of a plurality of initially identical copies of a virtual asset or a portion thereof to isolate a feature of the virtual asset or portion thereof; and enabling the isolated feature to be changed by a user in at least one of the transformed copies. In some embodiments, customizing virtual assets includes: receiving a three-dimensional model associated with the virtual asset; receiving an indication to save a two-dimensional virtual asset based on the 3D model with a 2D image wrapped on it; and using the 3D model with the 2D image wrapped on it to generate the 2D virtual asset.
US09472159B2 Method and apparatus for annotating point of interest information
An approach is provided for annotating point of interest information to structures. One or more representations of at least one structure are determined. One or more partitions of the at least one structure is determined based, at least in part, on one or more features of the one or more representations. One or more points of interest associated with the at least one structure are determined. One or more points of interest are determined to be rendered for presentation based, at least in part, on the one or more partitions.
US09472158B2 Image data correction for VCOM error
Systems and methods are provided for adjusting and displaying image data to account for variable common voltage error across separate common electrode sub-plates. The image data may be adjusted based on a common mode common voltage error on a common voltage line coupled to more than one different common electrode sub-plate. Each common electrode sub-plate may carry a common voltage that varies depending on values of the image data programmed to pixels associated with that common electrode sub-plate.
US09472157B2 Liquid crystal display device
A device according to an embodiment includes an array substrate including electrodes corresponding to pixels arranged in a matrix, a color filter substrate opposed to the array substrate and including color filters corresponding to the pixels, a liquid crystal layer provided between the substrates, a backlight, and a controller which controls the substrates and the backlight. The pixels are configured to each have a parallelogrammatic shape elongated in a lateral direction, such that identical colors are arranged in the lateral direction, and different colors are arranged in a vertical direction. Pixels neighboring in the lateral direction are in line-symmetry with respect to a center line of the neighboring pixels. Liquid crystal molecules have negative dielectric constant anisotropy, and rotate horizontally relative to a substrate plane in a direction of the line-symmetry with respect to the center line when the voltage is applied to the electrodes of the neighboring pixels.
US09472152B2 Circuit for driving liquid crystal display
A circuit for driving a liquid crystal display includes a high selection unit turned on by a high selection signal, a low selection unit turned on by a low selection signal and transferring a low data signal to one side of the first storage capacitor, a high transfer unit connected to one side of the first storage capacitor, turned on by a high transfer signal and transferring voltage, a low transfer unit connected to one side of the first storage capacitor, turned on by a low transfer signal and transferring the voltage stored at one side of the first storage capacitor to one side of the liquid crystal capacitor, and a reset unit connected to one side of the liquid crystal capacitor, turned on by a reset signal and transferring a center voltage to one side of the liquid crystal capacitor.
US09472149B2 Display apparatus
A display apparatus includes a display panel having a first liquid crystal layer, a timing controller that converts image signals to have gray scales corresponding to a first reference value, and compensates the converted image signals to over-drive the first liquid crystal layer, the first reference value being a product of a refractive index anisotropy and a thickness of the first liquid crystal layer, a first driver that converts the compensated image signals to voltages that drive the first liquid crystal layer, a liquid crystal lens panel including a second liquid crystal layer, a liquid crystal lens controller that generates lens signals corresponding to a second reference value defined by a product of a refractive index anisotropy and a second thickness of the second liquid crystal layer, and a second driver that convert the lens signals to voltages that drive the second liquid crystal layer.
US09472148B2 Liquid crystal display device having gate sharing structure and method of driving the same
The present invention provides a liquid crystal display device including gate lines extending on a substrate; data lines crossing the gate lines to define a plurality of pixels; a thin film transistor in each pixel; and a liquid crystal capacitor in each pixel region, an electrode of the liquid crystal capacitor is connected to the thin film transistor, wherein the thin film transistors of a (2a−1)th pixel and a (2a)th pixel in a (2b)th pixel column share a (2a)th gate line, and the thin film transistors in a (2a)th pixel and a (2a+1)th pixel in a (2b+1)th pixel column share a (2b+1)th gate line, and wherein each of a and b is a positive integer.
US09472147B2 Display apparatus
A display device includes a display panel, a timing controller, a gate driver, and a data driver. The display panel includes a display area for displaying an image and a non-display area adjacent to one side of the display area. The display area includes gate lines, data lines, gate dummy lines, a data contact portion, and pixels. The data lines cross and are isolated from at least a part of the gate lines. The gate dummy lines are parallel with and are spaced from the gate lines. The data contact portion couples the gate dummy lines and the data lines at one side of a second direction perpendicular to the first direction.
US09472142B2 Display assembly and LCD device
A liquid crystal display (LCD) device includes a first LCD panel and a second LCD panel. The first LCD panel is arranged on a backlight source, and is the black mode, the second LCD panel is the white mode. A response time of the first LCD panel changing from the black mode to the white mode is less than a response time of the second LCD panel changing from the black mode to the white mode, and a response time of the first LCD panel changing from the white mode to the black mode is longer than a response time of the second LCD panel changing from the white mode to the black mode.
US09472141B2 Display apparatus and control method thereof
A display apparatus according to the present invention includes: a backlight; a displaying unit configured to display an image on a screen by allowing the light from the backlight to be transmitted therethrough; a first measuring unit provided on a light-emitting surface of the backlight, to detect the brightness on the light-emitting surface; a correcting unit configured to correct the detection brightness which is the brightness detected by the first measuring unit; and a controlling unit configured to control the light emission brightness of the backlight. The correcting unit reduces the detection brightness by a greater reduction amount, when the image displayed in a predetermined area corresponding to a position where the first measuring unit is provided is dark, than when the image displayed in the predetermined area is bright.
US09472140B2 Drive circuit, optoelectronic device, electronic device, and drive method
A device includes pixel circuits arranged in columns and rows, n data lines (n being an integer of 2 or more) for each column, gate lines supplied with scan signals, and light-emitting control lines supplied with light-emitting control signals. The pixel circuits are divided into n groups of rows, each group of rows being exclusively connected to a corresponding data line. Each pixel circuit includes a write control transistor to control writing a data voltage in response to a scan signal, a driving transistor to control the amount of current to be supplied to a current light-emitting element, a light-emitting control transistor to control supply of a current to the light-emitting element in response to a light-emitting control signal, a capacitor to retain a voltage corresponding to a write data voltage, and a reset transistor to set the gate electrode of the driving transistor with the initial voltage.
US09472136B2 Display module
A display module including a substrate having a plurality of pixels, a data line that supplies a data signal to a pixel, a current supply line that supplies electric current to the pixel, a data driving circuit that supplies a data signal to the data line, and a gate driving circuit thereon. The plurality of pixels are arranged in a display area of the substrate, and each of the plurality of pixels includes a light emitting device, a first thin film transistor connected to the data line that supplies the data signal, a second thin film transistor connected to the current supply line, and a capacitor. The light emitting device includes a first electrode layer connected to the second thin film transistor, an organic layer formed on the first electrode layer, and a second electrode layer formed on the organic layer.
US09472133B2 Devices and method of adjusting synchronization signal preventing tearing and flicker
A display controller includes a synchronization signal adjusting circuit, which adjusts at least one of the delay and the pulse width of a synchronization signal generated in a display driver and outputs an adjusted synchronization signal, and a transmission timing control circuit configured to control the transmission timing of display data, which will be transmitted to the display driver, in response to the adjusted synchronization signal.
US09472132B2 Display device and driving method thereof
A display device includes a timing controller for controlling the display of an image. The timing controller forms a frame for an image signal based on a main frame, a compensation frame, and at least one blank frame. The timing controller also determines a driving method for the display pixels to generate output image data. The main frame serves to display the image signal. The compensation frame serves to compensate luminance of the main frame. The blank frame serves to express a black gray scale value.
US09472129B2 Automatically folded LED display screen and application method
The present invention disclosed an automatically folded LED display screen and application method. The automatically folded LED display screen includes LED sub-displays hinged to each other, of which the LED sub-displays arranged at the top are provided with a fixture, with motors and winding reels, and the LED sub-displays screen arranged at the bottom are connected to a tray. The said winding reel is wound with steel wires, which are connected to the tray. The display screen can be automatically folded and unfolded, very easy to use.
US09472124B2 Safety label covering an individual packaging
The invention relates to a security label for protecting medicaments contained in an individual packaging, comprising a security layer (10, 110, 210) that can be stuck on the individual packaging. Removable elements (16, 216) are formed in the security layer (10, 110, 210), in the region of the medicaments (15) to be inserted, in such a way that cuts (17) are made in the security layer (10, 110, 210), on the edge of the removable elements (16, 216), said cuts (17) following a virtual cut strip. In order to produce such a security label that can be easily opened, but still provides protection against unauthorized opening by children or inadvertent opening, and can be produced cost-effectively, obstacle points are provided on the cut strip, forming a resistance when the removal element is removed.
US09472122B2 Central line simulation and training device
An anatomical simulation training device is disclosed in an embodiment herein. The anatomical device includes an anatomical model comprising a quadrant of a torso. The model includes a first opening and a second opening, wherein a first passageway connects between the first and the second opening. The model further includes a third opening, wherein a second passageway connects between the third opening and the second opening. The first passageway is configured to receive a first conduit, and the second passageway is configured to receive a second conduit. The first and second conduits are removable and replaceable. The model is comprised of, in part or in whole, a hydrogel, and said model quadrant torso mimics at least a portion of a human or non-human animal quadrant torso, and simulates at least one predetermined physical characteristic of a human or non-human animal torso with at least fifty percent or more similarity.
US09472116B2 Computing method and system with detached sensor in a network environment
One embodiment includes a computer-implemented method and system in a network environment using at least a display and a detached sensor. Another embodiment includes a computer-implemented system helping a user learn using a detached imaging sensor. In yet another embodiment, a computer-implemented system monitors automatically more than once a user's behavior while the user is working on materials. Through monitoring the user's voluntary or involuntary behavior, the system determines what to present by the display. The presentation could include providing rewards, punishments, stimulation, and other materials. The system can also react by asking the user a question. Based on the user's response, the system may change to more appropriate materials, or different presentation styles.
US09472109B2 Obstacle detection system providing context awareness
In sonic examples, an obstacle detection system is configured to generate and display a graphical user interface (GUI) that includes an overhead image of an area in which a vehicle is positioned, a graphical representation of the vehicle, and graphical representations of one or more obstacles, The graphical representations of the one or more obstacles and vehicle can be arranged relative to the overhead image to indicate determined real-world positions of the one or more obstacles and vehicle, respectively, relative to other features shown in the overhead (e.g., airport structure or other buildings).
US09472108B2 Updating an airfield lighting system with an LED light source
Methods and systems for updating an airfield lighting system with an LED light source are described herein. One method includes removing a light source from an existing light fixture of an airfield lighting system, wherein the removed light source is not a light emitting diode (LED) light source, and replacing the removed light source with an LED light source in the existing light fixture without modifying or replacing any other element of the existing light fixture.
US09472106B2 Automated flight object procedure selection system
Systems and methods for processing aircraft flight information and flight plan information are described. Specific techniques are described for managing flight data in real time, sharing flight data between a plurality of systems, dynamically managing flight information, generating flight plan information, providing flight plan information to a user, and closing flight plan discontinuities.
US09472098B2 Vehicle-based abnormal travel event detecting and reporting
A travel reporter system is used to report abnormal travel events. In use, a sensor mounted on a vehicle obtains real-time data about an object near the vehicle. The object has an object type which is identified by processing the real-time data with an object recognition subsystem of the travel reporter system. An event evaluation subsystem of the travel reporter system processes the real-time data and the object type in order to determine that the object is associated with an abnormal travel event. The abnormal travel event has an event type which is processed by an event notification subsystem of the travel reporter system in order to select a first information consumer type. The event notification subsystem reports the abnormal travel event to information consumers having the first information consumer type.
US09472088B2 Apparatus and method for locating and updating low-power wireless communication devices
A low-power wireless communication device is in a sleep or standby mode of operation for extended periods of time, periodically becoming fully operational and issuing a “check in” message to a base station, thereby inhibiting the ability of the base station to assist in the locating of device, and remotely updating the settings or operational programming of the device much of the time. Upon receipt of a command to locate a misplaced low-power wireless device or to update the device, a base station queues an associated command in a task queue. Upon receipt of a check-in message from an associated low-power wireless device, indicating it is in a fully powered and communicative state of operation, the base station searches its task queue for applicable commands relative to the specific wireless device and executes them via communication with the now fully-operational wireless device.
US09472086B2 System and method for noise detection
Embodiments provide a system and method for noise detection.
US09472085B2 Ambient and processor temperature difference comparison
Embodiments herein relate to ambient and processor temperature difference comparison. Processor and ambient temperatures are measured. A difference between the processor and ambient temperatures is compared to an initial difference. A warning may be signaled if a difference between the determined difference and the initial difference is greater than a threshold value.
US09472083B2 Direct observation event triggering of drowsiness
A system for event triggering comprises an interface and a processor. An interface configured to receive a face tracking data and receive a sensor data. The processor configured to determine a degree of drowsiness based at least in part on the face tracking data and the sensor data; in the event that the degree of drowsiness is greater than a first threshold, capture data; and in the event that the degree of drowsiness is greater than a second threshold, provide a warning.
US09472081B1 Child locator system
The child locator system comprises a display unit and a tracking unit. The tracking unit is a GPS locator that is attached to the child's clothing using a magnetic lock similar to those used to protect clothing in retail stores. The display unit is also fitted with a GPS locator. The tracking unit wirelessly communicates its position to the display unit. The display unit monitors the position of the tracking unit relative to the position of the display unit. Should the display unit lose contact with the tracking unit or should the tracking unit move more than a predetermined distance away from the display unit an alarm is sounded. The display unit is integrated with mapping software that can display the current (or last known) positions of both the display unit and the tracking unit on demand.
US09472076B2 Method and a system for supervising intruder alarm systems
A method of supervising intruder alarm systems, each alarm system comprising a plurality of alarm sensors and at least one gateway communicating with a remote alarm receiving center. The method includes the steps: a) receiving in a first intruder alarm system radio signals transmitted from a second intruder alarm system, b) transmitting from said first intruder alarm system information relating to the received radio signals to said remote alarm receiving center, c) analysing in said remote alarm receiving center information received from intruder alarm systems to identify at least one first intruder alarm system and at least one second intruder alarm system capable of exchanging information via radio signals, d) transmitting from said remote alarm receiving center control signals to said first intruder alarm system and to said second intruder alarm system to operate as a supervising system by monitoring radio signals from the other intruder alarm system operating as a supervised system, e) observing in either one of said first intruder alarm system and said second intruder alarm system absence of the monitored radio signals, and f) transmitting from a supervising alarm system an alarm signal when absence of said monitored signals is detected.
US09472073B2 EAS tag for bottles
An anti-theft device monitors bottles. It is comprised of a two components hingably connected together. They can move from an open position to a closed position to enclose the neck of a bottle. One component has a first latch element and contains electronics including switches. The other component has a second latch element. The latch elements combine to hold the two components in the closed position. When the two components are moved to the closed position, and a bottle is in position, the bottle contacts elements which in turn change the states of associated switches. One of these elements also functions to retain the bottle on the tag. The anti-theft device may be armed or disarmed by remote devices. The latching elements may be releasably lockable such as by a magnet. The anti-theft device may have passcode protection capabilities.
US09472071B1 Covert infrared monitoring and recording of images and video in controlled-environment facilities
An infrared image and/or a video of one or more residents of a controlled-environment facility is captured using an imaging device of a controlled-environment facility resident communication and/or media device disposed within the controlled-environment facility when the device is not being used in a communication session. The imaging device of the controlled-environment facility resident communication and/or media device is capable of operation with an infrared light source. The infrared image or video may be stored and/or presented to an entity associated with the controlled-environment facility, such as personnel of the facility, a facility administration system, etc. Capturing the image may include turning on at least one infrared light source on the device and/or turning off any indication that the capturing is taking place. The device may be located in a resident sleeping area and a bed check may be performed by the entity or device, using the infrared image.
US09472067B1 Security devices and related features
Aspects of the present disclosure are directed to security-based apparatuses and methods. As may be implemented in accordance with one or more embodiments, an apparatus includes a presence sensor that senses the presence of an individual, and an image sensor that captures an image of the individual in response to the sensed presence, and that provides the captured image as image data. A user authorization circuit identifies the individual as being authorized or unauthorized based upon the provided image data and stored image data for authorized individuals. An electromechanical device operates with the user authorization circuit to deploy one or more deterrents in the vicinity of the individual, in response to the user authorization circuit identifying the individual as being unauthorized.
US09472065B2 Gaming system and method for providing a cascading symbol game with interacting symbols
A gaming system including a cascading symbol game which utilizes a plurality of interacting symbols. In certain embodiments, the cascading symbol game utilizes a plurality of symbol display position matrices or grids. Each symbol display position matrix includes a plurality of symbol display positions. In operation, the gaming system generates and displays a symbol at each symbol display position of each employed symbol display position matrix, wherein the gaming system utilizes a separate set or pool of available symbols for each employed symbol display position matrix. Upon an occurrence of an interacting symbol triggering event, such as the shifting of one or more symbols between symbol display position matrices, the gaming system causes one or more symbols to interact to provide one or more benefits to a player.
US09472064B2 Gaming device having variable speed of play
This concept is directed to gaming devices configured to vary the speed of game play, as well as method of operating gaming devices to vary the speed of play. In some examples of the this concept, a gaming device may be configured to include a game initiating button that when pressed by a player triggers a game processor to ascertain and display a first game outcome, determine if the first game outcome is a winning outcome, and automatically ascertain and display a second game outcome if the first game outcome is not a winning outcome. If the first game outcome is a winning outcome the gaming device may pause to allow the player to appreciate the win before retriggering the processor to ascertain and display subsequent gaming event outcomes, or the gaming device may wait to receive further player input.
US09472063B2 Gaming system and method for providing a multiple sided card game
The present disclosure relates generally to gaming systems and methods for providing a card game that employs multiple-sided playing cards. In various embodiments, the gaming system enables a player to play one or more games which utilize one or more sets or decks of multiple-sided playing cards or multiple-sided tiles. In such embodiments, a first side of each multiple-sided playing card is associated with one of a plurality of playing cards from a first set or deck of playing cards for a first game and a second side of each multiple-sided playing card is associated with one of a plurality of playing cards from a second, different set or deck of playing cards for a second, different game.
US09472062B2 Gaming system and method providing a keno-type primary game associated with persistence pools that may be incremented to trigger one or more bonuses
Various embodiments of the present disclosure are directed to a gaming system and method providing a keno-type primary game including designated values that may be accumulated to trigger one or more bonuses. In one embodiment, the gaming system is configured to operate a keno-type primary game and a plurality of bonuses. Each bonus is associated with a different one of a plurality of different designated values. The gaming system accumulates the designated values upon the occurrence of certain events during play of the primary game. When the gaming system accumulates a designated quantity of a particular designated value during play of the primary game, the gaming system provides the bonus associated with that designated value. The gaming system thus enables accumulation of designated values across a plurality of plays of the primary game and, in some instances, over a plurality of gaming sessions to attempt to trigger the bonuses.
US09472060B2 Gaming system and method for providing team progressive awards
A gaming system and method which forms, tracks and maintains one or more groups or teams. The gaming system and method also maintains at least one team progressive award. At any designated point in time, each group or team includes one or more players, wherein as a player plays one or more games at one or more gaming devices, the player accumulates or builds up equity in their current team or group. Upon a determination to provide a team progressive award to a player of a designated team, each eligible player actively associated with the designated team (i.e., each player actively belonging to the team) is provided a portion of the team progressive award. Each player's provided portion of the team progressive award is based on that player's relative accumulated equity in the designated team compared to each other eligible player's accumulated equity in the designated team.
US09472050B2 Community award distribution system
Disclosed are community award distribution systems and related methods, which are arranged to control an award made to a use playing the systems. Also disclosed, the community award systems are arranged to communicate over the Internet and/or make use of the World Wide Web.
US09472046B2 Electronic gaming machines as service gateways
Managing a plurality of electronic gaming machines includes receiving a designation at a first electronic gaming machine (EGM) that the first EGM is a service gateway, broadcasting to other EGMs of the plurality of EGMs that the first EGM is the service gateway, and performing at least one of: discovering the other EGMs, identifying the other EGMs as client EGMs, and obtaining data from all of the client EGMs and retrieving crash data from all of the client EGMs, and communicating with a server to request performance of the at least one of the operations on selected ones of the plurality of EGMs.
US09472045B2 Method and system for managing a power-charging space for a vehicle, especially a self-service electrical vehicle
The invention relates to a method and a system for managing a parking space for a vehicle, for a space comprising means for detecting whether the space is occupied and at least one power-charging terminal suitable for automatic charging, especially automatic electrical charging following manual correction. Said method comprises, within a so-called occupation monitoring phase (as opposed to other phases such as a non-allocated vehicle storage phase): detection of a state of presence or absence of a vehicle or an object occupying the managed space, and detection of a state of connection or disconnection (operation or state) of a vehicle at the charging terminal. According to the invention, said method also comprises, in the event of a detection of presence without detection of connection, at least one so-called parking processing operation, for example, emitting at least one alert by acoustic or visual means, or recording or emitting at least one computer message.
US09472042B2 Controllable kiosk return gate
Techniques are described to substantially reduce a return of wrong DVD or return of a right DVD in an improperly sized DVD case to a DVD rental kiosk. An RFID tag on the DVD, as well as an RFID tag on the case, are sensed external to the kiosk. A controllable shutter normally closes the return slot and is driven open only upon detecting the correct predetermined condition or conditions. A supplemental camera may be employed to detect if a single DVD in its case is being placed proximate the return slot by the user. Help screens are employed as part of the above described system to reduce potential customer frustration from returning a DVD to the wrong DVD rental kiosk and the like.
US09472041B2 Clamping of media items
The present invention provides apparatus and a method for transporting at least one media item along a transport path, comprising locating a bunch of media items between at least one support surface and at least one clamp surface, and selectively moving said clamp surface towards or away from said support surface to apply a predetermined clamp force to the bunch of media items, wherein a predetermined angle of said clamp surface relative to said support surface is substantially constant when said clamp surface is moved towards or away from said support surface.
US09472034B2 Electronic lock system
A system is provided including a smartphone configured to wirelessly communication with an electronic lock. The smartphone wirelessly transmits data relating to a personalized user interface configuration, and the electronic lock receives the data from the smartphone, implements the personalized user interface configuration, receives additional information from the smartphone, and performs at least one function based on the additional information and the personalized user interface configuration. A method is also provided including personalizing a user interface configuration, transmitting the personalized user interface configuration from a smartphone to an electronic lock, implementing the personalized user interface configuration to the electronic lock, and performing via the electronic lock a function based upon the personalized user interface configuration.
US09472030B2 Systems and methods for utilizing telematics data to improve fleet management operations
According to various embodiments, a fleet management system is provided for capturing, storing, and analyzing telematics data to improve fleet management operations. The fleet management system may be used, for example, by a shipping entity (e.g., a common carrier) to capture telematics data from a plurality of vehicle sensors located on various delivery vehicles and to analyze the captured telematics data. In particular, various embodiments of the fleet management system are configured to analyze engine idle data in relation to other telematics data in order to identify inefficiencies, safety hazards, and theft hazards in a driver's delivery process. The fleet management system may also be configured to assess various aspects of vehicle performance, such as vehicle travel delays and vehicle speeds. These analytical capabilities allow the fleet management system to assist fleet managing entities, or other entities, in analyzing driver performance, reducing fuel and maintenance costs, and improving route planning.
US09472025B2 Compressible eyecup assemblies in a virtual reality headset
A virtual reality (VR) headset includes an electronic display element, an optics block, and an adjustment mechanism. The electronic display element outputs image light. The optics block includes a cone and an additional cone coupled to a lens and an additional lens, respectively. Image light is directed to the lens and to the additional lens via the cone and additional cone, respectively. Each of the cones comprises an opaque material that is deformable to adjust a distance from a base portion of a cone to a top portion of a cone may be adjusted, via, compression, elongation, or both. An adjustment mechanism may receive input from a user and configured to adjust the distance one or more of the cone and the additional cone.
US09472024B2 Computer-implemented method for designing a three-dimensional modeled object
A computer-implemented method for designing a three-dimensional modeled object comprising the steps of providing a three-dimensional designing scene (41) in a display screen (40); and providing a graphical tool (42) in a first area (43) with a reduced size in the display area (44) of the screen (40) comprising at least one image (45, 46, 47). The graphical tool (42) is permanently superimposed over the scene (41).
US09472019B2 System and method of from-region visibility determination and delta-PVS based content streaming using conservative linearized umbral event surfaces
A method determines a set of mesh polygons or fragments of the mesh polygons visible from a view region having a plurality of view region vertices, the mesh polygons forming polygon meshes. The method includes determining at least one supporting polygon between the view region and the polygon meshes. The method further includes constructing at least one wedge from the at least one supporting polygon, the at least one wedge extending away from the view region beyond at least the polygon meshes. Further, the method includes determining one or more intersections of the wedges with the mesh polygons. Also, the method includes determining the set of the mesh polygons or fragments of the mesh polygons visible from the view region using the determined one or more intersections of the at least one wedge with the polygon meshes.
US09472016B2 Bidirectional point distribution functions for rendering granular media
The disclosure provides an approach for rendering granular media. According to one aspect of the disclosure, granular media are rendered using bidirectional point scattering distribution functions (BPSDFs). The dimensionality of BPSDFs may be reduced by making certain assumptions, such as random orientations of grains, thereby simplifying light transport for computational efficiency. To generate a BPSDF from a grain, light transport may be precomputed using a Monte Carlo simulation in which photons are shot onto the grain from all directions. The precomputed BPSDF may be used, during rendering, for describing the interactions within grains. When a light ray traced during rendering intersects proxy geometry which replaces grain geometry, the BPSDF may be evaluated to determine light transport. By repeating this process for many light rays in a Monte Carlo simulation, the light propagation through the granular medium may be determined.
US09472011B2 System and method for 3D projection mapping with robotically controlled objects
A system for motion control is presented. In one embodiment, a motion control 3D projection system includes a projector; and a projection surface coupled to a robotic arm, where the robotic arm moves the projection surface through a set of spatial coordinates, and a 3D projection from the projector is projected onto a set of coordinates of the projection surface and matches the 3D projection to the set of coordinates of the projection surface as the projection surface moves through the set of spatial coordinates. In additional embodiments, a master control system may integrate additional robotic arms and other devices to create a motion control scene with a master timeline.
US09472009B2 Display of context based animated content in electronic map
Aspects provide for selection and display of context-based animated objects and streaming video content display within an electronic map presentation. Animated content data collected from network data sources includes live-action video or animation representations of the location-based user activity. Location context data is extracted from the collected animated content data that identifies a geographic location of a user activity depicted within the animated content data live-action video or animation representations. Boundaries of an area within an electronic cartographic map are correlated with the identified geographic location of the activity, as well as with a type of the activity depicted within the live-action video or animation. The correlated boundaries are stored for use in plotting locations of the live-action video or animations within presentations of the electronic cartographic map, at the correlated area boundaries.
US09472003B2 Generating a tree map
A method for generating a tree map for tree map visualization includes obtaining node information of a plurality of nodes to be processed, the plurality of nodes to be processed being sub-nodes sharing a same parent node and the node information comprising at least sizes of the nodes; determining from the plurality of nodes a plurality of candidate nodes whose sizes are less than a threshold size; determining at least one super node including the plurality of candidate nodes based on the node information of the determined plurality of candidate nodes, a screen size, and the threshold size, such that when displaying in a zooming-in mode the super node on the screen, all candidate nodes in the super node are displayed at display sizes not less than the threshold size; and determining data required for displaying the tree map based on the determined super node.
US09471997B2 Image composition based on remote object data
When a scene is generated, a content item may identify graphics object service requests associated with the scene. Each scene may have any number of associated graphics object service requests that may be sent to any number of different graphics object services. The graphics object services may be accessible over a network such as the Internet. By requesting object data from graphics object services, a content item may, for example, reduce at least part of the computational burden on a graphics processing unit of a client device.
US09471996B2 Method for creating graphical materials for universal rendering framework
Embodiments of the invention provide a renderer-agnostic method for representing materials independently from an underlying rendering engine. Advantageously, materials libraries may be extended with new materials for rendering with an existing rendering engine and implementation. Also, new rendering engines and implementations may be added for existing materials. Thus, at run-time, rather than limiting the rendering to being performed on a pre-determined rendering engine, the rendering application may efficiently and conveniently manage rendering a graphics scene on a plurality of rendering engines or implementations.
US09471994B2 Image based systems for detecting information on moving objects
Systems and methods for generating images of an object having a known object velocity include imaging electromagnetic radiation from the object onto a sensor array of an imaging system, adjusting at least one of a shutter rate and a shutter direction of the imaging system in accordance with an image velocity of the image across the sensor array, and sampling output of the sensor array in accordance with the shutter rate and the shutter direction to generate the images. Systems and methods for generating images of an object moving through a scene include a first imaging system generating image data samples of the scene, a post processing system that analyzes the samples to determine when the object is present in the scene, and one or more second imaging systems triggered by the post processing system to generate one or more second image data samples of the object.
US09471993B2 Method and apparatus for sensor aided extraction of spatio-temporal features
A method, apparatus and computer program product are provided for extracting spatio-temporal features with the aid of sensor information. An exemplary method comprises receiving video data and auxiliary sensor data and associating the two with timestamp information. The method may also include segmenting an input data stream into stable segments and extracting temporal features from the associated video data. The method may further include extracting temporal features either form the whole video or only from the video data where little or no stable segments are detected and performing camera view motion compensation by using information provided by the auxiliary sensors for modifying the feature-descriptors.
US09471992B2 Moving image processing apparatus, moving image processing method, and computer product
A moving image processing apparatus cumulatively sums for each reference block and in a predetermined sequence, values representing differences between corresponding pixels in a first block of a reduced image of a given image and a reference block within a search range in a reduced reference image; detects a motion vector of the first block, based on a calculation result; compares the amounts of increase among intervals of the summing process when the evaluation value is calculated for the reference block represented by the motion vector; and based on the comparison, determines a sequence to be used when the evaluation value of the reference block is calculated by cumulatively summing the values that represent differences between corresponding pixels in a second block in the given image and corresponding to the first block, and in a reference block within a search range in the reference image indicated by the motion vector.
US09471991B2 Image editing using level set trees
A method comprising: mapping an image onto multiple level sets connected by multiple branches, wherein each of said level sets corresponds to a predefined range of values for an attribute of said image; associating multiple pixels of said image to said multiple level sets in accordance with the value of each pixel; identifying a source level set associated with a source pixel of said multiple pixels; for each of said multiple pixels, determining that a distance between said source pixel and one of said multiple pixels is within a predefined threshold, wherein said distance is calculated as a function of a first distance between said source level set and said level set associated with said one of said multiple pixels; in one embodiment, the determined distance is applied to an image processing application to produce a processed image, and the processed image is rendered on a rendering medium.
US09471990B1 Systems and methods for detection of burnt-in text in a video
A method and a system implementing the method for detecting presence of burnt-in text in a video sequence are described. Initially, possible text candidates are separated from the background information. Individual candidates are then validated against the character features like similar font width, resolution, width height ratio, etc. These characters are further validated for the formation of words/sentences. Finally, the temporal features are used for validation for determining valid burnt-in text candidates.
US09471982B2 Information processing apparatus and information processing method for associating an image with related information
An association degree evaluation unit acquires pieces of position information of an image sensing apparatus at respective times within an adjacent time range to an imaging time of a designated image of those sensed by the image sensing apparatus. Furthermore, the association degree evaluation unit acquires pieces of position information of a moving object at the respective times within the adjacent time range. Then, the association degree evaluation unit calculates a similarity between routes of the image sensing apparatus and moving object based on the acquired position information group, and decides a degree of association between the designated image and moving object based on the calculated similarity. An associating unit registers information indicating the degree of association in association with the designated image.
US09471980B2 Image processing apparatus, image processing method thereof, and image processing system thereof
The image processing apparatus includes a receiver for receiving a first image acquired by photographing scattered radiation of X-rays existing in a closed space and a second image acquired by photographing the closed space; and an image processor for generating a third image by combining the first image and the second image.
US09471977B2 Image processing device, image processing system, and non-transitory computer readable medium
There is provided an image processing device. Pixels serving as a candidate for a nucleus are extracted from pixels included in a captured image obtained by imaging a sample including a target cell having the nucleus. A connected pixel group constituted of adjacent connected pixels is extracted from the extracted pixels. A value indicating a possibility that the target cell is included within a region surrounding the connected pixel group is determined. The value indicates the possibility being determined based on a value obtained by aggregating image feature amounts expressing luminance gradients determined based on luminance distribution with respect to a blue component within different partial regions included in the region surrounding the connected pixel group without performing normalization on each partial region.
US09471976B2 System and method for data driven gating of multiple bed positions
A method implemented using at least one processor includes receiving time-varying image dataset generated by a medical imaging modality. The image dataset corresponds to a bed position and is affected by quasi-periodic motion data. The method also includes applying a signal decomposition technique to the time-varying image dataset to generate a plurality of dataset components and a plurality of motion signals. The method also includes determining reference data based on the time-varying image dataset, wherein the reference data is representative of a direction of the quasi-periodic motion. The method further includes deriving polarity of each of the plurality of motion signals based on the reference data to generate a plurality of sign corrected motion signals. The method also includes determining a gating signal corresponding to the bed position based on at least one of the plurality of sign corrected motion signals.
US09471975B2 Methods, systems and computer program products for dynamic optical histology using optical coherence tomography
Methods of acquiring an image are provided. The methods include deriving a first boundary surface from a volumetric image; deriving a second boundary surface, different and spaced apart from the first boundary surface, of the volumetric image, the first and second boundary surfaces defining a slice of the volumetric image therebetween; and deriving at least one intermediate thin section between the first and second boundary surfaces, the thin section having a thickness that is less than a thickness of the slice of the volumetric image defined by the first and second boundary surfaces. Systems and computer program products are also provided.
US09471974B2 Method and system for feature extraction and decision making from series of images
Apparatus and methods comprise examination of a subject using images of the subject. The images can provide a non-invasive analysis technique and can include a plurality of images of a portion of the subject at different times a temperature stimulus applied to the subject. An image of the portion of the subject can be aligned such that each pixel of the image corresponds to the same point on the subject over a sequence of images of the portion. The sequence of images can be processed after aligning the images such that data is extracted from the images. The extracted data can be used to make decisions regarding the health status of the subject. Additional apparatus, systems, and methods are disclosed.
US09471971B2 System and method for image-based analysis of a slurry and control of a slurry process
A system for characterizing a slurry in a slurry process includes a flow tube, a camera, and a computer. The system is suitable for use with an oil sands extraction slurry processed or treated by an oil sands extraction slurry process. The slurry is diverted from the slurry process into the flow tube. The camera images the slurry as it flows through a transparent portion of the flow tube to produce a digital image of the slurry. The computer analyzes the digital image to determine a slurry characteristic. Based on the determined slurry characteristic, the computer may predict a performance metric of the slurry process and adjust an operating parameter of the slurry process to optimize the slurry process towards a target performance metric. Multiple systems may be used to continuously monitor slurry characteristics at upstream and downstream steps of the slurry process, and determine correlations between those characteristics.
US09471970B2 Infrared resolution and contrast enhancement with fusion
The present disclosure relates to combination of images. A method according to an embodiment comprises: receiving a visual image and an infrared (IR) image of a scene and for a portion of said IR image extracting high spatial frequency content from a corresponding portion of said visual image. The method according to the embodiment further comprises combining said extracted high spatial frequency content from said portion of the visual image with said portion of the IR image, to generate a combined image, wherein the contrast and/or resolution in the portion of the IR image is increased compared to the contrast and/or resolution of said received IR image.
US09471967B2 Relighting fragments for insertion into content
A fragment is relit for insertion into a target scene of an image by obtaining a fragment model for the fragment. A set of detail maps for the fragment model are generated, each of which encodes fine-scale shading effects from the surface detail of the fragment. A target scene model is obtained for the target scene, and the fragment model is inserted into the target scene model. The target scene model with inserted fragment model is rendered, and a composited target scene is generated. A modified target scene is generated by combining the composited target scene and the set of detail maps. Weights assigned to the different detail maps can be changed by the user, allowing the modified target scene to be readily altered without re-rendering the target scene model with the inserted fragment model.
US09471961B2 Method for rotating an original image using self-learning and apparatuses performing the method
A method of rotating an original image includes performing a self-learning using addresses related to at least one page miss and generating address generation rules using a result of the self-learning. The method includes pre-fetching the original image from a memory device based on the address generation rules to obtain a pre-fetched image and generating a rotated image using the pre-fetched image.
US09471958B2 Image processing method and apparatus
Embodiments of the present invention provide an image processing method and apparatus, where the image processing method includes: performing image magnification processing on a low-resolution image to obtain an initial high-resolution image; selecting a central similar block corresponding to a first pixel from the initial high-resolution image; selecting a search block corresponding to the first pixel from the low-resolution image, and determining each similar block in the search block, where the central similar block and the search block have a same block size; and determining a pixel value of the first pixel according to the central similar block and each similar block in the search block. By using technical solutions in the embodiments of the present invention, calculation complexity and an occupied memory resource can be effectively reduced.
US09471957B2 Method for partitioning, managing and displaying a collaboration space and interactive input system employing same
A computerized method of managing a collaboration space comprises partitioning the collaboration space into a plurality of tiles in a tree structure; and associating each graphic object with a tile in said tree structure; said tile being the smallest tile in the tree structure that substantially accommodate said graphic object.
US09471955B2 Multiple display pipelines driving a divided display
Systems, apparatuses, and methods for driving a split display with multiple display pipelines. Frames for driving a display are logically divided into portions, a first display pipeline drives a first portion of the display, and a second display pipeline drives a second portion of the display. To ensure synchronization between the two display pipelines, a repeat vertical blanking interval (VBI) signal is generated if either of the display pipelines has not already received the frame packet with configuration data for the next frame. When the repeat VBI signal is generated, both display pipelines will repeat processing of the current frame.
US09471951B2 Watermarking and scalability techniques for a virtual desktop planning tool
A method for measuring performance of virtual desktop services offered by a server including a processor is described. A first encoded watermark is embedded into user interface display generated by a virtual desktop when initiating an operation. The first encoded watermark includes pixels identifying the operation and indicating its initiation. A second encoded watermark is embedded into the user interface upon completion of the operation indicating completion of the operation. An action performance time is then computed and stored in a memory. Multiple performance times may be compiled from multiple operations of multiple virtual desktops to assess the performance of the system as a whole.
US09471950B2 Device and method of inserting watermarks through conversing contents automatically
Provided are a watermark insertion apparatus and method. The watermark insertion method includes acquiring content through upload by a user, storing the uploaded content, receiving a content conversion request from a user or a manager, determining whether content for which content conversion has been requested is video or an image, converting the content according to the determined content kind, and inserting watermark suitable for the content kind into the converted content.
US09471948B2 System and method for administering licenses stored by a product unit, and administration of said unit in the field
The product unit disclosed herein has identification data that are stored internally in memory. This stored identification data can be viewed as the product unit's “digital nameplate,” in that the data can represent the product unit's identifier, brand, and so on. Each data set is digitally signed while on the production line by using an encryption technique. The digitally signed data set is then written into the product unit's memory where it can be used for verification. A first digitally-signed data set can be used to control the use of one or more software modules that are provided by a software owner. The data that are undergoing signature contain at least one globally-unique identifier, which can be used to identify cloning attempts. Additionally, more than one digital signature can be used, in order to protect and control the use of features other than the software, such as the product brand.
US09471942B2 Apparatus and method for processing query in portable terminal for social network
A portable terminal which supports a social network, more particularly, an apparatus and a method for generating a community with agents of the same character in a social network and processing an answer to a query by sharing information between the generated communities. The apparatus includes an agent determiner configured to set an agent for a first network object. The apparatus also includes a community setting part configured to establish a community with an agent for a first network and an agent for a second agent, select a first representative agent of the community, and establish a community with the first representative agent selected and other adjacent representative agents.
US09471937B2 Download account with shared data plan
A device is configured to create an account including a plurality of members and a shared data plan. The device stores a content associated with the account and the shared data plan is set up to be charged for data used on an operating network to provide the content to the plurality of members associated with a plurality of operator networks. Further, the device provides the content to a user device associated with a member of the plurality of members. The content is provided through the operator network. The device charges the shared data plan for the amount of data used by the operator network to provide the content to the user device without causing a data plan between the member and the operator network to be charged for the amount of data.
US09471934B2 Method and apparatus for feature-based presentation of content
An approach is provided for location-based presentation of content. A content service platform determines one or more representations of at least one structure. The content service platform also processes and/or facilitates a processing of the one or more representations to determine one or more features of the one or more representations. The content service platform further causes, at least in part, designation of the one or more features as elements of a virtual display area, wherein the one or more representations comprise, at least in part, the virtual display area. The content service platform also causes, at least in part, presentation of one or more outputs of one or more applications, one or more services, or a combination thereof in the virtual display area.
US09471932B2 Systems and methods for enhancing user data derived from digital communications
A computer-implemented method for enhancing and utilizing user data derived from digital interactions includes receiving a submission generated by input into a client side application interface by a first user on a first computing device, and determining, based on the attributes of the submission, that the submission is in response to an issue-specific communication advertising information concerning a first issue. The method includes generating a first dataset associated with the first user, searching one or more additional datasets for additional data to be associated with data elements of the first dataset, associating the additional data from the one or more additional datasets with the first user, generating a data model, and requesting records associated with additional users.
US09471926B2 Systems and methods to provide offers to travelers
In one aspect, a computing apparatus includes: a transaction handler configured to process transactions; a data warehouse configured to store transaction data recording the transactions and to store event data for travel related events; a pattern detector configured to identify correlation data relating transaction patterns in the transaction data and the events identified in the event data; a portal configured to, in response to an occurrence of a first event, provide merchants with a report of a predicted spending pattern, including the identification of a set of consumers, identified based on the correlation data and data identifying the first event; a score generator to compute a value score for a traveler based on transaction data of the traveler; and a data services platform configured to provide the value score to a hotelier in response to a transaction processed by the transaction handler to check in the traveler at the hotelier.
US09471925B2 Increasing mobile interactivity
In embodiments of the present invention improved capabilities are described for caching search related data on a mobile communication facility, coordinating the presentation of the cached information with network information to the mobile communication facility display to facilitate response to user queries with up to date information, and implicitly downloading updates to cached information while previously cached information is available to the user.
US09471924B2 Control of digital media character replacement using personalized rulesets
An apparatus, program product and method utilize rulesets associated with particular individuals to restrict or otherwise control the use of such individuals' likeness data into media presentations using character replacement or like technologies. A ruleset includes at least one rule configured to define a condition under which the likeness data for an individual may or may not be incorporated into a media presentation. As such, during the generation of a media presentation, the ruleset may be accessed and analyzed, whereby the likeness data for an individual may be selectively incorporated into a media presentation based upon the ruleset to generate a personalized version of the media presentation.
US09471923B2 Providing licensed content to a user
When a user requests licensed content, a dynamic licensing mechanism automatically requests and receives licenses for the licensed content when one or more criterion in a licensing policy is satisfied by license information relating to the content, without the user providing any further input to acquire the licenses.
US09471919B2 Systems and methods for biometric authentication of transactions
Systems and methods are provided for authorizing a user in connection with a transaction at a transaction terminal. The systems and methods described herein enable a series of operations whereby a user using a mobile device can capture a code that uniquely identifies a transaction terminal. In addition the mobile device can also capture a user's biometrics, generate a biometric identifier and biometrically verify the user's identity by comparing the biometric identifier to a previously generated biometric identifier. If the user is biometrically authenticated the mobile device can generate a transaction request including, a user identifier, a mobile device identifier, and the transaction terminal code and transmit the transaction request to a system server. Based on the transaction request, the system server can further authenticate the user and/or approve the requested transaction. If the user is authenticated, the system server can instruct the terminal to advance the financial transaction.
US09471916B2 Wireless establishment of identity via bi-directional RFID
A method, a system, and a computer program product are provided for wireless establishment of identity via bi-directional radio-frequency identification (RFID). The method is implemented in a computer infrastructure having computer executable code tangibly embodied on a computer readable storage medium having programming instructions operable for sending device data including at least a username and a password to a transceiver. The method also includes receiving an identifier of an access point in a wireless network from the transceiver, the transceiver sending the device data to the access point via a security server. The device data is sent to the access point based on the identifier of the access point, the access point establishing a secure connection to the computer infrastructure based on the device data received from the transceiver and the computer infrastructure.
US09471913B1 Method and system for cardless processing of E-invoicing
A method for paying invoices using a mobile device. A retail enterprise (i.e., a seller) generates an invoice for goods or services that a client (i.e., a buyer) has selected. The invoice is stored in a database of a common payment service (CPS) and the invoice number is sent to buyer's mobile phone. The buyer uses his mobile phone to access his bank account via e-commerce 3-D Secure mechanism supported by the bank. The buyer is authenticated based on a procedure used by a particular bank. If the authentication is successful, the CPS initiates a payment for the seller's invoice. The payment information is sent to the buyer's mobile phone and also is sent to the seller for confirmation of closing the transaction.
US09471908B2 ATM customer defined user interface for security purposes
Embodiments of the invention are directed to a system, method, or computer program product for receiving a customization that will be displayed on the screen of an ATM based on a customer initiating a session with the ATM. The customization is associated with a function to perform a financial transaction. The function is performed as a result of the customer interacting with the customization on the screen of the ATM. The customization may be altered based on a handicap impairment of the customer. The displaying of the customization may be restricted for security purposes or as a request of the customer.
US09471906B2 Digital transactional procedures and implements
This invention describes a set of related procedures designed to co-operate with mints of digital money in order to allow for said money to be properly, securely, and conveniently traded by, various size and various type of trading crowds. The procedures refer mainly to distribution of responsibility. This invention also specifies the construction of digital coins encapsulated in a physical housing to amount to off-line tradable digital coins.
US09471905B2 Methods and systems for processing electronic documents
A method, a system, and a computer program product for processing a plurality of electronic documents are provided. The method includes marking at least one area in an electronic document selected from the plurality of electronic documents. The marked at least one area is then matched with corresponding area in the remaining electronic documents of the plurality of electronic documents. A score is computed for each of the remaining electronic documents of the plurality of electronic documents based on the matching. The plurality of electronic documents is then grouped into one or more groups based on the score.
US09471901B2 Accessible white space in graphical representations of information
Mechanisms are provided for representing white space in a graphical representation of a data model. These mechanisms involve analyzing output data that is to be output to a user via an output device, to identify white spaces in the output data. White spaces comprise portions of a range of metrics of output data values where the output data does not have data objects representing those portions of the range of metrics of output data. For each identified white space, a white space data object is created. The white space data objects are provided to an application which performs an operation on the white space data objects to output the white space data objects in a manner that identifies the white space data objects differently from non-white space data objects in the output data.
US09471896B2 Memo synchronization system, mobile system, and method for synchronizing memo data
Provided is a memo synchronization system, a mobile system, and a method for synchronizing memo data. The memo synchronization system includes a storage device, an authentication unit configured to authenticate a user by receiving authentication information of the user from a mobile terminal via a memo application installed in the mobile terminal, and a synchronization unit stored on the storage device and configured to synchronize memo data stored in the mobile terminal with memo data stored in a web storage space of an online memo service based on a request for synchronization transmitted from the mobile terminal through the memo application. The request for synchronization includes a synchronization request generated by the memo application according to an event set by the user.
US09471893B2 Methods and apparatus to monitor products in stores
Methods and apparatus are disclosed to audit products in stores. An example method includes receiving, at a collection entity, a first request from a first entity to audit a first product, the first request including a first instruction to determine information about a second product that competes with the first product, in response to the first request, assigning a first auditor to audit the first product and to record the information about the second product, receiving, at the collection entity, a second request from a second entity to audit a third product, determining that the second request includes a second instruction to determine information about the second product identified in the first request, and in response to the second request, assigning a second auditor to audit the third product without including a further instruction to record the information about the second product.
US09471891B2 Method, system and apparatus for automatic quality control using a plurality of computers
A system and method for automatic quality control is provided. A database is maintained storing quality control rules for producing a product, the quality control rules determined via a first computing device associated with a first entity controlling production of the product, the database maintained by a second computing device associated with a second entity for maintaining quality control of the product, the product produced by a plurality of production lines respectively associated with third entities. Quality control data is received at the second computing device from data collection devices at the plurality of production lines, each of the data collection devices enabled to collect the quality control data for the product. At the second computing device, the quality control data is compared with the quality control rules; at least one quality control event is triggered when the quality control data fails at least one of the quality control rules.
US09471886B2 Class discriminative feature transformation
A method for feature transformation of a data set includes: receiving a data set including original feature samples with corresponding class labels; splitting the data set into a direction optimization set and a training set; using the direction optimization set to calculate an optimum transformation vector that maximizes inter-class separability and minimizes intra-class variance of the feature samples with respect to corresponding class labels; using the optimum transformation vector to transform the rest of the original feature samples of the data set to new feature samples with enhanced discriminative characteristics; and training a classifier using the new feature samples, wherein the method is performed by one or more processors.
US09471879B2 Dynamic mathematical validation using data mining
Provided are techniques for dynamic mathematical validation using data mining. As text is being received, a mathematical statement is identified in the text based on context of the text. A mathematical solution to the mathematical statement is identified in the text based on the context of the text. It is determined that the mathematical solution is incorrect using data mining. In response to determining that auto-correction is to be performed, the mathematical solution is corrected.
US09471878B2 Dynamic mathematical validation using data mining
Provided are techniques for dynamic mathematical validation using data mining. As text is being received, a mathematical statement is identified in the text based on context of the text. A mathematical solution to the mathematical statement is identified in the text based on the context of the text. It is determined that the mathematical solution is incorrect using data mining. In response to determining that auto-correction is to be performed, the mathematical solution is corrected.
US09471875B2 Using ontologies to comprehend regular expressions
Ontologies are used to comprehend regular expressions, by selecting, based on a context relating to a domain of a regular expression, an ontology and an assertion base, parsing the regular expression to identify at least one fragment of the regular expression, identifying one or more assertions in the assertion base corresponding to one of the identified fragments, identifying, for each identified assertion, an associated node in the ontology, and returning, based on the associated nodes, a concept in the ontology as representing the associated fragment of the regular expression.
US09471873B1 Automating user patterns on a user device
Methods and systems for automating user patterns on a user device are described. A user device receives data representing inputs to a user interface (UI) of the user device and system data associated with each of the inputs, wherein the system data comprises information describing an environment of the user device when the input to the UI was received. The user device then determines that a subset of the inputs to the UI and the system data associated with the subset of the inputs exceeds a threshold probability of matching a pattern of previously-identified UI inputs and system data associated with the previously-identified UI inputs. The user device then executes additional inputs to the UI to complete the matched pattern.
US09471870B2 Brain-machine interface utilizing interventions to emphasize aspects of neural variance and decode speed and angle using a kinematics feedback filter that applies a covariance matrix
A brain machine interface (BMI) for restoring performance of poorly performing decoders is provided. The BMI has a decoder for decoding neural signals for controlling the brain machine interface. The decoder separates in part neural signals associated with a direction of movement and neural signals associated with a speed of movement of the brain machine interface. The decoder assigns relatively greater weight to the neural signals associated with a direction of movement.
US09471863B2 Retroreflective articles having a machine-readable code
Retroreflective articles comprise a substrate and a bar code provided on the substrate. The bar code comprises at least one human-readable information which provides framing information and a machine-readable information which provides variable information. The human-readable information is visible under a first condition and invisible under a second condition, and the machine-readable information is invisible under the first condition and visible under the second condition.
US09471862B2 Intelligent label device and method
Briefly, an intelligent label is associated with a good, and includes one or more permanent and irreversible electrochromic indicators that are used to report the condition of that good at selected points in the movement or usage of that good. These electrochromic indicators provide immediate visual information regarding the status of the good without need to interrogate or communicate with the electronics or processor on the intelligent label. In this way, anyone in the shipping or use chain for the good, including the end user consumer, can quickly understand whether the product is meeting shipping and quality standards. If a product fails to meet shipping or quality standards, the particular point where the product failed can be quickly and easily identified, and information can be used to assure the consumer remains safe, while providing essential information for improving the shipping process. It will be understood that the label may take many forms, such as a tag attached to the good, integrated into the packaging for the good, integrated into the good itself, or may even be an information area on a prepaid card for example. The label may also include, for example, print information regarding the good, usage or shipping rules, or address and coded information.
US09471861B2 Method for printing a print job on a media
The invention relates to a method for printing a digital image on a piece of media by means of a printer system comprising a printer and a computer for storing digital objects, the method comprising the steps of printing at least one digital image on a piece of media, cutting the printed at least one digital image out of the piece of media, attaching an identifying object to the leftover of the piece of media, storing the leftover of the piece of media in a depository, and storing a digital object representing the leftover of the piece of media in a database on the computer, wherein the digital object comprises a reference to the attached identifying object. The invention also relates to a method for printing a print job on a printer system, the method comprises the steps of submitting a print job for printing at least one digital image to the printer system, selecting a digital object from a database comprising digital objects representing a collection of leftovers of pieces of media in a depository and each comprising a reference to an identifying object of the corresponding leftover, wherein the leftover represented by the selected digital object is large enough to print the at least one digital image upon said leftover, retrieving the reference from the selected digital object, locating in the depository the leftover represented by the digital object by means of the retrieved reference, and printing the at least one digital image on the leftover.
US09471860B2 Image forming apparatus and power saving controlling method for the same
An image processing apparatus is connected to an image forming apparatus that operates at least in a standby state and in a power saving state requiring less power consumption than the standby state. The image processing apparatus, which is configured to perform image processing on an externally received print job and to input the print job to the image forming apparatus, includes a determination unit configured to determine a power state of the image forming apparatus, and a transmission unit configured to transmit a reserved print job to the image forming apparatus at a reserved time if the determined power state of the image forming apparatus is the power saving state, and to transmit the reserved print job to the image forming apparatus prior to the reserved time if the determined power state of the image forming apparatus is the standby state.
US09471848B2 Classifying objects displayed on a device
A method, system, and/or computer program product classifies a plurality of objects displayed on a display device and displays the classified plurality of objects. The method comprises: selecting one object from a plurality of objects as a selected object; and classifying the plurality of objects, where classification of each of the plurality of objects is based on a degree of association with the selected object. Classifying the plurality of objects comprises: reading a feature setting for computation of the degree of association; specifying a plurality of features that are subject to the computation of the degree of association; computing, for each of the plurality of objects, the degree of association based on a difference in feature value from the selected object with regard to the plurality of features; and dividing the plurality of objects into a plurality of groups, where each group is based on the degree of association.
US09471845B1 Background modeling for imaging surveillance
A surveillance system and method includes imaging means for processing images so that objects in the foreground are detected in the background and threats are identified. In the method, the imaging means acquires images and an initial background model is constructed from those images. Pixels are classified as either background or foreground for subsequent processing stages. In some embodiments, the imaging means is fixed in location and attitude, while in other embodiments, the imaging means is mounted to a moving platform and can alter its attitude. In such mobile applications, the system exploits geo-referencing as an aid in determining information about the pixels.
US09471841B2 Electronic document generation system, image forming apparatus and program
An electronic document generation system includes: an image forming apparatus configured to generate a scanned image of an original document; and an external terminal configured to receive image data of the scanned image from the image forming apparatus, and generate an electronic document based on the scanned image, wherein the image forming apparatus includes: a divided data generation unit; a determination unit; and a communication unit, of the plurality of divided image data, the communication unit transmits, to the external terminal, divided image data that is determined to be the processing target data at an earlier point in time, and transmits, to the external terminal, divided image data that is determined not to be the processing target data after the divided image data that is determined to be the processing target data are transmitted, and the external terminal includes: an obtaining unit; and a document generation unit.
US09471840B2 Apparatus and method for low-power object-detection in images using hardware scanning window
An apparatus includes a hardware sensor array including a plurality of pixels arranged along at least a first dimension and a second dimension of the array, each of the pixels capable of generating a sensor reading. A hardware scanning window array includes a plurality of storage elements arranged along at least a first dimension and a second dimension of the hardware scanning window array, each of the storage elements capable of storing a pixel value based on one or more sensor readings. Peripheral circuitry for systematically transfers pixel values, based on sensor readings, into the hardware scanning window array, to cause different windows of pixel values to be stored in the hardware scanning window array at different times. Control logic coupled to the hardware sensor array, the hardware scanning window array, and the peripheral circuitry, provides control signals to the peripheral circuitry to control the transfer of pixel values.
US09471839B2 Vehicle identification based on an image
A machine may be configured as a vehicle identification machine to identify a model of a vehicle based on an image that depicts a dashboard of the vehicle. As configured, the machine may receive an image of the dashboard, where the image depicts a layout of instrumentation within the dashboard. The machine may identify the layout of instrumentation by processing the image. For example, the machine may process the image by determining a position of an instrument within the layout of instrumentation, determining an outline of instrument, or both. The machine may access a data record that correlates a model of the vehicle with the identified layout of instrumentation and, based on the data record, identify the model of the vehicle. The machine may then provide a notification that references the vehicle, references the identified model of the vehicle, or references both.
US09471838B2 Method, apparatus and system for performing facial recognition
A method, apparatus, and system for performing facial recognition utilizing large databases is provided herein. During operation a large database is quickly narrowed by determining an automobile attribute (e.g., a license plate number) and determining a registered owner and possibly an address based on the automobile attribute. The image database is narrowed based on the registered owner of the vehicle, and possibly the address of the registered owner.
US09471832B2 Human activity determination from video
Automated analysis of video data for determination of human behavior includes segmenting a video stream into a plurality of discrete individual frame image primitives which are combined into a visual event that may encompass an activity of concern as a function of a hypothesis. The visual event is optimized by setting a binary variable to true or false as a function of one or more constraints. The visual event is processed in view of associated non-video transaction data and the binary variable by associating the visual event with a logged transaction if associable, issuing an alert if the binary variable is true and the visual event is not associable with the logged transaction, and dropping the visual event if the binary variable is false and the visual event is not associable.
US09471829B2 Method of facial landmark detection
Detecting facial landmarks in a face detected in an image may be performed by first cropping a face rectangle region of the detected face in the image and generating an integral image based at least in part on the face rectangle region. Next, a cascade classifier may be executed for each facial landmark of the face rectangle region to produce one response image for each facial landmark based at least in part on the integral image. A plurality of Active Shape Model (ASM) initializations may be set up. ASM searching may be performed for each of the ASM initializations based at least in part on the response images, each ASM search resulting in a search result having a cost. Finally, a search result of the ASM searches having a lowest cost function may be selected, the selected search result indicating locations of the facial landmarks in the image.
US09471827B2 Method of validation of the use of a real finger as support of a fingerprint
Validation of using a finger as support of a fingerprint may include: placing the support such that it bears; capturing a captured image of the print; transforming the captured image into a resulting image by passage through a low-pass filter; locating on the resulting image an origin point, the intensity of whose pixel is representative of the maximum pressure exerted on the support; verifying that, on the resulting image, for a plurality of radii issuing from the origin point, and for each of said radii, for a plurality of points M, the intensity of the pixel of each point M of said radius is representative of a decline in the pressure exerted on the support as the distance from the origin point to the point M increases, and a decision as regards the validity of the support is taken as a function of the results of the verification step.
US09471824B2 Embedded barcodes for displaying context relevant information
Described herein are systems and methods employing embedded barcodes to convey supplemental information about an image, for example a motion picture. In some systems the barcodes may be subliminal because they are spliced, physically or digitally, into a movie frame shown too briefly to be consciously detectable to the human eye, but still detectable by camera sensors. Other described systems may display the barcodes in infrared or ultraviolet light, which is outside of the visible spectrum of light perceived by the human eye, but still detectable by camera sensors.
US09471819B2 System and method for quality control, inspection and audit of utility assets
Method for capturing, organizing and retrieving data for utility assets using RFID tags, including: storing data related to a plurality of utility assets in a database, wherein the stored data include data about type of the utility asset; repair, documentation, testing validation, and inspection of the utility asset; programming a plurality of RFID tags for placement on a utility asset, by one or more processors; placing the programmed RFID tags on the utility asset; linking stored data related to the utility asset with the programmed data for the placed RFID tags, including location data of the placed RFID tags; and querying one or more of the placed RFID tags to retrieve data about the utility asset including data about the location of the utility asset, the specific segment and the specific joint, the type of the utility asset; repair, documentation, testing validation, and inspection of the utility asset, by one or more processors.
US09471818B2 Communication station for communication with transponders and further communication stations with the aid of different protocols
A communication station (1) is suitable for contactless communication with transponders and with further communication stations and has a first protocol-executing circuit (12) and a second protocol-executing circuit (13), the first protocol-executing circuit (12) being designed to effect communication between the communication station (1) and transponders under a station/transponder protocol and the second protocol-executing circuit (13) being designed to effect communication between the communication station (1) and further communication stations under a station/station protocol.
US09471812B2 Method for implementing security of non-volatile memory
An integrated circuit includes a non-volatile memory module that can censor access to various memory regions based upon a censorship criteria. Information used to implement the censorship criteria is stored at a non-volatile memory location. A one-time programmable non-volatile memory location stores a value representing permanent censorship key. If the permanent censorship key is in an erased state, one or more resources are allowed to modify the non-volatile memory location and disable censorship. If the permanent censorship key has one or more programmed bits, no resource is allowed to modify the non-volatile memory location and disable censorship.
US09471811B2 Learning a new peripheral using a security provisioning manifest
A secure provisioning manifest used to authenticate and securely communicate with peripherals attached to a computer is provided with techniques to learn about a new peripheral not authorized to be attached to the computer and possibly gain authorization for the peripheral. A secure I/O module, that is separate from an operating system and transaction software executed by a processor of the computer, uses the secure provisioning manifest to authenticate and establish a secure encrypted session for communicating with each peripheral authorized to be attached to the computer. When an unauthorized peripheral is found, identifying information for the peripheral is transmitted to an enterprise provisioning server with a request to authorize the peripheral.
US09471810B2 Method and system for determining hidden states of a machine using privacy-preserving distributed data analytics and a semi-trusted server and a third-party
A method classifies data to determine hidden states of a machine by first acquiring data from the machine in a client, which is permuting randomly, and then chaff is inserted before transmitting to server as private data. The server classifies the private data according to a hidden Markov model to obtain permuted noisy estimates of states of the machine and the chaff, which are transmitted to a third party. The third party removes the chaff and inverts noisy estimates using a permutation ordering to obtain unpermuted noisy estimates of the states of the machine.
US09471809B2 Method and system for providing secure transactions via a broadband gateway
A broadband gateway may be used to authorize transactions associated with one or more accounts, which may be associated with a user of the broadband gateway. The transaction may be handled by the broadband gateway. The authorizations may be performed based on information associated with the accounts, whose storage may be controlled by the broadband gateway. The broadband gateway may block and/or terminate transactions failing authentication and/or validation, which may be performed based on the stored information. The transactions may be initiated within a network serviced by the broadband gateway. The transactions may also be initiated outside the serviced network. The stored information may comprise a user profile, which may comprise a plurality of settings for controlling and/or managing authorization performed by the broadband gateway. The user profiles may be configurable by users, wherein configuration may comprise initializing and/or modifying one or more of the transaction related settings.
US09471808B2 File management system and method
A file management system comprises an identification device, an administration device, and a supervisory device. A first computing processor of the administration device generates an encrypted file from an original file and encryption information, and stores the encryption information into the identification device. The first computing processor further defines file management information for access control of the encrypted file, and the first computing processor also stores the file management information into the identification device. A second processor of the supervisory device loads the encryption information and the file management information in the identification device to control the usage of the encrypted file. The second computing processor further records the file usage information into the identification device, and transmits to the administration device. The file management system also records the file usage information for clarifying the responsibility of disclosing the content of the encrypted files.
US09471807B1 System and method for creating a security slices with storage system resources and related operations relevant in software defined/as-a-service models, on a purpose built backup appliance (PBBA)/protection storage appliance natively
Exemplary methods include receiving a message from an agent requesting to perform a first set of operations on a first set of storage namespaces mapped to a first set of file system management objects (FSMOs) in the PBBA. The methods include determining whether to allow or deny the first set of operations based on information stored in a plurality of security units, each security unit comprising of an operation set identifier (ID), a set of FSMO IDs, and an agent ID, wherein the agent ID identifies an agent that is allowed to perform a set of operations identified by the operation set ID on a set of FSMOs in the PBBA identified by the set of FSMO IDs, and in response to determining to allow the first set of operations, performing the first set of operations.
US09471806B1 Protection of state data in computer system code
Method and system are provided for protecting state data of computer system code. The computer system code may be operating system code, subsystem code or application code and the item of state data is not expected to change within the execution of the computer system code. The method includes: creating or modifying an item of state data having a field value and being stored in memory for access by computer system code; registering an item of state data for protection; preserving the field value of the item of state data in a form inaccessible to third party software; validating the field value of the item of state data by comparing a current field value with the preserved field value to determine if the field value has been modified; and, if the field value has been modified, taking appropriate action.
US09471803B2 System and method for secure multi-tenancy in an operating system of a storage system
Exemplary methods for providing secure multi-tenancy in a Purpose Built Backup Appliance include creating a set of tenant-units (TUs), associating file system management objects (FSMOs) and users with the TUs. The methods further include maintaining a protocol config-metadata store based on the association of the FSMOs and users with the TUs. In one embodiment, in response to a first request from a first user to access a first FSMO of a first TU, the methods include determining whether the first user is authorized to access the first FSMO based on information of the protocol config-metadata store, and in response to the protocol config-metadata store indicating the first user is authorized to access the first FSMO, allowing the first user to access the first FSMO.
US09471802B2 Hybrid file systems
Methods may provide a virtual system with direct access to one or more sectors of a resource of a computer system. The method may include providing, by a computer system to a virtual system, first access control data associated with a regular computer file that corresponds to a resource on the computer system. The method may additionally include receiving, at the computer system, a direct read from or direct write to one or more sectors of the resource represented by the regular computer file from the virtual system. The method may further include hiding, at the computer system, a hidden computer file from the virtual system. The method may additionally include routing, at the computer system, the direct read from or direct write to the hidden computer file on the computer system.
US09471799B2 Method for privileged mode based secure input mechanism
A system and method are disclosed for securely receiving data from an input device coupled to a computing system. The system includes an interface configured to receive data from an input device, a coprocessor, and a host computer, wherein the host computer includes an input handler and a host processor. The host processor is configured to execute code in a normal mode and in a privileged mode. The host processor switches from the normal mode to the secure mode upon data being available from the interface while the host computer is in a secure input mode. The input handler receives the data from the interface and sends the received data to the coprocessor responsive to receiving the data while operating in the secure mode.
US09471790B2 Remediation of security vulnerabilities in computer software
Processing a downgrader specification by constructing a set of candidate downgrader placement locations found within a computer software application, where each of the candidate downgrader placement locations corresponds to a transition between a different pair of instructions within the computer software application, and where each of the transitions participates in any of a plurality of data flows in a set of security-sensitive data flows within the computer software application, applying a downgrader specification to the set of candidate downgrader placement locations, and determining that the downgrader specification provides full coverage of the set of security-sensitive data flows within the computer software application if at least one candidate downgrader placement location within each of the security-sensitive data flows is a member of the set of candidate downgrader placement locations.
US09471784B1 Automated firmware settings verification
Systems and methods are described for managing computing resources. In one embodiment, data representative of an abstracted firmware framework is maintained. The data may comprise computing firmware settings and determined based on standardized associations between vendor-specific firmware settings and abstracted firmware settings that are independent of the vendor-specific firmware settings. In response to receiving a request for a computing firmware setting, the requested computing firmware setting is translated to one or more vendor-specific firmware settings based on the data. A computing resource capable of implementing the one or more vendor-specific firmware settings is identified.
US09471783B2 Generic unpacking of applications for malware detection
A technique for detecting malware in an executable allows unpacking of a packed executable before determining whether the executable is malware. In systems with hardware assisted virtualization, hardware virtualization features may be used to iteratively unpack a packed executable in a controlled manner without needing knowledge of a packing technique. Once the executable is completely unpacked, malware detection techniques, such as signature scanning, may be employed to determine whether the executable contains malware. Hardware assisted virtualization may be used to facilitate the scanning of the run-time executable in memory.
US09471778B1 Automatic baselining of anomalous event activity in time series data
Software that automatically creates baselines from time series data of computer system activity, thereby providing immediate value from observed system data. The software performs the following operations: (i) receiving values of one or more attributes of a computing system that correspond to one or more time periods; (ii) determining a first set of statistical thresholds for the received values, wherein the received values include a subset of values that exceed the first set of statistical thresholds; (iii) determining a second set of statistical thresholds for the subset of values that exceed the first set of statistical thresholds; and (iv) determining a baseline pattern for the one or more attributes based, at least in part, on the determined first set of statistical thresholds and the determined second set of statistical thresholds.
US09471776B2 Secured execution of a web application
Methods and nodes for securing execution of a web application by determining that a call dependency from a first to a second function needs to be protected, adding a Partial Execution Stub (PES) function comprising code to establish a communication connection with a trusted module. Methods and nodes for secured execution of a web application by invoking a function of the web application, invoking a Partial Execution Stub (PES) function during execution of the function of the web application, sending, from the PES function, a message call with current execution information to a trusted module and receiving, a verification result from the trusted module.
US09471775B1 Security protocols for low latency execution of program code
A system for providing security mechanisms for secure execution of program code is described. The system may be configured to maintain a plurality of virtual machine instances. The system may be further configured to receive a request to execute a program code and allocate computing resources for executing the program code on one of the virtual machine instances. One mechanism involves executing program code according to a user-specified security policy. Another mechanism involves executing program code that may be configured to communicate or interface with an auxiliary service. Another mechanism involves splitting and executing program code in a plurality of portions, where some portions of the program code are executed in association with a first level of trust and some portions of the program code are executed with different levels of trust.
US09471773B2 Apparatus, system, and method for context-sensitive rolling password generation
An apparatus, system, and method are disclosed for context-sensitive password generation. The inspection module may accept entry of at least a new portion of a password by a user into a security mechanism and determine a dynamic parameter candidate within the password. The analysis module may recommend to the user a context-sensitive interpretation of the dynamic parameter candidate. The confirmation module may receive a selection by the user of the context-sensitive interpretation.
US09471767B2 CAPTCHA techniques utilizing traceable images
Techniques are disclosed for generating, utilizing, and validating traceable image CAPTCHAs. In certain embodiments, a traceable image is displayed, and a trace of the image is analyzed to determine whether a user providing the trace is human. In certain embodiments, a computing device receives a request for an image, and in response, creates a traceable image based upon a plurality of image elements. The computing device transmits data representing the traceable image to cause a second computing device to display the traceable image via a touch-enabled display. The computing device receives a user trace input data generated responsive to a trace made at the second computing device, and determines whether the trace is within an error tolerance range of the set of coordinates associated with the traceable image. The computing device then sends a result of the determination.
US09471764B2 Electronic device switchable to a user-interface unlocked mode based upon spoof detection and related methods
An electronic device may include a finger biometric sensor and a processor being switchable between a user-interface locked mode and a user-interface unlocked mode. The processor may cooperate with the finger biometric sensor to acquire spoof detection data based upon an object being placed adjacent the finger biometric sensor, and determine whether the acquired spoof detection data is representative of a live finger. The processor may also switch from the user-interface locked mode to the user-interface unlocked mode when the acquired spoof detection data is representative of a live finger, and cooperate with the finger biometric sensor to acquire biometric matching data. The processor may further perform finger matching based upon the acquired biometric matching data and stored biometric enrollment data.
US09471760B2 Authentication of an end user
A method and system for authenticating access of secure information by a user device. An authentication request for accessing the secure information is received, the authentication request including a user identifier of a user at the user device. A position of a secret quadrilateral within a first pattern of colored quadrilaterals is determined and is identifiable by the user identifier; the secret quadrilateral includes an authenticating color. The first pattern of colored quadrilaterals including the secret quadrilateral is generated. A second pattern including colored nodes that include the authenticating color at positions within a transparent authenticating card assigned to the user. The first pattern and the second pattern are sent to the user. Location information from the user device is received. It is determined that the subset of nodes that include the authenticating color, which allows access to the secure information by the user device.
US09471759B2 Enabling device functionality based on indoor positioning system detection of physical customer presence
A computing platform may receive a plurality of messages comprising data indicating physical presence of customers at a physical location from an indoor positioning system located at the physical location. Responsive to receiving the plurality of messages comprising the data indicating the physical presence of the customers at the physical location, the computing platform may determine that one or more customers of the customers at the physical location are authorized to utilize one or more functions of one or more computing devices physically located at the physical location.
US09471758B2 Method, a device and a computer program support for verification of checksums for self-modified computer code
A function of a software program is stored in a memory during execution in a device of the software program. A processor relocates the function in a region of the memory comprising dummy code, transforms the dummy code in a predictable manner, generates a predicted checksum for the region based on a previous checksum, generates a calculated checksum over the region, and verifies the integrity of the function by comparing the predicted checksum and the calculated checksum. Also provided are a device and a computer program product.
US09471750B2 Systems, methods and computer program product for streamlined medication dispensing
Methods, apparatuses and computer program products are provided for facilitating the expedited dispensing of medications from an automated medication storage device. In this regard, a method may cooperate with the first device to facilitate the presentation of various displays that include features to reduce number of user interactions to dispense medications safely and effectively.
US09471748B2 Method for sharing medical image data based on cloud platform, cloud platform and system
A method for sharing medical image data based on a cloud platform, a cloud platform and a system are disclosed. The cloud platform is connected to at least one medical imaging device. The method includes: receiving a medical image and/or scan data transmitted from the at least one medical imaging device; and storing, on the cloud platform, the medical image and/or scan data from the at least one medical imaging device.
US09471744B2 Triple-pattern lithography layout decomposition
Provided is a method for evaluating and decomposing a semiconductor device level for triple pattern lithography in semiconductor manufacturing. The method includes generating a conflict graph and simplifying the conflict graph using various methods to produce a simplified conflict graph which can either be further simplified or evaluated for decomposition validity. The disclosure also provides for applying decomposition validity rules to a simplified conflict graph to determine if the conflict graph represents a semiconductor device layer that is decomposable into three masks. Methods of the disclosure are carried out by a computer and instructions for carrying out the method may be stored on a computer readable storage medium.
US09471743B1 Predicting process fail limits
In an approach for predicting a process fail limit for a semiconductor manufacturing process, a computer determines a potential working process condition for each of a plurality of process parameters varied in forming a test wafer feature. The computer determines a process sigma value for each of the plurality of process parameters in forming the test wafer feature and a measurement sigma value. The computer evaluates a set of measurements of the test wafer feature compared to an acceptable wafer feature dimension, where each measurement of the set of measurements is a pass or fail as compared to the acceptable wafer feature dimension. The computer determines whether one or more fails are evaluated compared to the acceptable wafer feature dimension. The computer produces a predicted process fail limit based, at least in part, on the evaluation of fails, the measurement sigma value, and a desired target sigma value.
US09471741B1 Circuit routing based on total negative slack
A method, executed by a computer, for routing a circuit includes partitioning a netlist for a circuit into a plurality of nets, determining, for each net of the plurality of nets, a corresponding net cone to provide a corresponding plurality of net cones, computing a total negative timing slack for each net cone of the corresponding plurality of net cones, assigning routing constraints for the plurality of nets according to the total negative timing slack for the corresponding plurality of net cones, and routing the netlist according to the routing constraints. Examples of routing constraints include a routing priority, a routing weight, a scenic ratio, a wire code assignment, and a layer assignment. A corresponding computer program product and computer system are also disclosed herein.
US09471737B1 Semiconductor device with dummy cells of different data types
A method of designing a semiconductor device is provided. The method includes a step of defining a dummy structure area on the floorplan layout of the semiconductor device. The method also includes a step of adding dummy cells to the dummy structure area. Each dummy cell may be associated with a different data type. The method may improve a design optimization process of dummy cells on the semiconductor device layout by automating the removal process of dummy cells to optimize dummy density. Apart from that, semiconductor devices that are manufactured using the described method, and an apparatus to perform the steps described in the method are also described.
US09471709B1 Processing autocomplete suggestions
Methods and apparatus for processing autocomplete suggestions. Some implementations are directed to methods and apparatus for generating additional suggestions for provided multiple term autocomplete suggestions and determining additional suggestion scores for the additional suggestions. Like entries among the additional suggestions and the autocomplete suggestions may be identified and each similar grouping of the like entries combined into a consolidated entry. A combined consolidated score for each consolidated entry may be determined based on one or more of the additional suggestion scores and any of the autocomplete scores of the like entries combined into the consolidated entry.
US09471706B2 Method and system for refining a semantic search on a mobile device
System and method are disclosed for refining a semantic search query through large quantities of dynamically created concept categories and their associated extracted values on a mobile device using only two filtering controls or buttons. The first filtering control is a Semantic Categorization Filter control and the second filtering control is a Semantic Categorization Selection control. The user queries a semantic search engine using text or voice controls. The results returned to the user imply the full scope of search results along with a dynamically created semantic categorization. The most relevant semantic categorization will be considered as the pre-selected category in the Semantic Categorization Filter control along with a list of possible dynamically created sub-categorizations and the Semantic Categorization Selection control will be pre-populated with other possible semantic categorizations of the result set.
US09471702B2 System and method for exposing internal search indices to internet search engines
A system and method for exposing internal search indices to Internet search engines. The internal search indices are exposed to external search engines in such a way that the data may be segregated into at least two types including one layer of search data specifically for the search engines, and another for potential users of the application. This significantly improves the probability of discovery by search engines and also provides for presentation of discovered content to users in a manner consistent with the content itself, or consistent with the intended controls or presentations established by the content's owner. The system and method also includes one or more components that reproduce information about IP in a format that search engines can recognize and locate.
US09471695B1 Semantic image navigation experiences
Aspects of the disclosure relate to generating a sequence of images or other visual representations associated with an entity, otherwise known as a semantic image navigation experience. After an entity is selected, a set of sub-entities may be identified. Each sub-entity in the set has a containment relationship with the selected entity as well as at least one associated landmark and one associated pre-stored navigation experience. Then, a ranking order of the sub-entities in the set may be determined based on characteristics of each entity. Based on the determined ranking order, a subset of sub-entities may be selected. A semantic image navigation experience for the selected entity may then be generated using the pre-stored navigation experiences associated with the subset of sub-entities.
US09471687B2 Optimize follower and search relevancy ratio
System, method, and computer program product to perform an operation, the operation comprising publishing a content according to a content class ratio and a content impact on each of a plurality of metrics.
US09471680B2 Audio/video archiving system and method
A method of archiving audio/video content is presented. In the method, a plurality of audio/video content streams is received. Each of the received audio/video content streams is indexed according to time. Each of the indexed audio/video content streams is transferred to a data storage system for storage. A request for a portion of one of the stored audio/video content streams associated with a time period is received. The requested portion of the one of the stored audio/video content streams is retrieved from the data storage system. The requested portion of the one of the stored audio/video content streams is transferred.
US09471679B2 Systems and methods for improved coverage of input media in content summarization
The disclosed technology includes techniques for improved content coverage in automatically-generated content summaries. The technique may include clustering a set of input content, determining diffusion for each cluster, and selecting representatives of each cluster to optimize other secondary metrics. Various types of input content may be used, including groups of images, video clips, or other multimedia content. Contiguous content may be manually or programmatically divided into discrete portions before clustering, for example, a lengthy video divided into a number of short clips. In some implementations, the disclosed technique may be implemented effectively on a mobile device. In other words, the processing required may be computationally feasible for execution on a smartphone or similar device.
US09471677B2 Method and system for meta-tagging media content and distribution
A unique application within Video that allows for user generated Meta-tagging to be delivered in real time to individual clips is provided. This meta-tag creates its own tail based upon the user generated words population, which is searchable via a “spider network” that runs invisible behind the web pages of the site. These same “tagged” words are broadcast over various delivery networks including but not limited to live feeds from SMS, MMS, News Feeds within Community Web Sites, Video Sharing Web Sites, Widget applications any other forms of electronic communication that will be dropped in real time to identified users and friends of users.
US09471673B1 Audio matching using time-frequency onsets
Systems and methods are provided herein relating to audio matching. Interest points that are onsets are generally very efficient in audio matching in that they are robust to multiple types of distortion. Prominent onsets can be detected within an audio signal excerpt as interest points and combined as a function of a set of interest points to form a descriptor. Descriptors associated with an audio signal excerpt that contain a set of prominent onsets as interest points can be used in matching the audio signal excerpt to an audio reference. The benefits in generating and using prominent onsets within descriptors improve the accuracy of an audio matching system.
US09471672B1 Relevance sorting for database searches
An method for searching a database and sorting the results of a search to identify important, authoritative, and seminal records and to bring them to the front of the search result. The method comprises a means of rapidly identifying references to other records within each record and an algorithm that uses those references to identify the seminal, authoritative, and important cases. The invention may be used in legal research, permitting researches to find additional seminal documents that are missed by a standard Boolean search and to sort search results by seminality so that they can rapidly find the seminal case in an area of law.
US09471671B1 Identifying and/or recommending relevant media content
A system for identifying and/or recommending relevant media content is provided. The system includes a relevancy component, a classification component and a notification component. The relevancy component determines a topic or an event related to media content and associates the media content with a group of media content based on the topic or the event. The classification component assigns a classifier value to the media content based on data associated with the media content and the group of media content. The notification component generates a notification message associated with the media content for a user based on the classifier value and a temporal-based relevancy value generated as a function of user context.
US09471660B2 Partition lookup and state synchronization
Disclosed herein are system, method, and computer program product embodiments for multilevel synchronization of database table partition states. An embodiment operates by retrieving a partition from a partition lookup structure and determining whether the partition is in an active state. Based on a determination that the partition is in the active state an embodiment increments a counter associated with the partition using a compare-and-swap instruction accesses the partition.
US09471659B2 Providing continuous database access during database modification
The subject matter described herein relates to providing a continuous access to a database at times, including when the database is being modified or upgraded. Initially, access to an old version of a table is enabled and provided to a user. A copy of the old version is generated. Access is asynchronously redirected from the old version to the copy of the old version. A new version of the table is generated by modifying the structure of the first version of the table. The copy of the old version is accessible when the database is being modified or upgraded. When the structure is being modified, access is asynchronously redirected from the copy of the old version to the new version.
US09471655B2 Enabling symptom verification
Systems, products and methods for enabling symptom verification. Verifying a symptom may include eliminating repeated symptom definitions or eliminating symptoms having low accuracy. A computer system enables verification of a symptom including a rule for detecting a set of events related to a given problem. The computer system includes a symptom database which stores the symptom, a specimen database which stores a specimen including a set of events detected according to a rule of a certain symptom, and an analysis unit which analyzes the specimen stored in the specimen database using a new symptom in order to determine whether to add the new symptom to the symptom database. The present disclosure also includes a method and a computer program for enabling verification of a symptom including a rule for detecting a set of events related to a given problem.
US09471654B1 Modeling of a non-relational database as a normalized relational database
A system and method are disclosed for modeling a non-relational database as a normalized relational database. In one embodiment, the system identifies a column having a first type in a column-oriented, non-relational database; determines whether the column-oriented, non-relational database includes at least one column having a second type and identifies the one or more columns having the second type; virtually divides the column-oriented, non-relational database based on column type; and generates a normalized, relational model based on the virtual division of the column-oriented, non-relational database, the normalized, relational model including catalog information representing a parent table including the column having the first type and, when the column-oriented, non-relational database includes at least one column having the second type, catalog information representing a child table, the parent table and child table both represented as relational tables.
US09471650B2 System and method for contextual workflow automation
A program product, system and method, the program product comprising a non-transitory computer-readable medium, comprising computer program code comprising instructions to perform the method: receiving active content, where the active content comprises computer code for configuring a display in a first display interface; automatically matching without user intervention selected data from the active content to target category data; when there is a match, extracting data from the active content that matches object selector data, including a unique key; searching a customer database of database records using the unique key; when no records found, automatically creating new record; when one record is found, automatically updating without user intervention, items within the database record; when multiple records found, automatically determining a primary database record and automatically updating the primary database record; creating and displaying data in a second display interface from the records.
US09471649B1 Enhanced presentation mode for search results
Methods, systems, and apparatus, including computer programs encoded on a computer storage medium, for presenting search results. In one aspect, a method includes displaying a search engine results page in a first presentation mode or a second presentation mode, wherein, in the first presentation mode and the second presentation mode, the search engine results page includes (i) a text region that displays textual information relating to one or more search results that are responsive to a search query and (ii) an image region, wherein, in the first presentation mode, the image region displays contextual information relating to two or more of the search results that are responsive to the search query, and wherein, in the second presentation mode, the image region displays contextual information relating to a single search result that is responsive to the search query; and receiving a user input, then switching the search engine results page between the first presentation mode and the second presentation mode.
US09471646B2 Method and server device for exchanging information items with a plurality of client entities
The invention concerns a method of exchanging information items, e.g. HTTP headers, between a server device and a plurality of clients, and also concerns such a server device. The server device establishes connections with clients, wherein each connection involves a server-initiated indexing table for the server device to encode information items to be sent over the connection in the server-to-client direction. The method comprises the following steps performed at the server device: obtaining a same single indexing table as the server-initiated indexing table of the connections; in response to receiving a request for data from a client, pushing entries of the table to the client to configure the latter for item exchange in the server-to-client direction, encoding information items associated with the requested data using item indexing based on the table and sending the encoded information items to the client over the connection established with it.
US09471643B2 Generating ranked search results using linear and nonlinear ranking models
Generating ranked search results includes receiving a plurality of matching information items that match a search request, ranking at least some of the plurality of matching information items using a linear ranking model that linearly combines a first plurality of feature values to obtain a first set of ranked results, ranking at least some of the first set of ranked results using a nonlinear ranking model that nonlinearly combines a second plurality of feature values to obtain a second set of ranked results, and provide a search response based on the second set of ranked results.
US09471640B2 Automatic conversion of units of measure during data stream processing
Data streams are received for processing by a query. The query is associated with expected input data stream types and expected output data stream types. The received data streams are evaluated to determine if they correspond to the expected data stream types. If the received data stream types define data for a physical quantity that is defined in a unit of measure that is not the expected unit of measure, then unit conversion is required. Predefined mappings are utilized for performing required unit conversions and an optimal solution for conversion is determined. The unit conversions are performed automatically by unit conversion operators that are integrated within the process of generating of a runnable query. The runnable query is deployed and executed to generate result output streams that match the expected output stream type.
US09471636B2 Finding optimal query plans
Systems and methods for optimizing a query, and more particularly, systems and methods for finding optimal plans for graph queries by casting the task of finding the optimal plan as an integer programming (ILP) problem. A method for optimizing a query, comprises building a data structure for a query, the data structure including a plurality of components, wherein each of the plurality of components corresponds to at least one graph pattern, determining a plurality of flows of query variables between the plurality of components, and determining a combination of the plurality of flows between the plurality of components that results in a minimum cost to execute the query.
US09471635B2 Finding optimal query plans
Systems and methods for optimizing a query, and more particularly, systems and methods for finding optimal plans for graph queries by casting the task of finding the optimal plan as an integer programming (ILP) problem. A method for optimizing a query, comprises building a data structure for a query, the data structure including a plurality of components, wherein each of the plurality of components corresponds to at least one graph pattern, determining a plurality of flows of query variables between the plurality of components, and determining a combination of the plurality of flows between the plurality of components that results in a minimum cost to execute the query.
US09471632B2 Query optimization considering virtual machine mirroring costs
Techniques are disclosed for selecting between query execution plans in part based on virtual machine (VM) mirroring costs. In one embodiment, a query optimizer determines runtimes for multiple query execution plans, and modifies these runtimes based on flashing cost, which is itself determined based on the amount of memory which needs to be flashed to the secondary memory if each execution plan is executed. In so doing, the query optimizer may select a execution plan which takes a longer to run, but incurs less flashing cost. By considering both the query runtime itself and the flashing cost, the query optimizer may be better able to determine the fastest query execution plan to execute.
US09471631B2 Creating and using data that indicates misestimates of actual costs
Techniques for processing queries are provided. In one approach, an execution plan for a query includes multiple sub-plans, one or more of which are selected at runtime while one or more other sub-plans are not executed during execution of the execution plan. In another approach, data about misestimate is generated and stored persistently for subsequent queries. In another approach, statistics for a database object are generated automatically and efficiently while the database object is created or data items are added thereto. In another approach, a hybrid histogram is created that includes a feature of frequency histograms and a feature of height-balanced histograms. In another approach, computer jobs are executed in such a way to avoid deadlock. In another approach, changes to a database object trigger a hard parse of a query even though an execution plan already exists for the query.
US09471629B2 Method and apparatus for visual dynamic discovery and analytics exploration application on static and/or real-time data using an a priori model-free process
A computer system, a computer-readable non-transitory medium, and/or a computer-implemented method generates analytics applicable to data of an undetermined structure and type. A processor device receives data formatted in an undetermined structure. The processor device discovers, in a cross filter model processor, dynamically in response to receiving the data in the undetermined structure, a structure and a data type of the data which was received in the undetermined structure. The processor device determines, in response to the structure and the data type of the data discovered by the cross filter model processor, which of a plurality of analytic queries are applicable to the data.
US09471628B2 Methods and systems for calculating and retrieving analytic data
A data management system for calculating and retrieving analytic data involves a computing device coupled to a database. The system includes a plurality of data structures such as database tables. The data structures include a measure data structure including a measure-data element, a collection data structure including a collection-data element, and a fact data structure configured to store a fact-data element including an aggregated value. The aggregated value refers to the result generated by a query computation performed on a transaction database. The system includes a fact-analyzer module configured to generate the aggregated value from the transaction data utilizing the measure-data element and the collection-data element, wherein the measure-data element defines how the aggregated value is calculated. The fact-analyzer module is also configured to store the aggregated value and links to the measure-data element and the collection-data element in the fact-data element.
US09471626B2 Enhanced answers in DeepQA system according to user preferences
A semantic search engine is enhanced to employ user preferences to customize answer output by, for a first user, extracting user preferences and sentiment levels associated with a first question; receiving candidate answer results of a semantic search of the first question; weighting the candidate answer results according to the sentiment levels for each of the user preferences; and producing the selected candidate answers to the first user. Optionally, user preferences and sentiment levels may be accumulated over different questions for the same user, or over different users for similar questions. And, supplemental information may be retrieved relative to a user preference in order to further tune the weighting per the preferences and sentiment levels.
US09471623B2 Empathy injection for question-answering systems
Exemplary methods and devices herein receive an inquiry and automatically analyze words used in the inquiry, potential answers, and data maintained by evidence sources using the computerized device to determine the sensitivity level associated with the inquiry. The sensitivity level associated with the inquiry represents an emotional and cognitive state of the user. Such methods and devices automatically generate at least one follow-up question based on the sensitivity level associated with the inquiry and receive a follow-up response into the computerized device in response to the follow-up question(s). The methods and devices also automatically produce scores for the potential answers using the computerized device based on the inquiry, the follow-up responses, and ratings of the evidence sources. Following this, these methods and devices automatically generate output answers to the inquiry based on the sensitivity level associated with the inquiry using the computerized device.
US09471617B2 Schema evolution via transition information
Disclosed herein are system, method, and computer program product embodiments for transforming data from a first version, for example an initial version of a database, to a second version, for example a subsequent version of a database. An embodiment operates by modifying the metadata of the data to include transformational clauses, each of which describes how a portion of the data in the first version is transformed to data required by the second version.
US09471613B2 Methods and systems for indexing references to documents of a database and for locating documents in the database
Methods and systems allow indexing references to documents of a database according to database reference profiles. Documents may then be located in the database using decoding protocols based on the database reference profiles. To this end, the documents are stored in the database and searchable terms extracted therefrom are associated with posting lists. Each posting list is divided into blocks of M database references. The blocks are encoded according to a pattern that depends on the M database references. A corresponding pointer to a table of encoding patterns is appended to each block. When a query is received for a searchable term, blocks are extracted from a posting list corresponding to the searchable term and a pointer for each block is used to extract a decoding protocol related to an encoding pattern for the block.
US09471611B2 Distributed scalable policy based content management
A method for defining and constraining the behavior of a shared, mobile content management system is disclosed. The method includes providing an admin console for defining, modifying, and managing declarative policies. Declarative policies are defined based on an XML policy model. The XML policy model dictates the policies that can be expressed by the admin console. The defined declarative policies are enacted without requiring the content management system to be restarted, reconfigured, or re-implemented. An XML-based policy wizard definition language is provided to define policy wizards in the admin console that guide an administrator through the steps of creating and editing the policies. Additionally, at least one policy repository based on LDAP is provided. The at least one policy repository has an interface and is adapted to store a plurality of declarative policies. The policy repository has scalable and distributed capabilities.
US09471609B2 Data cleansing tool with new cleansing tree
A system and method of de-duplicating data using a graphical user interface application. The graphical user interface application represents a model of the selected data records in a data tree. The graphical user interface application processes a selected target data record and potential duplicates data records. Nodes representing the potential duplicate data records can be added to the target data record. Nodes representing the potential duplicate data records can also be dragged and dropped into a node of the target data record. Nodes from the target data record can also be removed from the target data record. Differences between data associated with multiple nodes can be graphically presented with the graphical user interface application when multiple nodes are selected. Changes made to the data tree in the graphical user interface are applied to data records stored in a database.
US09471608B2 Method, apparatus and computer program for migrating records in a database from a source database schema to a target database schema
There is disclosed a method, apparatus and computer program for migrating records in a database from a source database schema to a target database schema. A request is received to delete a state from the source schema. The state is marked as the redundant state. A resultant state is identified to which to migrate database records in the redundant state and a valid migration path is calculated between the redundant state and the resultant state.
US09471607B2 Data loading tool
In an exemplary embodiment of this disclosure, a method for loading data from a backup image of a database includes selecting a subset statement defining a subset of the data in the database. Tables of the database are identified based on metadata of the database. A target database is written having the structure but not the data of the identified tables. One or more table statements are constructed, by a computer processor, defining a subset of each identified table based on the subset statement. Selected data is unloaded from a backup image into the target database using respective table statements as filters.
US09471597B2 Three-dimensional annotations for street view data
The present invention relates to annotating images. In an embodiment, the present invention enables users to create annotations corresponding to three-dimensional objects while viewing two-dimensional images. In one embodiment, this is achieved by projecting a selecting object onto a three-dimensional model created from a plurality of two-dimensional images. The selecting object is input by a user while viewing a first image corresponding to a portion of the three-dimensional model. A location corresponding to the projection on the three-dimensional model is determined, and content entered by the user while viewing the first image is associated with the location. The content is stored together with the location information to form an annotation. The annotation can be retrieved and displayed together with other images corresponding to the location.
US09471596B2 Systems and methods for processing search queries utilizing hierarchically organized data
Computerized systems and methods are provided for generating results of a search query. In accordance with some implementations, data is received that is indicative of a character string related to a location and provided as input by a user. One or more hierarchically organized data trees are retrieved, from a storage device, for administrative areas related to the input character. Thereafter, probable target addresses are determined for the location utilizing the hierarchically organized data trees for each of the administrative areas, and a list of probable target addresses is provided for display to the user based on the hierarchy of the administrative areas.
US09471595B1 Recovering file mapping information in file systems
A method is used in recovering file mapping information in file systems. Metadata of a file of a file system is evaluated. Mapping information associating the file to a file system hierarchy of the file system is missing a reference to an inode of the file. Based on the evaluation, the mapping information is updated for including the file to the file system hierarchy of the file system.
US09471594B1 Defect remediation within a system
Defect remediation in a system is disclosed. A defect is mapped to one or more remediation actions, at least in part by using a processor to generate and perform a defect-based query against one or more structured remediation action records. A remediation package is generated using the processor. The remediation package may include the one or more remediation actions and data associated with the defect. The remediation package may be sent to a destination associated with the defect.
US09471592B2 File management system, method and computer program
A file management system that provide a record file rapidly to a terminal, request source, by saving a record file to a storage device set at the local area, and to make it possible to refer it. A first device creates the record file and attribute information indicating the attribute about the record file, stores the record file in a first storage unit, and transmits the attribute information to the second device through the network. A second device receives the attribute information and the record file transmitted from the first device and stores them in a second storage unit. The terminal requests to acquire the record file based on the acquired attribute information to the first device or the second device. The first device or the second device transmits the record file requested to the terminal.
US09471586B2 Intelligent selection of replication node for file data blocks in GPFS-SNC
A mechanism is provided in a data processing system for replicating writing of a file with striping. The mechanism writes a file at an owner node within a plurality of nodes in a data processing system. The mechanism divides the file into a plurality of file chunks. The mechanism identifies at least one replication node within the plurality of nodes having a duplicate copy of a respective file chunk within the plurality of file chunks. The mechanism selects a plurality of replication nodes for the plurality of file chunks based on identification at least one replication node within the plurality of nodes having a duplicate copy of a respective file chunk and replicates the file at the plurality of replication nodes based on the selection of the plurality of replication nodes.
US09471583B2 Data race analysis with improved detection filtering
A method according to one embodiment includes the operations of receiving a list of one or more data race analysis targets, wherein the data race analysis targets comprise at least one of a source file name, source file line, function name, variable name or target address range; generating a data race analysis filter, wherein the data race analysis filter comprises a data structure including memory address ranges based on the list of data race analysis targets; and performing a data race analysis on a memory access, wherein the memory access is associated with memory addresses included in the data race analysis filter.
US09471582B2 Optimized pre-fetch ordering using de-duplication information to enhance network performance
A computer determines a degree of information duplication between at least two files included in an original pre-fetch list. The computer generates a re-ordered pre-fetch list by re-ordering the files included in the original pre-fetch list. The re-ordering is based, at least in part, on the degree of information duplication between the two files included in the original pre-fetch list. The files included in the original pre-fetch list are re-ordered by grouping files containing higher degrees of duplicate information closer together in the re-ordered pre-fetch list.
US09471574B2 Property list customization
Technologies are generally described for customization of a list of properties associated with media files based at least in part on user's preferences. In some examples, a method may include receiving, by a server, a plurality of user inputs that respectively identify the user's designated favorites from among a plurality of media files; determining, by the server, the user's preferences from among a plurality of properties associated with the user's designated favorites from among the plurality of media files, based at least in part on the received user inputs; and providing, by the server, the user with a list of the plurality of properties based at least in part on the user's preferences from among the plurality of properties.
US09471573B2 User preference based collecting of music content
A method of operating an entertainment system includes computer-implemented steps including determining an audio/video preference profile of the user. An item of audio/video content that fits the profile but that is not available to the system is identified. The identified item is wirelessly received from a source of audio/video content. The source is external to the entertainment system. The received item is stored in memory within the system. The stored item is retrieved from memory. The retrieved item is played back to a human user of the system.
US09471572B1 Recommending candidates for consumption
Methods and apparatus are described herein for recommending candidates for consumption. A first set of one or more candidates for first time consumption by a user and associated utility scores may be identified. A second set of one or more candidates for reconsumption by the user may be determined. Utility scores of the second set of one or more candidates for reconsumption may be determined based on consumption history of the user and aggregate consumption history of a population of users of which the user is associated. A candidate to be recommended to the user for consumption may be selected from the first or second set. The candidate may be selected based at least in part on the utility scores of the first and second sets.
US09471571B2 Digital media album creator
A computerized method is provided that includes (a) receiving from the user a selection of one of a plurality of templates for the digital media album; (b) receiving from the user a subset of media album components; (c) in response to a user input, compiling an interim multimedia album using the selected template, the subset of media album components, and default data for each media album component not included in the subset of media album components, and thereafter displaying to the user the interim multimedia album; (d) receiving from the user additions to the subset of the media album components, and repeating step (c) with the subset including said additions; (e) receiving from the user further additions to the subset of the media album components until all of said media album components are received; and (f) compiling the created multimedia album using the selected template and said media album components.
US09471568B2 Speech translation apparatus, speech translation method, and non-transitory computer readable medium thereof
According to one embodiment, a speech of a first language is recognized using a speech recognition dictionary to recognize the first language and a second language, and a source sentence of the first language is generated. The source sentence is translated into a second language, and a translation sentence of the second language is generated. An unknown word included in the translation sentence is detected. The unknown word is not stored in the speech recognition dictionary. A first pronunciation candidate of the unknown word is estimated, from a representation of the unknown word. A second pronunciation candidate of the unknown word is estimated from a pronunciation of an original word included in the source sentence corresponding to the unknown word. The unknown word, the first pronunciation candidate and the second pronunciation candidate, are registered into the speech recognition dictionary correspondingly.
US09471563B2 Systems, methods and media for translating informational content
Systems, methods, and media for translating informational content via a publishing server are provided herein. Methods may include receiving a request for informational content from a visitor device, the request including a language preference, responsive to the request, locating informational content stored in a database based upon analytical data corresponding to the visitor device, translating at least a portion of the informational content utilizing the language preference of the request if a language of the informational content does not correspond to the language preference of the request, and storing the translated at least a portion of the informational content in the database associated with the publishing server.
US09471561B2 Adaptive parser-centric text normalization
Embodiments of the present invention relate to a customizable text normalization framework providing for domain adaptability through modular replacement generators. In one embodiment, a method of and computer program product for text normalization are provided. An input sequence comprising a plurality of tokens is received. A plurality of generators is applied to the input sequence to generate a set of candidate replacements of the tokens of the sequence. A plurality of subsets of the set of candidate replacements is determined such that the candidate replacements of each subset are syntactically consistent. A probability is determined for each of the subsets. A subset of the plurality of subsets having the highest probability is selected. Each candidate replacement of the selected subset is applied to the input sequence to generate an output sequence. The output sequence is outputted.
US09471559B2 Deep analysis of natural language questions for question answering system
Creating training data for a natural language processing system may comprise obtaining natural language input, the natural language input annotated with one or more important phrases; and generating training instances comprising a syntactic parse tree of nodes representing elements of the natural language input augmented with the annotated important phrases. In another aspect, a classifier may be trained based on the generated training instances. The classifier may be used to predict one or more potential important phrases in a query.
US09471552B1 Optimization of scripting for web applications
A method of reprioritizing execution of a script is disclosed. At least a portion of the script is partitioned into a plurality of component functions. At least one of the plurality of component functions is encapsulated with a wrapper component function. The initial loading of at least one of the plurality of component functions is selectively disabled. A modified script including at least one wrapper component function is generated. In some embodiments, profiling of the plurality of component functions is performed by collecting usage information of the plurality of component functions. In some embodiments, the selective disabling of the initial loading of a component function is based at least in part on the collected usage information of the plurality of component functions.
US09471550B2 Method and apparatus for document conversion with font metrics adjustment for format compatibility
Method and apparatus for converting a document from a fixed-layout format (e.g., Microsoft Office, Adobe PDF) into a non-fixed layout format (e.g., HTML) portable to different platforms (e.g., desktop computers, tablet computer, smart phones) operating different operating systems (e.g., Microsoft Windows, Apple OS X) and different web browsers (e.g., Microsoft Internet Explorer, Apple Safari, Mozilla FireFox). In one stream, fonts are identified, extracted, and processed to enhance compatibility with the portable format. In another stream, textual content is extracted and processed to enhance compatibility and images are taken of non-textual content. These images are used as backgrounds in the output document, over which the textual content is rendered in the appropriate fonts, with sizing, spacing, positioning and/or other characteristics matching or closely approximating that of the original document. Error detection is applied by comparing images of the original document to corresponding images of the output document, to ensure high fidelity.
US09471546B2 System for generating reconfigurable web application
A system for generating an On-Demand reconfigurable Web application that provides create/read/update/delete-functionality on data managed in one or more external data sources. An XML-based definition is accessed to learn of desired create/read/update/delete-functionality in pre-defined form, graphical interfaces (GUIs) on functionality, non-typed definitions of data in the data sources, as well as data logic related to the data sources and the various relationships between these items. Upon request the definition is parsed and one of the GUIs is presented or some of the defined functionality is executed. An abstraction layer is used to obtain access to the data managed in the external data sources and On-Demand-Instantiation is applied to type the non-typed objects within the context of the definition of the functionality being executed.
US09471539B2 Method and devices for determining noise variance for gyroscope
Methods and devices for determining a noise variance of an axis of a gyroscope are described. In one aspect, the method includes: representing a plurality of gyroscope readings for the axis in a histogram, the histogram including a plurality of bins associated with respective ranges; determining a bias for the axis of the gyroscope by identifying a concentration of the gyroscope readings within the histogram; and determining a noise variance for the axis of the gyroscope based on the histogram and based on the identified concentration of gyroscope readings.
US09471532B2 Remote core operations in a multi-core computer
A multi-core processor with a shared physical memory is described. In an embodiment a sending core sends a memory write request to a destination core so that the request may be acted upon by the destination core as if it originated from the destination core. In an example, a data structure is configured in the shared physical memory and mapped to be accessible to the sending and destination cores. In an example, the shared data structure is used as a message channel between the sending and destination cores to carry data using the memory write request. In an embodiment a notification mechanism is enabled using the shared physical memory in order to notify the destination core of events by updating a notification data structure. In an example, the notification mechanism triggers a notification process at the destination core to inform a receiving process of a notification.
US09471529B2 Embedded storage device including a plurality of storage units coupled via relay bus
An embedded storage device for use with a computer device is provided. The embedded storage device includes a microprocessor, a master storage unit, a slave storage unit, and a relay bus. The microprocessor provides a clock signal and creates data transmission link to the computer device. The master storage unit has a master clock pin, at least a master data pin, and a master control pin. The master control pin receives a command signal from the microprocessor. The slave storage unit has a slave clock pin and at least a slave data pin. The relay bus is coupled to the master storage unit and the slave storage unit to enable communication between the master storage unit and the slave storage unit, such that the command signal from the microprocessor is sent from the master storage unit to the slave storage unit via the relay bus.
US09471527B2 Semiconductor device and memory system
A semiconductor device capable of communicating with a host apparatus includes a symbol generation unit, a coding unit, and a transmission unit. The symbol generation unit includes a random number generation circuit and generates a symbol according to a random number generated by the random number generation circuit. The coding unit performs 8b/10b coding for the symbol. The transmission unit transmits the symbol coded by the 8b/10b coding unit to the host apparatus.
US09471526B2 Bridge between two different controllers for transferring data between host and storage device
A system including a controller and a bridge module. The controller is configured to (i) communicate with a host via a first interface, and (ii) communicate with a storage device via a second interface. The second interface is separate from the first interface. The bridge module is configured to allow the controller to transfer data between the storage device and the host without buffering the data, and to access a memory of the host via the first interface during the transfer.
US09471523B2 Serial interface systems and methods having multiple modes of serial communication
An enhanced serial interface system is disclosed. The system includes a master component and a slave component. The master component is configured to operate in a standard mode and an enhanced mode for communication. The master component includes standard terminals and hybrid terminals. Only the standard terminals are used for communicating in the standard mode. The hybrid terminals and the standard terminals are used for communicating in the enhanced mode. The slave component is configured to operate in the enhanced mode and communicate with the master component.
US09471521B2 Communication system for interfacing a plurality of transmission circuits with an interconnection network, and corresponding integrated circuit
A communication system is arranged to interface a plurality of transmission circuits with an interconnection network. Each transmission circuit generates read requests and/or write requests. The communication system includes a first circuit that operates independently of the communication protocol of the interconnection network. In particular, the first circuit includes, a) for each transmission circuit a communication interface configured for receiving the read requests and/or write requests from the respective transmission circuit, b) a segmentation circuit configured for dividing, i.e., segmenting, the read requests and/or write requests received from the transmission circuits into transfer segments, and c) an interleaving circuit configured for generating, via an operation of interleaving of the transfer segments, a series of segments. The communication system also includes a second circuit configured for converting the transfer segments of the series of segments into data packets according to the protocol of the interconnection network and for transmitting the data packets to the interconnection network.
US09471520B2 Controlling operations according to another system's architecture
An I/O device operating according to a native computer architecture is accessed by a primary computer system operating according to a primary computer architecture. An application program of the primary computer system requests an I/O operation to access the I/O device. To facilitate this access, an application program interface formed of primary instructions for execution by the primary processor processes the I/O operation to provide an I/O request and to receive an interrupt in response to completion of the access. A thread is formed of primary instructions for execution by the primary processor for receiving the interrupt from the application program interface. A subsystem operates in response to the I/O request to access the I/O device and to provide the interrupt.
US09471511B2 System and methods for CPU copy protection of a computing device
The present disclosure relates to techniques for system and methods for software-based management of protected data-blocks insertion into the memory cache mechanism of a computerized device. In particular the disclosure relates to preventing protected data blocks from being altered and evicted from the CPU cache coupled with buffered software execution. The technique is based upon identifying at least one conflicting data-block having a memory mapping indication to a designated memory cache-line and preventing the conflicting data-block from being cached. Functional characteristics of the software product of a vendor, such as gaming or video, may be partially encrypted to allow for protected and functional operability and avoid hacking and malicious usage of non-licensed user.
US09471510B2 System and method for cache monitoring in storage systems
A system and method of cache monitoring in storage systems includes storing storage blocks in a cache memory. Each of the storage blocks is associated with status indicators. As requests are received at the cache memory, the requests are processed and the status indicators associated with the storage blocks are updated in response to the processing of the requests. One or more storage blocks are selected for eviction when a storage block limit is reached. As ones of the selected one or more storage blocks are evicted from the cache memory, the block counters are updated based on the status indicators associated with the evicted storage blocks. Each of the block counters is associated with a corresponding combination of the status indicators. Caching statistics are periodically updated based on the block counters.
US09471505B2 Efficient multi-threaded journal space reclamation
A method for reclaiming space in a journal is disclosed. In one embodiment, such a method includes identifying a plurality of ranks in a storage system. The method creates a destage wait list for each rank, where the destage wait list identifies metadata tracks to destage from a cache to the corresponding rank. The method dispatches one or more threads for each destage wait list. The threads destage metadata tracks identified in the destage wait lists from the cache to the corresponding ranks. In certain embodiments, the method moves metadata tracks to the destage wait lists only if performing such will not cause occupied space in the journal to fall below a low watermark. Once metadata tracks are destaged from the cache, the method releases, from the journal, entries associated with the destaged metadata tracks. A corresponding system and computer program product are also disclosed.
US09471498B2 Memory card access device, control method thereof, and memory card access system
The present invention discloses a memory card access device, the control method thereof and a memory card access system. Said device comprises: a memory card interface circuit to generate card-read data according to a card-read signal or generate a card-writing signal according to card-writing data; a host interface circuit to generate host-read data according to a host-read signal or generate the host-writing signal according to host-writing data; and a control circuit, coupled to the memory card and host interface circuits respectively, operable to generate the host-writing data by processing the card-read data according to a predetermined cache protocol or generating the card-writing data by processing the host-read data according to the predetermined cache protocol, so as to treat a memory card as a cache device.
US09471493B2 Invalidation of index items for a temporary data store
A data processing apparatus and corresponding method of data processing are provided. The data processing apparatus comprises a temporary data store configured to store data items retrieved from a memory, wherein the temporary data store selects one of its plural data storage locations in which to store a newly retrieved data item according to a predetermined circular sequence. An index data store is configured to store index items corresponding to the data items stored in the temporary data store, wherein presence of a valid index item in the index data store is indicative of a corresponding data item in the temporary data store. Invalidation control circuitry performs a rolling invalidation process with respect to the index items stored in the index data store, comprising sequentially processing the index items stored in the index data store and selectively marking the index items as invalid according to a predetermined criterion.
US09471490B2 Dynamically controlling cache size to maximize energy efficiency
In one embodiment, the present invention is directed to a processor having a plurality of cores and a cache memory coupled to the cores and including a plurality of partitions. The processor can further include a logic to dynamically vary a size of the cache memory based on a memory boundedness of a workload executed on at least one of the cores. Other embodiments are described and claimed.
US09471488B2 Techniques for improving reliability and performance of partially written memory blocks in modern flash memory systems
Methods and apparatus to improve reliability and/or performance of partially written memory blocks in flash memory systems are described. In some embodiments, a storage device stores information corresponding to a partial write operation performed on a partially programmed memory block of a non-volatile memory. Memory controller logic then cause application of a reduced voltage level and/or an offset value to portion(s) of the non-volatile memory during a read or write operation to the non-volatile memory based at least in part on the stored information. Other embodiments are also disclosed and claimed.
US09471484B2 Flash memory controller having dual mode pin-out
A memory controller of a data storage device, which communicates with a host, is configurable to have at least two different pinout assignments for interfacing with respective different types of memory devices. Each pinout assignment corresponds to a specific memory interface protocol. Each memory interface port of the memory controller includes port buffer circuitry configurable for different functional signal assignments, based on the selected memory interface protocol to be used. The interface circuitry configuration for each memory interface port is selectable by setting a predetermined port or registers of the memory controller.
US09471483B2 Electronic apparatus having non-volatile memory and method for controlling the same
Electronic apparatus, comprising: non-volatile memory configured to be written to or read from in memory portions which are erased a sector at a time, each said sector comprising a plurality of said portions, and the memory having at least three said sectors each of which is adapted to be erased independently of the others; and control means operable to control erasing of the sectors, wherein: the control means is configured to store in a plurality of the sectors other than a target said sector erasure information concerning an erasure procedure, the erasure procedure involving erasing the target sector, so that such information in the sectors may be inspected to establish a suitable recovery procedure following an interruption event.
US09471480B2 Data processing apparatus with memory rename table for mapping memory addresses to registers
A data processing apparatus has a memory rename table for storing memory rename entries each identifying a mapping between a memory address of a location in memory and a mapped register of a plurality of registers. The mapped register is identified by a register number. In response to a store instruction, the store target memory address of the store instruction is mapped to a store destination register and so the data value is stored to the store destination register instead of memory. A memory rename entry is provided in the table to identify the mapping between the store target memory address and store destination target register. In response to a load instruction, if there is a hit in the memory rename table for the load target memory address then the loaded value can be read from the mapped register instead of memory.
US09471478B1 Test machine management
A computer-implemented method includes creating a test suite, wherein the test suite includes a plurality of test cases for execution on a plurality of test agents. The method distributes a first portion of test cases to any available test agents, wherein each test case out of the first portion of test cases does not have any associated preconditions. The receives test results and event information for a first test case out of the first portion of test cases from a first test agent. Responsive to determining the event information for the first test case includes a satisfied condition for a second test case with one or more associated preconditions, the method determines whether the satisfied condition for the second test case relates to a global variable or local variable.
US09471477B2 Monitoring and capturing early diagnostic data
A deviance monitoring module is provided for examining various parameters of an operating system for deviance from a baseline behavior at specified intervals. A range of acceptable deviance values from a baseline behavior is set for parameters of an operating system. The parameters of the operating system are then monitored at specified intervals for deviance from the baseline behavior. In response to detecting that the deviance exceeds a predetermined threshold, the method triggers diagnostic data gathering on the parameters of the operating system according to an embodiment.
US09471474B2 Cloud deployment infrastructure validation engine
Embodiments of the invention provide a set of validators that can be used to determine whether an installation is operating within desired parameters and is in compliance with any requirements. The validators may be provided with a software application or release, for example, and may be run during and/or after installation to test the application operation. A set of self-healing operations may be triggered when faults are detected by the validators. This allows a software application to auto-diagnose and auto-self-heal any detected faults.
US09471468B2 System, method, and computer program to improve the productivity of unit testing
A method, system, and computer program for improving productivity of code development is provided. The method includes calculating an edge weight between nodes of a directed graph for a code project, where the nodes include a source node and a sink node, the source node corresponds to a method and the sink node corresponds to a testcase, calculating a flow value from an identified source node to the sink node, where the identified source node includes a source file of the method that has been changed and generating a list of testcases that correspond the sink node whose calculated flow value is greater than or equal to a threshold flow value.
US09471465B2 Trace value correlation with data field declarations
Data fields within a trace data set are interpreted using data field declarations of the data fields that each specify a data type definition of a respective data field. A data value of an interpreted data field is compared with the data type definition specified within a respective data field declaration for the interpreted data field within the trace date set. Based upon the comparison, a determination is made that the respective interpreted data field contains a data value that violates the data type definition specified within the respective data field declaration.
US09471464B1 Debug management using dynamic analysis based on state information
Disclosed aspects include a debugger evaluating an expression. The expression has a debug element. Using dynamic analysis, a set of state information related to the debug element is identified. The set of state information can be generated external to the debugger and used within the debugger subsequent to being generated. Utilizing the set of state information, a tolerance parameter is selected. The tolerance parameter is for a conditional breakpoint linked with the debug element. In response to selecting the tolerance parameter, a triggering event for the conditional breakpoint may be detected. Based on the tolerance parameter, it may be determined to disregard the triggering event. Subsequently, the triggering event can be disregarded. Altogether, aspects of the disclosure provide a methodology for debug management that may provide performance or efficiency benefits.
US09471461B2 Guarding a monitoring scope and interpreting partial control flow context
A computer implemented method for maintaining a program's calling context correct even when a monitoring of the program goes out of a scope of a program analysis by validating function call transitions and recovering partial paths before and after the violation of the program's control flow. The method includes detecting a violation of control flow invariants in the software system including validating a source and destination of a function call in the software system, interpreting a pre-violation partial path responsive to a failure of the validating, and interpreting a post violation path after a violation of program flow.
US09471450B2 Reducing data loss in a computing storage environment
For reducing data loss by a processor device in a computing storage environment, data blocks are prioritized for creating an N number of additional secondary copies of data using a vulnerability factor for identifying those of the data blocks having a probability of failure. The data blocks include at least a primary copy and a secondary copy of the data.
US09471436B2 Use of incremental checkpoints to restore user data stream processes
A method and system on failure recovery in a storage system are disclosed. In the storage system, user data streams (e.g., log data) are collected by a scribeh system. The scribeh system may include a plurality of Calligraphus servers, HDFS and Zookeeper. The Calligraphus servers may shard the user data streams based on keys (e.g., category and bucket pairs) and stream the user data streams to Puma nodes. Sharded user data streams may be aggregated according to the keys in memory of a specific Puma node. Periodically, aggregated user data streams cached in memory of the specific Puma node, together with a Incremental checkpoint, are persisted to HBase. When a specific process on the specific Puma node fails, Ptail retrieves the Incremental checkpoint from HBase and then restores the specific process by requesting user data streams processed by the specific process from the scribeh system according to the Incremental checkpoint.
US09471435B2 Information processing device, information processing method, and computer program
An information processing device includes: a nonvolatile memory having a program area storing a program for booting a system, and backup areas each storing a backup program identical in content to the program; a process executing unit that executes the program to perform a boot process of the system; an error detection unit that performs error detection on the program in parallel with the boot process; and a reboot unit that, when the error detection unit detects an error in the program, performs a recovery process to replace the program with one of the backup programs, and reboots the system using the replaced program. In the recovery process, the reboot unit refers to history information indicating a history of replacement of the program with the backup programs, selects the backup program used for the replacement from among the backup programs, and replaces the program with the selected backup program.
US09471434B2 Storage system and storage system failure management method
When a failure occurs in a storage system controller, the controller reboots after completing prescribed failure processing for respective control parts. Upon detecting a failure, first, second, and third control parts of the controller perform respective failure processing. The first control part controls block access requests, the second control part controls file system access, and the third control part manages the second control part. The first control part and third control part write prescribed information to a storage area and reboot at least a portion of the controller upon detecting the failure.
US09471430B2 Semiconductor device and semiconductor system including the same
A semiconductor device includes an internal circuit configured to perform a specified operation in response to a predetermined command; a normal data input/output section configured to input/output a normal data synchronized with a center of a source clock, in response to data input/output commands; and a data recovery information signal input/output block configured to receive and store a data recovery information signal synchronized with an edge of the source clock and having a predetermined pattern, in response to either a command of the data input/output commands or the predetermined command upon entry to a data recovery operating mode, and to output the data recovery information signal after the passage of a predetermined time period.
US09471429B2 Scalable protection scheme for protecting destaged data units
A method for disk failure protection, the method may include calculating a first set of parity units by processing a first group of sets of data units that are cached in a cache memory of a storage system; calculating a second set of parity units by processing the first group of sets of data units; wherein the calculating of the second set of parity units is responsive to a first shift that was virtually introduced between each set of data units of the first group of sets of data units; and destaging the first group of sets of data units and the first and second sets of parity units to the first group of disks.
US09471421B2 Data accessing method, memory storage device and memory controlling circuit unit
A data accessing method, a memory storage device and a memory controlling circuit unit are provided. The data accessing method includes: determining whether a first physical programming unit storing first data belongs to a first type physical programming unit or a second type physical programming unit; if the first physical programming unit belongs to the first type physical programming unit, generating a first verification code corresponding to the first data and a second verification code for being combined with the first verification code, and writing the first data and the first verification code into the first physical programming unit; and if the first data is decoded unsuccessfully by using the first verification code, combining the second verification code and the first verification code to decode the first data.
US09471418B2 Memory system that detects bit errors due to read disturbance and methods thereof
Methods and memory systems are provided that can detect bit errors due to read disturbances. A main page of a flash memory in a memory system is read. A bit error in data that is read from the main page is detected and corrected. In parallel with reading the main page, a bit error is detected in data that is read from a dummy page of the flash memory.
US09471417B1 Methods and apparatus for back-annotating errors in a RRAM array
A two-terminal memory array can be configured to address a single memory cell. A two-terminal memory array can further be configured to mitigate disturb errors associated with other types of memory (e.g., non-two-terminal memory such as NAND flash memory). Mitigation of disturb errors can allow re-writes and/or overwrites of data stored by the cells without a prior erase operation. In this regard, errors in the data read from a memory array can be corrected by error-correction code (ECC) and associated corrected data can be written back to the memory cells that store the portions of data determined by the ECC to be erroneous data and/or incorrect or bad data.
US09471414B2 Service response detection and management on a mobile application
Techniques for detecting and addressing performance issues related to a mobile application are provided. Examples of performance issues include a backend service (to which the mobile application is configured to transmit requests) becoming unavailable or overloaded, a third-party service that the mobile application relies on for data pertaining to the backend service becoming unavailable, and security vulnerabilities or code irregularities in the code of the mobile application. A fallback service that is separate from the backend service detects the performance issues and sends fallback data to the mobile application. The fallback data may cause the mobile application to operate in an offline mode, where the mobile application requests locally stored data instead of transmitting data requests to the backend service. The fallback data may reference page views that the mobile application downloads and displays instead of other page views that are based on data from the backend service.
US09471413B2 Memory device with secure test mode
A method in a memory device that operates in a testing mode, includes receiving a vector to be written to the memory device. The vector is written to the memory device only if the vector belongs to a predefined set of test vectors. If the vector does not belong to the set of test vectors, the vector is converted to one of the test vectors, and the converted vector is written to the memory device.
US09471411B2 Monitoring and capturing early diagnostic data
A deviance monitoring module is provided for examining various parameters of an operating system for deviance from a baseline behavior at specified intervals. A range of acceptable deviance values from a baseline behavior is set for parameters of an operating system. The parameters of the operating system are then monitored at specified intervals for deviance from the baseline behavior. In response to detecting that the deviance exceeds a predetermined threshold, the method triggers diagnostic data gathering on the parameters of the operating system according to an embodiment.
US09471409B2 Processing of PDSE extended sharing violations among sysplexes with a shared DASD
Method, system, and networked embodiments for processing PDSE extended sharing violations are provided. A single special page referred to as a “sync” page is added to the PDSE dataset. The sync page is loaded from DASD to local cache at PDSE dataset open and remains open until the last close of the PDSE dataset. The in-core version of the sync page maintains a list of index update records for all computer systems within a sysplex and the on-DASD version of the sync page maintains a list of index update records for all computer systems connected to shared DASD. By leveraging properties of the sync page, and more particularly by monitoring any divergence in the in-core and on-DASD sync pages, a PDSE error handling module can programmatically determine when a PDSE dataset has been accessed by a rogue system, diagnose the type of error associated with the rogue update, log and notice of all systems in the sysplex of the error (and eventually connected systems outside the sysplex) and, for certain types of errors, fix the PDSE dataset.
US09471407B2 Parametrizable system for centralized maintenance intended for an aircraft
A system for centralized maintenance, intended for an aircraft comprising a set of devices necessary for the flight and able to issue fault messages or alert messages, the maintenance system being able to communicate with this set of devices, comprises a software kernel parametrizable by means of a database of parameters, the software kernel comprising at least four elementary cells: a first cell for acquiring the fault messages and alert messages originating from the set of devices of the aircraft, a second cell for formulating a maintenance diagnosis defined by means of the fault messages and alert messages, a third cell for formulating and displaying a maintenance report to a maintenance operator of the aircraft, defined on the basis of the maintenance diagnosis, a fourth cell for communicating between the maintenance operator and the set of devices of the aircraft.
US09471405B1 Methods and systems for access to legacy programs using non-legacy interfaces
Development of interfaces for legacy programs. A system includes a client device displaying a series of screens output from a legacy program in a terminal emulator. The system further includes a tracking module logging activity in the terminal emulator in a trail file, and an analysis module adapted to analyze the trail file and produce, based on the analysis, a REST API based upon the analysis that supports a collection of different REST API calls corresponding to the series of screens output from the legacy program. The REST API is a stateless API utilized in a stateful manner in which each REST API call of the collection of REST API calls provides direct access to a corresponding screen of the series of screens.
US09471404B1 Enriching API registry using big data analytics
For data integration using APIs, a request for data is analyzed to determine a set of functional characteristics and a set of non-functional characteristics expected in the data. A first API entry is selected in a registry of API entries, the first API entry corresponding to a first API of the first data source. The first API entry includes a first metadata corresponding to a first functional characteristic in the set of functional characteristics. The first API is invoked to obtain a first portion of the data, the first portion having the first functional characteristic. Using a second API entry in the registry, a second API is invoked to obtain a second portion of the data. The first portion and the second portion are returned in a response to the request.
US09471401B2 Parallel runtime execution on multiple processors
A method and an apparatus that schedule a plurality of executables in a schedule queue for execution in one or more physical compute devices such as CPUs or GPUs concurrently are described. One or more executables are compiled online from a source having an existing executable for a type of physical compute devices different from the one or more physical compute devices. Dependency relations among elements corresponding to scheduled executables are determined to select an executable to be executed by a plurality of threads concurrently in more than one of the physical compute devices. A thread initialized for executing an executable in a GPU of the physical compute devices are initialized for execution in another CPU of the physical compute devices if the GPU is busy with graphics processing threads.
US09471399B2 Orderable locks for disclaimable locks
Systems and methods of protecting a shared resource in a multi-threaded execution environment in which threads are permitted to transfer control between different software components, for any of which a disclaimable lock having a plurality of orderable locks can be identified. Back out activity can be tracked among a plurality of threads with respect to the disclaimable lock and the shared resource, and reclamation activity among the plurality of threads may be ordered with respect to the disclaimable lock and the shared resource.
US09471395B2 Processor cluster migration techniques
Embodiments of the present technology provide for migrating processes executing one any one of a plurality of cores in a multi-core cluster to a core of a separate cluster without first having to transfer the processes to a predetermined core of the multi-core cluster. Similarly, the processes may be transferred from the core of the separate cluster to the given core of the multi-core cluster.
US09471388B2 Mapping network applications to a hybrid programmable many-core device
A hybrid programmable logic is described that performs packet processing functions on received data packets using programmable logic elements, and processors interleaved with the programmable logic elements. The header data may be scheduled for distribution to processing threads associated with the processors by the programmable logic elements. The processors may perform packet processing functions on the header data using both the processing threads and hardware acceleration functions provided by the programmable logic elements.
US09471387B2 Scheduling in job execution
The present invention relates to a method, apparatus, and computer program product for scheduling in job execution. According to embodiments of the present invention, there is provided a method for scheduling a plurality of job slots shared by one or more pre-processors and one or more post-processors in job execution, wherein the data generated by the pre-processor(s) will be fed to the post-processor(s) for processing. The method comprises: determining an overall data generation speed of the pre-processor(s); determining an overall data consumption speed of the post-processor(s); and scheduling allocation of at least one of the job slots between the pre-processor(s) and the post-processor(s) based on the overall data generation speed and the overall data consumption speed. Corresponding apparatus is disclosed as well.
US09471383B2 Task allocation in a computing environment
A method comprises, receiving, at each of a plurality of computing devices, a task execution estimation request message from a central server, the task execution estimation request message comprising a worst-case execution time (WCET) corresponding to the computing device. The method further comprises, computing, by each of the plurality of computing devices, an estimate task execution time for the task based on the WCET and a state transition model corresponding to the computing device, wherein the state transition model indicates available processing resources corresponding to the computing device. Further, the method comprises transmitting, by each of the plurality of computing devices, the estimate task execution time to the central server for allocation of the task to a computing device from amongst the plurality of computing devices based on the estimate task execution time corresponding to the computing device.
US09471382B2 Optimization of job scheduling in a computing environment
Optimizing job scheduling in a data processing system includes determining a time factor associated with a report, determining one or more jobs that contribute to the report, and narrowing execution frequency of the one or more jobs based on the time factor of the report. The time factor provides information about timing details for data included in the report. The jobs are executed in a computing environment according to a time schedule.
US09471377B2 Systems and methods for parallelizing and optimizing sparse tensor computations
A scheduling system can schedule several operations for parallel execution on a number of work processors. At least one of the operations is not to be executed, and the determination of which operation or operations are not to be executed and which ones are to be executed can be made only at run time. The scheduling system partitions a subset operations that excludes the one or more operation that are not to be executed into several groups based on, at least in part, an irregularity of operations resulting from the one or more operation that are not to be executed. In addition, the partitioning is based on, at least in part, locality of data elements associated with the subset of operations to be executed or loading of the several work processors.
US09471370B2 System and method for stack-based batch evaluation of program instructions
A batching module that inspects call stacks within a stack evaluator to identify current expressions that can be evaluated in batch with other expressions. If such expressions are identified, the corresponding stacks are blocked from further processing and a batch processing request for processing the expressions is transmitted to the application server. The application server processes the expressions in batch and generates a value for each of the expressions. The blocked stacks are then populated with the values for the expressions.
US09471369B2 Methods and systems for sharing computational resources
Methods and systems for sharing computational resources. A request from a first node is received for the one or more computational resources. The request comprises a service level agreement (SLA) associated with the requested one or more computational resources. The request is compared with one or more advertisements sent by at least two second nodes, other than the first node. The one or more advertisements correspond to an availability of a set of computational resources associated with each of the at least two second nodes. A portion of computational resources from the set of computational resources associated with each of the at least two second nodes is allocated to the first node, based on the comparison, such that a combination of the portion of computational resources satisfy the SLA associated with the request.
US09471366B2 Virtual machine disk image backup using block allocation area
The invention relates to a method for managing virtual machine image disk usage comprising a disk image emulator for a virtual machine provided by a hypervisor, comprising the steps of providing at least a first disk image comprising a sequence of data blocks for accumulating write operations to the first disk image, providing at least a second disk image comprising a sequence of data blocks for permanently storing disk image data, and providing a disk cleaning process for transferring disk image data from the first disk image to the second disk image and deleting unused data blocks in the first and/or the second disk image.
US09471360B2 Returning terminated virtual machines to a pool of available virtual machines to be reused thereby optimizing cloud resource usage and workload deployment time
A method, system and computer program product for optimizing cloud resources in utilizing a pool of virtual machines to service user workloads. A writeable partition is created to store middleware and user activity associated with a virtual machine obtained from a pool of available virtual machines to be deployed. In response to the obtained virtual machine being terminated, the contents of the created writeable partition are erased so that the data generated by the middleware and user activity will not be available for subsequent users. The virtual machine is later returned to the pool of available virtual machines after resetting its password and network address to a default state. In this manner, fewer cloud resources are used since resource intensive activities that were required in provisioning a new virtual machine can be eliminated since previously terminated virtual machines can be utilized in the pool of available virtual machines.
US09471358B2 Template provisioning in virtualized environments
In a method for provisioning a virtual machine, a processor rates a plurality of software images that include a first software image and a second software image. A processor provisions the virtual machine with the first software image in a first state and the second software image in a second state, wherein the second software image is rated higher than the first software image.
US09471342B2 Register mapping
A technique for register mapping in a virtual system includes preparing a register pool that includes a plurality of registers for mapping. A mapping table is prepared that has a register identifier (ID) and information related to each of a plurality of parameters that express an operational state of the virtual system for each of the registers. At the time a register access request is issued by a hardware thread, the register ID for an access target and information related to each of the plurality of parameters that express the operational state during operation is acquired. One of the registers, for which the acquired register ID and information related to each of the plurality of parameters match the register ID and information for each of the plurality of parameters within the mapping table, is set as a mapped register to be accessed per the register access request.
US09471340B2 Global entry point and local entry point for callee function
Embodiments relate to a global entry point and a local entry point for a callee function. An aspect includes executing, by a processor, a function call from a calling function to the callee function. Another aspect includes, based on the function call being a direct and external function call, entering the callee function at the global entry point and executing prologue code in the callee function that calculates and stores a table of contents (TOC) value for the callee function in a TOC register. Another aspect includes, based on the function call being a direct and local function call, entering the callee function at the local entry point, wherein entering the callee function at the local entry point skips the prologue code. Another aspect includes, based on the function call being an indirect function call, entering the callee function at the global entry point and executing the prologue code.
US09471335B2 Shell integration for an application executing remotely on a server
Methods and systems described herein are directed to providing shell integration for an application executing remotely on a server. By providing shell integration for the application executing on the server, the system provides a seamless user experience, in which a user perceives minor or no differences between applications executing locally and those executing remotely. New usability enhancements in operating systems, such as Destination Lists (a.k.a. Jump Lists), Thumbnail Toolbars, Overlay Icons, Progress Bars, and integration of web sites with the Shell, may work only in a local OS environment and fail to integrate at all in a remote environment. One of the goals of the invention is to integrate these Shell capabilities and achieve a unified desktop experience for the user.
US09471334B2 Content presentation with enhanced closed caption and/or skip back
Apparatuses, methods and storage medium associated with content consumption are disclosed herein. In embodiments, an apparatus may include a decoder, a user interface engine, and a presentation engine. The decoder may be configured to receive and decode a streaming of the content. The user interface engine may be configured to receive user commands. The presentation engine may be configured to present the content as the content is decoded from the stream, in response to received user commands. Further, the decoder, the user interface engine, the presentation engine, and/or combination/sub-combination thereof, may be arranged to adapt the presentation to enhance user experience during response to a skip back command, where the adaption is in addition to a nominal response to the skip back command, e.g., display of closed captions. Other embodiments may be described and/or claimed.
US09471333B2 Contextual speech-recognition user-interface driven system and method
In an effort to customize or enhance software applications, configuration data is often used. Configuration settings that are editable by users need not to be limited to a simple flat entry that can be taken out of context anymore. The present invention allows for multiple-levels of configuration settings to interact with each other, so that a single configuration for a given context to be calculated dynamically. In the process, the user gains flexibility to specify more adequately a required change or customization while propagating the information with minimal effort and not requiring additional coding. Furthermore, to simplify a speaker's interactions for controlling an automated device, the addition of a superposed layer over graphic user interface may be used. The superposed layer may display coordinates that a speaker may use to navigate the graphic user interface, for example to associate a location with a keyword or a coordinate.
US09471331B2 Maintaining resource availability during maintenance operations
One or more aspects of this disclosure may relate to using a configurable server farm preference for an application, desktop or other hosted resource. Additional aspects may relate to moving server farm workloads based on the configurable server farm preference. Further aspects may relate to performing reboot cycles, a reboot schedule and on-demand rebooting. Yet further aspects may relate to staggering individual machine reboot operations over a specified period of time and performing reboot operations such that some machines are available for user sessions during a reboot cycle.
US09471329B2 Optimizing computer hardware usage in a computing system that includes a plurality of populated central processing unit (‘CPU’) sockets
Optimizing computer hardware usage in a computing system that includes a plurality of populated central processing unit (‘CPU’) sockets, including: determining, by a socket configuration module, a number of CPUs to be utilized during operation of the computing system; determining, by the socket configuration module, performance characteristics associated with each available CPU, the performance characteristics associated with each available CPU including information describing computing devices such as memory devices, input/output (‘I/O) devices, and other downstream devices that are coupled to one or more of the available CPUs; and selecting, by the socket configuration module in dependence upon the performance characteristics associated with each available CPU and a predetermined performance policy, a target CPU to utilize as a boot CPU.
US09471324B2 Concurrent execution of heterogeneous vector instructions
A processor may include a vector functional unit that supports concurrent operations on multiple data elements of a maximum element size. The functional unit may also support concurrent execution of multiple distinct vector program instructions, where the multiple vector instructions each operate on multiple data elements of less than the maximum element size.
US09471322B2 Early loop buffer mode entry upon number of mispredictions of exit condition exceeding threshold
Systems, processors, and methods for determining when to enter loop buffer mode early for loops in an instruction stream. A processor waits until a branch history register has saturated before entering loop buffer mode for a loop if the processor has not yet determined the loop has an unpredictable exit. However, if the loop has an unpredictable exit, then the loop is allowed to enter loop buffer mode early. While in loop buffer mode, the loop is dispatched from a loop buffer, and the front-end of the processor is powered down until the loop terminates.
US09471321B2 Method and apparatus for controlling fetch-ahead in a VLES processor architecture
There is provided a method for controlling fetch-ahead of Fetch Sets into a decoupling First In First Out (FIFO) buffer of a Variable Length Execution Set (VLES) processor architecture, wherein a Fetch Set comprises at least a portion of a VLES group available for dispatch to processing resources within the VLES processor architecture, comprising, for each cycle, determining a number of VLES groups available for dispatch from previously pre-fetched Fetch Sets, and only requesting a fetch-ahead of a next Fetch Set in the next cycle if one of a select set of criteria related to the number of VLES groups available for dispatch is true.
US09471316B2 Using a single-instruction processor to process messages
The disclosed embodiments describe single-instruction processors that operates upon messages received from a network interface. A single-instruction processor comprises a register file, a functional unit, a bus connecting the register file and the functional unit, and a format decoder that receives messages from a network interface. This single-instruction processor supports a single instruction type (e.g., a “move instruction”) that specifies operands to be transferred via the bus. During operation, the format decoder is configured to write a parameter from a received message to the register file. A move instruction moves this parameter from the register file to the functional unit via the bus. The functional unit then uses the parameter to perform an operation.
US09471311B2 Vector checksum instruction
Elements from a second operand are added together one-by-one to obtain a first result. The adding includes performing one or more end around carry add operations. The first result is placed in an element of a first operand of the instruction. After each addition of an element, a carry out of a chosen position of the sum, if any, is added to a selected position in an element of the first operand.
US09471310B2 Method, computer program product, and system for a multi-input bitwise logical operation
A method, computer program product, and system are provided for multi-input bitwise logical operations. The method includes the steps of receiving a multi-input bitwise logical operation instruction that specifies two or more input operands and a function operand, where a first input operand of the two or more input operands comprises a number of bits, each bit having a corresponding bit in each of the additional input operands in the two or more input operands. The function operand is written to a lookup table. Then, the lookup table is accessed for each set of corresponding input operand bits in the two or more input operands to generate an output for the multi-input bitwise logical operation instruction.
US09471309B2 Arithmetic processing apparatus and method for high speed processing of application
An arithmetic processing apparatus and method for high speed processing of an application are provided. The arithmetic processing apparatus may include a program control unit to store operation processing information necessary for application operation in a communication channel by executing an application code, and an operation processing unit to process the application operation using the operation processing information stored in the communication channel.
US09471308B2 Vector floating point test data class immediate instruction
A Vector Floating Point Test Data Class Immediate instruction is provided that determines whether one or more elements of a vector specified in the instruction are of one or more selected classes and signs. If a vector element is of a selected class and sign, an element in an operand of the instruction corresponding to the vector element is set to a first defined value, and if the vector element is not of the selected class and sign, the operand element corresponding to the vector element is set to a second defined value.
US09471307B2 System and processor that include an implementation of decoupled pipelines
A system and apparatus are provided that include an implementation for decoupled pipelines. The apparatus includes a scheduler configured to issue instructions to one or more functional units and a functional unit coupled to a queue having a number of slots for storing instructions. The instructions issued to the functional unit are stored in the queue until the functional unit is available to process the instructions.
US09471305B2 Micro-coded transcendental instruction execution
A method for graphics processing includes generating one or more transcendental instructions in a graphics processing unit (GPU). Micro-code is formed for processing the one or more transcendental instructions in the GPU. The micro-code is processed using an iterative process including cubic interpolation and an evaluation of a cubic polynomial.
US09471300B2 Wireless firmware upgrades to an alarm security panel
A panel is described including stored data that is associated with the operation of the panel, and a server configured to provide a notification that an update to the data is available, the notification provided over a first communication network, and provide an update to the data via a wireless communication with the panel over a second communication network different than the first communication network.
US09471299B1 Updating code within an application
Disclosed are various embodiments for providing updateable code to a software library executed in a client device. Updateable code includes scripting language code and potentially other content employed by a software library invoked by an application executed by a client device. Updateable code can be updated upon launch of the application and/or upon invocation of a call associated with the software library.
US09471292B2 Binary translation reuse in a system with address space layout randomization
Generally, this disclosure provides systems, methods and computer readable media for binary translation (BT) reuse. The system may include a (BT) module to translate a region of code from a first instruction set architecture (ISA) to a second ISA, for execution associated with a first process. The BT module may also be configured to store a first physical page number associated with the translated code and the first process. The system may also include a processor to execute the translated code and to update a virtual address instruction pointer associated with the execution. The system may further include a translation reuse module to validate the translated code for reuse by a second process. The validation may include generating a second physical page number based on a page table mapping of the updated virtual address instruction pointer and matching the second physical page number to the stored first physical page number.
US09471291B2 Multi-processor code for modification for storage areas
A method for processing computer program code to enable different parts of the computer program code to be executed by different processing elements of a plurality of communicating processing elements. The method comprises identifying at least one first part of the computer program code, which is to be executed by a particular one of said processing elements. The method further comprises identifying at least one further part of the computer code which is related to the at least one first part of the computer code. The at least one first part of the computer program code and the at least one further part of the computer program code are caused to be executed by the particular one of said processing elements.
US09471289B2 Compiler optimization for many integrated core processors
Systems and methods for source-to-source transformation for compiler optimization for many integrated core (MIC) coprocessors, including identifying data dependencies in candidate loops and data elements used in each iteration for arrays, profiling candidate loops to find a proper number m, wherein data transfer and computation for m iterations take an equal amount of time, and creating an outer loop outside the candidate loop, with each iteration of the outer loop executing m iterations of the candidate loop. Data streaming is performed by determining optimum buffer size for one or more arrays and inserting code before the outer loop to create optimum sized buffers, overlapping data transfer between central processing units (CPUs) and MICs with the computation; reusing buffers to reduce memory employed on the MICs, and reusing threads on MICs to repeatedly launch kernels on the MICs for asynchronous data transfer.
US09471287B2 Systems and methods for integrating widgets on mobile devices
Embodiments of a system and method are described for generating and distributing programming to mobile devices over a network. Devices are provided with Players specific to each device and Applications that are device independent. Embodiments include a full-featured WYSIWYG authoring environment, including the ability to bind web components to objects.
US09471285B1 Identifying software components in a software codebase
Systems, methods, and computer program embodiments are disclosed for detecting third party software components in a software codebase. In an embodiment, a source file containing source code may be received at a server, and a code signature may be generated for the source file based on a determined structure of the source code. The generated code signature may then be compared to signatures stored in a reference database to identify matching third party software files. In an embodiment, the reference database may store a plurality of code signatures corresponding to third party software files. A list of the identified third party software files may be created and presented to a user.
US09471284B2 Apparatus, method, and non-transitory computer-readable storage medium
This invention provides an apparatus use environment with higher flexibility and convenience. To achieve this, in a program including the first program layer with an instruction set to be interpreted and executed by a processor and the second program layer with an instruction set compiled in advance by a unit other than the processor, this invention controls to perform communication between an external device and the first program layer via the second program layer. Based on information about the external device received from the external device via communication, display contents of a display screen for using a function of the external device, which are displayed in the first program layer, are controlled.
US09471282B2 System and method for using annotations to automatically generate a framework for a custom javaserver faces (JSF) component
A system and method for using annotations to automatically generate a framework for a custom JavaServer Faces (JSF) component is provided. Source code for a custom JSF Component class may be received, where the received source code may include annotations indicating how a declared element should be processed. For example, based on a type of annotation in the source code, the framework for the custom JSF component may be automatically generated, where the generated framework can include implementations for a Component class, a Tag Handler class, a Renderer class, a Tag Library Descriptor, a faces-config.xml file, tag unit test cases, or any other aspect of a custom JSF component. Thus, reusable, reliable, and readable custom JSF components may be easily developed at a substantially reduced development cost.
US09471280B2 Extraction of random numbers from physical systems
A method of generating a random bit string includes receiving a binary input string, creating copies of the binary input string received from the min-entropy source, and providing each of the copies of the binary input string to one of a plurality of randomness extractors. The method further includes, for each randomness extractor, providing the respective extracted output binary string to one of a plurality of quantum devices, where each of the plurality of quantum devices is configured to (i) receive the extracted output binary string as a locally random input signal string, random only to that respective quantum device, and (ii) transform the received locally random input string into a globally random output signal string. Still further, the method includes combining the plurality of globally random output signal strings from the plurality of quantum devices to generate the random bit string.
US09471279B2 Random number generation using untrusted quantum devices
A method of generating a sequence of random bits includes receiving a binary input signal from an input signal source and coupling the binary input signal into a plurality of components of the quantum device to initiate a random bit generation cycle. Each of the plurality of components of the quantum device produces a binary output during the random bit generation cycle, and the quantum device is configured to operate according to a non-local game during the random bit generation cycle. The method further includes maintaining isolation of the plurality of components of the quantum device during the random bit generation cycle, obtaining a plurality of binary outputs from the plurality of components of the quantum device, and producing a random bit based on the plurality of binary outputs and the binary input signal. After the random bit generation cycle, communication among the plurality of components of the quantum device is allowed.
US09471278B2 Low area full adder with shared transistors
A full adder is disclosed that utilizes low area. The full adder includes an exclusive NOR logic circuit. The exclusive NOR logic circuit receives a first input and a second input. A first inverter receives an output of the exclusive NOR logic circuit and generates an exclusive OR output. A carry generation circuit receives the output of the exclusive NOR logic circuit, the exclusive OR output and a third input. The carry generation circuit generates an inverted carry. A second inverter is coupled to the carry generation circuit and generates a carry on receiving the inverted carry. A sum generation circuit receives the output of the exclusive NOR logic circuit, the exclusive OR output and the third input. The sum generation circuit generates an inverted sum. A third inverter is coupled to the sum generation circuit and generates a sum on receiving the inverted sum.
US09471271B2 Systems and methods for portable audio synthesis
A method of performing audio synthesis has a first audio event input to an audio algorithm along with associated parameters. A synthesis algorithm accesses a soundbank to generate audio output. The soundbank has two or more levels for a first desired sound. A first level is associated with a first sample of a relatively chaotic waveform, and a second level is associated with a second sample of a relatively stable waveform. Parameter data is associated with one or more of the levels. The first sample and the second sample begin to sound at the same point in time in response to the first audio event. The audio output is based in part on the parameter data, and the second sample is continuously looped until a second audio event is detected.
US09471270B2 Mobile terminal and control method for the mobile terminal
A mobile terminal including a wireless communication unit configured to wirelessly communicate with an external device; a touch screen configured to sense a touch input, and switch between an active state and an inactive state; and a controller configured to receive a plurality of touch inputs applied to the touch screen in the inactive state, and when the received touch inputs satisfy a preset criteria, control the external device to release a locked state of the external device, activate a first region of the touch screen in the inactive state, and display screen information corresponding to the external device in the activated first region of the touch screen.
US09471269B2 Portable presentation system and methods for use therewith
An assembly for sharing information in a conference space comprising a contiguous large presentation display assembly including a large contiguous presentation surface, a processor programmed to perform the steps of dividing the large surface into a plurality of adjacent presentation sub-spaces including at least one master sub-space and a plurality of slave sub-spaces and enabling an interface that allows images to be presented via the sub-spaces and that enables moving images among the different sub-spaces, wherein, upon an image being moved from the master sub-space to one of the slave sub-spaces, the master presentation sub-space is left blank to receive another image.
US09471268B2 Multi-channel KVM server system employing multiresolution decomposition
A multi-channel KVM server system for supplying video data to a plurality of clients is disclosed. The KVM server includes a plurality of video processors and a video switch for connecting each video processor to one or more video sources. Each video processor processes video data using a multiresolution decomposition method to generate a plurality of decomposition components at different resolution levels. A main processor of the KVM server transmits the decomposition components generated by various video processors to various clients based on the clients' requirements. When some clients are in a multi-source (“TV wall”) mode and some clients are in a single-source mode, the main processor uses decomposition components generated by some video processors to supply both the clients in single-source mode and as a part of the TV wall data for the clients in multi-source mode.
US09471267B2 Mobile terminal and method of controlling the same
A mobile terminal, capable of effectively providing information by using double-sided display units, includes: first and second display units disposed on different sides; a memory unit configured to store both an image and information associated with the image; and a controller configured to control at least one of the first and second display units to display the image and the information associated with the image according to any one among first and second display modes, wherein, in the first display mode, the image and the information associated with the image are displayed on any one of the first and second display units, and in the second display mode, when the image is displayed on any one of the first and second display units, the information associated with the image is displayed on the other of the first and second display units.
US09471263B2 Resource authorization quantities
In one example of the disclosure, a subscription is received. The subscription is to authorize a computing device to at least one of dispense or consume a subscription quantity of a resource. An authorization quantity of the resource is calculated according to a formula that considers a parameter attributable to the subscription. The authorization quantity is to authorize at least one of a dispensation or consumption of the resource at the device. The authorization quantity is sent to the device.
US09471259B2 Shared storage architecture
A shared storage architecture is described for coordinating management of a shared storage between nodes of a network storage system. In various embodiments, the shared storage is partitioned into and different partitions are assigned to different nodes of the network storage system. The shared storage architecture provides techniques for asserting reservations on the shared storage, managing state of the shared storage, and implementing various configurations of the network storage system using the shared storage.
US09471258B2 Performance isolation for storage clouds
Embodiments of the present invention provide performance isolation for storage clouds. Under one embodiment, workloads across a storage cloud architecture are grouped into clusters based on administrator or system input. A performance isolation domain is then created for each of the clusters, with each of the performance isolation domains comprising a set of data stores associated with a set of storage subsystems and a set of data paths that connect the set of data stores to a set of clients. Thereafter, performance isolation is provided among a set of layers of the performance isolation domains.
US09471255B2 Tape storage device and writing method therefor
A mechanism is provided for tape writing of small transactions. A first file is written as a plurality of fixed-length data sets (DS), the DS number of the final DS in the plurality of DS is stored in memory as #N(DS#N) and the WP number as #M(WP#M), and the final first file and the second file in the DS following the final DS(DS#N, WP#M) containing the first file are packed and written in sequential DS units, and are stored as DS#N, DS#N+1, etc. and WP#M+1 in sequential order in DS containing the second file. The remaining first, second, or third file is packed and DS#N with WP#M is overwritten as DS#N with WP#M+2, and the remaining #N in the DS numbers of the second file and the third file in the subsequent DS are written as DS#N+1, N+2, etc. with WP#M+2, and the DS#N, #N+1, #N+2, etc. with WP#M+2 are stored.
US09471252B2 Use of flash cache to improve tiered migration performance
For data processing in a computing storage environment by a processor device, the computing storage environment incorporating at least high-speed and lower-speed caches, and tiered levels of storage, and at a time in which at least one data segment is to be migrated from one level to another level of the tiered levels of storage, a data migration mechanism is initiated by copying data resident in the lower-speed cache corresponding to the at least one data segment to be migrated to a target on the another level, reading remaining data, not previously copied from the lower-speed cache, from a source on the one level, and writing the remaining data to the target, and subsequent to the reading and the writing of the remaining data, destaging updates corresponding to the at least one data segment from either the higher and lower speed caches to the target.
US09471250B2 Intermittent sampling of storage access frequency
The intermittent sampling of storage access frequency is performed by determining a duration of a collection window and a duration of an observation window within the collection window. A position of the observation window within the collection window is randomly selected, and frequencies of accesses of one or more storage objects during the observation window are observed. When a new access of a given storage object occurs, a delta time for the given storage object is calculated as the time of the observed access minus the timestamp of the most recent observed prior access of the given storage object. Optionally, the delta time of two sequential accesses of a given storage object in two different observation windows may be calculated as if the two different observation windows are immediately adjacent to each other.
US09471247B2 Storage apparatus and area releasing method
A storage apparatus performs, in place of a copy process which involves physical resource allocation to a copy destination logical volume, a copy process which allows the copy destination logical volume to refer to an allocation destination managed by a management unit area of a copy source logical volume. A storage unit stores management information relating to the reference destination of the management unit area of the logical volume. A control unit releases the physical resource which has been allocated to the management unit area by exchanging the reference destination of the management unit area specified by a release command from a host computer with the reference destination of the management unit area of the other logical volume corresponding to the specified management unit area.
US09471245B1 Method and apparatus for transferring modified data efficiently
Techniques for transferring modified data with efficiency are described herein. According to one embodiment, the method starts with analyzing host write data to determine a host write pattern of a host writing to sectors at a primary storage, and then a data block size and a backup interval are determined based on at least one of the host write pattern, wherein a data block includes a number of sectors that is determined based on the host write pattern, and known characteristics of transferring dirty data blocks of the primary storage, wherein a dirty data block includes at least one sector that has been changed from a previous backup. Then dirty data blocks are transferred from the primary storage to a secondary storage as part of a backup.
US09471238B1 Low power storage array with metadata access
A method for low power storage array with metadata access includes sequentially writing data to a currently active disk drive in a storage array and storing metadata relating to the writes in a preallocated portion of the currently active disk drive, determining when the currently active disk drive is nearing full capacity, activating a next disk drive and cloning the stored metadata from the preallocated portion of the currently active disk drive to a preallocated portion of the next disk drive. When the currently active disk drive is full, sequentially writing data to the next disk drive.
US09471235B1 Storage device data overlay tracking and prevention
Aspects of the disclosure are direct towards managing data overlay in a direct access storage device (DASD) using metadata of data stored within the DASD. The DASD receives user input. The user input includes a value indicating activation of overlay tracking for a track of the DASD. The DASD updates the metadata to indicate overlay tracking activation. The DASD detects a write request from an application to overlay data on the track. In response to overlay tracking being activated for the track, the DASD determines the access method used to transmit the write request. The DASD determines an identifier for the application. The DASD determines the identifier using the protocol of the access method. The DASD records data regarding the write request within the metadata. In response to recording the data regarding the write request, the DASD overlays the track per the write request.
US09471234B2 Systems and methods for mirroring virtual functions in a chassis configured to receive a plurality of modular information handling systems and a plurality of modular information handling resources
A method may include, in a chassis configured to receive a plurality of modular information handling systems and a plurality of modular information handling resources, exposing a first virtual function instantiated on a management processor disposed in the chassis to a switch interfaced between a modular information handling system and the management processor. The method may also include communicating, by the management processor, an input/output request from the modular information handling system received by the first virtual function to at least one of a second virtual function instantiated on a first storage controller communicatively coupled to the management processor and a third virtual function instantiated on a second storage controller communicatively coupled to the management processor. The method may further include receiving, by the management processor, an acknowledgment of completion of the input/output request from at least one of the second virtual function and the third virtual function.
US09471233B1 Named mount optimization for virtual tape systems
Embodiments are described for named mounts in a virtual tape engine (VTE) system. A system maintains a file list of named volumes for each of the VTEs. When named mount requests are received, the system searches the file list for the named volume rather than searching through each of the file systems for each of the VTEs. When the volume name is found on a file list, the VTE for the volume name is identified and the mount request can be completed.
US09471226B2 Reverse copy on write for better cache utilization
Methods, systems, and computer program products for providing reverse copy-on-write for improved cache utilization are disclosed. Examples generally relate to both physical and virtualized computer systems. A computer-implemented method may include detecting when a first task is to write to a memory page that is shared with a second task, creating a copy of the memory page for use by the second task, and modifying a memory mapping to associate the second task with the copy of the memory page. In a virtualized computer system, a hypervisor may detect when a first virtual machine is to write to a memory page shared with a second virtual machine, create a copy of the memory page for the second virtual machine, and adjust a memory mapping to associate the second virtual machine with the copy of the memory page.
US09471224B2 Storage management system, management device and method therefor
A storage management method includes the following steps: detecting sizes of shared storage spaces of terminal devices joined in a sharing system; classifying the terminal devices joined in a sharing system to a number of kinds of terminal devices according to a size of the shared storage space of each terminal device; mapping the shared storage spaces of each kind of terminal devices of each device group to virtual disks with corresponding storage capacities of a virtual disk array card one by one; receiving a storing request to store a file to a cloud, and determining a size of the file to be stored and selecting one virtual disk whose storage capacity is nearest and greater than or equal to the size of the file, and storing the file to the shared storage spaces of the terminal devices mapping to the selected virtual disk.
US09471221B2 Generalized positional ordering
Implementations described and claimed herein provide a method and system for managing execution of commands for a storage device, the method comprising determining a plurality of commands to be executed for the storage device and while a storage device is executing at least one command, determining an execution order for at least two of the plurality of commands. Alternate implementation described and claimed herein provide a computer readable memory for storing a data structure, the data structure comprising a cost table comprising a number of cells, each cell containing one or more cost values related to one of a plurality of traversals between two locations on a storage device wherein each of the plurality of traversals is related to completion of one of a plurality of commands and a benefit array comprising a number of cells, each cell containing a benefit value related to completion of one of the plurality of commands.
US09471219B2 Text recognition apparatus and method for a terminal
A text recognition apparatus and method of the portable terminal is provided for recognizing text image selected by a pen on a screen image as text. The text recognition method of the present invention includes displaying an image; configuring a recognition area on the image in response to a gesture made with a pen; recognizing text in the recognition area; displaying the recognized text and action items corresponding to the text; and executing, when one of the action items is selected, an action corresponding to the selected action item.