最新美国发明专利第2016-05-31期 - 专利汇|PatentHub专利检索|专利查询网|发明专利查询分析

Document	Document Title
US09356399B2	Aircraft ground power connector An aircraft ground power connector for use in an aircraft ground power support system providing electrical power from a ground power unit through a ground power cable to the ground power receptacle of a parked aircraft. The axis of the portion of the connector housing which engages the aircraft ground power receptacle is angled relative to the axis of the portion of the housing which receives the ground power cable to minimize mechanical stress on the aircraft ground power receptacle when the connector is installed therein and to render the connector easier to insert and remove from the aircraft receptacle. Additionally, the ground power connector includes a capacitor connected to an electrical circuit within the connector supplying do voltage to the aircraft ground power receptacle to mitigate momentary voltage drops at the receptacle resulting from momentary surges in current demand by the aircraft.
US09356398B2	Lock mechanism of shield connector A shield connector is for assembling of a connector housing and a shield shell acted by a small insertion force and locking the connector housing and the shield shell by a large holding force. A flexible lock arm having a projection projecting outwardly is arranged at an insulation connector housing. A locked member engaged with the projection is arranged at a shield shell in which the connector housing is inserted. When the projection is half locked with the locked member, the lock arm is prevented from bending to unlock. When the connector housing is inserted into the shield shell, the lock arm is bent and also the projection is press-fitted along an inner surface of the shield shell. A stopper facing and abutting on an inner surface along a bending direction of the lock arm is arranged at an outer surface of the connector housing.
US09356394B2	Self-rejecting connector A plug-in connector for connecting to a receptacle includes a housing including tripping structures, electrically conductive terminals partly situated in the housing, latches arranged in the housing, and a slider slidingly coupled to the housing, and further includes blocking structures and trippable structures extending in a mating direction and that cooperate with the tripping structures, and a spring that urges the slider outward away from the housing in the mating direction. The tripping structures are situated to engage with the trippable structures during an initial stage of relative movement between the housing and slider against the spring bias while inward deflection of the latches is allowed. The blocking structures of the slider prevent inward deflection of the latches after a final stage of the relative movement between the housing and slider, and the connector has an electrically interconnected state only when in the final stage.
US09356393B2	Low profile connector system A low-profile electrical connector includes a housing having exterior perimeter sides and top and bottom surfaces, where the bottom surface is configured to extend along a user's body site and the top surface is spaced above the bottom surface. The connector also includes a side-entry guide channel disposed along the bottom surface. The channel includes an opening along the exterior perimeter side that is configured to receive an electrically conductive element. The channel is also configured to guide the electrically conductive element within the housing. The connector includes a receptacle positioned within the housing and forms an electrically conductive interface with the electrically conductive element.
US09356392B2	Lever-type connector with a lever lock and a lever lock releasing portion A lever-type connector has an outer housing (40) includes accommodating chambers (44) and lock receiving portions (52) at position facing the accommodating chambers (44) and outer surfaces. Inner connectors (11) are connectable to a mating connector by being inserted into the accommodating chambers (44). A rotatable lever (70) is mounted on the outer surfaces of the outer housing (40). The lever (70) includes locks (76) for restricting rotation of the lever by being fit into the lock receiving portions (52) from outer sides when the lever (70) is assembled with the outer housing (40). The inner connector (10) includes a releasing portion (26) for pressing the locking portion (76) from an inner side to separate the lock (76) from the lock receiving portion (52) when the inner connector (10) is inserted into the accommodating chamber (44).
US09356387B1	Sealed electrical connector assembly A connector assembly comprises front and rear connector bodies, a wire grommet with wire passages, and a nut. Tightening the nut forces a rearward portion of the grommet into a tapered segment of a passage through the rear connector body, thereby radially compressing the grommet and sealing the wires passing therethrough.
US09356380B1	Power adaptor The present invention provides a power adaptor with a retractable plug. The power adaptor contains a main member, a retractable plug, and power sockets. The plug contains an insulating plug body and three pins. The plug body has a rotary knob member on each of two opposing circumferential sides of the plug body. The main member has an indentation within which the plug is configured. The indentation has two opposing knob sockets on the side wall. The plug can be retracted and housed in the indentation, and the pins have their terminal sections away from connection plates of the main member. When the plug is pulled and erected from the main member, the pins have their terminal sections contacting the connection plates of the main member.
US09356378B1	Electric connector housing with a terminal interface A method to assemble an electric connector includes inserting a terminal assembly with a wire attached thereto into a wire opening defined by a connector body. The terminal assembly is moved in an insertion direction to engage a terminal guide and is moved in a seat direction. The terminal assembly is moved further in the insertion direction to a seated position.
US09356372B2	Techniques to convert signals routed through a fabric cable assembly Examples are disclosed for converting signals routed through a fabric assembly. In some examples, a connector housing may house a paddle card having a first edge portion coupled to a twin-axial cable having first signal pathways capable of routing first signals to/from a fabric controller integrated with a processor/processor package. The paddle card may have a second edge portion that may couple with an external fabric connector including a second plurality of signal pathways. In some examples, first signals received at the first edge portion may be converted to second signals following a coupling of the second edge portion with the external fabric connector. The second signals may then be routed via the second signal pathways included in and/or coupled with the external fabric connector. Other examples are described and claimed.
US09356371B2	Connector A connector comprises a first connector and a second connector. The first connector includes a first connector main body and a plurality of first terminals mounted side by side in the longitudinal direction of the first connector main body on both sides in the transverse direction of the first connector main body. The second connector includes a second connector main body for mating with the first connector main body and a plurality of second terminals mounted side by side in the longitudinal direction of the second connector main body on both sides in the transverse direction of the second connector main body. Each first terminal includes a first contact portion and a second contact portion facing each other. The first contact portion and the second contact portion overlap the corresponding second terminal. The amount of overlap is greater than the amount of clearance in the transverse direction of the first connector main body. Each second terminal is inserted between the first contact portion and the second contact portion of the corresponding first terminal and contacting the first terminal when the first connector main body is mated with the second connector main body.
US09356370B2	Interposer for connecting a receptacle tongue to a printed circuit board Connecting structures to mechanically connect to a connector receptacle tongue and a printed circuit board and to electrically connect contacts on the connector receptacle tongue to traces on the printed circuit board. One example may provide an interposer having a housing and a plurality of contacts to connect a vertical tongue to a horizontal printed circuit board. The contacts may have a side or tongue connecting portion extending beyond a side of the housing and a bottom or board contacting portion extending beyond a bottom of the housing. The contacts may form a ninety-degree bend. A shield may at least substantially surround a vertical side of the housing.
US09356365B2	Cable connection structure A cable connection structure includes a cable that has an outer skin and at least one conducting wire, and a substrate to which the cable is connected at a main surface side having a hard wiring, wherein the substrate includes, at the main surface side, a first flat section having flatness and a second flat section having flatness thinner than the first flat section via a level difference surface from the first flat section and an end part of the outer skin is arranged on the second flat section and at least one of the conducting wire is connected to a connecting electrode formed on the second flat section.
US09356364B2	Coaxial cable connector with continuity bus A coaxial cable connector includes a continuity bus that extends a ground circuit from a coaxial cable outer conductor to a connector part such as a connector fastener and/or a connector post.
US09356360B1	Dual polarized probe coupled radiating element An electronically scanned array radiating element includes a ground plane layer having a pair of conductive probes. A metallization layer is coupled with the ground plane layer and includes a first asymmetric cluster including HOF scattering members and impedance-matching dipoles. A first electrically-large impedance-matching dipole is coupled with one of the conductive probes and is associated with the first asymmetric cluster. The first electrically-large impedance-matching dipole and the first asymmetric cluster may cooperate with one another to produce a signal. A second asymmetric cluster includes HOF scattering members and impedance-matching dipoles. A second electrically-large impedance-matching dipole is coupled with the other conductive probe and is associated with the second asymmetric cluster. The electrically-large impedance-matching dipole and the asymmetric cluster may cooperate with one another to produce a second signal having a polarization orthogonal to the polarization of the first signal.
US09356359B2	Active antenna system (AAS) radio frequency (RF) module with heat sink integrated antenna reflector On-board heat dissipation can be achieved in radio frequency (RF) modules by integrating a heat sink into the RF module's antenna reflector. Said integration achieves a compact and aesthetically pleasing RF module design that reduces the overall footprint of modular active antenna systems (AASs). Embodiment antenna reflectors include portions that are perforated and/or exposed to free flowing air to provide enhanced heat dissipation capability.
US09356358B2	Architectures and methods for novel antenna radiation optimization via feed repositioning An antenna system comprises: multiple antenna elements; and multiple beam forming networks configured to produce radiation patterns for both receiving and transmission functions configured to be optimized by re-positioning said antenna elements, wherein said beam forming networks comprise a receiving beam forming network configured to combine multiple first inputs from said antenna elements into at least a first output, and a transmission beam forming network configured to divide a second input into multiple second outputs to said antenna elements.
US09356352B2	Waveguide coupler An apparatus is provided. In the apparatus, there is an antenna package and an integrated circuit (IC). A circuit trace assembly is secured to the IC. A coupler (with an antenna assembly and a high impedance surface (HIS)) is secured to the circuit trace assembly. An antenna assembly has a window region, a conductive region that substantially surrounds the window region, a circular patch antenna that is in communication with the IC, and an elliptical patch antenna that is located within the window region, that is extends over at least a portion of the circular patch antenna, and that is in communication with the circular patch antenna. The HIS substantially surrounds the antenna assembly.
US09356349B2	Micro antenna feeder for wide band, with a quad scheme antenna orthogonally installed to a cross dipole antenna Provided is a micro wideband antenna feeder, and more particularly, to a micro wideband antenna feeder in which a quad scheme antenna and a cross dipole antenna are coupled to each other. The micro wideband antenna feeder includes: a quad scheme antenna; and a cross dipole antenna installed orthogonal to the quad scheme antenna and irradiating current distribution orthogonal to current distribution irradiated from the quad scheme antenna. Since phases 0, 90, 180, and 270 can be shifted by being designed as a feeding network PCB, a circularly polarized wave can be implemented.
US09356348B2	Antenna structure An antenna structure includes a feed end, a grounding end, at least one main radiator, and at least one coupling radiator. The grounding end is separated from the feed end. The at least one main radiator is connected to the feed end. The at least one coupling radiator is connected to the grounding end. Current on the feed end is coupled to the grounding end, and current on the least one main radiator is coupled to the at least one coupling radiator.
US09356346B2	Single port dual antenna A system for transmitting radio frequency includes antenna elements configured to transmit radio frequency beams including a horizontal beam widths and vertical beam widths. The antenna elements are positioned to transmit radio frequency in directions to cover areas independent of each other. The system includes a port operatively coupled to the antenna elements to transmit power to the antenna elements to cause the antenna elements to transmit radio frequency in the respective directions. The antenna elements and the port form a distributed antenna system.
US09356340B2	High gain wideband omnidirectional antenna The present invention relates to a series fed collinear antenna which includes cone-shaped radiating elements energized via a series fed common transmission line. Phasing stubs are provided between selected radiating elements and are oriented such that the phasing stub improves gain and reliability by affecting the signal to produce a beneficial elevational coordinate signal pattern. The radiating elements may be cones. Each cone has an associated base diameter. The base diameter may be uniform, resulting in similarly sized cones, or a cone may have a distinct base diameter resulting in differently sized cone elements.
US09356339B2	Planar antenna array and article of manufacture using same A planar antenna array and articles of manufacture using the same are disclosed. In one embodiment, close-packed antenna elements, disposed on a substrate, number N where N=3x and x is a positive integer. Each of the close-packed antenna elements includes a substantially continuous photonic transducer arranged as an outwardly expanding generally logarithmic spiral having six turns. Each of the outwardly expanding generally logarithmic spirals may be a golden spiral. As an article of manufacture, the planar antenna array may be incorporated into a chip, such as a cell phone, or an article of clothing, for example.
US09356338B2	Antenna apparatus and feeding structure thereof An antenna apparatus includes: a radiator; a feeding structure including a feeding unit to provide a signal to the radiator, a ground unit to ground the radiator, and a resonance applying part between the feeding unit and the ground unit; and a contact part to connect the radiator with the feeding structure.
US09356336B1	Dual-folded monopole antenna (DFMA) Methods and systems for extending a bandwidth of a dual-folded monopole antenna of a user device are described. A dual-folded monopole antenna includes a first folded monopole structure coupled to a single radio frequency (RF) input and a parasitic folded monopole structure coupled to a ground plane. The first folded monopole structure is configured to operate as a feeding structure to a parasitic folded monopole structure that is not conductively connected to the RF input.
US09356335B2	Electrophoretic display device having integrated NFC antenna The present invention relates to near field communication technology. Specifically, disclosed is an electrophoretic display device having integrated an NFC antenna. The NFC antenna is arranged on a display screen of the electrophoretic display device, where the NFC interface is equipped with an output circuit of the display screen and is connected to a control mainboard of the display screen. The present invention combines the display screen and NFC antenna features into one, and has the NFC antenna provided directly on the electrophoretic display device, thus preventing the problem of signal quality deterioration and reception failure due to wearing of the NFC antenna interface and inaccurate alignment. In addition, a solution is provided for facilitating reception of an NFC signal from a display panel of the display device or for when the NFC signal must be received from the display panel of the display device.
US09356334B2	Meter register transmitting flow rate warning A method and apparatus for measuring a fluid and determining a leak comprising the steps of providing a meter and a meter register coacting with the meter. When a leak is detected, a signal is transmitted from the meter register regarding fluid consumption. The transmitted signal indicates a leak either when the measured flow rate remains a fixed volume over a fixed period of time, or the measured flow rate exceeds a threshold value.
US09356333B2	Transmission line resonator, band-pass filter and branching filter A transmission line resonator includes distributed coupled lines including first distributed constant line which one ends are connected to a short-circuit grounding portion and second distributed constant line which is disposed in parallel to the first distributed constant line while being separated therefrom by a predetermined distance and which one ends opposing the short-circuit grounded one ends of the first distributed constant line are connected to the short-circuit grounding portion, and a single transmission line which both ends are connected to the respective other ends of the distributed coupled lines.
US09356330B1	Radio frequency (RF) couplers An RF coupler implementable as an integrated circuit includes a first transmission line having a first line portion and a second line portion. A first end of the first transmission line is coupled to an input port for receiving an RF input signal. A second end of the first transmission line is coupled to an output port for providing an RF output signal. The RF coupler further includes a second transmission line formed between the first line portion and the second line portion such that magnetic field produced due to the RF input signal in the first line portion and the second line portion envelops the second transmission line. A first end of the second transmission line is configured as a coupled port for providing a coupled RF signal, and a second end of the second transmission line is coupled to a termination element to form an isolation port.
US09356325B1	Electrified vehicle battery pack monitoring assembly and method An exemplary monitoring assembly includes, among other things, a controller configured to identify a change in an internal pressure of a battery cell using a resistance measurement and a reference temperature measurement, the resistance measurement provided by a strain gauge associated with the battery cell.
US09356320B2	Lithium battery having low leakage anode A lithium battery comprises a support, and a plurality of battery component layers on the support, the battery component layers including a cathode having a cathode area with a plurality of cathode perimeter edges. An electrolyte is on the cathode, and an anode is on the electrolyte. The anode comprises an anode area with a plurality of anode perimeter edges, each anode perimeter edge having a corresponding cathode perimeter edge that lies adjacent to and below the anode perimeter edge. The anode area is sized so that at least one anode perimeter edge is terminated before its corresponding cathode perimeter edge to define a gap between the anode perimeter edge and the corresponding cathode perimeter edge, the gap having a gap distance G.
US09356319B2	Method for producing lithium tetrafluoroborate solution Disclosed is a production method of a lithium tetrafluoroborate solution for use as a lithium battery electrolytic solution, including: a reaction step of forming lithium tetrafluoroborate by reaction of lithium fluoride and boron trifluoride in a chain carbonate ester solvent and thereby obtaining a reaction solution of the lithium tetrafluoroborate dissolved in the chain carbonate ester solvent; a water removal step of adding a water removing agent to the reaction solution; an acidic impurity removal step of removing an acidic impurity component from the reaction solution by concentrating the reaction solution after the water removal step; and a dilution step of diluting the concentrated solution after the acidic impurity removal step. It is possible by this method to obtain the lithium tetrafluoroborate solution whose acidic impurity content and water content are reduced to be 50 mass ppm or lower and 15 mass ppm or lower, respectively.
US09356317B2	Amorphous ionically conductive metal oxides and sol gel method of preparation Amorphous lithium lanthanum zirconium oxide (LLZO) is formed as an ionically-conductive electrolyte medium. The LLZO comprises by percentage of total number of atoms from about 0.1% to about 50% lithium, from about 0.1% to about 25% lanthanum, from about 0.1% to about 25% zirconium, from about 30% to about 70% oxygen and from 0.0% to about 25% carbon. At least one layer of amorphous LLZO may be formed through a sol-gel process wherein quantities of lanthanum methoxyethoxide, lithium butoxide and zirconium butoxide are dissolved in an alcohol-based solvent to form a mixture which is dispensed into a substantially planar configuration, transitioned through a gel phase, dried and cured to a substantially dry phase.
US09356316B2	Pinhole-free solid state electrolytes with high ionic conductivity The present invention relates to vacuum-deposited solid state electrolyte layers with high ionic conductivity in electrochemical devices, and methods and tools for fabricating said electrolyte layers. An electrochemical device may comprise solid state electrolytes with incorporated thin layers and/or particles of transition metal oxides, silicon, silicon oxide, or other suitable materials that will induce an increase in ionic conductivity of the electrolyte stack (for example, materials with which lithium is able to intercalate), or mixtures thereof. An improvement in ionic conductivity of the solid state electrolyte is expected which is proportional to the number of incorporated layers or a function of the distribution uniformity and density of the particles within the electrolyte. Embodiments of the present invention are applicable to solid state electrolytes in a broad range of electrochemical devices including thin film batteries, electrochromic devices and ultracapacitors. The solid state electrolyte layers may be nominally pinhole-free.
US09356313B2	Solid electrolyte for lithium battery, comprising at least one zone of lithium-containing glass ceramic material and method of production At least one zone made of lithium-containing glass-ceramic material, in a solid electrolyte for a lithium battery, is formed from a lithium-containing ceramic material, advantageously in the form of a layer such as a thin film. It is obtained by melting of at least a part of the lithium-containing ceramic material, followed by a recrystallization heat treatment. Melting is obtained by a laser beam irradiation operation, which enables fabrication of the solid electrolyte to be performed directly on a multilayer stack comprising certain active components of the lithium battery.
US09356311B1	Manufacturing a display with integrated battery Manufacturing an electronic device including embedding a first electrochemical cell and a second electrochemical cell in an insulative substrate. The first electrochemical cell and the second electrochemical cell are separated from one another by a distance that is greater than half a cell diameter of at least one of the first electrochemical cell or the second electrochemical cell.
US09356310B2	Method for forming a microbattery A method for forming a microbattery including, on a surface of a first substrate, one active battery element and two contact pads, this method including the steps of: a) forming, on a surface of a second substrate, two contact pads with a spacing compatible with the spacing of the pads of the first substrate; and b) arranging the first substrate on the second substrate so that the surfaces face each other and that the pads of the first substrate at least partially superpose to those of the second substrate, where a portion of the pads of the second substrate is not covered by the first substrate.
US09356307B2	Multiple stack fuel cell system A fuel cell system is disclosed comprising a plurality of fuel cell modules including a sealed planar fuel cell stack, the stack including internal manifold channels for transport of fuel and air to fuel cells within the stack and transport of tail gas and spent air away from fuel cells within the stack. Each of the fuel cell stacks is mounted on a stack footprint area of a top member of a base manifold. The base manifolds are configured to allow for interconnection of a number of fuel cell stack modules to provide a fuel cell system capable of producing power outputs that otherwise would have required large surface area cells or stack with a large number of cells.
US09356305B2	Fuel cells This invention relates to fuel cells. A fuel cell 10 defines a space 11 having an air/ethanol inlet 12 and an outlet source 13. The operative part of the fuel cell, 14, includes a pvc substrate 15, a working electrode 16 and a counter electrode 17. A working electrode current collector 20 extends over the working electrode 16, whilst a counter electrode current collector 21 extends across the counter electrode 17. The electrodes formed from tantalum. At least one of the current collector electrodes 20, 21 are non-conformably depressed into their associated electrode to define a channel for containing electrolyte whereby charge can be transferred to the current collector by ionic exchange.
US09356303B2	System and method for sensing and mitigating hydrogen evolution within a flow battery system A method is provided for mitigating hydrogen evolution within a flow battery system that includes a plurality of flow battery cells, a power converter and an electrochemical cell. The method includes providing hydrogen generated by the hydrogen evolution within the flow battery system to the electrochemical cell. A first electrical current generated by an electrochemical reaction between the hydrogen and a reactant is sensed, and the sensed current is used to control an exchange of electrical power between the flow battery cells and the power converter.
US09356300B2	Fuel cell electrode interconnect contact material encapsulation and method A fuel cell stack includes a plurality of fuel cell cassettes each including a fuel cell with an anode and a cathode. Each fuel cell cassette also includes an electrode interconnect adjacent to the anode or the cathode for providing electrical communication between an adjacent fuel cell cassette and the anode or the cathode. The interconnect includes a plurality of electrode interconnect protrusions defining a flow passage along the anode or the cathode for communicating oxidant or fuel to the anode or the cathode. An electrically conductive material is disposed between at least one of the electrode interconnect protrusions and the anode or the cathode in order to provide a stable electrical contact between the electrode interconnect and the anode or cathode. An encapsulating arrangement segregates the electrically conductive material from the flow passage thereby, preventing volatilization of the electrically conductive material in use of the fuel cell stack.
US09356298B2	Abrasion resistant solid oxide fuel cell electrode ink A method for forming a solid oxide fuel cell (SOFC) includes co-firing the anode and cathode electrode layers, which involves placing an unfired anode onto a surface during the cathode print cycle. To avoid damage to the electrolyte and cathode production cycle by the green anode ink, an abrasion resistant ink is used to print the anode electrode layer.
US09356289B2	Secondary battery A secondary battery 100 includes: a positive electrode mixture layer 223 containing a positive electrode active material 610 and an electrically conductive material 620; a positive electrode current collector 221 on which the positive electrode mixture layer 223 is coated; a negative electrode mixture layer 243 containing a negative electrode active material 710; and a negative electrode current collector 241 on which the negative electrode mixture layer 243 is coated, wherein a porosity A1 of the positive electrode mixture layer 223 satisfies 0.30≦A1 and, at the same time, a porosity A2 of the negative electrode mixture layer 243 satisfies 0.30≦A2.
US09356288B2	Transition metal composite hydroxide and lithium composite metal oxide Provided are a transition metal mixed hydroxide comprising an alkali metal other than Li, SO4 and a transition metal element, wherein the molar ratio of the molar content of the alkali metal to the molar content of the SO4 is not less than 0.05 and less than 2, and a lithium mixed metal oxide obtained by calcining a mixture of the transition metal mixed hydroxide and a lithium compound by maintaining the mixture at a temperature of 650 to 1000° C.
US09356282B2	Method of manufacture of homodispersed silicon carbide-derived carbon composites The present invention concerns a method of manufacture of the homodispersed composite of the synthetic carbon material derived from carbide and silicon where the powder of the carbon material is first dispersed mechanically with the powder of silicon to homodispersed mixture, then the homodispersed mixture of the carbon material and silicon is sintered in an inert environment at a temperature between 1200 to 1500° C. to synthetic homodispersed composite of the silicon carbide and silicon. The homodispersed composite of the silicon carbide and silicon is heated in an inert environment at a temperature between 800 to 1100° C. and then the homodispersed composite of the silicon carbide and silicon is chlorinated at a temperature from 800 to 100° C.
US09356280B2	Lithium ion secondary battery electrode, method of manufacturing the same, and lithium ion secondary battery A lithium ion secondary battery electrode according to the present invention includes (A) a non-fluorinated polymer; (B) an active material; (C) a thickener; and (D) a conductive auxiliary agent. An elution ratio of (A) the non-fluorinated polymer in an electrolytic solution solvent at 60° C. is equal to or less than 1.0 mass %, and a swelling ratio of (A) the non-fluorinated polymer in the electrolytic solution solvent at 60° C. is equal to or more than 10 mass % and equal to or less than 50 mass %.
US09356278B2	Battery pack In order to provide a battery pack that can be produced highly efficiently and contribute to an improvement in productivity, a battery pack of the present invention includes: a plurality of unit batteries 100 that include a positive-electrode pulled-out tab 120 and a negative-electrode pulled-out tab 130; and a board 300 on which pulled-out tab connection sections are formed to connect the pulled-out tabs of different polarities of adjacent unit batteries 100.
US09356275B2	Laminated separator including inorganic particle and polyolefin layer for electricity storage device Disclosed is a laminated separator including a first polyolefin microporous layer and a second polyolefin microporous layer which is laminated on the first polyolefin microporous layer and which is different from the first polyolefin microporous layer, wherein at least one of the first microporous layer and the second microporous layer includes an inorganic particle having a primary particle size of 1 nm or more and 80 nm or less.
US09356273B2	Nonaqueous electrolyte secondary battery and separator A nonaqueous electrolyte secondary battery includes a positive electrode, a negative electrode, and a separator disposed between the positive electrode and the negative electrode. The separator includes a substrate layer and a surface layer formed on at least one principal plane of the substrate layer, the surface layer contains polyvinylidene fluoride and an inorganic material particle, and an amount of deformation against pressure of the surface layer is larger than that of the substrate layer.
US09356263B2	Lithium secondary battery including a gasket having an adhesive layer A cylinder type lithium secondary battery may include an electrode assembly, a cylindrical can configured to retain the electrode assembly, a cap assembly coupled to a top opening of the cylindrical can, an electrolyte disposed in the cylindrical can, and a gasket between the cap assembly and the cylindrical can, the gasket including an adhesive layer having a reaction product of the electrolyte and a material of the gasket.
US09356260B2	Active organic electroluminescence device back panel and manufacturing method thereof The present invention provides an active organic electroluminescence device back panel and a manufacturing method thereof. The device back panel includes: a substrate (20), a plurality of active TFT pixel arrays formed on the substrate (20), and organic planarization layers (228), organic electroluminescence electrodes (229), pixel definition layers (25), and support bodies (28) formed on the active TFT pixel arrays. Each of the active TFT pixel arrays includes a driving TFT (22) and a switch TFT (24). The driving TFT (22) has a gate insulation layer (220) that has a thickness greater than a thickness of a gate insulation layer (240) of the switch TFT (24). Through thickening the gate insulation layer of the driving TFT, the gate capacitance of the driving TFT can be reduced and the sub-threshold swing of the driving TFT is increased to realize well definition of grey levels. Further, the thickness of the gate insulation layer of the switch TFT can be kept unchanged so that the sub-threshold swing of the switch TFT maintains relatively small so as to lower down the operating voltage and increase the circuit operation speed to thereby effectively improve the quality of the organic electroluminescence device.
US09356257B2	Organic light-emitting display apparatus and method of manufacturing the same In an aspect, an organic light-emitting display apparatus and a method of manufacturing the same are provided. The organic light-emitting display apparatus may include a substrate; a display unit formed on the substrate; and a thin film encapsulating layer encapsulating the display unit. The thin film encapsulating layer may include a plurality of organic layers and inorganic layers that are laminated alternately. At least one of the plurality of the inorganic films may include a first layer formed of a first material, a second layer formed of a second material other than the first material, and an intermediate layer provided between the first and second layers.
US09356254B2	Organic EL display device and method for producing the same A method includes: forming, in a first substrate, a display area in which a plurality of pixels including an organic EL light-emitting layer are arrayed; forming, in a second substrate, a plurality of opening areas respectively located in correspondence with the plurality of pixels and a light-blocking area that demarcates the plurality of opening areas; providing a dam material such that the dam material encloses the display area; dripping a filler material to an area enclosed by the dam material; and attaching the first substrate and the second substrate to each other, and fusing together dripped portions of the filler material, thereby bonding the both substrates to each other. The both substrates are attached to each other while being positionally aligned such that borders between the dripped portions of the filler material that is generated by the fusion are located in an area corresponding to the light-blocking area.
US09356248B2	Organic thin-film transistor An n-type organic thin-film transistor including a substrate, a gate, and a dielectric layer covering the substrate and the gate. A semiconductor-insulator polymer blend layer is disposed on the dielectric layer; A source and a drain are disposed on top of the semiconductor-insulator polymer blend layer.
US09356245B2	Carbene metal complexes as OLED materials An organic light emitting device having an anode, a cathode and an organic layer disposed between the anode and the cathode is provided. In one aspect, the organic layer comprises a compound having at least one zwitterionic carbon donor ligand.
US09356237B2	Forming resistive random access memories together with fuse arrays A resistive random access memory array may be formed on the same substrate with a fuse array. The random access memory and the fuse array may use the same active material. For example, both the fuse array and the memory array may use a chalcogenide material as the active switching material. The main array may use a pattern of perpendicular sets of trench isolations and the fuse array may only use one set of parallel trench isolations. As a result, the fuse array may have a conductive line extending continuously between adjacent trench isolations. In some embodiments, this continuous line may reduce the resistance of the conductive path through the fuses.
US09356235B2	Structure and formation method of memory device Structures and formation methods of memory devices are provided. The memory device includes a first electrode, a second electrode, and a resistive layer positioned between the first electrode and the second electrode. The resistive layer has a crystalline portion. A volume ratio of the crystalline portion to the resistive layer is in a range from about 0.2 to about 1.
US09356228B2	Magnetic tunneling junction devices, memories, memory systems, and electronic devices Provided is a magnetic tunneling junction device including a first structure including a magnetic layer; a second structure including at least two extrinsic perpendicular magnetization structures, each including a magnetic layer and; a perpendicular magnetization inducing layer on the magnetic layer; and a tunnel barrier between the first and second structures.
US09356227B2	Method for manufacturing a piezoelectric element A piezoelectric element includes a support body having a displacing part capable of undergoing displacement, a lower electrode layer having a lower main electrode body and a lower electrode wire part with the lower main electrode body being formed on the support body and provided within the displacing part in a plan view and the lower electrode wire part being connected to the lower main electrode body and provided across an interior and an exterior of the displacing part, a first piezoelectric layer provided on the lower main electrode body, an upper electrode layer provided across the interior and exterior of the displacing part with at least a part of the upper electrode layer being layered on the first piezoelectric layer and insulated from the lower electrode layer, and a second piezoelectric layer provided on the support body to cover at least a part of the lower electrode wire part.
US09356223B2	Liquid ejecting head and liquid ejecting apparatus A liquid ejecting head includes a plate which is composed of a material containing silicon, a titanium oxide layer which is disposed above the plate, a bismuth-containing layer which is disposed above the titanium oxide layer and contains bismuth, a first electrode which is disposed above the bismuth-containing layer and composed of platinum, a piezoelectric layer which is disposed above the first electrode and composed of a piezoelectric material containing at least bismuth, and a second electrode which is disposed above the piezoelectric layer.
US09356221B2	Piezoelectric vibrator Disclosed is piezoelectric vibrator including a piezoelectric vibrator unit. The piezoelectric vibrator has a vibrating portion, a mass attached on the vibrating portion and having an connecting portion attached on the vibrating portion and at least one extending portion extending from the connecting portion and away from the vibrating portion, and a holder having a stopping portion disposed between the extending portion of the mass and the vibrating portion. A distance from the extending portion to the at least one stopping portion is less than the amplitude of the vibration portion for limiting the vibrating portion and avoiding excessive amplitude of the vibrating portion.
US09356217B2	Electrically conductive composition, an electrically conductive film using the composition and a method of producing the same An electrically conductive composition, containing (A) a carbon nanotube, (B) an electrically conductive polymer, and (C) an onium salt compound, an electrically conductive film using the composition, and a method of producing the electrically conductive film.
US09356208B2	Manufacturing method of pixel structure A manufacturing method of pixel structure includes forming a first conductive layer on a substrate and forming a first insulation layer thereon; forming a second conductive layer on the first insulation layer; forming a second insulation layer on the second conductive layer; forming a semiconductor layer on the second insulation layer above the gate; forming a third conductive layer on the second insulation layer, wherein the gate, the semiconductor layer, the source, and the drain together constitute a thin film transistor, and the first electrode, the second electrode, and the third electrode together constitute a capacitor; forming a third insulation layer on the third conductive layer; and forming a pixel electrode on the third insulation layer, the pixel electrode being electrically connected to the drain.
US09356206B2	Light emitting device A light emitting device includes a semiconductor light emitting element that is disposed on a surface of a board, a transparent phosphor plate that includes phosphors, a transparent bonding member that fixedly bonds an upper surface of the semiconductor light emitting element to a lower surface of the phosphor plate, and a reflective layer that surrounds the semiconductor light emitting element and the phosphor plate and contains light-reflective fine particles. The semiconductor light emitting element includes an exposed portion that is provided near an outer peripheral edge of the upper surface of the semiconductor light emitting element and is not covered by the phosphor plate but exposed. A portion of an outer peripheral end surface of the phosphor plate, which is located near the upper surface of the phosphor plate, is not covered by the bonding member.
US09356204B2	Using quantum dots for extending the color gamut of LCD displays A light emitting diode system, with an LED junction, energized to emit light, and a lens cap, covering the LED junction device and receiving the light. The lens cap can be formed in a shape to focus the light, for example. The material forming the lens cap has quantum dots mixed in with the supporting material, which can be in multiple colors. The supporting material can also have particles of glass or other crystalline material mixed therein. There can also be an outer casing over the supporting material, and the outer casing can also have glass or other crystalline particles mixed in.
US09356202B2	Wavelength converting material and application thereof This disclosure discloses a wavelength converting material. The wavelength converting material comprises a plurality of wavelength converting particles, the wavelength converting particles having an average particle size greater than 5 μm, and wherein each of the wavelength converting particles has a particle size. 90% of the wavelength converting particles have the particle size smaller than a μm; 50% of the wavelength converting particles have the particle size smaller than b μm; and 10% of the wavelength converting particles have the particle size smaller than c μm; wherein (a−c)/b≦0.5.
US09356201B2	Die emitting white light Various methods and apparatuses are disclosed. A method may include disposing at least one die on a location on a carrier substrate, forming at least one stud bump on each of at least one die, forming a phosphor layer on the at least one stud bump and the at least one die, removing a top portion of the phosphor layer to expose the at least one stud bump, and removing a side portion of the phosphor layer located between two adjacent dies. An apparatus may include a die comprising top, bottom, and side surfaces. A phosphor layer may be disposed on the top, bottom, and side surfaces of the die. The phosphor layer may have substantially equal thicknesses on the top and side surfaces of the die as well as one or more stud bumps disposed on the top surface of the die.
US09356200B2	Light emitting device package Disclosed is a light emitting device package including a package body having at least one cavity, at least one light emitting device mounted on the cavity, and a molding member disposed on the light emitting device to fill the cavity. The package body has at least one first recess formed at an upper portion than a bottom surface of the cavity, and the molding member is disposed to an inner edge of the at least one first recess.
US09356198B2	Light emitting device having wide beam angle and method of fabricating the same A light emitting device having a wide beam angle and a method of fabricating the same. The light emitting device includes a light emitting structure, a substrate disposed on the light emitting structure, and an anti-reflection layer covering side surfaces of the light emitting structure and the substrate, and at least a portion of an upper surface of the substrate is exposed.
US09356196B2	Method of manufacturing light emitting element A method of manufacturing a semiconductor light emitting element includes providing a semiconductor stacked layer body; forming an insulating layer on a portion of the semiconductor stacked layer body; forming a light-transmissive electrode covering an upper surface of the semiconductor stacked layer body and an upper surface of the insulating layer, and on a region at least partially overlapping a region for disposing an extending portion in a plan view; forming a light reflecting layer in each of the openings of the light-transmissive electrode; forming a protective layer on a main surface side of the semiconductor stacked layer body; forming a mask on an upper surface of the protective layer except for the region for forming the pad electrode; etching the protective layer to form an opening in the protective layer; and forming a pad electrode in the opening of the protective layer.
US09356191B2	Epitaxial layer wafer having void for separating growth substrate therefrom and semiconductor device fabricated using the same An epitaxial wafer includes a growth substrate, a mask pattern disposed on the growth substrate and comprising a masking region and an opening region, and an epitaxial layer covering the mask pattern and including a first void disposed on the masking region. The first void includes a lower void disposed between a lower surface of the epitaxial layer and the masking region, and an upper void extending from the lower void into the epitaxial layer, the lower void having a greater width than the upper void.
US09356188B2	Tensile separation of a semiconducting stack A stressor layer is applied to a semiconducting stack in order to separate the semiconducting stack at a predetermined depth. Tensile force is applied to the stressor layer, fracturing the semiconducting stack at the predetermined depth and allowing the resulting upper portion of the semiconducting stack to be used in manufacturing a semiconducting end-product (e.g., a light-emitting diode). The resulting lower portion of the semiconducting stack may be reused to grow a new semiconducting stack thereon.
US09356184B2	Shingled solar cell module A high efficiency configuration for a solar cell module comprises solar cells arranged in a shingled manner to form super cells, which may be arranged to efficiently use the area of the solar module, reduce series resistance, and increase module efficiency.
US09356183B1	Optoelectronic device with enhanced efficiency and method of use A compound III/V optoelectronic device and method associated with such a device is disclosed. In one aspect, a method for an improved III/V compound optoelectronic device is disclosed. The method comprises applying a sulfur surfactant on the III/V compound optoelectronic device to improve passivation of the III/V compound optoelectronic device. In a second aspect, a III/V compound optoelectronic device is disclosed. The III/V compound optoelectronic device comprises a thin film device with a III/V compound semiconductor absorbing material, and a sulfur surfactant on the III/V compound thin film device to improve passivation of the III/V compound optoelectronic device.
US09356181B2	Substrate cleaving under controlled stress conditions A thickness of material may be detached from a substrate along a cleave plane, utilizing a cleaving process controlled by a releasable constraint plate. In some embodiments this constraint plate may comprise a plate that can couple side forces (the “P-plate”) and a thin, softer compliant layer (the “S-layer”) situated between the P-plate and the substrate. In certain embodiments a porous surface within the releasable constraint plate and in contact to the substrate, allows the constraint plate to be secured to the substrate via a first pressure differential. Application of a combination of a second pressure differential within a pre-existing cleaved portion, and a linear force to a side of the releasable constraint plate bound to the substrate, generates loading that results in controlled cleaving along the cleave plane.
US09356179B2	Display panel integrated with photoelectric device A display panel comprising a substrate, a meshed shielding pattern, a plurality of light-emitting devices and a solar cell is provided. The substrate has a first surface and a second surface opposite to the first surface, the substrate comprises a first circuit layer disposed over the first surface and a second circuit layer disposed over the second surface. The meshed shielding pattern is disposed on first surface of the substrate to define a plurality of pixel regions over the substrate. The light-emitting devices are disposed on the first surface of the substrate and electrically connected to the first circuit layer, and at least one of the light-emitting devices is disposed in one of the pixel regions. The solar cell is disposed on the second surface of the substrate and electrically connected to the second circuit layer.
US09356174B2	Roofing flashings and roofing systems and photovoltaic roofing systems using the same The present invention relates more particularly to improved flashings for use in integrating specialized roof-mounted structures, such as photovoltaic devices for the generation of electrical energy, with conventional roofing materials on a roof. In one aspect, the invention provides a flashing element having a cross-sectional shape comprising a laterally-extending flange, the flange having an edge, a first end and a second end, the side flashing element comprising a return hem disposed at the edge and comprising a folded-over strip of material disposed over the top surface of the flange at the edge, the return hem having a first end disposed toward the first end of the edge, and a second end disposed toward the second end of the edge, wherein the total thickness of the return hem at its second end is no greater than the interior thickness of the return hem at its first end.
US09356173B2	Dynamically reconfigurable photovoltaic system A PV system composed of sub-arrays, each having a group of PV cells that are electrically connected to each other. A power management circuit for each sub-array has a communications interface and serves to connect or disconnect the sub-array to a programmable power grid. The power grid has bus rows and bus columns. A bus management circuit is positioned at a respective junction of a bus column and a bus row and is programmable through its communication interface to connect or disconnect a power path in the grid. As a result, selected sub-arrays are connected by selected power paths to be in parallel so as to produce a low system voltage, and, alternately in series so as to produce a high system voltage that is greater than the low voltage by at least a factor of ten.
US09356171B2	Method of forming single-crystal semiconductor layers and photovaltaic cell thereon A method for forming single crystal or large-crystal-grain thin-film layers deposits a thin-film amorphous, nanocrystalline, microcrystalline, or polycrystalline layer, and laser-heats a seed spot having size on the order of a critical nucleation size of the thin-film layer. The single-crystal seed spot is extended into a single-crystal seed line by laser-heating one or more crystallization zones adjacent to the seed spot and drawing the zone across the thin-film layer. The single-crystal seed line is extended across the thin-film material layer into a single-crystal layer by laser-heating an adjacent linear crystallization zone and drawing the crystallization zone across the thin-film layer. Photovoltaic cells may be formed in or on the single-crystal layer. Tandem photovoltaic devices may be formed using one or several iterations of the method. The method may also be used to form single-crystal semiconductor thin-film transistors, such as for display devices, or to form single-crystal superconductor layers.
US09356170B2	THz distributed detectors and arrays Terahertz (THz) distributed detectors, and arrays of detectors that utilize structured surface plasmonic effects for more efficient coupling to free space are discussed. One example distributed detector includes a detector junction comprising a Schottky or tunneling interface between a semiconductor and a detector metal, an ohmic junction comprising an ohmic interface between the semiconductor and an ohmic metal, and a gap that separates the detector junction from the ohmic junction. Structured surface plasmons concentrate an electric field in the gap when the distributed detector is exposed to THz radiation polarized perpendicular to the gap.
US09356169B2	Apparatus, system and method of back side illumination (BSI) complementary metal-oxide-semiconductor (CMOS) pixel array Some demonstrative embodiments include devices and/or methods of Back Side Illumination (BSI) Complementary Metal-Oxide-Semiconductor (CMOS) pixel array. For example, a BSI CMOS pixel array may include a plurality of pixels, a pixel of the plurality of pixels may include one or more Metal-Oxide-Semiconductor (MOS) transistors comprising one or more well regions, a well region of the one or more well regions comprising an N-Well (NW) region or a P-well (PW) region; a photodiode; an epitaxial (epi) layer comprising an absorption area and a collection area, the absorption area to absorb incoming photons and to generate electrons responsive to absorbed photons, and the collection area connecting the absorption area to the photodiode to provide the electrons from the absorption area to the photodiode; and a barrier layer separating the absorption area from the one or more well regions.
US09356164B2	Integrated photodetector waveguide structure with alignment tolerance An encapsulated integrated photodetector waveguide structures with alignment tolerance and methods of manufacture are disclosed. The method includes forming a waveguide structure bounded by one or more shallow trench isolation (STI) structure(s). The method further includes forming a photodetector fully landed on the waveguide structure.
US09356163B1	Structure and method of integrating waveguides, photodetectors and logic devices A method for monolithically integrating semiconductor waveguides, photodetectors and logic devices, i.e., field effect transistors, on a same substrate is provided. The method includes the use of a double semiconductor-on-insulator substrate that includes from bottom to top, a handle substrate, a first insulator layer, a first semiconductor material layer, a second insulator layer, and a second semiconductor material layer. The waveguides, photodetectors and logic devices can be formed in different regions of the substrate and are present atop a first insulator layer of the double semiconductor-on-insulator substrate.
US09356157B2	Semiconductor devices comprising floating gate transistors and methods of forming such semiconductor devices Semiconductor devices include one or more transistors having a floating gate and a control gate. In at least one embodiment, the floating gate comprises an intermediate portion extending between two end portions. The intermediate portion has an average cross-sectional area less than one or both of the end portions. In some embodiments, the intermediate portion may comprise a single nanowire. In additional embodiments, semiconductor devices have one or more transistors having a control gate and a floating gate in which a surface of the control gate opposes a lateral side surface of a floating gate that defines a recess in the floating gate. Electronic systems include such semiconductor devices. Methods of forming semiconductor devices include, for example, forming a floating gate having an intermediate portion extending between two end portions, and configuring the intermediate portion to have an average cross-sectional area less than one or both of the end portions.
US09356156B2	Stable high mobility MOTFT and fabrication at low temperature A method of fabricating a stable high mobility amorphous MOTFT includes a step of providing a substrate with a gate formed thereon and a gate dielectric layer positioned over the gate. A carrier transport structure is deposited by sputtering on the gate dielectric layer. The carrier transport structure includes a layer of amorphous high mobility metal oxide adjacent the gate dielectric and a relatively inert protective layer of material deposited on the layer of amorphous high mobility metal oxide both deposited without oxygen and in situ. The layer of amorphous metal oxide has a mobility above 40 cm2/Vs and a carrier concentration in a range of approximately 1018 cm−3 to approximately 5×1019 cm−3. Source/drain contacts are positioned on the protective layer and in electrical contact therewith.
US09356155B2	Semiconductor device structures and arrays of vertical transistor devices A semiconductor device structure is disclosed. The semiconductor device structure includes a mesa extending above a substrate. The mesa has a channel region between a first side and second side of the mesa. A first gate is on a first side of the mesa, the first gate comprising a first gate insulator and a first gate conductor comprising graphene overlying the first gate insulator. The gate conductor may comprise graphene in one or more monolayers. Also disclosed are a method for fabricating the semiconductor device structure; an array of vertical transistor devices, including semiconductor devices having the structure disclosed; and a method for fabricating the array of vertical transistor devices.
US09356151B2	Fabrication of graphene nanoribbons and nanowires using a meniscus as an etch mask In some embodiments, the present disclosure pertains to methods of preparing graphene nanoribbons from a graphene film associated with a meniscus, where the method comprises patterning the graphene film while the meniscus acts as a mask above a region of the graphene film, and where the patterning results in formation of graphene nanoribbons from the meniscus-masked region of the graphene film. Additional embodiments of the present disclosure pertain to methods of preparing wires from a film associated with a meniscus, where the method comprises patterning the film while the meniscus acts as a mask above a region of the film, and where the patterning results in formation of a wire from the meniscus-masked region of the film. Additional embodiments of the present disclosure pertain to chemical methods of preparing wires from water-reactive materials.
US09356150B2	Method for incorporating impurity element in EPI silicon process The present disclosure provides a method of fabricating a semiconductor device that includes forming a plurality of fins, the fins being isolated from each other by an isolation structure, forming a gate structure over a portion of each fin; forming spacers on sidewalls of the gate structure, respectively, etching a remaining portion of each fin thereby forming a recess, epitaxially growing silicon to fill the recess including incorporating an impurity element selected from the group consisting of germanium (Ge), indium (In), and carbon (C), and doping the silicon epi with an n-type dopant.
US09356148B2	Fin-type semiconductor device and manufacturing method One embodiment of a semiconductor device includes a fin at a first side of a semiconductor body, a body region of a second conductivity type in at least a part of the fin, a drain extension region of a first conductivity type, a source region and a drain region of the first conductivity type, a source contact in contact with the source region, the source contact extending along a vertical direction along the source region, and a gate structure adjoining opposing walls of the fin. The body region and the drain extension region are arranged one after another between the source region and the drain region.
US09356146B2	Semiconductor device with recess, epitaxial source/drain region and diffuson A semiconductor device including a gate electrode disposed on a semiconductor substrate and source/drain regions disposed at both sides of the gate electrode, the source/drain regions being formed by implanting impurities. The source/drain regions include an epitaxial layer formed by epitaxially growing a semiconductor material having a different lattice constant from that of the semiconductor substrate in a recessed position at a side of the gate electrode, and a diffusion layer disposed in a surface layer of the semiconductor substrate.
US09356145B2	Electronic device with asymmetric gate strain The use of strained gate electrodes in integrated circuits results in a transistor having improved carrier mobility, improved drive characteristics, and reduced source drain junction leakage. The gate electrode strain can be obtained through non symmetric placement of stress inducing structures as part of the gate electrode.
US09356144B1	Remote gate protection diode for field effect transistors The present disclosure relates to gate oxide protection circuits, which are used to protect the gate oxides of field effect transistor (FET) elements from over voltage conditions, particularly during situations in which the gate oxides are particularly vulnerable, such as during certain manufacturing stages. Each gate oxide protection circuit may be coupled to a corresponding FET element through corresponding first and second resistive elements, which are coupled to a corresponding gate connection node and a corresponding first connection node, respectively, of the FET element. The gate connection node and the first connection node are electrically adjacent to opposite sides of the gate oxide of the FET element. Each gate oxide protection circuit may protect its corresponding FET element by limiting a voltage between the gate connection node and the first connection node.
US09356138B2	Semiconductor device There is provided a semiconductor device having LDMOS transistors embedded in a semiconductor substrate to boost source-drain breakdown voltage, with arrangements to prevent fluctuations of element characteristics caused by electric field concentration so that the reliability of the semiconductor device is improved. A trench is formed over the upper surface of a separation insulating film of each LDMOS transistor, the trench having a gate electrode partially embedded therein. This structure prevents electric field concentration in the semiconductor substrate near the source-side edge of the separation insulating film.
US09356137B2	Power MOS device structure Various embodiments of a power MOS device structure are disclosed. In one aspect, a power MOS device structure includes a plurality of LDMOS and a plurality of bonding pads. The basic units of LDMOS are coupled in parallel and electrically coupled to the bonding pads to couple to a gate terminal, a source terminal, a drain terminal and a substrate of each of the basic units of LDMOS. The basic units of LDMOS are disposed below the bonding pads. The bonding pads include a single layer of metal with a thickness of 3.5 um to 4.5 um and a width of 1.5 um to 2.5 um. The region below the bonding pads of the power MOS device of the present disclosure is utilized to increase the number of basic units of LDMOS, thereby effectively reducing the on-resistance.
US09356136B2	Engineered source/drain region for n-Type MOSFET Integrated circuit devices with field effect transistors have source and drain regions that include a first and a second layer. The first layer is formed below the plane of the channel region. The first layer includes doped silicon and carbon that has a crystal lattice structure that is smaller than that of silicon. The second layer is formed over the first layer and rises above the plane of the channel region. The second layer is formed by a material that includes doped epitaxially grown silicon. The second layer has an atomic fraction of carbon less than half that of the first layer. The first layer is formed to a depth at least 10 nm below the surface of the channel region. This structure facilitates the formation of source and drain extension areas that form very shallow junctions. The devices provide sources and drains that have low resistance while being comparatively resistant to short channel effects.
US09356135B2	Semiconductor device and method of manufacturing the same To provide a semiconductor device capable of suppressing a reduction in breakdown voltage by suppressing a change in dimensions of a double RESURF structure, and a method of manufacturing the same.In the semiconductor device, an upper RESURF region is formed so as to contact with a first buried region on a side of the one main surface within a semiconductor substrate. The semiconductor substrate has a field oxide formed so as to reach the upper RESURF region on the one main surface. The semiconductor substrate includes a second conductivity type body region formed so as to contact with the upper RESURF region on a side of the one main surface and so as to neighbor the field oxide within the semiconductor substrate.
US09356131B2	Metal-gate MOS transistor and method of forming the transistor with reduced gate-to-source and gate-to-drain overlap capacitance The gate-to-source and gate-to-drain overlap capacitance of a MOS transistor with a metal gate and a high-k gate dielectric are reduced by forming the high-k gate dielectric along the inside of a sidewall structure which has been formed to lie further away from the source and the drain.
US09356127B2	Layout structure of heterojunction bipolar transistors A layout structure of HBTs comprising one or more HBTs, each of which comprises a base electrode, an emitter electrode, and a collector electrode. A passive layer, a first dielectric layer, a collector redistribution layers, one or more emitter copper pillars, and one or more collector copper pillars are formed above the one or more HBTs. The passive layer comprises a collector and an emitter pads. The first dielectric layer has one or more emitter and collector via holes. The emitter copper pillar is disposed on the emitter via hole and forms an electrical connection to the emitter electrode. The collector copper pillar is disposed on the collector redistribution layer and forms electrical connection to the collector electrode. The layout design of the emitter and collector copper pillars is therefore flexible, and the heat dissipation efficiency is improved.
US09356124B2	Method for fabricating multi-gate structure device with source and drain having quasi-SOI structure A method for fabricating a multi-gate structure device with a source and a drain having a quasi-SOI structure, comprising forming an active region in a shape of a fin bar, forming an oxide isolation layer for shallow trench isolation (STI), forming a polysilicon dummy gate, forming source and drain extension regions, forming the source and the drain with the quasi-SOI structure, and forming a high-K metal gate. Solution(s) consistent with the present innovations may be achieved by using a process method compatible with the conventional bulk silicon CMOS processes and can be easily integrated into the process flow. Moreover, innovations here may provide a small leakage current even in a case of having a short channel length, thereby reducing the power consumption of the device.
US09356121B2	Divot-free planarization dielectric layer for replacement gate After formation of a silicon nitride gate spacer and a silicon nitride liner overlying a disposable gate structure, a dielectric material layer is deposited, which includes a dielectric material that is not prone to material loss during subsequent exposure to wet or dry etch chemicals employed to remove disposable gate materials in the disposable gate structure. The dielectric material can be a spin-on dielectric material or can be a dielectric metal oxide material. The dielectric material layer and the silicon nitride liner are planarized to provide a planarized dielectric surface in which the disposable gate materials are physically exposed. Surfaces of the planarized dielectric layer is not recessed relative to surfaces of the silicon nitride layer during removal of the disposable gate materials and prior to formation of replacement gate structures, thereby preventing formation of metallic stringers.
US09356118B2	Metalization of a field effect power transistor A metalization of a field effect power transistor having lateral semiconductor layers on an insulator substrate or an intrinsically conducting semiconductor substrate is described. The lateral semiconductor layers have different band gaps such that a two-dimensional electron gas can form in their semiconductor depletion layer. Upon application of a voltage between source electrode contact areas and drain electrode contact areas or source and drain, an electric current can flow through the lateral semiconductor depletion layer. Current intensity in a channel region between the source electrode contact areas and the drain electrode contact areas is controllable via gate electrode contact areas by means of a gate voltage.
US09356117B2	Method for forming avalanche energy handling capable III-nitride transistors A method for forming a semiconductor device including a GaN FET, an overvoltage clamping component, and a voltage dropping component. The GaN FET is formed by forming a low-defect layer comprising gallium nitride, a barrier layer comprising AlxGa1−xN, a gate, and source and drain contacts. The overvoltage clamping component is coupled to a drain node of the GaN FET. The overvoltage clamping component conducts insignificant current when a voltage at the drain node is less than a safe voltage limit and conducts significant current when the voltage rises above the safe voltage limit. The voltage dropping component is coupled to the overvoltage clamping component and to a terminal for a bias potential. The voltage dropping component provides a voltage drop which increases as current from the overvoltage clamping component increases. The GaN FET turns on when the voltage drop reaches a threshold value.
US09356116B2	Power semiconductor device and method of fabricating the same There is provided a power semiconductor device, including a first conductive type drift layer; a second conductive type body layer formed on the drift layer, a second conductive type collector layer formed below the drift layer; a first gate formed by penetrating through the body layer and a portion of the drift layer, a first conductive type emitter layer formed in the body layer and formed to be spaced apart from the first gate, a second gate covering upper portions of the body layer and the emitter layer and formed as a flat type gate on the first gate, and a segregation stop layer formed between contact surfaces of the first and second gates with the body layer, the emitter layer, and the drift layer.
US09356115B2	Method of manufacturing a semiconductor device A method of manufacturing an RC-IGBT provided with an IGBT and an FWD on the same substrate is provided. First, top surface device structures of an IGBT and an FWD are formed on the top surface of a semiconductor substrate. Then, with the side of an IGBT region on the top surface of the semiconductor substrate shielded by a first shielding mask, only an FWD region is irradiated with light ions. Next, with the side of the FWD region on the bottom surface of the semiconductor substrate shielded by a second shielding mask, only the IGBT region is irradiated with light ions. With this, a first lifetime control region 10-1 is formed on the collector side A2 in the IGBT region A1-A2 and a second lifetime control region 10-2 is formed on the anode side B1 of the FWD region B1-B2.
US09356114B2	Lateral heterojunction bipolar transistor with low temperature recessed contacts A method of forming the heterojunction bipolar transistor that includes providing a stack of a base layer, an extrinsic base layer, a first metal containing layer, and a dielectric cap layer. The dielectric cap layer and the first metal containing layer may be etched to provide a base contact and a dielectric cap. Exposed portions of the base layer may be etched selectively to the dielectric cap. A remaining portion of the base layer provides the base region. A hydrogenated silicon containing layer may be deposited with a low temperature deposition method. At least a portion of the hydrogenated silicon containing layer is formed on at least sidewalls of the base region. A second metal containing layer may be formed on the hydrogenated silicon containing layer. The second metal containing and the hydrogenated silicon containing layer may be etched to provide an emitter region and a collector region.
US09356113B2	Method of producing a junction field-effect transistor (JFET) The invention concerns a method for producing a field effect transistor having a trench gate comprising: —the forming (110) of at least one trench (11, 12, 13) in a semi-conductive substrate (1) having a first type of conductivity, said substrate comprising two opposing faces called front face and rear face, —the primary implantation (120) of ions having a second type of conductivity so as to implant each trench of the substrate to form an active gate area, —the depositing (160) of a layer of polycrystalline silicon having the second type of conductivity on the implanted active gate area, —the oxidation (160) of the layer of polycrystalline silicon, and —the metallization (180) of the substrate on the front and rear faces of same in order to form active source and drain areas.
US09356112B2	Charge trapping dielectric structures A dielectric structure may be arranged having a thin nitrided surface of an insulator with a charge blocking insulator over the nitrided surface. The insulator may be formed of a number of different insulating materials such as a metal oxide, a metal oxycarbide, a semiconductor oxide, or oxycarbide. In an embodiment, the dielectric structure may be formed by nitridation of a surface of an insulator using ammonia and deposition of a blocking insulator having a larger band gap than the insulator. The dielectric structure may form part of a memory device, as well as other devices and systems.
US09356104B2	Structure and formation method of semiconductor device with gate stack A structure and a formation method of a semiconductor device are provided. The semiconductor device includes a semiconductor substrate and a gate stack over the semiconductor substrate. The semiconductor device also includes a contact etch stop layer over the semiconductor substrate and sidewalls of the gate stack. The semiconductor device further includes a dielectric layer over the contact etch stop layer. In addition, the semiconductor device includes an interfacial layer between the contact etch stop layer and the dielectric layer.
US09356103B2	Reduction of edge effects from aspect ratio trapping A device includes a crystalline material within an area confined by an insulator. In one embodiment, the area confined by the insulator is an opening in the insulator having an aspect ratio sufficient to trap defects using an ART technique. Method and apparatus embodiments of the invention can reduce edge effects in semiconductor devices. Embodiments of the invention can provide a planar surface over a buffer layer between a plurality of uncoalesced ART structures.
US09356099B2	Techniques for forming contacts to quantum well transistors Techniques are disclosed for providing a low resistance self-aligned contacts to devices formed in a semiconductor heterostructure. The techniques can be used, for example, for forming contacts to the gate, source and drain regions of a quantum well transistor fabricated in III-V and SiGe/Ge material systems. Unlike conventional contact process flows which result in a relatively large space between the source/drain contacts to gate, the resulting source and drain contacts provided by the techniques described herein are self-aligned, in that each contact is aligned to the gate electrode and isolated therefrom via spacer material.
US09356096B2	Method providing an epitaxial growth having a reduction in defects and resulting structure Disclosed are methods and resulting structures which provide an opening for epitaxial growth, the opening having an associated projection for reducing the size of the contact area on a substrate at which growth begins. During growth, the epitaxial material grows vertically from the contact area and laterally over the projection. The projection provides a stress relaxation region for the lateral growth to reduce dislocation and stacking faults at the side edges of the grown epitaxial material.
US09356094B2	Method for making a semi-conducting substrate located on an insulation layer A method for making a silicon layer extending on an insulation layer, including the steps of forming a silicon-germanium layer on at least a portion of a silicon wafer; transforming portions of the silicon-germanium layer into porous silicon pads; growing a monocrystalline silicon layer on the silicon-germanium layer and on the porous silicon pads; removing the silicon-germanium layer; oxidizing the porous silicon pads; and depositing an insulation material on the silicon layer.
US09356090B2	PMOS transistor with improved mobility of the carriers A substrate includes an active region oriented along a crystallographic face (100) and limited by an insulating region. A MOS transistor includes a channel oriented longitudinally along a crystallographic direction of the <110> type. A basic pattern made of metal and formed in the shape of a T is electrically inactive and situated over an area of the insulating region adjacent a transverse end of the channel. A horizontal branch of the T-shaped basic pattern is oriented substantially parallel to the longitudinal direction of the channel.
US09356084B2	Display device and method of manufacturing the same According to one embodiment, a method of manufacturing a display device, includes preparing a first substrate formed such that a first resin layer is formed on a first support substrate, and thereafter a display element portion and a mounting portion are formed above the first resin layer and a protection layer, which extends from an end portion of the first resin layer along the mounting portion onto the first support substrate, is disposed, preparing a second substrate formed such that a second resin layer is formed on a second support substrate, attaching the first substrate and the second substrate, and mounting a flexible printed circuit board, which is in a state in which the flexible printed circuit board is opposed to the protection layer, on the mounting portion.
US09356083B2	Organic light-emitting display apparatus and method of manufacturing the same Provided is a method of manufacturing an organic light-emitting display apparatus which may reduce white angular dependency (WAD). The method includes forming a common layer on each of subpixel areas at the same time without discretion within one pixel area, the common layer not being formed on connection areas between pixel areas.
US09356078B2	High aperture ratio organic light emitting diode display having double bank structure The present disclosure relates to an organic light emitting diode display having high aperture ratio. The present disclosure suggests an organic light emitting diode display comprising: a substrate having a plurality of pixel area arrayed in a matrix manner; an anode electrode formed within the pixel area on the substrate; a first bank having an open area exposing most of the anode electrode and defining an emission area; a second bank exposing the open area exposed by the first bank and some upper surface of the first bank; an organic light emitting layer covering the some upper surface of the first bank by the second bank and the most of anode electrode exposed by the first bank; and a cathode electrode formed over the substrate having the organic light emitting layer.
US09356075B2	Organic EL display device An organic EL display device includes a thin film transistor substrate in which a light-emitting element is provided for each of plural sub-pixels constituting each pixel, a counter substrate provided with a coupled color filter which is a color filter arranged to be extended over plural adjacent sub-pixels and allowing light in one wavelength region to pass through and a light-shielding film which is arranged on a boundary between adjacent color filters to allow lights in different wavelength regions to pass through and shields light, a filler arranged between the thin film transistor substrate and the counter substrate and made of a transparent organic material, and a filler thickness adjustment part which adjusts to cause a thickness of the filler in a region where the light-shielding film is provided to be thinner than a thickness of the filler in a region where the light-emitting element is provided.
US09356073B1	Semiconductor device including air gaps and method of fabricating the same A semiconductor device including air gaps and a method of fabricating the same. The semiconductor device in accordance with an embodiment may include a bit line structure having a bit line formed over a first contact plug, a second contact plug formed adjacent to the first contact plug and the bit line structure, an air gap structure comprising two or more air gaps to surround the second contact plug and have an outer sidewall in contact with the bit line structure, and one or more capping support layers separating the air gaps, a third contact plug capping a part of the air gap structure and being formed over the second contact plug, and a capping layer for capping a remainder of the air gap structure.
US09356068B2	Image sensor and method for fabricating the same An image sensor may include a substrate having photoelectric conversion regions respectively formed on a plurality of pixels and charge trap regions overlapping with the respective photoelectric conversion regions and having depths or thicknesses that are different, for each of the respective pixel.
US09356066B2	Interconnect structure for stacked device and method A stacked integrated circuit (IC) device and a method are disclosed. The stacked IC device includes a first semiconductor element and a second semiconductor element bonded on the first semiconductor element. The first semiconductor element includes a first substrate, a common conductive feature in the first substrate, a first inter-level dielectric (ILD) layer, a first interconnection feature and a conductive plug connecting the first interconnection feature to the common conductive feature. The second semiconductor element includes a second substrate, a second ILD layers over the second substrate and a second interconnection feature in second ILD layers. The device also includes a conductive deep plug connecting to the common conductive feature in the first semiconductor element and the second interconnection feature. The conductive deep plug is separated with the conductive plug by the first ILD layer.
US09356064B2	Solid state imaging device and manufacturing method, and electronic apparatus A solid state imaging device includes a substrate, in which the substrate includes a photoelectric conversion unit that generates a charge according to a light amount of incident light by a pixel unit, an accumulation unit that divides the charge of the pixel unit which is generated in the photoelectric conversion unit and accumulates the charge, a first element isolation unit that is formed at a boundary of the photoelectric conversion unit of the pixel unit, and a second element isolation unit that is formed at a boundary of the accumulation unit of a divided unit of the pixel.
US09356057B2	Solid-state imaging apparatus and electronic device Disclosed herein is a solid-state imaging apparatus including: a semiconductor base; a photodiode created on the semiconductor base and used for carrying out photoelectric conversion; a pixel section provided with pixels each having the photodiode; a first wire created by being electrically connected to the semiconductor base for the pixel section through a contact section and being extended in a first direction to the outside of the pixel section; a second wire made from a wiring layer different from the first wire and created by being extended in a second direction different from the first direction to the outside of the pixel section; and a contact section for electrically connecting the first and second wires to each other.
US09356056B2	Solid-state imaging device, imaging apparatus, and method of driving the solid-state imaging device A solid-state imaging device including a semiconductor substrate; plural photoelectric conversion units formed side by side on the semiconductor substrate to form a light receiving unit; a peripheral circuit formed in a portion on an outside of the light receiving unit on the semiconductor substrate; a wiring section formed on the light receiving unit and formed for connecting the plural photoelectric conversion units and the peripheral circuit; and a dummy wiring section formed on an opposite side of the wiring section for at least one photoelectric conversion unit among the plural photoelectric conversion units on the light receiving unit and formed for functioning as a non-connected wiring section not connected to the photoelectric conversion units and the peripheral circuit, wherein the dummy wiring section has a predetermined potential.
US09356049B2	Display device with a transistor on an outer side of a bent portion A non-breakable display device, electronic appliance, or lighting device is provided. A bendable display device in which a first flexible substrate and a second flexible substrate provided with transistors overlap each other with a bonding layer therebetween is fabricated. The display device is bent so that the first substrate is positioned on the inner side (the valley side) and the second substrate is positioned on the outer side (the mountain side).
US09356048B2	Light emitting device It is an object of the present invention to prevent an insulating film from peeling in a section where the insulating film is adjacent to a sealing region. Over a first substrate 104, a pixel portion 100 provided with a light emitting element, a source driver 101, a gate driver 102, and a sealing region 103 are provided. A light emitting element is sealed between the first substrate 104 and a second substrate 110 by a sealant 108. An insulating film 107 serves as a partition wall of the light emitting element. An end portion of the insulating film 107 which is adjacent to the sealing region 103 does not overlap with a step formed by a side surface and an upper surface of a conductive film 106 which serves as a wiring.
US09356046B2	Structure and method for forming CMOS with NFET and PFET having different channel materials Embodiments of the present invention provide an improved structure and method for forming CMOS field effect transistors. In embodiments, silicon germanium (SiGe) is formed on a PFET side of a semiconductor structure, while silicon is disposed on an NFET side of a semiconductor structure. A narrow isolation region is formed between the PFET and NFET. The NFET fins are comprised of silicon and the PFET fins are comprised of silicon germanium.
US09356044B2	Vertical type memory device A semiconductor device, comprising: a plurality of memory cell strings; a bitline; and an interconnection coupling at least two of the memory cell strings to the bitline. Memory cell strings can be coupled to corresponding bitlines through corresponding interconnections. Alternate memory cell strings can be coupled to different bitlines through corresponding different interconnections.
US09356040B2	Junction formation for vertical gate 3D NAND memory A method is provided for manufacturing a memory device. A plurality of layers of a first semiconductor material is formed, and a plurality of holes is formed through the layers. An etch process is applied to the layers through the holes, to form pull-back regions in the layers adjacent and surrounding the holes. A film of second semiconductor material is deposited over the holes and into the pull-back regions. Portions of the film are removed from the holes while leaving elements of the second semiconductor material in the pull-back regions in contact with the first semiconductor material. The holes are filled with insulating material. Layers in the plurality of layers have respective first doping concentration profiles, and the elements of the second semiconductor material in the pull-back regions have second doping concentration profiles. The second doping concentration profiles establish a higher conductivity in the elements of second semiconductor material.
US09356038B2	Semiconductor device and method of fabricating the same A semiconductor device and a method of fabricating the same are provided. The semiconductor device includes insulating layers stacked in the shape of stairs, and conductive layers alternately stacked with the insulating layers, wherein the conductive layers each include a first region interposed between upper and lower insulating layers thereof, among the insulating layers, and a second region which extends from the first region and protrudes between the upper and lower insulating layers, and wherein a protruding part formed on a sidewall or an upper surface of the second region.
US09356037B2	Memory architecture of 3D array with interleaved control structures A 3D memory device includes a first plurality and a second plurality of stacks of semiconductor material strips on a substrate. The second plurality of stacks of gate material strips on the substrate is interleaved with, and coplanar with, the first plurality of stacks. The second plurality of stacks is configured as gates for the first plurality of stacks. A first plurality of word lines is arranged orthogonally over, and having surfaces conformal with, the first plurality of stacks, such that a 3D array of memory elements is established at cross-points between surfaces of the first plurality of stacks and the plurality of word lines.
US09356030B2	Method for manufacturing semiconductor device having antifuse with semiconductor and insulating films as intermediate layer An object is to provide an antifuse with little power consumption at the time of writing. The antifuse is used for a memory element in a read-only memory device. The antifuse includes a first conductive layer, a multilayer film of two or more layers in which an amorphous silicon film and an insulating film are alternately stacked over the first conductive layer, and a second conductive layer over the multilayer film. Voltage is applied between the first and second conductive layers and resistance of the multilayer film is decreased, whereby data is written to the memory element. When an insulating film having higher resistance than amorphous silicon is formed between the first and second conductive layers, current flowing through the antifuse at the time of writing is reduced.
US09356023B2	Planar device on fin-based transistor architecture Techniques are disclosed for forming a planar-like transistor device on a fin-based field-effect transistor (finFET) architecture during a finFET fabrication process flow. In some embodiments, the planar-like transistor can include, for example, a semiconductor layer which is grown to locally merge/bridge a plurality of adjacent fins of the finFET architecture and subsequently planarized to provide a high-quality planar surface on which the planar-like transistor can be formed. In some instances, the semiconductor merging layer can be a bridged-epi growth, for example, comprising epitaxial silicon. In some embodiments, such a planar-like device may assist, for example, with analog, high-voltage, wide-Z transistor fabrication. Also, provision of such a planar-like device during a finFET flow may allow for the formation of transistor devices, for example, exhibiting lower capacitance, wider Z, and/or fewer high electric field locations for improved high-voltage reliability, which may make such devices favorable for analog design, in some instances.
US09356019B2	Integrated circuit with on chip planar diode and CMOS devices An electrical circuit, planar diode, and method of forming a diode and one or more CMOS devices on the same chip. The method includes electrically isolating a portion of a substrate in a diode region from other substrate regions. The method also includes recessing the substrate in the diode region. The method further includes epitaxially forming in the diode region a first doped layer above the substrate and epitaxially forming in the diode region a second doped layer above the first doped layer.
US09356018B2	Semiconductor devices and methods of fabricating the same Provided is a semiconductor device including a substrate, first and second gate structures provided on the substrate, a source/drain region provided adjacent to the first gate structure, an interlayered insulating layer provided on the substrate to cover the source/drain region and the first and second gate structures, a source/drain contact hole penetrating the interlayered insulating layer and exposing the source/drain region, a trench formed in the interlayered insulating layer to expose a top surface of the second gate structure, a source/drain contact plug provided in the source/drain contact hole to be in contact with the source/drain region, and a resistor pattern provided in the trench to be in contact with a top surface of the second gate structure.
US09356014B2	High-voltage metal-insulator-semiconductor field effect transistor structures Semiconductor structures and methods of manufacture are disclosed herein. Specifically, disclosed herein are methods of manufacturing a high-voltage metal-oxide-semiconductor field-effect transistor and respective structures. A method includes forming a field-effect transistor (FET) on a substrate in a FET region, forming a high-voltage FET (HVFET) on a dielectric stack over a over lightly-doped diffusion (LDD) drain in a HVFET region, and forming an NPN on the substrate in an NPN region.
US09356011B2	Junction-isolated blocking voltage structures with integrated protection structures Junction-isolated blocking voltage devices and methods of forming the same are provided. In certain implementations, a blocking voltage device includes an anode terminal electrically connected to a first p-well, a cathode terminal electrically connected to a first n-well, a ground terminal electrically connected to a second p-well, and an n-type isolation layer for isolating the first p-well from a p-type substrate. The first p-well and the first n-well operate as a blocking diode. The blocking voltage device further includes a PNPN silicon controlled rectifier (SCR) associated with a P+ region formed in the first n-well, the first n-well, the first p-well, and an N+ region formed in the first p-well. Additionally, the blocking voltage device further includes an NPNPN bidirectional SCR associated with an N+ region formed in the first p-well, the first p-well, the n-type isolation layer, the second p-well, and an N+ region formed in the second p-well.
US09356007B2	Light emitting device and lighting apparatus including the same A light emitting device is disclosed. The disclosed light emitting device includes a light emitting structure including a first-conductivity-type semiconductor layer, an active layer, and a second-conductivity-type semiconductor layer, a second electrode layer disposed beneath the light emitting structure and electrically connected to the second-conductivity-type semiconductor layer, a first electrode layer including a main electrode disposed beneath the second electrode layer, and at least one contact electrode branching from the main electrode and extending through the second electrode layer, the second-conductivity-type semiconductor layer and the active layer, to contact the first-conductivity-type semiconductor layer, and an insulating layer interposed between the first electrode layer and the second electrode layer and between the first electrode layer and the light emitting structure. The first-conductivity-type semiconductor layer includes a first region and a second region having a smaller height than the first region, and the first region overlaps with the contact electrode.
US09356005B2	Package of light emitting diode with heat sink Disclosed herein is a light emitting diode (LED) package. The present invention is directed to a light emitting diode (LED) package capable of efficiently dissipating heat generated from LEDs. The present invention is also directed to a LED package in which a plurality of LEDs are disposed and heat generated from the plurality of LEDs is efficiently dissipated.
US09355993B2	Integrated circuit system with debonding adhesive and method of manufacture thereof A system and method of manufacture of an integrated circuit system includes: a die having a via, the die having a top side and a bottom side; a top interconnect mounted to the via at the top side; an interconnect pillar mounted to the via at the bottom side; a device interconnect mounted to the interconnect pillar; and a base adhesive covering the interconnect pillar and the device interconnect.
US09355990B2	Manufacturing method of device embedded substrate and device embedded substrate manufactured by this method The present invention provides a manufacturing method of a device embedded substrate, including: forming a bonding layer of an insulation material on a metal layer formed on a support plate; and mounting an electric or electronic device on the bonding layer, wherein the device is formed of a device main body and a protruding terminal; the bonding layer includes a first bonding body bonded with the metal layer and a second bonding body bonded with the device; the first bonding body is formed along the outer edge of the device; the second bonding body is formed in an area equal or smaller than the area defined by the outer edge of the terminal; and, in the bonding layer forming step, the second bonding body is formed on the first bonding body after the first bonding body is cured.
US09355989B2	Wire bonding device and method of eliminating defective bonding wire A method of eliminating a defective bonding wire is provided, including moving a bonding member from a first region of a carrier to a second region of the carrier if the bonding wire of the bonding member is defective, and cooperatively operating a movement member and the bonding member so as to cause the defective bonding wire to be removed from the bonding member and bonded to the second region of the carrier, thereby auto-debugging the bonding member and improving the production efficiency.
US09355986B2	Solder joint structure, power module, power module substrate with heat sink and method of manufacturing the same, and paste for forming solder base layer There are provided a solder joint structure, a power module using the joint structure, a power module substrate with a heat sink and a method of manufacturing the same, as well as a solder base layer forming paste which is disposed and fired on a metal member to thereby react with an oxide film generated on the surface of the metal member and form the solder base layer on the metal member, capable of suppressing the occurrence of waviness and wrinkles on the surface of the metal member even at the time of loading the power cycle and heat cycle and improving the joint reliability with a joint member.
US09355984B2	Electronic device and method for fabricating an electronic device An embodiment method for fabricating electronic devices having two components connected by a metal layer includes applying a metal layer to each component and connecting the metal layers such that a single metal layer is formed.
US09355977B2	Bump structures for semiconductor package A package structure includes a first substrate bonded to a second substrate by connecting metal pillars on the first substrate to connectors on the second substrate. A first metal pillar is formed overlying and electrically connected to a metal pad on a first region of the first substrate, and a second metal pillar is formed overlying a passivation layer in a second region of the first substrate. A first solder joint region is formed between metal pillar and the first connector, and a second solder joint region is formed between the second metal pillar and the second connector. The thickness of the first metal pillar is greater than the thickness of the second metal pillar.
US09355976B2	Semiconductor memory chips and stack-type semiconductor packages including the same Provided are semiconductor memory chips and semiconductor packages with the same. The semiconductor package may include a memory chip including first data pads and first command/address pads arranged adjacent to a first side region thereof and second data pads and second command/address pads arranged adjacent to a second side region thereof arranged opposite to the first side region, and a package substrate including first CA connection pads and second CA connection pads. The memory chip may be mounted on a top surface of the package substrate, the first CA connection pads may be connected to the first command/address pads, and the second CA connection pads may be provide to be opposite to the first CA connection pads and be connected to the second command/address pads.
US09355974B2	Semiconductor device and manufacturing method therefor A semiconductor device includes a plurality of protrusions formed on a first face of the semiconductor device; first bonding portions formed on upper portions of the plurality of protrusions; second bonding portions formed on side faces of the plurality of protrusions; and third bonding portions formed on the first face between the plurality of protrusions, wherein the semiconductor device is configured to bond to an other semiconductor device through the third from the first bonding portions.
US09355969B2	Semiconductor package A semiconductor package includes a package substrate including a ground pad; a a conductive spacer and a first semiconductor chip disposed on the package substrate; a second semiconductor chip on the conductive spacer and the first semiconductor chip; a molding unit that covers the package substrate, the first semiconductor chip, the second semiconductor chip, and a first portion of the conductive spacer, and exposes a second portion of the conductive spacer; and an electromagnetic interference (EMI) shield that covers the molding unit.
US09355966B2	Substrate warpage control using external frame stiffener A chip package and methods of manufacturing the same are disclosed. In particular, a chip package comprising a ball grid array is disclosed in which the chip package includes a package substrate supporting the ball grid array and in which the chip package further includes a warpage control frame that helps to minimize or mitigate warpage of the chip package.
US09355958B2	Semiconductor device having a corrosion-resistant metallization and method for manufacturing thereof A semiconductor device includes a semiconductor substrate having a first side, a second side opposite the first side, an active area, an outer rim, and an edge termination area arranged between the outer rim and the active area. A metallization structure is arranged on the first side of the semiconductor substrate and comprising at least a first metal layer comprised of a first metallic material and a second metal layer comprised of a second metallic material, wherein the first metallic material is electrochemically more stable than the second metallic material. The first metal layer extends laterally further towards the outer rim than the second metal layer.
US09355956B2	Inductor for semiconductor integrated circuit An inductor includes a plurality of first conductive lines, a plurality of second conductive lines and a plurality of contacts. Each of the first conductive lines is spaced apart from one another. Each of the second conductive lines is spaced apart from one another, and each of the second conductive lines crosses over each of the first conductive lines. Each of the contacts electrically interconnects one of the first conductive lines and one of the second conductive lines. These contacts are arranged in a way such that at least parts of the first conductive lines and at least parts of the second conductive lines form an electric current path serving as an inductor.
US09355953B2	Vertical semiconductor MOSFET device with double substrate-side multiple electrode connections and encapsulation A semiconductor device with substrate-side exposed device-side electrode (SEDE) is disclosed. The semiconductor device has semiconductor substrate (SCS) with device-side, substrate-side and semiconductor device region (SDR) at device-side. Device-side electrodes (DSE) are formed for device operation. A through substrate trench (TST) is extended through SCS, reaching a DSE turning it into an SEDE. The SEDE can be interconnected via conductive interconnector through TST. A substrate-side electrode (SSE) and a windowed substrate-side passivation (SSPV) atop SSE can be included. The SSPV defines an area of SSE for spreading solder material during device packaging. A device-side passivation (DSPV) beneath thus covering the device-side of SEDE can be included. A DSE can also include an extended support ledge, stacked below an SEDE, for structurally supporting it during post-wafer processing packaging. The projected footprint of extended support ledge onto the major SCS plane can essentially enclose the correspondingly projected footprint of SEDE.
US09355946B2	Converter having partially thinned leadframe with stacked chips and interposer, free of wires and clips Power supply system comprises vertically sequentially a QFN leadframe, a first chip with FET terminals on opposite sides, a flat interposer, and a second chip with FET terminals and the terminals of the integrated driver-and-control circuit on a single side. Leadframe pad has a portion recessed as pocket with a depth and an outline suitable for attaching the first chip with one terminal in the pocket and the opposite terminal co-planar with the un-recessed pad surface. The interposer comprises metal patterned in traces separated by gaps; the traces include metal of a first height and metal of a second height smaller than the first height, and insulating material filling the gaps and the height differences; one interposer side attached to the leadframe pad with the first chip, the opposite interposer side attached to the terminals of the second chip.
US09355942B2	Gang clips having distributed-function tie bars Gang clips (500) having a flat area (510), a ridge (510a), and tie bars (530b) extending from the flat area, the end portions of the ties bars aligned in a common x-direction; a plurality of gang clips having respective end portions of tie bars merged in x-direction to form an elongated chain (701) of clips; and a plurality of chains arrayed parallel to each other, free of tie bars between adjacent chains, the plurality having the chain ends tied at both ends (730a) to rails (740) normal to the chains to form a matrix (700) of clips having the rails as a stable frame.
US09355941B2	Semiconductor device with step portion having shear surfaces A semiconductor device includes a source electrode pad formed to a front surface of a semiconductor chip and a metal clip (metal plate) to which a lead is electrically connected. The metal clip includes a chip-connecting portion electrically connected to the source electrode pad via a conductive bonding material, a lead-connecting portion electrically connected to the lead via a conductive bonding material, and an intermediate portion positioned between the chip-connecting portion and the lead-connecting portion. Further, between the intermediate portion and the chip-connecting portion, a step portion, which has shear surfaces disposed to face each other, is provided interposing a joining portion.
US09355938B2	Conductive compositions and methods of using them A conductive composition includes a mono-acid hybrid that includes an unprotected, single reactive group. The mono-acid hybrid may include substantially non-reactive groups elsewhere such that the mono-acid hybrid is functional as a chain terminator. Methods and devices using the compositions are also disclosed.
US09355936B2	Flattened substrate surface for substrate bonding Methods for bonding substrate surfaces, bonded substrate assemblies, and design structures for a bonded substrate assembly. Device structures of a product chip are formed using a first surface of a device substrate. A wiring layer of an interconnect structure for the device structures is formed on the product chip. The wiring layer is planarized. A temporary handle wafer is removably bonded to the planarized wiring layer. In response to removably bonding the temporary handle wafer to the planarized first wiring layer, a second surface of the device substrate, which is opposite to the first surface, is bonded to a final handle substrate. The temporary handle wafer is then removed from the assembly.
US09355935B2	Connecting through vias to devices Methods and devices for connecting a through via and a terminal of a transistor formed of a strained silicon material are provided. The terminal, which can be a source or a drain of a NMOS or a PMOS transistor, is formed within a substrate. A first contact within a first inter-layer dielectric (ILD) layer over the substrate is formed over and connected to the terminal. A through via extends through the first ILD layer into the substrate. A second contact is formed over and connected to the first contact and the through via within a second ILD layer and a contact etch stop layer (CESL). The second ILD layer is over the CESL, and the CESL is over the first ILD layer, which are all below a first inter-metal dielectric (IMD) layer and the first metal layer of the transistor.
US09355933B2	Cooling channels in 3DIC stacks An integrated circuit structure includes a die including a semiconductor substrate; dielectric layers over the semiconductor substrate; an interconnect structure including metal lines and vias in the dielectric layers; a plurality of channels extending from inside the semiconductor substrate to inside the dielectric layers; and a dielectric film over the interconnect structure and sealing portions of the plurality of channels. The plurality of channels is configured to allow a fluid to flow through.
US09355923B2	Semiconductor device with an overlay mark including segment regions surrounded by a pool region Disclosed herein is a semiconductor device that includes a plurality of segment regions arranged with a first distance, each of segment regions including a plurality of first grooves arranged with a second distance that is smaller than the first distance, and a second groove enclosing the plurality of the segment regions with a third distance that is larger than the second distance. The third distance may be substantially equal to the first direction.
US09355920B2	Methods of forming semiconductor devices and FinFET devices, and FinFET devices Methods of forming semiconductor devices and fin field effect transistors (FinFETs), and FinFET devices, are disclosed. In some embodiments, a method of forming a semiconductor device includes forming a barrier material comprising AlInAsSb over a substrate, and forming a channel material of a transistor over the barrier layer.
US09355918B2	Method for producing high-purity polycrystalline silicon The present invention provides technology for realizing higher purification of a polycrystalline silicon. First, trichlorosilane is prepared as a sample (S101) and then the carbon-containing impurities content in the trichlorosilane is analyzed by GC/MS-SIM method (S102). The quality of the trichlorosilane is determined based on the analysis results (S103) and the trichlorosilane determined to be a good material (S103: Yes) is used as the raw material for producing a high-purity polycrystalline silicon by CVD method (104). In case, the trichlorosilane determined to be a bad material (S103: No) is not used as the raw material for producing a polycrystalline silicon. When the impurities analysis by GC/MS-SIM method is performed using, as a separation column, a column having a non-polar column and a medium-polar column connected in series with each other, it is possible to simultaneously perform both of the separation of chlorosilanes and hydrocarbons and the separation of chlorosilanes and methylsilanes.
US09355916B2	Semiconductor manufacturing method and semiconductor device A method manufactures a semiconductor device which allows nanocarbon materials, such as high-quality graphene and carbon nanotube to be used. The method of manufacturing the semiconductor device comprises forming on a substrate a wiring structure including wires of nanocarbon material; forming on the wiring structure an element structure including a semiconductor element; and interconnecting the wires of the wiring structure and the semiconductor element of the element structure.
US09355912B2	Jog design in integrated circuits A device includes an active region in a semiconductor substrate, a gate strip over and crossing the active region, and a jog over the active region and connected to the gate strip to form a continuous region. The jog is on a side of the gate strip. A first contact plug is at a same level as the gate strip, wherein the first contact plug is on the side of the gate strip. A second contact plug is over the jog and the first contact plug. The second contact plug electrically interconnects the first contact plug and the jog.
US09355908B2	Semiconductor pillar transistors having channels with different crystal orientations According to an embodiment, a semiconductor device includes an underlying layer and a plurality of transistors. The underlying layer includes a first region and a second region provided adjacently to the first region. The transistors are arranged in a plane parallel to an upper surface of the underlying layer. Each transistor includes a channel allowing a current to flow in a first direction intersecting the plane. The plurality of transistors includes a first transistor provided on the first region and a second transistor provided on the second region, a first channel of the first transistor having a first crystal orientation, and a second channel of the second transistor having a second crystal orientation different from the first crystal orientation.
US09355907B1	Hybrid wafer dicing approach using a line shaped laser beam profile laser scribing process and plasma etch process Methods of dicing semiconductor wafers, each wafer having a plurality of integrated circuits, are described. In an example, a method of dicing a semiconductor wafer having a plurality of integrated circuits involves forming a mask above the semiconductor wafer, the mask composed of a layer covering and protecting the integrated circuits. The mask is then patterned with a line shaped laser beam profile laser scribing process to provide a patterned mask with gaps, exposing regions of the semiconductor wafer between the integrated circuits. The semiconductor wafer is then plasma etched through the gaps in the patterned mask to singulate the integrated circuits.
US09355906B2	Packaging devices and methods of manufacture thereof Packaging devices and methods of manufacture thereof for semiconductor devices are disclosed. In some embodiments, a method of manufacturing a packaging device includes forming an interconnect wiring over a substrate, and forming conductive balls over portions of the interconnect wiring. A molding material is deposited over the conductive balls and the substrate, and a portion of the molding material is removed from over scribe line regions of the substrate.
US09355904B2	Method for strain-relieved through substrate vias A semiconductor die including strain relief for through substrate vias (TSVs). A method for strain relief of TSVs includes defining a through substrate via cavity in a substrate. The method also includes depositing an isolation layer in the cavity. The method further includes filling the cavity with a conductive material. The method also includes removing a portion of the isolation layer to create a recessed portion.
US09355902B2	Method of fabricating semiconductor apparatus with through-silicon via and method of fabricating stack package including the semiconductor chip In a semiconductor apparatus, a plurality of semiconductor chips including through-silicon vias are stacked in a vertical direction, wherein the through-silicon via formed in each semiconductor chip protrudes beyond heights of each semiconductor chip.
US09355901B2	Non-lithographic formation of three-dimensional conductive elements A method of forming a conductive element on a substrate and the resulting assembly are provided. The method includes forming a groove in a sacrificial layer overlying a dielectric region disposed on a substrate. The groove preferably extends along a sloped surface of the substrate. The sacrificial layer is preferably removed by a non-photolithographic method, such as ablating with a laser, mechanical milling, or sandblasting. A conductive element is formed in the groove. The grooves may be formed. The grooves and conductive elements may be formed along any surface of the substrate, including within trenches and vias formed therein, and may connect to conductive pads on the front and/or rear surface of the substrate. The conductive elements are preferably formed by plating and may or may not conform to the surface of the substrate.
US09355900B2	Semiconductor device and method of manufacturing the same A semiconductor device of an embodiment includes: a substrate on which a semiconductor circuit is formed; an interlayer insulating film in which a contact hole is formed on the substrate; a catalyst metal film on a side wall of the contact hole; catalyst metal particles on a bottom of the contact hole; graphene on the catalyst metal film; and carbon nanotubes, which penetrates the contact hole, on the catalyst metal particles.
US09355898B2	Package on package (PoP) integrated device comprising a plurality of solder resist layers Some features pertain to an integrated device that includes a first substrate, a first solder resist layer coupled to the first substrate, a second solder resist layer coupled to the first solder resist layer, and an opening in the first and second solder resist layers, the opening comprising a sidewall completely covered with the second solder resist layer, where a sidewall of the second solder resist layer covers a sidewall of the first solder resist layer. In some implementations, the opening is at least partially filled with an electrically conductive material. The electrically conductive material includes one of solder and/or an interconnect. The integrated device includes a first interconnect coupled to the electrically conductive material. The first interconnect is one of at least a solder, and/or an interconnect ball. In some implementations, the integrated device includes a pad coupled to the substrate, and a first interconnect coupled to the pad.
US09355897B2	Methods of forming semiconductor structures Methods of forming semiconductor structures that include bodies of a semiconductor material disposed between rails of a dielectric material are disclosed. Such methods may include filling a plurality of trenches in a substrate with a dielectric material and removing portions of the substrate between the dielectric material to form a plurality of openings. In some embodiments, portions of the substrate may be undercut to form a continuous void underlying the bodies and the continuous void may be filled with a conductive material. In other embodiments, portions of the substrate exposed within the openings may be converted to a silicide material to form a conductive material under the bodies. For example, the conductive material may be used as a conductive line to electrically interconnect memory device components. Semiconductor structures and devices formed by such methods are also disclosed.
US09355890B2	Method of manufacturing semiconductor device and semiconductor device Disclosed is a miniaturized semiconductor device having an SOI layer, in which: a silicon layer is formed over a semiconductor substrate via an BOX film; after the silicon layer is patterned by using a nitride film as a mask, an insulating film covering the surface of each of the nitride film, the silicon layer, and the BOX film is formed; subsequently, an opening, which penetrates the insulating film and the BOX film and which exposes the upper surface of the semiconductor substrate, is formed, and an epitaxial layer is formed in the opening; subsequently, the SOI region and a bulk silicon layer are formed over the semiconductor substrate by flattening the upper surface of the epitaxial layer with the use of the nitride film as an etching stopper film.
US09355889B2	Semiconductor-on-insulator device and method of fabricating the same The disclosed technology generally relates to semiconductor-on-insulator (SOI) devices and more particularly to SOI devices having a channel region comprising a Group III-V or a Group IV semiconductor material, and also relates to methods of fabricating the same. In one aspect, a method comprises providing a pre-patterned donor wafer, providing a handling wafer and bonding the pre-patterned donor wafer to the handling wafer by contacting the first oxide layer to the handling wafer. Providing a pre-patterned donor wafer comprises providing a donor substrate comprising a first semiconductor material, forming shallow trench isolation (STI) regions in the donor substrate, and forming fins in the donor substrate in between the STI regions, where each fin comprises a Group III-V or Group IV semiconductor material that is different from the first semiconducting material and laterally extends in a direction parallel to a major surface of the donor substrate and between the STI regions. Providing the pre-patterned donor wafer additionally includes providing a first oxide layer overlying the STI regions and the fins. After bonding the donor wafer to the handling wafer, at least part of the first semiconducting material of the pre-patterned donor wafer is removed and the STI regions and the fins are thinned thereby forming channel regions comprising the Group III-V or Group IV semiconductor material.
US09355882B2	Transfer module for bowed wafers A wafer grinding system includes a robot arm having a suction board at one end and a table within reach of the robot arm. An upper surface of the table has a vacuum surface for sucking and holding wafers. A pusher coupled to the robot arm extends about the periphery of the suction board. The pusher flattens wafers against the upper surface of the table, allowing the table to hold by suction wafers that would otherwise be too bowed to be held in that way. Additionally, a table can have a vacuum area that is small in comparison to the wafers, which is another way of increasing the magnitude of wafer bow that can be tolerated. A grinding system can use the reduced vacuum area concept to allow the positioning table to hold bowed wafers and the pusher concept to allow the chuck tables to hold bowed wafers.
US09355881B2	Semiconductor device including a dielectric material A method for manufacturing a semiconductor device includes providing a carrier and a semiconductor wafer having a first side and a second side opposite to the first side. The method includes applying a dielectric material to the carrier or the semiconductor wafer and bonding the semiconductor wafer to the carrier via the dielectric material. The method includes processing the semiconductor wafer and removing the carrier from the semiconductor wafer such that the dielectric material remains on the semiconductor wafer to provide a semiconductor device comprising the dielectric material.
US09355876B2	Process load lock apparatus, lift assemblies, electronic device processing systems, and methods of processing substrates in load lock locations A process load lock apparatus is disclosed. The process load lock apparatus includes a load lock chamber adapted to couple between a mainframe section and a factory interface, the load lock chamber including an entry and an exit each having a slit valve, and a load lock process chamber located at a different level than the load lock chamber at the load lock location wherein the load lock process chamber is adapted to carry out a process on a substrate, such as oxide removal or other processes. Systems including the process load lock apparatus and methods of operating the process load lock apparatus are provided. A lift assembly including a containment ring is also disclosed, as are numerous other aspects.
US09355864B2	Method for increasing adhesion of copper to polymeric surfaces Techniques disclosed herein a method and system for conditioning a polymeric layer on a substrate to enable adhesion of a metal layer to the polymeric layer. Techniques may include conditioning the polymeric layer with nitrogen-containing plasma to generate a nitride layer on the surface of the polymeric layer. In another embodiment, the conditioning may include depositing a CuN layer using a lower power copper sputtering process in a nitrogen rich environment. Following the condition process, a higher power copper deposition or sputtering process may be used to deposit copper onto the polymeric layer with good adhesion properties.
US09355860B2	Method for achieving uniform etch depth using ion implantation and a timed etch A method of performing a timed etch of a material to a precise depth is provided. In this method, ion implantation of the material is performed before the timed etch. This ion implantation process substantially enhances the etch rate of the material within a precisely controlled depth range corresponding to the range of implantation-induced damage. By using the ion implantation, the variation in vertical etch depth can be reduced by a factor approximately equal to the etch rate of the damaged material divided by the etch rate of the undamaged material. The vertical etch depth can be used to provide a vertical dimension of a non-planar semiconductor device. Minimizing vertical device dimension variations on a wafer can reduce device and circuit performance variations, which is highly desirable.
US09355853B2	Systems and methods for bidirectional device fabrication Methods and systems for double-sided semiconductor device fabrication. Devices having multiple leads on each surface can be fabricated using a high-temperature-resistant handle wafer and a medium-temperature-resistant handle wafer. Dopants can be introduced on both sides shortly before a single long high-temperature diffusion step diffuses all dopants to approximately equal depths on both sides. All high-temperature processing occurs with no handle wafer or with a high-temperature handle wafer attached. Once a medium-temperature handle wafer is attached, no high-temperature processing steps occur. High temperatures can be considered to be those which can result in damage to the device in the presence of aluminum-based metallizations.
US09355852B2	Method for manufacturing semiconductor device A method for manufacturing a semiconductor device includes: preparing a Si substrate having a flat portion with flat front and back surfaces and a bevel portion located at a periphery of the flat portion; forming a III-V nitride semiconductor film on the front surface of the Si substrate by epitaxial growth; and after forming the III-V nitride semiconductor film, grinding the Si substrate from the back surface. Amounts of working at the bevel portion on the front surface and the back surface of an outermost end portion of the bevel portion are asymmetrical. A first thickness measured from the front surface of the flat portion to the outermost end portion is smaller than a second thickness measured from the back surface of the flat portion to the outermost end portion.
US09355849B1	Oxide-nitride-oxide stack having multiple oxynitride layers A semiconductor device including an oxide-nitride-oxide (ONO) structure having a multi-layer charge storing layer and methods of forming the same are provided. Generally, the method involves: (i) forming a first oxide layer of the ONO structure; (ii) forming a multi-layer charge storing layer comprising nitride on a surface of the first oxide layer; and (iii) forming a second oxide layer of the ONO structure on a surface of the multi-layer charge storing layer. Preferably, the charge storing layer comprises at least two silicon oxynitride layers having differing stochiometric compositions of Oxygen, Nitrogen and/or Silicon. More preferably, the ONO structure is part of a silicon-oxide-nitride-oxide-silicon (SONOS) structure and the semiconductor device is a SONOS memory transistor. Other embodiments are also disclosed.
US09355848B2	Semiconductor structure and method for forming the same A semiconductor structure and a method for forming the same are provided. The method includes following steps. A gate electrode layer is formed on a substrate. A spacer structure is formed on a sidewall of the gate electrode layer. A dielectric cap film is formed to cover the gate electrode layer and the spacer structure. A source/drain implantation is performed to the substrate with the dielectric cap film exposed to a condition of the source/drain implantation.
US09355846B2	Non-uniform silicon dioxide and air gap for separating memory cells According to one embodiment, a method for forming a semiconductor device includes: forming a first underlayer film that contains a first chemical element selected from the group consisting of germanium, aluminum, tungsten, hafnium, titanium, tantalum, nickel, cobalt and alkaline earth metals; forming, on the first underlayer film, a second underlayer film that contains a second chemical element selected from the group consisting of germanium, aluminum, tungsten, hafnium, titanium, tantalum, nickel, cobalt and alkaline earth metals, the second chemical element being an chemical element not contained in the first underlayer film; and forming, on the second underlayer film, a silicon oxide film by a CVD or ALD method by use of a silicon source containing at least one of an ethoxy group, a halogen group, an alkyl group, and an amino group, or a silicon source of a siloxane system.
US09355844B2	Method for manufacturing semiconductor device Electrical characteristics of transistors using an oxide semiconductor are greatly varied in a substrate, between substrates, and between lots, and the electrical characteristics are changed due to heat, bias, light, or the like in some cases. In view of the above, a semiconductor device using an oxide semiconductor with high reliability and small variation in electrical characteristics is manufactured. In a method for manufacturing a semiconductor device, hydrogen in a film and at an interface between films is removed in a transistor using an oxide semiconductor. In order to remove hydrogen at the interface between the films, the substrate is transferred under a vacuum between film formations. Further, as for a substrate having a surface exposed to the air, hydrogen on the surface of the substrate may be removed by heat treatment or plasma treatment.
US09355842B2	Direct and sequential formation of monolayers of boron nitride and graphene on substrates The invention generally related to a method for preparing a layer of graphene directly on the surface of a substrate, such as a semiconductor substrate. The layer of graphene may be formed in direct contact with the surface of the substrate, or an intervening layer of a material may be formed between the substrate surface and the graphene layer.
US09355840B2	High quality devices growth on pixelated patterned templates A method of producing a template material for growing semiconductor materials and/or devices, comprises the steps of: (a) providing a substrate with a dielectric layer on the substrate; and (b) forming a pixelated pattern on the dielectric layer, the pattern comprising a plurality of discrete groups of structures.
US09355838B2	Oxide TFT and manufacturing method thereof Embodiments of the invention provide an oxide TFT and a manufacturing method thereof. The oxide thin film transistor comprises: a substrate; a gate electrode formed on the substrate; a gate insulation layer covering the gate electrode; an oxide active layer formed on the gate insulation layer and comprising a source region, a drain region, and a channel between the source region and the drain region; an etching barrier layer entirely covering the active layer and the gate insulation layer; and a source electrode and a drain electrode formed on the etching barrier layer and respectively provided on both sides of the channel. The etching barrier layer is a metal layer. The oxide thin film transistor further comprises a channel protective layer, which is a non-conductive oxidation layer converted from the metal layer by performing an oxidation treatment on the metal layer.
US09355837B2	Methods of forming and using materials containing silicon and nitrogen Some embodiments include methods utilizing atomic layer deposition to form material containing silicon and nitrogen (e.g., silicon nitride). The atomic layer deposition uses SiI4 as one precursor and uses a nitrogen-containing material as another precursor. Some embodiments include methods of forming a structure in which a chalcogenide region is formed over a semiconductor substrate; and in which SiI4 is used as a precursor during formation of silicon nitride material directly against a surface of the chalcogenide region.
US09355834B2	Adhesive transfer An adhesive transfer method includes depositing an adhesive on a first substrate, transferring a layer of the adhesive from the first substrate to an intermediate substrate, and transferring adhesive from the layer of the adhesive to at least one area of a second substrate.
US09355832B2	Reflectrons and methods of producing and using them Certain embodiments described herein are directed to reflectron assemblies and methods of producing them. In some configurations, a reflectron comprising a plurality of lenses each comprising a planar body and comprising a plurality of separate and individual conductors spanning a central aperture from a first side to a second side of a first surface of the planar body is described. In some instances, the plurality of conductors are each substantially parallel to each other and are positioned in the same plane.
US09355831B2	Ion guide or filters with selected gas conductance Certain embodiments described herein are directed to rod assemblies such as, for example, quadrupole, hexapole and octupole rod assemblies. In some instances, the rod assemblies include at least one pole comprising an integral fluid path configured to fluidically couple an ion volume formed by the assembly to an outer volume of the assembly to remove fluid within the ion volume to the outer volume while containing ions of a selected mass-to-charge range.
US09355828B1	Recording spatial and temporal properties of ions emitted from a quadrupole mass filter An ion detection system for a detecting a quantity of ions exiting from a mass analyzer of a mass spectrometer comprises: (a) photon generating means configured to receive the quantity of ions and to generate a quantity of photons that is proportional to the quantity of ions; (b) a light collection lens optically coupled to the photon generating means and configured to transmit a beam of the generated photons; (c) line focusing means operable to focus at least a first portion of the beam to a line; and (d) a linear array of photo-detectors configured to detect a variation of the quantity of generated photons along the focused line.
US09355827B2	Triple quadrupole mass spectrometer and non-transitory computer-readable medium recording a program for triple quadrupole mass spectrometer A triple quadrupole mass spectrometer provided with: a calibration information storage section for storing mass calibration information showing the relationship between the mass-to-charge ratio and a calibration value, with a CID gas pressure as a parameter, for each measurement mode of an MS/MS analysis including a dissociating operation using a collision cell; and a controller for calibrating the mass-to-charge ratio of the ion to be detected by a detector, by reading, from the calibration information storage section, the mass calibration information corresponding to the measurement mode to be performed and a specified CID gas pressure and by driving each the front and rear quadrupoles and using that information.
US09355826B2	Method for imaging mass analysis using physical vapor deposition of platinum nanoparticles The present invention provides an improved method for imaging mass spectrometry using an ionization-assisting matrix of a test sample, wherein the ionization efficiency is high, migration and visual information reduction are inhibited, no interference peaks originating from the matrix occur, and the analysis can be performed at high spatial resolution.Specifically, the present invention provides a method for imaging mass spectrometry using a sample prepared by physical vapor depositing platinum nanoparticles on the surface of a test sample to be subjected to imaging mass spectrometry.
US09355824B2	Arc suppression and pulsing in high power impulse magnetron sputtering (HIPIMS) An apparatus for generating sputtering of a target to produce a coating on a substrate is provided. The apparatus comprises a magnetron including a cathode and an anode. A power supply is operably connected to the magnetron and at least one capacitor is operably connected to the power supply. The apparatus also includes an inductance operably connected to the at least one capacitor. A first switch and a second switch are also provided. The first switch operably connects the power supply to the magnetron to charge the magnetron and the first switch is configured to charge the magnetron according to a first pulse. The second switch is operably connected to discharge the magnetron. The second switch is configured to discharge the magnetron according to a second pulse.
US09355820B2	Methods for removing carbon containing films Embodiments of methods for removing carbon-containing films are provided herein. In some embodiments, a method for removing a carbon-containing layer includes providing an ammonia containing process gas to a process chamber having a substrate with a silicon oxide layer disposed atop the substrate and a carbon-containing layer disposed atop the silicon oxide layer disposed in the process chamber; providing RF power to the process chamber to ignite the ammonia containing process gas to form a plasma; and exposing the substrate to NH and/or NH2 radicals and hydrogen radicals formed in the plasma to remove the carbon-containing layer.
US09355815B2	Electron microscope and electron beam detector An electron microscope is provided with a scintillator (7) and a light guide (8). The scintillator (7) has an index of refraction greater than the index of refraction of the light guide (8), and an end surface (72) joined to the light guide (8) is formed from a curved surface with a convex shape on the outside. The scintillator (7) is formed by a Y—Al—O based ceramic sintered body represented by the compositional formula (Ln1-xCex)3M5O12 (wherein Ln represents at least one element selected from the group consisting of Y, Gd, La, and Lu, and M represents either or both of Al and Ga).
US09355814B2	Charged particle beam apparatus Aiming for easily carrying out an energy discrimination or an angle discrimination of a secondary particle emitted from a sample or easily setting an optimal observation condition, a charged particle beam apparatus is provided with a charged particle source for emitting a charged particle beam, a lens for focusing the charged particle beam to a sample, a detector for detecting a secondary particle emitted from the sample, and an orbit simulator for calculating a position at which the secondary particle emitted from the sample arrives; and in this structure, the orbit simulator calculates an orbit of a secondary particle that satisfies a predetermined condition, and a sample image is formed by using a signal detected at a position where the secondary particle satisfying the predetermined condition arrives at the detector.
US09355812B2	Processing apparatus and processing method A processing apparatus according to the present embodiment includes a piezoelectric sensor unit, an irradiating unit, a calculating unit, a moving unit, and a controlling unit. The piezoelectric sensor unit is mounted with an object and outputs an electric signal corresponding to a pressure due to the weight of the object. The irradiating unit irradiates a portion of the object on the piezoelectric sensor unit with a beam. The calculating unit calculates a first amount of misregistration between the portion of the object which should be irradiated with the beam and an actual position irradiated by the beam on the basis of the electric signal from the piezoelectric sensor unit. The moving unit moves the irradiating unit. The controlling unit controls the irradiating unit or the moving unit in accordance with the first amount of misregistration.
US09355810B2	Integrated flying-spot X-ray apparatus Disclosed is an integrated flying-spot X-ray apparatus comprising a ray generator configured to generate the X-ray, a revolving collimator device provided thereon with at least one aperture and arranged to be rotatable about the ray generator, a frameless torque motor configured to drive the revolving collimator device to rotate about the ray generator, and a cooling device configured to cool the ray generator, wherein the ray generator, the revolving collimator device, the frameless torque motor and the cooling device are mounted on an integrated mounting frame. Compared with the prior art, the integrated flying-spot X-ray apparatus according to the present disclosure has a simple and compact structure and is used as a kernel apparatus for fields of safety inspection and medical treatment.
US09355809B2	Ion source According to one embodiments, an ion source connected with a vacuum-exhausted downstream apparatus is provided. The ion source includes a vacuum chamber which is vacuum-exhausted, a target which is set in the vacuum chamber and generates ions by irradiation of a laser beam, a transportation unit which transports the ions generated by the target to the downstream apparatus, and a vacuum sealing unit which seals the transportation unit so as to separate vacuum-conditions of the vacuum chamber side and the downstream apparatus side before exchanging the target set in the vacuum chamber.
US09355808B2	Injection locked magnetron microwave generator with recycle of spurious energy An injection locked magnetron microwave generator with a recycle of spurious energy, relating to a microwave power source, includes a frequency selective reflector for recycling the spurious energy of a magnetron and satisfies locking requirements of an output frequency of a high-output-power magnetron with a low-power injection signal. The microwave generator includes n magnetrons and n locking devices, n≧1. The locking devices inject locking signals into the corresponding magnetrons. The n locking devices are connected with a microwave source. Output terminals of the magnetrons are connected with corresponding frequency selective reflectors for reflecting the spurious microwave signals outputted by the magnetrons back to the magnetrons. The microwave generator, with a simple structure, effectively recycles the spurious energy outputted by the magnetrons, and reduces the power of the injection signal and costs of the microwave source and the overall microwave generator.
US09355806B2	Cathode assembly for use in a radiation generator A cathode assembly is for use in a radiation generator and includes an ohmically heated cathode, and a support having formed therein a hole and a recess at least partially surrounding the hole. In addition, there is a mount coupled to the support. The mount includes a larger outer frame positioned within the recess, a smaller inner frame carrying the ohmically heated cathode and spaced apart from the larger outer frame, and a plurality of members coupling the smaller inner frame to the larger outer frame.
US09355805B2	Input device An input device having a touch sensor installed on a push switch includes a first detection unit for detecting a first predetermined operation on the push switch, a second detection unit for detecting a second predetermined operation on the touch sensor, and a control unit for invalidating the second predetermined operation when the second predetermined operation is detected by the second detection unit within a predetermined time after detection of the first predetermined operation by the first detection unit. For example, the device is disposed on a spoke unit that is operable by a driver's thumb while the driver grips a steering wheel.
US09355803B2	Actuator with thermomagnetic shunt, especially for triggering a circuit breaker An electromagnetic actuator including a saturable magnetic shunt system. The shunt is associated with a coil of the actuator and allows channeling of a more or less large part of the flow according to current circulating in the product. In this way, when the actuator is used in a circuit breaker, the actuator allows the circuit breaker to be triggered from a short circuit as usual and also from overload caused by action of the shunt.
US09355801B2	Bimetal part and temperature-dependent switch equipped therewith A bimetal part (10) for use as an active switching element in a temperature-dependent switch has at least one inner region (13) and an outer region (12) surrounding the at least one inner region (13), the inner region (13) and the outer region (12) being formed such that in certain portions they are in one piece with one another and in certain portions they are mechanically separated from one another and being stamped in opposite directions, and at least one contact area (21) being provided on the inner region (13).
US09355799B2	Fast closing mechanism A fast closing mechanism includes a rotation shaft and an ejector pin. The ejector pin is rotatably assembled to the side plate by the rotation shaft. The ejector pin strides over the side plate. The ejector pin includes a first portion and a second portion. The first portion is connected to a handle via a rod, and the second portion is located above a press plate. The fast closing mechanism may have an additional ejector pin based on current structures, the press plate may press against a moving contact at an initial stage of a closing process, so that the moving contact will not move during the initial stage of the closing process. The mechanical energy generated during the closing process is stored in an energy storage spring. At a later stage of the closing process, the ejector pin releases the press plate to accomplish closing quickly.
US09355798B2	System and method for quenching an arc An arc quenching system is presented. The arc quenching system includes a mounting structure, a plurality of movable arc chute plates mounted on the mounting structure, and a motion delivery unit mechanically coupled to the mounting structure. The motion delivery unit is configured to impart at least one of a rotation motion and a vibration motion to one or more movable arc chute plates of the plurality of movable arc chute plates.
US09355793B2	User interface of a vehicle A method for operating a user interface of a vehicle, a user interface for a vehicle, and a vehicle are described.
US09355791B2	Discrete input circuit Embodiments are directed to a discrete input circuit comprising: a switch, a capacitor coupled to the switch, a first resistor connected in series with the capacitor and coupled to a power supply, and a second resistor coupled to the power supply and the switch, wherein a value of the capacitor, a value of the first resistor, and a value of the second resistor are selected to provide a wetting current from the power supply to the switch when the switch is closed in order to clean contacts associated with the switch.
US09355785B2	Electrolyte mixture, electrolytic capacitor having the same and oxidant mixture for conjugated polymer synthesis An electrolyte mixture for an electrolytic capacitor is provided. The electrolyte mixture includes a conjugated polymer, a polyether and a nitrogen-containing compound, or includes the conjugated polymer, the polyether and a nitrogen-containing polymer, or includes the conjugated polymer and a polyether with nitrogen-containing functional groups. The electrolyte mixture provides a very high static capacitance for an electrolytic capacitor having the same.
US09355782B2	Vertically mounted capacitor assembly A capacitor assembly comprises a plurality of capacitor elements, a clamping assembly, and a conductive path. The clamping assembly retains the plurality of capacitor elements longitudinally perpendicular to an adjacent mounting surface. The conductive path electrically connects the plurality of capacitor elements to one or more circuit elements disposed proximate the adjacent mounting surface. The clamping assembly includes a base with a central strut and a plurality of peripheral struts projecting perpendicularly therefrom, and the clamping assembly also includes a central conductive path.
US09355776B2	Capacitor assemblies for coupling radio frequency (RF) and direct current (DC) energy to one or more common electrodes Embodiments of a capacitor assembly for coupling radio frequency (RF) and direct current (DC) power to an electrode and substrate support incorporating same are provided herein. In some embodiments, the capacitor assembly includes a first conductive plate to receive RF power from an RF power source, the first conductive plate including a central bore; at least one capacitor coupled to the first conductive plate and surrounding the central bore; and a second conductive plate electrically coupled to the first conductive plate via the at least one capacitor, the second conductive plate including an input tap to receive DC power from a DC power source and at least one output tap to couple the RF and DC power to an electrode.
US09355773B2	Apparatus and method for shielding leakage magnetic field in wireless power transmission system A leakage magnetic field shielding apparatus includes a resonator configured to counterbalance a leakage magnetic field generated when a source resonator and a target resonator resonate at a resonant frequency of the source resonator and the target resonator.
US09355771B2	Integrated reactance module A contactless energy transfer circuit, comprising a magnetic receiving element (EMO) comprising a reactance receiving element (L4) configured to receive magnetic field energy from an integrated reactance module comprising a magnetic element (EM) and a plurality of coaxial windings of reactance power elements (L1), (L2) . . . (LN), separated from each other by means of magnetic flux conductors (SM) constituting an integral part of the magnetic element (EM), which is configured to concentrate magnetic field lines generated by the reactance power elements (L1), (L2) . . . (LN), wherein the outermost winding of reactance power elements (L2) is situated outside the magnetic element (EM) and the other windings of reactance power elements (L1), (L3) . . . (LN) are situated inside the magnetic element (EM), wherein the magnetic receiving element (EMO) is separated from the magnetic element (EM) by an insulating spacer (I).
US09355768B1	Battery removal tool A battery removal tool including a cylindrical housing having a front segment and a back segment, an opening continuously disposed within a front end of the front segment, a channel disposed within an interior surface of the front segment, a wall laterally disposed between the opening and the channel, a pair of magnets comprising a first magnet and a second magnet, a plurality of hollow cylindrical adjustable grips, and a cap. Each of the plurality of adjustable grips slidingly engages an exterior surface of the front segment.
US09355764B2	Magnetoelectric control of superparamagnetism A magnetoelectric composite device having a free (i.e. switchable) layer of ferromagnetic nanocrystals mechanically coupled a ferroelectric single crystal substrate is presented, wherein application of an electrical field on the composite switches the magnetic state of the switchable layer from a superparamagnetic state having no overall net magnetization to a substantially single-domain ferromagnetic state.
US09355763B2	Electronic protection component An electronic protection component comprises an outer case bounding an outer cavity therein; a varistor with a first varistor lead connected to a first varistor electrode and a second varistor lead connected to a second varistor electrode, wherein the varistor is placed in the outer cavity; a low melting point alloy wire with a first thermal fuse lead in one end and a second thermal fuse lead in the other end; wherein either the first thermal fuse lead or the second fuse lead is connected to either the first varistor electrode or the second varistor electrode therefore forming a lead junction.
US09355760B2	Integrating optical fiber with coaxial cable Certain embodiments herein relate to a hybrid cable that includes a center conductor for distributing electrical signals and one or more optical fibers adjacent to the center conductor for distributing light signals in a service provider network. According to one configuration, materials found in a coaxial cable may be included in the hybrid cable, such as a dielectric material, one or more protective shields, and an outer protective core. Such a hybrid cable may be utilized to replace drop cables in a service provider network, which may connect an access point, such as a tap, to a customer location. Certain embodiments herein may also relate to making and installing the hybrid cable.
US09355757B2	Electrical cable fitted with a theft deterrence means The invention relates to an electrical cable (1, 10) comprising at least two conducting strands (2, 3) and theft deterrence means in the form of a marking (8). The main characteristic of an electrical cable (1, 10) according to the invention is that the marking consists of a series of relief prints (8) akin to a bar code.
US09355752B2	Irradiation field-limiting apparatus, X-ray-generating unit including the irradiation field-limiting apparatus, and X-ray radiography system including the irradiation field-limiting apparatus An irradiation field-limiting apparatus connected to an X-ray-generating apparatus includes a pair of first limiting blades defining a width of an opening through which radiation is to pass; a first opening width-adjusting mechanism including a first opening width-adjusting shaft operable to adjust the width of the opening by moving the pair of first limiting blades toward or away from each other; and a first opening center-adjusting mechanism including a first opening center-adjusting shaft operable to adjust a center position of the opening by moving the pair of first limiting blades in a same direction. The first opening width-adjusting shaft and the first opening center-adjusting shaft are coaxially arranged.
US09355749B2	Device for the dry handling of nuclear fuel assemblies A device for the dry handling of nuclear fuel assemblies is provided. The device includes a transfer basket which can be connected to a lifter and which includes a gripper for gripping the fuel assembly to be transferred, the gripper being supported by a lift built into the basket; and an indexing table which can be placed on a cask and which comprises a positioner for positioning the basket over a slot in the cask.
US09355745B2	BIST circuit The BIST circuit includes an address data converting circuit that receives the logical address signal, the logical data signal, and the logical expected value signal. The address data converting circuit converts the logical data according to a physical configuration in the memory so as to generate a physical data signal specifying physical data to be written into the memory. The address data converting circuit converts the logical address according to the physical configuration in the memory so as to generate a physical address signal specifying a physical address of the memory for the physical data. The address data converting circuit converts the logical expected value according to the physical configuration in the memory so as to generate a physical expected value signal specifying a physical expected value that is an expected value of read data of the memory for the physical data.
US09355741B2	Display apparatus having a gate drive circuit A gate drive circuit includes a shift register having a plurality of stages, in which an n-th stage (‘n’ is a natural number) of the plurality of stages is connected to at least one subsequent stage. The n-th stage includes a pull-up part configured to output a high voltage of an n-th gate signal using a high voltage of a clock signal as in response to a high voltage of a control node, a control pull-down part configured to pull-down a voltage of the control node into a low voltage in response to a carry signal outputted from at least one of next stages of the n-th stage and receiving a back-bias voltage corresponding to the low voltage, and a carry part configured to output the high voltage of the clock signal as an n-th carry signal in response to a high voltage of the control node.
US09355740B2	Semiconductor nonvolatile memory device with one-time programmable memories A semiconductor nonvolatile memory device of an embodiment includes: a plurality of transistors arranged in a matrix, the transistors in the same row being connected in series to form a transistor string having a first terminal and a second terminal; a plurality of first wiring lines each corresponding to one of the columns, and being connected to the gates of the transistors of the corresponding column; a common first electrode connected to each semiconductor region in which each transistor is disposed; and a write unit that selects one of the first wiring lines and one of the transistor strings, and applies a first voltage to the first electrode, a first write voltage to the selected first wiring line, a second voltage to the other first wiring lines, and a second write voltage to the first terminal and the second terminal of the selected transistor string in a write operation.
US09355734B2	Sensing circuits for use in low power nanometer flash memory devices Improved sensing circuits for use in low power nanometer flash memory devices are disclosed.
US09355733B2	Memory sensing system comprising nonvolatile memory device and related method of operation A memory system performs a first sensing operation to sense whether multi-level cells assume an on-cell state or an off-cell state in response to a first read voltage applied to a selected word line. It then supplies a pre-charge voltage to bit lines corresponding to multi-level cells that have been sensed as assuming the off-cell state in response to the first read voltage, and it performs a second sensing operation with the supplied pre-charge voltage to sense whether each of the multi-level cells that have been sensed as assuming the off-cell state assumes an on-cell state or an off-cell state in response to a second read voltage applied to the selected word line.
US09355732B2	Latch initialization for a data storage device A data storage device may include a memory die. The memory die includes a memory and a latch. A method may include receiving a command corresponding to a write operation to write information to the memory. The method may further include loading a set of bits into the latch prior to receiving the information at the memory die. The set of bits includes at least a first bit having a first value and a second bit having a second value that is different than the first value. The method further includes receiving the information at the memory die and overwriting at least a portion of the set of bits at the latch with the information.
US09355728B2	Very dense nonvolatile memory bitcell An asymmetric non-volatile memory bitcell is described. The bitcell comprises source and drain regions comprising carriers of the same conductivity type. A floating gate rests on top of the well, and extends over a channel region, and at least a portion of the source and drain regions. The drain region comprises additional carriers of a second conductivity type, allowing band to band tunneling. The source region comprises additional carriers of a first conductivity type, thereby increasing source-gate capacitance. Thus, the bitcell incorporates a select device, thereby decreasing the overall size of the bitcell. The bitcell may be created without any additional CMOS process steps, or through the addition of a single extra mask step.
US09355727B1	Three-dimensional memory structure having a back gate electrode A memory stack structure includes a cavity including a back gate electrode, a back gate dielectric, a semiconductor channel, and at least one charge storage element. In one embodiment, a line trench can be filled with a memory film layer, and a plurality of semiconductor channels can straddle the line trench. The back gate electrode can extend along the lengthwise direction of the line trench. In another embodiment, an isolated memory opening overlying a patterned conductive layer can be filled with a memory film, and the back gate electrode can be formed within a semiconductor channel and on the patterned conductive layer. A dielectric cap portion electrically isolates the back gate electrode from a drain region. The back gate electrode can be employed to bias the semiconductor channel, and to enable sensing of multinary bits corresponding to different amounts of electrical charges stored in a memory cell.
US09355726B2	EPROM cell array, method of operating the same, and memory device including the same An EPROM cell array includes a cell array including multiple unit cells, each of which includes a MOSFET having a floating gate, and which are disposed in an array with a plurality of rows and a plurality of columns; multiple first selection lines each coupled with drains of unit cells, which are disposed on the same row among the multiple unit cells; and multiple second selection lines each coupled with sources of unit cells, which are disposed on the same column among the unit cells, wherein a selected unit cell to be programmed or read is selected by one of the multiple first selection lines, and one of the multiple second selection lines.
US09355724B2	Memory system comprising nonvolatile memory device and method of adjusting read voltage based on sub-block level program and erase status A method of operating a nonvolatile memory device configured to erase a memory block in sub-block units comprises detecting state information of unselected sub-blocks associated with a selected sub-block comprising selected memory cells, adjusting a read bias of the selected memory cells based on the state information, and reading data from the selected memory cells according to the adjusted read bias. The state information indicates a number of the unselected sub-blocks having a programmed state or an erased state.
US09355723B1	Semiconductor device including a non-volatile memory preserving data stored in a volatile memory when powered off A semiconductor device may include a controller configured to generate a data retention path control signal in response to a power condition change signal. The semiconductor device may include a plurality of data retention paths configured to sequentially couple a plurality of global input/output (I/O) lines coupled to a volatile memory to a dummy I/O line in response to the data retention path control signal. The semiconductor device may include a dummy I/O pad coupled to the dummy I/O line. The semiconductor device may include a non-volatile memory device coupled to the dummy I/O pad, configured to retain a plurality of storage data received from the volatile memory when the volatile memory is powered off, or provide data retained in the volatile memory as recovery data when power is recovered by the volatile memory.
US09355720B2	Write driver, variable resistance memory apparatus including the same, and operation method A write driver is configured to determine a magnitude and an application time of a pre-emphasis current pulse in response to control codes generated according to parasitic components on a path from a write driver to a program target cell and a resistance value of the program target cell, and supply a preset program current to a memory circuit block by adding a pre-emphasis current to the preset program current in a program mode.
US09355718B2	Metallization scheme for integrated circuit For multi-level interconnect metallization, each metal level maintains a parallel line arrangement within a region, and the lines of each adjacent metal level are orthogonal or otherwise cross with one another. Vertical shunting among levels for routing in different directions employs short paddles that stay within the parallel scheme, and multiple paddles within a region at the same metal level can be co-linear. Parallel lines in the same metal level can be rotated with respect to one another in adjacent regions, for example to better interface with driver circuitry with orthogonal orientations in the different regions.
US09355717B1	Memory array with embedded source line driver and improved voltage regularity Providing a memory array having an embedded source line driver is described herein. By way of example, the source line driver can comprise a dissipation line and a switching component that connects or disconnects the dissipation line with a source line of the memory array. When the switching component is activated, the dissipation line can provide a low resistance path from the source line to ground, as one example. Disclosed are circuits in which one or more dissipation lines are situated along a length of the source line, facilitating reduced variation in electrical characteristics (e.g., voltage drop) along the source line, improving regularity of memory operations for memory cells associated with the source line.
US09355716B2	Memory channel detector systems and methods A method for determining decision metrics in a detector for a memory device. The method includes receiving a plurality of signal samples and extracting a set of statistics from the signal samples, wherein at least one of the statistics is non-linear or complex, is derived from a plurality of the signal samples, and is not a function of at least one real linear statistic that is derived from a plurality of the signal samples. The method also includes applying at least one decision metric function to the set of statistics to determine at least one decision metric value corresponding to at least one postulated symbol.
US09355710B2	Hybrid approach to write assist for memory array A hybrid write-assist memory system includes an array voltage supply and a static random access memory (SRAM) cell that is controlled by bit lines and a word line and employs a separable cell supply voltage coupled to the array voltage supply. Additionally, the hybrid write-assist memory system includes a supply voltage droop unit that is coupled to the SRAM cell and provides a voltage reduction of the separable cell supply voltage during a write operation. Also, the hybrid write-assist memory system includes a negative bit line unit that is coupled to the supply voltage droop unit and provides a negative bit line voltage concurrently with the voltage reduction of the separable cell supply voltage during the write operation. A method of operating a hybrid write-assist memory system is also provided.
US09355709B2	Digit line equilibration using access devices at the edge of sub-arrays A method of equilibrating digit lines, a memory array, device, system and wafer for digit lines configured in an open digit line architecture. The digit lines are equilibrated by coupling a terminated end of a first digit line to an equilibration reference and coupling an unterminated end of a second digit line to the terminated end of the first digit line. The memory array is configured with the first and second digit lines arranged directly adjacent to each other.
US09355705B2	Semiconductor device, method for controlling the same, and semiconductor system The semiconductor device includes a temperature sensor controlled so that temperature measurement is made once at each of a plurality of different reference temperatures at an interval of a preset number of times of refresh operations and a plurality of latch circuits holding the results of temperature measurement. A refresh period is set from outputs of the latch circuits inclusive of the result of temperature measurement carried out last time for each of a plurality of different reference temperatures. After start of measurement, temperature measurements are repeated every wait time corresponding to circulation of the refresh operations. The refresh period is set such that the high-temperature side results of temperature measurement are prioritized (FIG. 2).
US09355700B2	Read circuit for memory Embodiments are directed to detecting a state of a memory element in a memory device, comprising: applying a pulse of a predetermined magnitude and duration to the memory element to induce a transition in the state of the memory element when a polarity of the pulse is opposite to the state, monitoring, by a device, a signal associated with the memory element to detect a presence or absence of a transition in the signal in an amount greater than a threshold, and determining the state of the memory element based on said monitoring.
US09355698B2	Memory and logic device and methods for performing thereof In accordance with one exemplary embodiment of the present technique, there is disclosed a spins selective device, including a first layer comprising a ferromagnetic material. The spin selective device further includes a second layer coupled to the first layer. The second layer includes at least one molecule having a specified chirality, such that when an electrical current flows between the first layer and the second layer one or more regions of the ferromagnetic material become magnetically polarized along a certain direction.
US09355695B2	Semiconductor memory device and method of testing the same A semiconductor memory device includes a row input section suitable for receiving a first row signal including a first row command and a first row address, corresponding to an active command, during a test operation of the active command, a column input section suitable for receiving a second row signal including a second row address corresponding to the active command during the test operation of the active command, and a signal control section suitable for generating an internal row signal for an operation of the active command by transforming the first row signal and the second row signal outputted from the row input section and the column input section.
US09355694B2	Assist circuit for memory Embodiments include apparatuses, methods, and systems related to an assist circuit that may be coupled to one or more components of a memory system to selectively lower a supply voltage that is delivered to the component. For example, the assist circuit may be coupled to a plurality of bitcells (e.g., register file bitcells). The assist circuit may selectively lower the supply voltage delivered to the bitcells during at least a portion of a write operation and/or during an inactive state of the bitcells. Additionally, or alternatively, the assist circuit may be coupled to a read circuit to selectively lower the supply voltage delivered to the read circuit during an inactive state of the read circuit. The assist circuit may include a control transistor coupled in parallel with one or more diodes between a main supply rail and a supply node of the bitcells and/or read circuit.
US09355693B2	Memory receiver circuit for use with memory of different characteristics Embodiments include systems, methods, and apparatuses for reading a data signal from a memory, such as a dynamic random access memory (DRAM). In one embodiment, a memory receiver may include a differential amplifier to receive a data signal from the memory and pass a differential output signal based on a voltage difference between the data signal and a reference voltage. The data signal may have a first direct current (DC) average voltage level, and the differential amplifier may shift the differential output signal to a second DC average voltage level that is substantially constant over a range of values of the first DC average voltage level. In another embodiment, a voltage offset compensation (VOC) circuit may apply a compensation voltage to the output signal that is based on an activated rank or an identity of the memory module. Other embodiments may be described and claimed.
US09355692B2	High frequency write through memory device Embodiments include a high frequency write through memory device including a plurality of memory cells and a plurality of local evaluation circuits. Each of the plurality of local evaluation circuits are coupled to at least one of the plurality of memory cells and are configured to prevent data stored in the coupled memory cells from being written to a latch node during a write through operation.
US09355687B2	Storage circuit A storage circuit includes a volatile storage portion in which storage of a data signal is controlled by a clock signal and an inverted clock signal, and a nonvolatile storage portion in which a data signal supplied to the volatile storage portion can be held even after supply of power supply voltage is stopped. A wiring which supplies a power supply voltage and is connected to a protective circuit provided for a wiring for supplying the clock signal is provided separately from a wiring which supplies a power supply voltage and which is connected to the storage circuit. The timing of stop and restart of supply of the power supply voltage supplied to the wiring which is connected to the protective circuit is different from that of stop and restart of supply of the power supply voltage supplied to the wiring which is connected to the storage circuit.
US09355685B2	Multi-chip package and memory system A multi-chip package includes a first group of memory chips that includes a first memory chip and a second memory chip, a second group of memory chips that includes at least one memory chip, a first internal wiring system that couples the first memory chip and the second memory chip to a first terminal configured to receive a chip-enable signal, a second internal wiring system that couples the at least one memory chip to a second terminal configured to receive the chip-enable signal. The first memory chip and the second memory chip each include a chip address memory region configured to store an address associated with the memory chip, and an address rewrite module configured to rewrite the address associated with the memory chip and stored in the chip address memory region in response to an external operation.
US09355684B2	Thumbnail generation and presentation for recorded TV programs Thumbnail images representative of recorded TV programs are generated and presented to aid a user in browsing the recorded TV programs. In one implementation, a temporary thumbnail image is generated when a TV program first starts recording. The temporary thumbnail is used to populate any user interface (UI) screens that reference the recoded TV program. Once the TV program has reached a threshold amount of recording (e.g., a prescribed duration of recording, or completion of the recording), a permanent thumbnail image is generated and associated with the TV program. The permanent thumbnail is then presented in any subsequent UI screens, replacing the temporary thumbnail. In another implementation, display of the thumbnail images in the UI screens may be further controlled by setting preferences, such as parental controls.
US09355683B2	Audio playing method and apparatus Provided are a method and apparatus thereof for setting a marker within audio information, the method including: receiving the audio information including a silent portion and a non-silent portion; receiving a selection for a selected marker insertion point; determining, based on the received selection and received audio information, whether the selected marker insertion point occurs during the non-silent portion; and if the selected marker insertion point occurs during the non-silent portion, determining a time of the silent portion, and setting the marker to correspond to the determined time of the silent portion.
US09355680B1	On the fly formatting The disclosure is related to systems and methods of On the Fly Formatting. Various parameters that influence aerial density of hard disc regions can be changed on the fly based on storage capacity and reliability needs. Further adjustments can be made to the formatting of the region to fine tune achievable storage capacity and reliability values. In some cases, the formatting can include error correction code strength, gap widths between user data sectors and servo data sectors, other characteristics or parameters, or any combinations thereof.
US09355677B2	Preamplifier for adjustable write current The implementations disclosed herein provide for a storage device including a preamplifier that dynamically adjusts at least one of a rise time and fall time of an analog write current pulse based on a length of a corresponding write transition and/or characteristics of a media location where the write transition is to be recorded.
US09355674B2	Data storage device and system having adaptive brownout detection Technologies are described herein for adaptive brownout detection and mitigation in a storage device having rotational storage media. A target position on the rotational storage media for a current write operation is received. A value for a brownout mitigation parameter is determined based on the target position. A brownout condition is then detected on the storage device, and upon detecting the brownout condition, the current write operation is completed before a power-on reset of the storage device.
US09355673B2	Recording medium delivery mechanism and recording medium changer The recording medium delivery mechanism includes a slider, a holding lever, a biasing portion, a lever-opening operation portion, and a housing and discharging drive unit. The slider is supported on a chassis to be movable in housing and discharging directions of a recording medium. The holding lever is rotatably supported by the slider and configured to hold the recording medium. The biasing portion is configured to bias the holding lever toward the recording medium. The lever-opening operation portion is provided to the holding lever, is engaged with a lever engagement portion provided to the chassis by a movement of the slider in the discharging direction of the recording medium, and configured to rotate the holding lever in a direction away from the recording medium. The housing and discharging drive unit is configured to move the chassis and the slider in the housing and discharging directions of the recording medium.
US09355670B2	Increased spectral efficiency and reduced synchronization delay with bundled transmissions Techniques are provided for increasing spectral efficiency over data channels in a storage or communication system. In some embodiments, data may be encoded and transmitted over multiple channels. The transmitted data from the multiple channels may be considered together as a channel bundle, thereby increasing the edge transitions of the group of signals to improve clock recovery and reduce coding constraints. In some embodiments, the channel bit size is reduced to maximize data rates based on the reduced coding constraints. Furthermore, the channel bundle has only one channel with timing markers, so that a receiver may receive information from the channel bundle and recover clocking based on the timing markers in the one channel.
US09355662B2	Polarization rotator A polarization rotator for a recording head. The polarization rotator comprises a first waveguide coupled to an input coupler at a first end and a second waveguide. The first waveguide is offset from the second waveguide and a second end of the first waveguide is coupled to a second end of the second waveguide.
US09355658B2	Magnetic head and magnetic disk device According to one embodiment, a magnetic head is arranged opposite a magnetic recording medium including a recording layer. The magnetic head includes a magnetic pole, a light emitting unit, and a distance adjusting unit. The magnetic pole includes a soft magnetic material. The light emitting unit is arranged with respect to the magnetic pole in a travel direction of the magnetic head, and emits light with respect to the recording layer. The distance adjusting unit adjusts a distance between the magnetic pole and the light emitting unit.
US09355657B1	Implementing spin torque oscillator erasure prevention in microwave-assisted magnetic recording (MAMR) hard disk drives A method, apparatus, and system are provided for implementing spin-torque oscillator (STO) erasure prevention for microwave assisted magnetic recording (MAMR) hard disk drives (HDDs). A first voltage is applied to an STO element in the MAMR head at the time of write operation. A second voltage is applied to the STO element at the time of read operation, or not write operation, to prevent STO erasure otherwise resulting from remnant magnetization of STO at the time of read operation.
US09355654B1	Spin torque oscillator for microwave assisted magnetic recording with increased damping A microwave assisted magnetic recording (MAMR) write head includes a write pole tip, a trailing shield, and a spin torque oscillator between the write pole tip and the trailing shield. The spin torque oscillator may have a field generating layer and a damping layer which is exchanged coupled to the field generating layer.
US09355650B2	Real-time emotion tracking system Devices, systems, methods, media, and programs for detecting an emotional state change in an audio signal are provided. A plurality of segments of the audio signal is received, with the plurality of segments being sequential. Each segment of the plurality of segments is analyzed, and, for each segment, an emotional state and a confidence score of the emotional state are determined. The emotional state and the confidence score of each segment are sequentially analyzed, and a current emotional state of the audio signal is tracked throughout each of the plurality of segments. For each segment, it is determined whether the current emotional state of the audio signal changes to another emotional state based on the emotional state and the confidence score of the segment.
US09355649B2	Sound alignment using timing information Sound alignment techniques that employ timing information are described. In one or more implementations, features and timing information of sound data generated from a first sound signal are identified and used to identify features of sound data generated from a second sound signal. The identified features may then be utilized to align portions of the sound data from the first and second sound signals to each other.
US09355643B2	Evaluation of the voice quality of a coded speech signal A method is provided for determining an indicator evaluating the voice quality of a coded speech signal. The method includes the following steps: calculation per signal frame, of a predetermined number of coefficients of a linear prediction filter for the coded speech signal; determination per frame, of a speech signal reconstructed on the basis of the filter coefficients thus calculated; obtaining per sample, of the residual between the coded speech signal and the reconstructed speech signal; calculation of an evaluation indicator on the basis of the mean or the absolute value of the residuals obtained for all the samples. Also provided are a device for determining an indicator implementing the above method, a method of evaluating the quality or of identifying the class of coding of the coded signal using the indicator determined, as well as a measurement terminal implementing these methods.
US09355641B2	Monitoring device using selective attention model and method for monitoring same A monitoring device is provided, which includes an inputter configured to receive an input of a plurality of images captured at separate positions and a plurality of sound sources heard at separate positions, a saliency map generator configured to generate a plurality of mono saliency maps for the plurality of images and to generate a dynamic saliency map using the plurality of mono saliency maps generated, a position determinator configured to determine the positions of the sound sources through analysis of the plurality of sound sources, a scan path recognizer configured to generate scan paths of the plurality of images based on the generated dynamic saliency map and the determined positions of the sound sources, and an outputter configured to output the generated scan paths.
US09355631B2	Multilayer interlayer having sound damping properties over a broad temperature range A polymer interlayer having improved sound insulation is disclosed. The polymer interlayer comprises at least one soft layer wherein the soft layer comprises: a first poly(vinyl butyral) resin having a first residual hydroxyl content and a first glass transition temperature (Tg); a second poly(vinyl butyral) resin having a second residual hydroxyl content and a second glass transition temperature (Tg), wherein the difference between the first residual hydroxyl content and the second residual hydroxyl content is at least 1.0 weight percent; wherein the difference between the first glass transition temperature (Tg) the second glass transition temperature (Tg) is at least 1.5° C.; and a plasticizer; at least one stiffer layer comprising a third poly(vinyl butyral resin) having a third residual hydroxyl content; and a plasticizer, wherein the polymer interlayer has a damping loss factor (η) (as measured by Mechanical Impedance Measurement according to ISO 16940) of at least about 0.16 measured at two or more different temperatures selected from 10° C., 20° C. and 30° C.
US09355627B2	System and method for combining a song and non-song musical content A system with a decision engine having logic for using metadata for one or more song recordings and one or more non-song musical content items. The logic performs the steps of: interpreting the metadata for the first song recording; identifying a first non-song musical content item for playback at or near an end of the first song recording based on a similarity between the first song recording and the first non-song musical content item; and, in response to determining that the first song recording is at or near its end of playback, forming an altered playback of the first non-song musical content item by performing via real time digital audio signal processing an alteration of the first non-song musical content item to be rhythmically continuous in terms of tempo to the first song recording and/or harmonically continuous in terms of key and/or mode to the first song recording.
US09355624B2	Drum pedal with dynamic tension An improved drum pedal utilizes an advanced dampening system in combination with a base, pedal, beater assembly, and support structure. The pedal is mounted to the base while the support structure forms a first pillar and second pillar that allow rotation of an axle positioned between them. A cam on the axle is connected to the pedal by a first chain, allowing the beater assembly to be actuated by the pedal. The dampening system provides an opposed first dampening mechanism and second dampening mechanism, which are tethered to each other by a second chain. The second chain is engaged with a sprocket that is connected to the axle, such that rotation of the axle results in corresponding movement of the dampening mechanisms. Compression springs, combined with cylinders and flanges, respond to movement of the axle with dynamic tension. This is an improvement over the spring implementation of current drum pedals.
US09355621B2	Marked precoated strings and method of manufacturing same A coated string for a stringed device which includes a coating applied to the surface of the string. The coating includes a base layer bonded to the surface of the string and an at least partially transparent low-friction top coat applied to the base layer. The base layer includes heat activated pigments that change color when heated above a color shifting temperature. In one embodiment, the color of the pigment in one area contrasts with the color of the pigment in an adjacent area without otherwise affecting the low-friction surface of the coating. The areas of different color created in locations along the length of the low-friction coated string.
US09355618B2	Tuning peg covers The present disclosure details a tuning peg accessory. The tuning peg accessory may comprise a tuning peg cover. The tuning peg cover may be configured to cover a tuning peg of a stringed instrument. The tuning peg may serve multiple purposes, including, but not limited to, for instrument personalization and learning aid. Still consistent with embodiments of the present disclosure, a tuning peg cover purchase and customization platform may be provided. The platform may enable a user to specify a shape and size of a desired tuning peg cover. Moreover, the platform may enable the user to provide a custom design to be adapted to an exterior surface of the tuning peg cover. Having received the user's specifications, the platform may enable the manufacture, package, and delivery of the customized tuning peg cover.
US09355616B2	Multi-user multi-GPU render server apparatus and methods The invention provides, in some aspects, a system for rendering images, the system having one or more client digital data processors and a server digital data processor in communications coupling with the one or more client digital data processors, the server digital data processor having one or more graphics processing units. The system additionally comprises a render server module executing on the server digital data processor and in communications coupling with the graphics processing units, where the render server module issues a command in response to a request from a first client digital data processor. The graphics processing units on the server digital data processor simultaneously process image data in response to interleaved commands from (i) the render server module on behalf of the first client digital data processor, and (ii) one or more requests from (a) the render server module on behalf of any of the other client digital data processors, and (b) other functionality on the server digital data processor.
US09355615B2	Apparatuses, systems, and methods for converting a display driver sync signal into an image sensor sync signal In one embodiment, the converter is configured to receive a first sync signal from a display driver and to convert the first sync signal into a second sync signal. The second sync signal is for controlling image sensing.
US09355614B2	Image quality processing method and display device using the same This embodiment herein relates to an image quality processing method and a display device using the same which decrease a hardware processing load of the display device and improve both a contrast ratio and sharpness of edges in an image.
US09355608B2	Electronic device A receiving unit acquires a zoom instruction to enlarge or reduce a displayed image. An image processing unit is provided with a function of enlarging or reducing a displayed image in accordance with a zoom instruction. A zoom processing unit can enlarge or reduce a displayed image until the zoom factor of the displayed image reaches the limit. If the zoom factor of a displayed image reaches the limit, the indicator generating unit generates an indicator for notifying a user thereof.
US09355605B2	Electro optical device including correction unit that generates correction data for image signal and electronic apparatus Vertical cross-talk is reduced. A correction circuit includes a correction amount calculation unit that calculates a correction amount on the basis of input image data Din and that generates correction amount data U; a correction coefficient generation unit that generates correction coefficient data C which represents a correction coefficient decided upon in accordance with a position in a horizontal scanning direction of a data line to which input image data Din to be corrected is supplied; and a correction unit that corrects the input image data Din on the basis of the correction amount data U and the correction coefficient data C and thereby generates correction image data Dh.
US09355601B2	Methods and systems for sub-pixel rendering with adaptive filtering Processing data for a display including pixels, each pixel having color sub-pixels, comprises receiving pixel data. Once the pixel data is received, processing data for a display includes converting the pixel data to sub-pixel rendered data, the conversion generating the sub-pixel rendered data for a sub-pixel arrangement including alternating red and green sub-pixels on at least one of a horizontal and vertical axis. Next processing data for a display includes correcting the sub-pixel rendered data if a condition exists and outputting the sub-pixel rendered data.
US09355596B2	Organic light emitting display device An organic light emitting diode display including a display including data lines, scan lines, sense lines, and pixels electrically coupled to the data, scan, and sense lines, a compensator for sensing first and second driving currents flowing to the pixels corresponding to first and second test data in a compensation mode, to compare first and second reference currents with the first and second driving currents, respectively, and to update compensation data, a signal controller for compensating input data according to the compensation data to generate image data, and for changing the input data into the first and second test data in the compensation mode; and a data driver for generating a plurality of data signals by using one of the image data, the first and second test data, and to supply the data signals to the data lines.
US09355591B2	Organic light emitting diode display and method for compensating for degradation of pixel luminance An organic light emitting diode (OLED) display and a method of compensating for degradation are disclosed. One inventive aspect includes a panel assembly including a plurality of pixels. Luminance measuring units are formed along a perimeter of the panel assembly to measure luminance of light emitted from the pixels. A processing unit compares the measured luminance data so as to detect and also compensate for a degraded pixel.
US09355586B2	Display device, display driving method and display driver A display device includes: a plurality of display panels arranged adjacent to each other in a line scanning direction to form one screen; a master controller configured to drive one of the display panels; and one or more slave controllers configured to drive the other display panels, each of the slave controllers corresponding to each of the other display panels. The master controller is configured to drive the display panel based on a scanning control signal and a clock signal which are generated, and output the generated scanning control signal and the generated clock signal and each of the slave controllers is configured to drive the corresponding display panel based on the scanning control signal and the clock signal inputted from the master controller.
US09355585B2	Electronic devices with adaptive frame rate displays An electronic device may be provided with a display. The display may be a variable frame rate display capable of adaptively adjusting a frame rate at which display frames are displayed in response to information associated with the current state of operation of the device. The information may be gathered using control circuitry in the electronic device. The control circuitry may gather the information for adjusting the frame rate by monitoring the electronic device power supply configuration, other device components, the type of content to be displayed, and user-input signals. The control circuitry may adjust the frame rate based on the gathered information by increasing or decreasing the frame rate. The control circuitry may be formed as a portion of display control circuitry for the device such as a display driver integrated circuit or may be formed as a portion of storage and processing circuitry external to the display.
US09355584B2	System and methods for extraction of threshold and mobility parameters in AMOLED displays A system to improve the extraction of transistor and OLED parameters in an AMOLED display includes a pixel circuit having an organic light emitting device, a drive device to provide a programmable drive current to the light emitting device, a programming input to provide the programming signal, and a storage device to store the programming signal. A charge-pump amplifier has a current input and a voltage output. The charge-pump amplifier includes an operational amplifier in negative feedback configuration. The feedback is provided by a capacitor connected between the output and the inverting input of the operational amplifier. A common-mode voltage source drives the non-inverting input of the operational amplifier. An electronic switch is coupled across the capacitor to reset the capacitor. A switch module including the input is coupled to the output of the pixel circuit and an output is coupled to the input of the charge-pump amplifier.
US09355580B2	Video and content controlled backlight A display device includes a display panel; and a backlight panel provided below the display panel and defining a plurality of regions. A first array of light emitting diodes (LEDs) is provided along a first direction, each LED of the first array being coupled to a first line. A driver is coupled to the first line to drive the LEDs coupled to the first line. A second array of LEDs is provided along a second direction, each LEDs of the second array being coupled to a second line. A lighting condition of the regions defined by the backlight panel is controlled by turning on or off the LEDs.
US09355571B2	Modules and methods for biasing power to a multi-engine power plant suitable for one engine inoperative flight procedure training A system and method for conducting flight procedures training in a rotary-wing aircraft with a multi-engine powerplant includes determining a variable bias relative an available power margin to simulate a reduced power available flight condition; and displaying symbology indicative of the simulated reduced power available flight condition.
US09355569B2	Systems, methods, and computer program products for providing a learning aid using pictorial mnemonics A system, method and computer program product for providing a learning aid using pictorial mnemonics. The method can include receiving a first input including a selection of a content topic. The method further includes displaying a first pictorial mnemonic associated with the selected topic, wherein the first pictorial mnemonic comprises one or more sub-images, and a list of one or more attributes, wherein each attribute is associated with a corresponding sub-image.
US09355568B2	Systems and methods for providing an electronic reader having interactive and educational features The present invention relates to an electronic reader. More particularly, the present invention relates to systems and methods for providing an electronic reader having interactive and educational features. Generally, the electronic reader allows a user to view text on a visually perceptible output device (e.g., a screen) and to interact with the electronic reader through a tactile input device (e.g., a mouse). The user selects and, thereby, visually and/or audibly emphasizes words in the text through the use of the tactile input device. In some cases, the electronic reader records and reports the words that the user selects. Additionally, in some cases, pages of text displayed on the visually perceptible output device can be peeled back to reveal additional pages of text.
US09355567B2	System and method for highlighting an area encompassing an aircraft that is free of hazards A system and method display a hazard free area around an aircraft that is modified to alert a pilot if a threshold distance between a detected object and the aircraft is reached. The modification may include, for example, altering the size of the hazard free area and its color. Additional information that may be displayed includes distance to the object, width of the hazard free area, stopping distance of the aircraft, and a route to avoid the object.
US09355565B2	Crossing traffic depiction in an ITP display Provided are methods and systems for the disambiguation of an in trail procedure (ITP) vertical display by calculating and rendering symbology on a plan view traffic collision avoidance system (TCAS) display. The symbology represents an intersection point between the ground track of an ITP aircraft and the ground track of a blocking aircraft and further represents an association between the intersection point and the respective ITP blocking aircraft.
US09355564B1	Position determination systems and methods for a plurality of aircraft Systems and methods for use in navigating aircraft are provided. A method includes transmitting messages from a plurality of aircraft within time slots of a data transmission using a data link radio of each of the aircraft. The time slots of the data transmission are divided by time. The master aircraft transmits a message within a first time slot. Each message includes position data, time data, aircraft orientation data, and intended flight path data for the aircraft transmitting the message. The method further includes, for each of the plurality of aircraft, receiving a plurality of received messages transmitted by the other aircraft within the data transmission, and generating a representation of an environment around the aircraft based on the data within the received messages. The representation includes a current position and an intended path for one or more of the other aircraft.
US09355555B2	System and method for issuing commands in a media playback system Embodiments are described herein that provide a device that is bonded to a zone player or zone to cause an adjustment to be made by the zone player or zone.
US09355553B1	Relaying key code signals through a remote control device Upon receiving a keystroke indicator signal from a remote control device, a key code generator device identifies a codeset usable to communicate with a selected consumer device. The keystroke indicator signal contains an indication of a pressed key, which corresponds to a function of the selected consumer device. Using the identified codeset and the key indication, the key code generator device generates a key code and modulates that key code onto a radio frequency carrier signal, thereby generating a first key code signal. The remote control device receives the first key code signal from the key code generator device and modulates the key code onto an infrared frequency carrier signal, thereby generating a second key code signal. The remote control device relays the key code to the selected consumer device in the second key code signal. The key code causes the selected consumer device to perform the desired function.
US09355550B2	Operating state warning device An operating state warning device (1) for visually and/or audibly indicating at least one operating state or, respectively, a number of different operating states of a technical device such as a machine, an installation, a vehicle or the like having at least one visual and/or audible warning element (2), wherein at least one adjusting unit (4) for setting and/or adapting at least one operating parameter of the warning element (2) such as lighting color, color intensity, luminous image, volume, melody, tone sequence or the like is provided, wherein the adjusting unit (4) comprises at least one interface (6, 16) for receiving setting information of the operating parameter, is proposed for improving the configuration or the setting of such devices. According to the invention, this is achieved by the fact that the interface (16) of the adjusting unit (4) is designed as a wave receiver (6) for receiving waves as wireless setting information of the operating parameters.
US09355549B2	Method and system to schedule repairs for vehicles Systems and methods of the invention relate to identifying a repair facility for a vehicle and scheduling a repair for the vehicle while minimizing a downtime of the vehicle. Embodiments of the invention include receiving a route of a vehicle and a repair via a request for a repair. Based on the request for a repair, an evaluation component can identify a repair facility that can handle or perform the repair defined as well as be within proximity of the vehicle. A repair component can assign a repair facility to the vehicle based on a capability of performing or handling the repair, a geographic distance from the vehicle, or an inventory of parts for the repair.
US09355546B2	Method and apparatus for analyzing concentration level of driver Provided is an apparatus and method for analyzing a concentration level of a driver, the method including analyzing quantitative data associated with a time at which a line of sight (LOS) of a driver is dispersed and a time at which the LOS of the driver is focused, analyzing a reaction speed of a human machine interface (HMI) when a command based on device input information, voice information, and gesture information is input, and evaluating a degree of LOS dispersion of the driver based on the quantitative data of the driver and the reaction speed of a user interface (UI) of the HMI.
US09355545B2	Secure optionally passive RFID tag or sensor with external power source and data logging A secure optionally passive RFID tag or sensor system comprises a passive RFID tag having means for receiving radio signals from at least one base station and for transmitting radio signals to at least one base station, where the tag is capable of being powered exclusively by received radio energy, and an external power and data logging device having at least one battery and electronic circuitry including a digital memory configured for storing and recalling data. The external power and data logging device has a means for powering the tag, and also has a means.
US09355544B1	Method and apparatus for optically storing a binary state A fault indication method for equipment includes receiving a fault signal indicative of a fault of a device; energizing a light emitter based on the received fault indication, in which a luminous material is made to fluoresce based on receipt of light emitted by the light emitter; detecting fluorescence of the luminous material by a light detector, and outputting a voltage and/or current indicative of the fluorescence; and providing a fault output signal when the voltage and/or current exceeds a predetermined value.
US09355539B2	One time use multi-function tag An anti-theft tag has two slightly concave shells attached to each other by a hinge. One shell has an aperture through it and the other shell has a post located to insert through the aperture when the two shells are brought together. At least one catch tab extends laterally from the end of the post. The catch tab exceeds the width of the aperture and is constructed to give to allow the post to insert into the aperture, but to resist and prevent the extraction of the post. The post is severable to allow the remove of the catch tab to allow the opening of the tag. One of the shells also has a slot and the other has a tack. When the post is inserted through the aperture, the tack inserts into the slot. The tack passes through an object to be protected and maintains the tag in place.
US09355536B2	Resonance driver for determining a resonant frequency of a haptic device This document discusses, among other things, apparatus and methods for controlling a haptic transducer. In an example, a haptic controller can include an active termination driver having a configurable output impedance. The active termination driver can be configured to drive a haptic transducer and to process back electro-magnetic force (EMF) of the haptic transducer to provide motion feedback of the haptic transducer. In an example, the haptic controller can include a processor to provide a command signal to the active termination driver and to determine a resonant frequency of the haptic device using the motion feedback of the haptic transducer.
US09355534B2	Causing display of a notification on a wrist worn apparatus A method comprising determining of a notification based, at least in part, on occurrence of an event, the notification comprising a notification type associated with the event, causing display of a representation of the notification at a position on a wrist adherence portion of a wrist worn apparatus, the wrist adherence portion being distinct from a primary display, and the representation of the notification being indicative of the notification type, receiving information indicative of a notification selection input associated with the notification, and causing display of a different representation of the notification on the primary display of the wrist worn apparatus based, at least in part, on the notification selection input is disclosed.
US09355529B2	Enhanced slot-machine for casino applications A gaming system is provided, the gaming system including an entertainment software engine constructed to provide an entertainment game and display a received wager result separately of the entertainment game; a first and second real world engine constructed to provide a wager result in response to a wager request; and a game world engine connected to the entertainment software engine, the first and second real world engine using a network, the game world engine constructed to: receive a request for a wager for a player of the entertainment game, each request being triggered by a player action taken while playing the entertainment game in head-to-head competition; communicate, the first and second wager requests; receive a first and second wager result; and generate, based on the first and second wager result, a controlled sequence of a portion of the entertainment game, the controlled sequence changing the state of the entertainment game.
US09355527B2	Amusement devices and chance devices based on financial market indicators A method for wagering comprises receiving a bet regarding a spin of the reels of a slot machine. An outcome may be determined based on one or more financial market indicators. Other embodiments are disclosed.
US09355525B2	Method and system to fund and conduct second chance games A lottery second chance game program method is provided for a single lottery jurisdiction or across multiple participating lottery jurisdictions. The lottery jurisdictions are networked to a lottery server system. One or more production runs of primary game tickets are provide to each lottery jurisdiction, with each production run of game tickets having a total face value. For each of the production runs of game tickets, a percentage of the total face value is contributed by the lottery jurisdiction to fund prize awards in a plurality of second chance games that are common to all of the lottery jurisdictions. The plurality of second chance games are provided to all eligible players in all of the lottery jurisdictions by entry of a unique identifier from one or more losing primary game tickets into a central server system. The lottery jurisdictions thus fund the plurality of second chance games as a function of the total face value of game ticket production runs sold to players within their respective jurisdiction.
US09355524B2	Gaming machine displaying selected symbols in cells The present invention is a gaming machine, including a display which displays a plurality of cells for presenting a plurality of symbols in a game, a processor which executes the game, chooses at least two cells from the plurality of cells and a symbol from the plurality of symbols and presents the chosen symbol in the chosen cells, and a payout device which awards a reward according to an symbol arrangement on the cells, wherein each of the plurality of cells displays a symbol independently from each other.
US09355520B2	Apparent skill games for use with predetermined outcomes A gaming system having a game outcome generator separate from a gaming device, where the gaming device is wirelessly connected to the game outcome generator and, upon a game play request from a player, generates a request for a game play result. The game outcome generator generates a specific game outcome (won amount if the game play is a winning result, or a no-win, 0-value result) and sends it back to the gaming device. The gaming device uses the predetermined result to mimic or simulate a skill based game. The skill based game is designed to play just like an actual skill based game, which may result in poor players not getting the game to a state that has an equivalent value as that which is supposed to be awarded (equal to the predetermined game play). Each game includes a final game event, consistent with the game just played, which enables the game to make up any difference between the actual result of the skill based and the predetermined amount. This preserves the look and feel of the skill based game while allowing the game to award the player the total amount of the predetermined award.
US09355519B2	System and method for augmented reality gaming using a mobile device Disclosed is a method and system for preventing replay attacks for mobile promotions associated with gaming devices. Upon the occurrence of a promotion winning event such as a designated outcome of a game played on the gaming device the user, via a software application accessible to their mobile device, forwards images of the event to a server over a network. The server determines entitlement to the promotion and analyzes data associated with the images and mobile device location and time to confirm that the event is new promotion winning event. Upon such confirmation an entitlement to the promotion is awarded to the user. The foregoing prevents unscrupulous users from logging multiple claims for the same promotion winning event.
US09355517B2	Gaming machine with persistent wild feature Machines and methods are described for displaying a particular symbol at a corresponding symbol position for multiple consecutive outcome events, such as outcome events including a wager game played on a stand-alone machine located within a casino or a machine within a client-server architecture. After displaying the particular symbol for a first outcome event, the particular symbol can be displayed at the same symbol position within a symbol-display-portion for one or more successive outcome events without the particular symbol being selected to be displayed at the same symbol position. Other symbols displayed within the symbol-display-portion for the first and successive outcome events can be determined or selected by a processor using a random selection process. The particular symbol can be a Wild symbol. A data structure can include data for tracking whether the particular symbol is locked down for an outcome event after the first outcome event.
US09355509B1	Sign detection in multi-dimensional signal measurements Systems, methods, circuits and computer-readable mediums are disclosed for sign detection in multi-dimensional signal measurements. In some implementations, orthogonally oriented antennas are configured to generate signals in response to a magnetic field, where the signals correspond to components of magnetic field vectors in space. A circuit is coupled to the antennas and configured to: determine polarities of the signals based on phase measurements between the signals; reduce a possible number of magnetic field vector interpretations based on the determined polarities of the signals; reduce a possible number of angles or angle differences between the magnetic field vectors based on the reduced possible number of magnetic field vector interpretations; compare the reduced possible number of angles or angle differences to predetermined angle or angle differences; and detect a relay attack based on results of the comparing.
US09355508B2	System and method for deploying handheld devices to secure an area A handheld security system includes a set of handheld devices positioned at a group of access points to a secure area. The handheld device includes a set of input/output devices including a text and graphics display, a camera, a local security database and a set of security devices including an RFID reader, a bar code reader, a magnetic stripe card reader and a biometric scanner. The set of handheld devices are communicatively connected through wireless signaling and protocol to one another and to a server operating a global a global security database. The local security database is synchronized to the global security database. A location stack table is continuously updated with security events and monitored for violation of a set of anti-passback rules. An association table associates a set of assets and a set of personnel, allowing for visitor tracking and asset tracking on a schedule.
US09355505B2	Vehicle diagnosis apparatus A vehicle diagnosis apparatus includes an accumulation unit and a storage control unit. The accumulation unit cumulatively adds a numerical value indicating a normal operation history of each normal operation made to a vehicle to an initialized cumulative total value having a predetermined number of digits, during a time period from an assembly of a vehicle component to an actual use of the vehicle, and stores the cumulative total value in a non-volatile storage unit. The storage control unit, in response to an abnormality occurrence in the vehicle, stores a corresponding diagnosis code in the non-volatile storage unit. The accumulation unit further cumulatively adds a numerical value indicating the abnormality occurrence to the cumulative total value. The storage control unit stores, in the non-volatile storage unit, the diagnosis code indicating the abnormality occurrence in association with the cumulative total value.
US09355502B2	Synthetic image generation by combining image of object under examination with image of target Among other things, one or more techniques and/or systems for combining a three-dimensional image of a target with a three-dimensional image of an object that is under examination via radiation to generate a three-dimensional synthetic image are provided. Although the target is not actually comprised within the object under examination, the three-dimensional synthetic image is intended to cause the target to appear to be comprised within the object. In one embodiment, one or more artifacts may be intentionally introduced into the three-dimensional synthetic image that are not comprised within the three-dimensional image of the target and/or within the three-dimensional image of the object to generate a synthetic image that more closely approximates in appearance a three-dimensional image that would have been generated from an examination had the target been comprised within the object.
US09355499B1	Augmented reality content for print media A computer-implemented method includes: receiving, at a mobile computing device that includes a camera, an input that specifies one or more dimensions for a photograph to be included with a print media item; determining an aspect ratio based on the received input and presenting, on a display screen of the mobile computing device, a camera viewer with an aspect ratio that matches the determined aspect ratio; capturing, via the camera of the mobile computing device, a photograph at a first resolution, where an aspect ratio of the captured photograph matches the determined aspect ratio; uniquely associating the recorded video with the captured photograph, and transmitting, for receipt by a remote computer system, the captured photograph at the first resolution, the recorded video at the second resolution, and an indication of the unique association between the recorded video and the captured photograph, via a transmitter of the mobile computing device.
US09355498B2	Viewpoint control of a display of a virtual product in a virtual environment A method, system, and apparatus for visually presenting a virtual environment relative to a physical workspace. An output device visually presents a view of the virtual environment to guide a human operator in performing a number of operations within the physical workspace. A mounting structure holds the output device and is movable with at least one degree of freedom relative to the physical workspace. A sensor system measures movement of the output device relative to the physical workspace to generate sensor data. A controller computes a transformation matrix and the set of scale factors to align the virtual environment and the physical workspace. The controller changes the view of virtual environment based on the sensor data to thereby change the view of the virtual environment in correspondence with the movement of the output device relative to the physical workspace.
US09355494B1	Systems and methods for coordinated editing of seismic data in dual model A system and method may model physical geological structures. Seismic and geologic data may be accepted. A three-dimensional (3D) transformation may be generated between a 3D present day model having points representing present locations of the physical geological structures and a 3D past depositional model having points representing locations where the physical geological structures were originally deposited. An indication may be accepted to locally change the 3D transformation for a subset of sampling points in a first model of the models. The 3D transformation may be locally changed to fit the updated subset of sampling points. A locally altered or updated version of the first model and, e.g., second model, may be displayed where local changes to the first model are defined by the locally changed 3D transformation. The transformation may also be used to extract geobodies in the past depositional model.
US09355492B2	System, method, and computer program product for utilizing a wavefront path tracer A system, method, and computer program product are provided for utilizing a wavefront path tracer. In use, a set of light transport paths associated with a scene is identified. Additionally, parallel path tracing is performed, utilizing a wavefront path tracer.
US09355487B2	Coloring kit for capturing and animating two-dimensional colored creation A digital template animation kit is provided for generating a three-dimensional animation corresponding to a captured two-dimensional template. In embodiments, a template animation kit includes a template portfolio having template designs for coloring in by a user. A computing device executing a template animation kit application, such as a digital fashion portfolio kit application, may then capture an image of the user-completed drawings on each template design. In some embodiments, capturing an image of a template design includes identifying a coloring figure identifier, an upper page guide identifier, and a lower page guide identifier. In further embodiments, the captured images of two-dimensional template designs are applied to three dimensional digital templates for animation within a digital template animation environment.
US09355484B2	System and method of tile management A device selectively loads map tiles into its memory while re-using others. As a user chooses different sections of a master map to be displayed, the device determines an intersection between the formerly and currently viewed sections. The device copies selected references to map tiles in the intersection, with some re-indexing, from an array for the formerly displayed section into an array for the newly displayed section. The view of the map might be a three-dimensional perspective view of a two-dimensional surface. The device can create bounding boxes around polygonal perimeters of the viewed areas. The bounding boxes are divided into rectangles corresponding to the tiles located on the master map. The device determines which rectangles within the bounding boxes both (a) contain portions of their respective polygons and (b) overlap each other respective to their locations on the master map. The device already stores map tiles for those rectangles.
US09355483B2	Variable fragment shading with surface recasting A system, method, and computer program product are provided for shading primitive fragments. A target buffer may be recast when shaded samples that are covered by a primitive fragment are generated at a first shading rate using a first sampling mode, the shaded samples are stored in the target buffer that is associated with the first sampling mode and the first shading rate, a second sampling mode is determined, and the target buffer is associated with the second sampling mode. A sampling mode and/or shading rate may be changed for a primitive. A primitive fragment that is associated with a first sampling mode and a first shading rate is received and a second sampling mode is determined for the primitive fragment. Shaded samples corresponding to the primitive fragment are generated, at a second shading rate, using the second sampling mode and the shaded samples are stored in a target buffer.
US09355482B2	Dimension reducing visual representation method In a data visualization system, a method of arranging, in n dimensions, data points representing n or more variables, the method including the steps of: a data point ranking module ranking a set of data points with respect to a first axis of a visual representation using a first variable; and based on a second variable, a data point distribution module distributing the set of data points along the first axis while retaining information relating to the ranking of data points determined in step i).
US09355479B2	Automatic tuning of value-series analysis tasks based on visual feedback A method for selecting an analysis procedure for a value series, including displaying a value series on a computer display monitor, receiving one or more sequences of user provided annotations, where the annotations overlay at least a sub-interval of the value series on the computer display monitor, using the sequences of user provided annotations to select an optimal value series analysis method from a set of value series analysis methods, where selecting an optimal value series analysis method includes determining parameter values for the optimal value series analysis method, and presenting the selected optimal value series analysis method and parameters, and the optimal reconstruction of the annotation sequences to the user.
US09355477B2	Historical alarm analysis apparatus and method A method includes partitioning alarms into two or more alarm groups. The alarms are associated with operation of an industrial process system performing a process, and each alarm has multiple states. The method also includes generating a graphical display for presentation to a user. The graphical display identifies at least one of the alarm groups and multiple alarm indicators. Each alarm indicator indicates a state transition of an associated alarm between two of the alarm's states. The alarm indicators are arranged in the graphical display based on times of their respective state transitions.
US09355472B2	Device, method, and graphical user interface for adjusting the appearance of a control An electronic device with a display displays a user interface on the display. The device determines a first set of content-display values for one or more content-display properties of first content that corresponds to a respective region of the display. The device determines a first set of control-appearance values for one or more control-appearance parameters based on the first set of content-display values. The device displays a control in the respective region of the display, wherein an appearance of the control is determined based on the first content and the first set of control-appearance values.
US09355471B2	Color balancing apparatus for multiple image synthesis and method therefor A color balancing apparatus for multiple image synthesis and a method therefore, in which an automatic white balance unit, with respect to each of a plurality of input images that are obtained by sequentially capturing adjacent scenes, is configured to compare a neutral color representing the input image with chromaticity of standard sources that are predefined, determine a standard source which is closest to the neutral color among the standard sources as a standard illuminant, and perform a white balance on the input image based on the standard illuminant, so that a natural wide-area synthesis image is generated by use of a light source estimation scheme considering multiple light sources, without complex computation of the conventional wide-area image synthesis, are provided.
US09355470B2	Method and system for interactive layout In an embodiment of the present invention, an interactive system employs sets of interior design guidelines. In an embodiment, the user begins by specifying the shape of a room and the set of furniture that must be arranged within it. The user then interactively moves furniture pieces. In response, the system suggests a set of furniture layouts that follow the interior design guidelines. The user can interactively select a suggestion and move any piece of furniture to modify the layout.
US09355468B2	System, method, and computer program product for joint color and depth encoding A system and method are provided for performing joint color and depth encoding. Color data and depth data for an image is received. Based on the color data, confidence values are computed for the depth data and the depth data is encoded based on the confidence values to represent a correlated portion of the depth data and a decorrelated portion of the depth data. In one embodiment, the depth data comprises per-pixel vergence angles.
US09355465B2	Dynamic programmable texture sampler for flexible filtering of graphical texture data For a given texture address, a multi-mode texture sampler fetches and reduces texture data with a multi-mode filter accumulator suitable for providing a weighted average over a variety of filter footprints. A multi-mode texture sampler is configurable to provide both a wide variety of footprints and allow for a filter footprint significantly wider than the bi-linear (2×2 texel) footprint. In embodiments, filter coefficients specifying a weighting for each texel in a flexible footprint are cached from coefficient tables stored in memory. Techniques and systems are provided for dynamic allocation, update and handling of weighting coefficient tables as resources independent of sampler state.
US09355463B1	Method and system for processing a sequence of images to identify, track, and/or target an object on a body of water Airborne tracking systems use sensors to track objects of interest. In order to track the objects of interests, the sensors need to be steered such that the object is kept, ideally, in the center of the sensors field of view. Automatic steering of optical sensors requires the generation of a track on an object of interest. When tracking boats on the water, current approaches to image processing may generate multiple detections on the object of interest. Embodiments of the present disclosure solve the track multiplicity problem by grouping tracks associated with the object of interest into a cluster and by estimating a most likely location of the object within the cluster of tracks. Based on the estimated location, embodiments of the present disclosure outputs a single track for the object. The single track is used by an automatic steering system to maintain a sensor aimed at the object of interest.
US09355458B2	Image processing apparatus, method and program A path detection-use graph structure is generated based on a plurality of nodes representing the plurality of linear structures, and a path that is included in the generated path detection-use graph structure and connects a plurality of root nodes representing points of origin of the plurality of linear structures to each other is detected. Then, based on a predetermined condition representing a feature of an erroneous connection edge erroneously connecting two nodes that are to belong to different graph structures to each other, a connection cost is set for each of edges forming the path so that the erroneous connection edge is hard to connect, and based on the set connection costs, the plurality of graph structures corresponding respectively to the plurality of linear structures are generated.
US09355454B2	Automatic estimation of anatomical extents A hierarchical multi-object active appearance model (AAM) framework is disclosed for processing image data, such as localizer or scout image data. In accordance with this approach, a hierarchical arrangement of models (e.g., a model pyramid) maybe employed where a global or parent model that encodes relationships across multiple co-located structures is used to obtain an initial, coarse fit. Subsequent processing by child sub-models add more detail and flexibility to the overall fit.
US09355452B2	Camera and sensor augmented reality techniques Camera and sensor augmented reality techniques are described. In one or more implementations, an optical basis is obtained that was generated from data obtained by a camera of a computing device and a sensor basis is obtained that was generated from data obtained from one or more sensors that are not a camera. The optical basis and the sensor basis describe a likely orientation or position of the camera and the one or more sensors, respectively, in a physical environment. The optical basis and the sensor basis are compared to verify the orientation or the position of the computing device in the physical environment.
US09355443B2	System, a method and a computer program product for CAD-based registration A system for location based wafer analysis, the system comprising: (i) a first input interface; (ii) a second input interface; (iii) a correlator; and (iv) a processor, configured to generate inspection results for the inspected wafer, with the help of at least one frame run-time displacement.
US09355439B1	Joint contrast enhancement and turbulence mitigation method A method involves generating a denoised image by performing a denoising operation on an input image of an object, the input image having turbulence and a contrast reducing scattering medium therein, generating a contrast enhanced image from the denoised image using a contrast enhancement algorithm, estimating a global motion vector of the contrast enhanced image using an image alignment algorithm, generating a contrast enhanced aligned image by globally aligning the contrast enhanced image to the global motion vector and locally aligning the contrast enhanced image with an optical flow method, temporally averaging the contrast enhanced aligned image, and generating an output image of the object by performing a deblur operation on the temporally averaged contrast enhanced aligned image. The method may further include measuring turbulence using sequences of input images and output images.
US09355436B2	Method, system and computer program product for enhancing a depth map A first depth map is generated in response to a stereoscopic image from a camera. The first depth map includes first pixels having valid depths and second pixels having invalid depths. In response to the first depth map, a second depth map is generated for replacing at least some of the second pixels with respective third pixels having valid depths. For generating the second depth map, a particular one of the third pixels is generated for replacing a particular one of the second pixels. For generating the particular third pixel, respective weight(s) is/are assigned to a selected one or more of the first pixels in response to value similarity and spatial proximity between the selected first pixel(s) and the particular second pixel. The particular third pixel is computed in response to the selected first pixel(s) and the weight(s).
US09355434B2	Method and device for reconstructing super-resolution images The invention relates to a method for generating super-resolution images using a processing device, the method includes: oversampling an input image to generate an oversampled image; modifying the pixel value of a first pixel of the oversampled image by: generating a similarity value for each one of a plurality of candidate pixels in the input image and/or in one or more other input images, candidate pixels being selected based on the position of the first pixel in the oversampled image, similarity value being generated by evaluating the similarity of a group of pixels adjacent to each of the candidate pixels to a group of pixels adjacent to the first pixel; selecting a first subset of candidate pixels on the basis of similarity values, and generating the modified pixel value of the first pixel based on the pixel values and on the similarity values of the first subset of candidate pixels.
US09355432B1	Method and system for automatically cropping images The present invention relates to methods and systems for automatic image cropping. An automatic image cropping system includes a downsampling system, a saliency analyzer, a spatial scatter, and a face detector configured to detecting one or more faces within the image. The saliency value of each pixel not associated with a detected face within the image is adjusted if one or more faces within the image are detected. A search system defines a saliency region based on a total value of saliency values within the saliency region and on a parameter, where the parameter value is based on a relative importance of a false positive pixel to a false negative pixel. The search system also defines a crop region using an aspect ratio that includes the saliency region and determines a position of the crop region based the saliency values within the crop region by performing a one dimensional search.
US09355429B1	Client computing system for and method of receiving cross-platform remote access to 3D graphics applications A client computing system in a client-server computing environment includes a client display driver that receives a transmission from a server, decodes graphics commands from the transmission using a client application, executes the functions using a client 3D library stored in a memory of the client, and renders the resulting image data to a display. The client may transmit capability information to the server, allowing the resolution of differences between the graphics application programming interfaces (APIs) supported on the server and the client.
US09355428B2	Method and apparatus for data processing using graphic processing unit A method of processing data using a Graphic Processing Unit (GPU) is provided. The method includes obtaining operand data and operator information to be applied to the operand data, partitioning the operand data by a channel element size unit of a texel of the GPU, transmitting an instruction which controls the GPU to return an operation result by performing an operation for the partitioned data and transmitting the partitioned data, and obtaining an operation result value from the GPU.
US09355424B2	Analyzing hack attempts of E-cards Transactions using a bank customer's electronic debit or credit card (“e-card”) are monitored by the card owner's consumer electronic (CE) device and reported to a server associated with the financial institution maintaining the e-card records for analysis of aggregated hack attempts.
US09355421B2	Product options framework and accessories Techniques are described for describing and associating custom products. In an embodiment, a first attribute value that defines an attribute of a custom product is received from a user that is customizing the custom product. In response to receiving the first attribute value, a legal set of attribute values for a second attribute of the custom product or an accessory product may be determined. The legal set of attribute values identifies one or more attribute values of the second attribute of the custom product or accessory product that are compatible with the first attribute value. The legal set of attribute values may identify a continuous range of values where any value within the continuous range of values is compatible with the first attribute value. In an embodiment, the user may be limited to selecting accessory products having a legal attribute value.
US09355420B2	Bandwidth management A computer identifies a plurality of available network connections, wherein at least one of the identified network connections is contractually available to the computer under terms of a monthly data plan. The computer determines, based, at least in part, on characteristics of each network connection of the plurality of network connections and anticipated bandwidth consumption of the computer, a network connection to connect to from the plurality of network connections. The computer connects to the determined network connection. The computer determines, based, at least in part, on anticipated bandwidth consumption of the computer and contractual terms of the monthly data plan, an amount of excess bandwidth available for sale.
US09355419B2	Metadata map repository Disclosed are various embodiments for a catalog mapping tool application. The application is executable in at least one computing device and comprises logic that identifies a system catalog of an item and a user catalog of the item. The system catalog may include a system acceptable format for a value of an attribute associated with the item, and the user catalog may include a user defined format for the value of the attribute associated with the item. The application further comprises logic that receives a selection of one of a plurality of recommended metadata maps for translation from a client device associated with the seller. In addition, the application comprises logic that facilitates translating the user catalog to the system catalog based at least in part on the one of the plurality of recommended metadata maps.
US09355416B2	Forward path multi-media management system with end user feedback to central content sources The Forward Path Multi-Media Management System architecture enables end user devices to share a common wireless forward path of a multicast communication architecture in which the forward path delivered content is dynamically changed or modified based on a real-time, near-real-time, or delay-time basis via aggregated reverse path feedback from at least one of a plurality of end user devices. The Forward Path Multi-Media Management System periodically or continuously aggregates the feedback input received via the reverse path (having wired and/or wireless connectivity), modifies the forward path multi-media content, and delivers this dynamically modified multi-media content to the then connected population of end user devices via a wireless forward path multicast in a repetitive closed loop fashion.
US09355409B2	Intelligent communication and advertising mechanism Disclosed is a system and method for exchanging information between a mobile device and a physical advertising medium, such as a billboard. The method and system enables a pluggable device, coupled with the mobile device, to detect the mobile device within its vicinity of the physical advertising medium. On detection of the mobile device, the pluggable device establishes a handshake communication channel with the mobile device by authorizing the mobile device. Upon authorizing the mobile device, the pluggable device initiates the advertisement information exchange between the physical advertising medium and the mobile device in a non-intrusive manner. In one aspect, the method and system further enables the mobile device to relay the advertisement information to other mobile devices or any other physical advertisement mediums within its vicinity.
US09355407B2	Systems and methods for searching cloud-based databases Systems and methods for searching cloud-based databases are provided herein. A service provider may have a need to make their database(s) searchable through search technology. However, the service provider may not have the resources to implement such search technology. The search technology may allow for search queries against these cloud-based databases. The technology described herein provides a solution addressing the service provider's need, by giving a search technology that furnishes search results in a fast, accurate manner. In further embodiments, systems and methods to monetize those search results are also described herein.
US09355405B2	System and method for advertisement transmission and display The disclosure herein provides systems and methods for a media enhancement system configured to associate a secondary media signal (for example, the secondary media signal can comprise an advertisement) to a primary media signal (for example, a radio broadcast). The disclosure herein additionally provides systems and methods for a media enhancement system that enables the generating, transmitting, displaying, and/or responding to a plurality of associated and/or unassociated secondary media signals, based on a primary media content from a primary media signal, user characteristics (for example, demographic and/or geographic information), and/or third-party preferences (for example, the goals of advertisers). The secondary media signals can be used to enhance the primary media content already being provided to the user on a user device. The secondary media signals can also be used to create psychological associations or relationships with the primary media content already being provided to the user.
US09355404B2	Voting with your feet A method of voting with your feet is disclosed. A notification regarding a survey question is communicated to a player of a computer implemented game. The notification includes an indication of a particular location-based action that is to be performed by the player to answer the survey question. The answer of the player to the survey question is determined based on detection of performance of the particular location-based action by the player.
US09355402B2	System, method and computer program product for improving messages content using user'S tagging feedback The present invention is a system and method to improve the impact of marketing messages broadcasted to various web communities. Marketing communication keywords that are predefined are matched against tags set by private and public user's tagging communities. Semantic analysis is applied on the keywords and the tags and resulting associations allow determining relevance of marketing keywords. Matches indicate where marketing people have met their goals while matching gaps indicate marketing messages have not been perceived by the companies or the market. Valuable feedback is thus obtained to help re-enforce the initial messages that were not received or to replace the message wording by the one perceived from the identified market tags.
US09355400B1	Local item availability information Techniques are described for determining merchants that are able to provide items of interest. In some situations, consumers or other users supply requests for information about particular items of interest, and appropriate local merchants that are currently available to provide those items are identified and indicated to the users who made the requests. The identification of such appropriate local merchants may include automatically contacting human representatives of potentially appropriate merchants in order to automatically solicit information about the merchant, such as quantity and pricing information for items currently available in local inventory and current operating hours. The described techniques may be performed in an automated manner by an item availability information system, such as to provide a corresponding item availability information service to users (e.g., in exchange for fees from users).
US09355399B1	System and method for providing contactless payment with a near field communications attachment A system and method in accordance with exemplary embodiments may include an attachment with a near field communication antenna, a secure element, a plug capable of connecting the attachment to an audio jack on a mobile device. Further, a system and method in accordance with exemplary embodiments may include receiving a payment initiation instruction from a customer, using a near field communication antenna, sending payment information to a point of sale device, using one or more computer processors, encoding data related to the payment as audio data, and transmitting the data related to the payment through an audio jack.
US09355389B2	Purchase transaction system with encrypted payment card data Online ordering systems allow a user to submit sensitive information such as payment card information to a merchant in encrypted form. A payment card processor server may be used to provide the user's web browser with code for an encryption function, a cryptographic key, and a key identifier. The web browser may encrypt the payment card information by executing the encryption function and using the key. The encrypted payment card information may be supplied to the merchant over the internet. A key identifier that identifies which cryptographic key was used in encrypting the payment card information may be provided to the merchant without providing the merchant with access to the key. The merchant can forward the encrypted payment card information to the credit card processor server with the key identifier. The processor server can use the key identifier to obtain the key and decrypt the payment card information for authorization.
US09355388B2	Scheduling for service projects via negotiation Assignment scheduling for service projects, in one aspect, may comprise preparing input parameter data for servicing a client service request; generating a schedule for servicing the client service request by executing an optimization algorithm with the input parameter data; determining whether the schedule is acceptable by the client; and repeating automatically the preparing, the generating, the transmitting and the determining until it is determined that the schedule is acceptable by the client, wherein each iteration automatically prepares different input parameter data for inputting to the optimization algorithm and generates a different schedule based on the different input parameter data.
US09355384B2	Providing access to documents requiring a non-disclosure agreement (NDA) in an online document sharing community Provided are a computer program product, system, and method for providing access to documents requiring a non-disclosure agreement (NDA) in an online document sharing community. A document request is received from a requesting participant at a requesting participant computer comprising one of the participant computers in the network environment. In response to receiving the document request, an access page is returned to the requesting participant computer including a non-disclosure agreement (NDA) requesting that the requesting participant accept terms of the NDA in order to access the content of the document in the storage system. The content of the document is returned to the requesting participant computer in response to receiving indication from the requesting participant computer accepting the terms of the NDA.
US09355375B2	Launch of target user interface features based on specific business process instances A current use context can be extracted based on concrete data related to a currently displayed user interface feature in a business software architecture user interface environment. Relevant related business objects and transactional data for concrete instances of a process or scenario relevant to the current use context can be identified and a specific business object instance can be determined from a plurality of business object instances related to a specific current instance of the process or scenario relevant to the current use context. At least one target user interface feature associated with the process or scenario can be pre-populated with at least one parameter specific to a current data entry state of the specific current instance of the process or scenario and displayed via a user interface.
US09355374B2	Systems and methods for creating fingerprints of encryption devices Systems and methods for creating fingerprints for encryption devices are described herein. In various embodiments, the system includes an encryption device operatively connected to a device management system. According to particular embodiments, the device management system: 1) receives a first payload from the encryption device, the first payload including data in a particular format; 2) creates a fingerprint for the encryption device, the fingerprint including a section format for each of one or more distinct sections of the particular format; 3) storing a record of the fingerprint for the encryption device and the unique identifier at the at least one database; and 4) comparing a format of each subsequent payload received from the encryption device to the fingerprint for the device to determine whether the device has been compromised.
US09355364B2	Reciprocal quantum logic comparator for qubit readout One aspect of the present invention includes a reciprocal quantum logic (RQL) readout system. The system includes an input stage on which a read pulse is provided and an output stage configured to propagate an output pulse. The system also includes an RQL comparator comprising a first Josephson junction and a second Josephson junction that are coupled to a qubit. A bias current switches between a first Josephson junction in a first quantum state of the qubit and a second Josephson junction in a second quantum state of the qubit. The first Josephson junction triggers to provide the output pulse on the output stage in the first quantum state in response to the read pulse and the second Josephson junction triggers to provide no output pulse on the output stage in the second quantum state in response to the read pulse.
US09355363B2	Systems and methods for virtual parallel computing using matrix product states A virtual parallel computing system and method represents bits with matrices and computes over all input states in parallel through a sequence of matrix operations. The matrix operations relate to logic gate operators to carry out a function implementation that represents a problem to be solved. Initial matrices are prepared to encode the weights of all input states, which can be binary states. Intermediate results can be simplified to decrease computational complexity while maintaining useful approximation results. The final matrices can encode the answer(s) to the problem represented by the function implementation. The system and method are particularly useful in speeding up database searches and in counting solutions of satisfiability problems.
US09355352B1	Personal search results The search engine optimizer transforms input information interactively and works independently and in parallel with a browser and search engine supercomputer. The optimizer reorganizes the input, and provides an optimized version as an output. The output (Optimized, reorganized input) is sent to the search engine, which responds to the end user with search results. The optimizer recognizes each request as a pattern and stores the pattern in an advanced Glyph format. This permits the optimizer to use left brain English language and right brain geospatial key featured association equation to gain factor the best results, and then using deductive reasoning feedback equation attenuate content with confounding variables in order to stabilize and reduces sensitivity parameter variations due to the environment and identify a left and right side human brain checkmate combination required to achieve certitude.
US09355351B2	System for storing information related to objects and further transmitting the object information to users Disclosed is a system for storing information related to one or more objects and transmitting the object information to one or more users. The system includes first electronic circuitry, second electronic circuitry and third electronic circuitry. The first electronic circuitry interacts with one or more users and one or more objects. The second electronic circuitry capacitively coupled with first electronic circuitry and transmits the object information to the users via capacitive coupling. The third electronic circuitry capacitively coupled with first electronic circuitry via one or more users. The system further transmits the user related object information to one or more output devices.
US09355349B2	Long range RFID tag A Radio Frequency Identification (RFID) tag according to one embodiment includes a radiating element lying primarily along a plane, a conductive loop lying along a plane oriented about perpendicular to the plane of the radiating element, and an integrated circuit coupled to the conductive loop.
US09355347B2	Card, information processing unit, and recording medium having information processing program A card is provided comprising an information setting unit configured to output a first signal including unique information of the card, and a bending sensor configured to output a second signal corresponding to a curvature of the card. An information processing apparatus is also provided comprising a card reading unit configured to acquire information from a card a processor, and a memory device. The memory device stores instructions which when executed by the processor, causes the processor to acquire unique information from the card, and acquire curvature information from the card corresponding to a curvature of the card.
US09355343B2	Image forming apparatus and image formation method allowing for quick actual start for printing document described by page describing language To provide an image forming device that allows for quick actual start for printing a document described by a page describing language even while an auxiliary storage device such as an HDD is in an unmount state in sleep mode or the like. A main controller checks, in sleep mode, for a mount state of the auxiliary storage device, upon receipt of a request from an external device to process for printing a document described by a page describing language. Then, the main controller, upon judgement of the mount state of the auxiliary storage device, controls for storing printing data set related to the printing document temporally in the auxiliary storage device. On the contrary, the main controller, upon judgement of the unmount state of the auxiliary storage device, controls for storing the printing data set in a random access memory.
US09355342B2	Image forming apparatus that automatically prompts migration of box between image forming apparatuses at appropriate timing Provided is an image forming apparatus. The image forming apparatus includes a box configured to store data, a usage amount count unit, a threshold value storage unit, a comparison unit, a box search unit, a user interface unit, and a box migration unit. The usage amount count unit counts a usage amount for a user identification. The threshold value storage unit stores a threshold value associated with the usage amount. The comparison unit determines whether or not the usage amount is equal to or larger than the threshold value. The box search unit acquires, based on the usage amount and threshold, box identification information on the box corresponding to the user identification within another image forming apparatus. The box migration unit migrates data on the box within the other image forming apparatus to the box corresponding to the user identification within the image forming apparatus.
US09355341B2	Device and method for determining color of output image in image forming apparatus In a case where image processing, in which a ratio of the number of color pixels greatly fluctuates, is executed after performing charging determination, an output result might not match a result of the charging determination. There is provided a device for determining a color of an output image in a case where an image to be printed is printed with an additional image attached thereto, the device including: a unit configured to divide the image to be printed into blocks of a predetermined size; a unit configured to calculate an average value of color components of pixels included in the block; a correction value calculation unit configured to correct a calculated average value using a correction value corresponding to the additional image; and a color/monochrome determination processing unit configured to determine, based on the corrected average value, whether the block is a color block or a monochrome block.
US09355337B2	Consistent hierarchical labeling of image and image regions Classification of image regions comprises: recursively partitioning an image into a tree of image regions having the image as a tree root and at least one image patch in each leaf image region of the tree, the tree having nodes defined by the image regions and edges defined by pairs of nodes connected by edges of the tree; assigning unary classification potentials to nodes of the tree; assigning pairwise classification potentials to edges of the tree; and labeling the image regions of the tree of image regions based on optimizing an objective function comprising an aggregation of the unary classification potentials and the pairwise classification potentials.
US09355335B2	Image filtering method for detecting orientation component of edge and image recognizing method using the same The present disclosure relates to an image filtering method for detecting an orientation component of an edge and an image recognizing method using the same. The image filtering method includes receiving an original image, generating a plurality of first images by filtering the original image with filters respectively generated along a plurality of channels, generating a second image by selecting a channel having a maximum value for each image unit, from the generated first images, and generating an output image whose edge is detected so as to maintain the consistency of channel by filtering the second image with filters respectively generated along the plurality of channels to generate a plurality of third images and comparing the channel of the second image with the channels of the third images.
US09355325B2	Method for differentiating between background and foreground of scenery and also method for replacing a background in images of a scenery The present invention relates to a method for differentiating between background and foreground in images or films of scenery recorded by an electronic camera. The invention relates in addition to a method for replacing the background in recorded images or films of scenery while maintaining the foreground.
US09355322B2	Road environment recognition device This road environment recognition device is equipped with: a connecting line determination unit, which determines primary connecting lines indicating lane marks by setting candidate points at a position near a vehicle as starting points, and sequentially connecting two or more candidate points along a first direction, which is a direction away from the vehicle; and branch point determination unit, which determines whether a branch point exists on the primary connecting lines on the basis of the positional relationships between the primary connecting lines and a residual candidate point that does not form part of the primary connecting lines.
US09355321B2	Automatic detection of the number of lanes into which a road is divided This invention concerns a computer-implemented method for determining a number of lanes on a road. The method comprises receiving an image, the image being a photographic image of the road or an image derived from the photographic image of the road, carrying out an analysis of the image to identify lane dividers of the road and determining a number of lanes into which the road is divided from the identification of the lane dividers. The method may comprise determining a confidence level for the determined value for the number of lanes. Map data of a plurality of roads may be generated using the value for the number of lanes determined from the computer-implemented method.
US09355318B2	System and method for contexually interpreting image sequences A system and method for contextually interpreting image sequences are provided. The method comprises receiving video from one or more video sources, and generating one or more questions associated with one or more portions of the video based on at least one user-defined objective. The method further comprises sending the one or more portions of the video and the one or more questions to one or more assistants, receiving one or more answers to the one or more questions from the one or more assistants, and determining a contextual interpretation of the video based on the one or more answers and the video.
US09355312B2	Systems and methods for classifying objects in digital images captured using mobile devices In one embodiment, a method includes receiving a digital image captured by a mobile device; and using a processor of the mobile device: generating a first representation of the digital image, the first representation being characterized by a reduced resolution; generating a first feature vector based on the first representation; comparing the first feature vector to a plurality of reference feature matrices; and classifying an object depicted in the digital image as a member of a particular object class based at least in part on the comparing.
US09355310B2	Monitoring individuals using distributed data sources One or more processors receive data from one or more devices including an image of an individual and information that indicates the identity of the individual. One or both of the image and the information include data that indicates a location. One or more processors analyze the image of an individual and the information to generate a set of identifying characteristics for the individual. Based on a result of the analysis, one or more processors determine whether the set of identifying characteristics of the individual matches a recorded set of identifying characteristics of that individual within a threshold. In response to a determination that there is a match within the threshold, one or more processors associate the location with the individual.
US09355308B2	Auditing video analytics through essence generation Video analytics data is audited through review of selective subsets of visual images from a visual image stream as a function of a temporal relationship of the images to a triggering alert event. The subset comprehends an image contemporaneous with the triggering alert event and one or more other images occurring before or after the contemporaneous image. The generated subset may be presented for review to determine whether the triggering alert event is a true or false alert, or whether additional data from the visual image stream is required to make such a determination. If determined from the presented visual essence that the additional data is required to make the true or false determination, then additional data is presented from the visual image stream for review.
US09355303B2	Face recognition using multilayered discriminant analysis Face recognition using multilayered discriminant analysis includes systems and methods applying an initial linear discriminate analysis to a database of face images in a more-or less conventional manner. Initial fuzzy logic then is applied to the results of the initial linear discriminate analysis to produce a subset of the database of face images. Thereafter, a subsequent linear discriminate analysis is applied to the subset of the database of face images and subsequent fuzzy logic is applied to the results of the subsequent linear discriminate analysis to produce a further subset of the subset of the database of face images. The application of the subsequent linear discriminate analysis and application of the subsequent fuzzy logic may be repeated until the further subset contains only one, or zero, face images.
US09355299B2	Fraud resistant biometric financial transaction system and method A method and system for authenticating financial transactions is disclosed wherein biometric data is acquired from a person and the probability of liveness of the person and probability of a match between the person or token and known biometric or token information are calculated, preferably according to a formula D=P(p)*(K+P(m)), wherein K is a number between 0.1 and 100, and authenticating if the value of D exceeds a predetermined value.
US09355296B2	Authentication of articles Authentication apparatus (1, 100) and methods which authenticate an item (4, 110) responsive to the detection that a portion of the item has one or more predetermined characteristics, the said predetermined characteristics comprising either or both the thickness of the said portion of the item, and the thickness of one or more layers within the said portion of the item, determined by optically-based thickness measuring apparatus (6, 102-108). The item may be a product and the portion of the item may be a sheet of packaging material. The item may be a security document and the portion of the item may be a sheet of security document substrate.
US09355292B2	Optical information acquisition device An optical information acquisition device that comprises a main body and a connector assembly associated with said main body and comprising three connectors. The connector assembly can be rotated with respect to said main body between a first operating position wherein said connectors extend substantially perpendicularly to a first side of said main body and a second operating position in which said connectors extend substantially perpendicularly to a second side of said main body. The three connectors are positioned at the vertices of an acute-angled triangle, more preferably at the vertices of an equilateral triangle.
US09355288B2	Image capture and processing system supporting a multi-tier modular software architecture An image capture and processing system supports a multi-tier modular software, and plug-in extendable, architecture. The image capture and processing system can be realized as an image-capturing cell phone, a digital camera, a video camera, mobile computing terminal and portable data terminal (PDT), provided with suitable hardware platform, communication protocols and user interfaces. A third-party customer can write and install a software plug-in into the application layer so as to enhance or modify the behavior of the image capture and processing system without any required knowledge of the hardware platform, communication protocols and/or user interfaces.
US09355286B2	Passive radio frequency identification (RFID) reader, passive RFID tag, and transmitting and receiving methods using extended pulse-interval encoding (PIE) An extended Pulse-Interval Encoding (PIE) modulating method in a Radio Frequency IDentification (RFID) system, wherein the method modulates 2-bit transmitted data and comprises: adjusting a length of a symbol according to a value of the first bit of the transmitted data; and adjusting a length of an energy transfer waiting section according to a value of the second bit of the transmitted data.
US09355285B1	Tone-based wake up circuit for card reader A card reader for a point-of-sale system that is configured to accept both magnetic strip-type and integrated circuit (IC) chip-type payment cards. The card reader is a component of a point-of-sale system including a portable computing device in communication with the card reader that is configured to present a first graphical user interface (GUI) when a magnetic stripe-type card is detected and a second GUI when an IC chip-type card is detected in the card reader. The card reader comprises a slot configured to receive the payment card, a magnetic reading device and an IC chip reading device. The card reader also includes a discriminator contact disposed within the slot that is configured to conduct across a surface of a metal pad of the IC chip-type card prior to the CI chip reading device making contact with the IC chip.
US09355282B2	Using multiple display servers to protect data A first display server and a second display server execute on a processing device. The first display server provides a secure environment for data presented in first application windows of the first display server and the second display server provides an unsecure environment for data presented in second application windows of the second display server. The processing device receives at least one user command to copy data from one of the first application windows of the first display server to one of the second application windows of the second display server. The processing device prompts a user to perform an authentication upon receiving the at least one user command. In response to the user successfully performing the authentication, data is copied from said one of the first application windows to said one of the second application windows.
US09355280B2	Apparatus and method for providing hardware security A technique to provide a hardware security module that provides a secure boundary for retention of a secure key within the secure boundary and prevention of unauthorized accesses from external sources outside of the secure boundary to obtain the secure key. The hardware security module includes a security processor to unwrap and authenticate a secure key within the secure boundary to decrypt or encrypt data and to provide data through a single interface that communicates with external sources, so that all data transfers between the secure boundary, formed by the hardware security module, and external sources are transferred only through the interface. The hardware security module ensures no unwrapped key leaves the secure boundary established by the hardware security module.
US09355278B2	Server chassis physical security enforcement Discrete-component-level physical security is provided by the physical securing of defined hardware computing components through computer-controlled processes. Physical locking mechanisms are provided for individual components of a datacenter server chassis and are communicationally coupled to a computing device, which controls the state of the physical locking mechanisms, including in response to user identification and authentication information provided through a user input device that is also part of the server chassis. An access control list controlling physical access correlates user identities to the state of the physical locking mechanisms and other physical security devices and provides for one-time passwords and other like mechanisms. The state of physical security devices are also based on security requirements associated with processing being performed on one or more computing devices protected by such physical security devices. The server chassis can also comprise a backup power source for the physical locking mechanisms.
US09355276B2	Processing system A processing system is disclosed. The system comprises: a processing unit; a memory adapted to store firmware code and application code for execution by the processor; and a memory access control unit adapted to control access of the processing unit to firmware code and application code stored in the memory. The memory access control unit is adapted to disable access to firmware code when access to application code is enabled, and to disable access to application code when access to firmware code is enabled.
US09355275B1	Heterogeneous data from multiple sources A computer implemented method, system and product for transferring information between systems of record connected to a bus comprising generating an event in response a change in a system of record of the systems of record; transforming the change event into a generic event at an adapter for the system of record, wherein the adapter is communicatively coupled to the system of record and the bus; conveying the generic event to the bus from the adapter; reasoning on the generic event to determine if at least some information of the generic event should be propagated to another system of record; based on a positive determination, using a policy based system of record information filter to determine what information of the event to send to the another system of record, and propagating at least some of the information of the generic event in a new event to another adapter communicatively coupled to the another system of record; and translating the new event, at the adapter, to an event able to be understood by the another system of record.
US09355274B2	Method and device for archiving a document The method for archiving a document includes a step of encryption of the document with a symmetric key, a step of transmission of said encrypted document to an archiving operator, and a step of transmission of the symmetric encryption key of said document to an escrow operator distinct from the archiving operator. The method may also include a step of encrypting of the symmetric key with a key consisting of a dual key comprising asymmetric keys. Depending on whether it is applied to personal archiving or to document transmission, during the step of encryption with the asymmetric key, the asymmetric key is that of the user having transmitted said document or that of the recipient of the document.
US09355268B2	Managing access by applications to perceptual information Functionality is described herein by which plural environment-sensing applications capture information from an environment in a fine-grained and least-privileged manner. By doing so, the functionality reduces the risk that private information that appears within the environment will be released to unauthorized parties. Among other aspects, the functionality provides an error correction mechanism for reducing the incidence of false positives in the detection of objects, an offloading technique for delegating computationally intensive recognition tasks to a remote computing framework, and a visualization module by which a user may inspect the access rights to be granted (or already granted) to each application.
US09355264B2	Secretly transmitting messages over public channels An apparatus and a method for secretly transmitting messages over public channels is described. Data from a first enterprise service bus (ESB) of a first computer system is encoded in a new media file using steganography. The new media file is transmitted to a third party server over a public channel. The new media file is then downloaded and decoded at a second enterprise service bus (ESB) of a second computer system.
US09355259B1	Method and apparatus for accessing sensitive information on-demand Exposure of sensitive tenant information is minimized in a multi-tenant/multi-user environment. A unique encryption key is provided for each tenant. The tenant encryption key is never stored in the clear and each copy of the tenant encryption key is protected by a user derived password. A secure folder is created for each tenant and encrypted by the tenant encryption key. Secure folders are mounted only on-demand, i.e. when an authenticated request is received for that tenant. The secure folders are mounted only for specific durations only. Otherwise, they are un-mounted. When a secure folder is mounted, any read/write operation to the secure folder is encrypted/decrypted on-the-fly. When the secure folder is un-mounted, all file contents in the secure folder, and the secure folder itself, are not visible in the file system and no application can browse to the secure folder without the tenant encryption key.
US09355256B2	Sanitization of virtual machine images Sanitizing a virtual machine image of sensitive data is provided. A label for a sensitivity level is attached to identified sensitive data contained within each software component in a plurality of software components of a software stack in a virtual machine image based on labeling policies. In response to receiving an input to perform a sanitization of the identified sensitive data having attached sensitivity level labels contained within software components of the software stack in the virtual machine image, the sanitization of the identified sensitive data having the attached sensitivity level labels contained within the software components of the software stack in the virtual machine image is performed based on sanitization policies.
US09355253B2	Set top box architecture with application based security definitions A media processing device, such as a set top box, having selectable hardware and software components for forming media pathways compliant with security definitions provided by downloaded or preinstalled software applications. Such applications may include, for example, a downloadable conditional access security or DRM element/definition. A corresponding certification process can entail certifying a portion of an overall secure pathway, with one or more applications providing the final portion of the certification. Alternatively, predefined conditional access mechanisms are provided, with an application establishing which mechanism is to be used. In various embodiments, a set top box or resident software application may exchange capabilities with other devices in a media consumption network to compare against the requirements of the software application. Once the information exchange is complete, the software application may select which one or more modes of operation or media pathways, if any, that it will permit.
US09355252B1	Hosting architecture A service provider can maintain one or more host computing devices which may be utilized as bare metal instances by one or more customers of the service provider. Illustratively, each host computing device includes hardware components that are configured in a manner to allow the service provider to implement one or more processes upon a power cycle of the host computing device and prior to access of the host computing device resources by customers. In one aspect, a hosting platform includes components arranged in a manner to limit modifications to software or firmware on hardware components. In another aspect, the hosting platform can implement management functions for establishing control plane functions between the host computing device and the service provider that is independent of the customer. Additionally, the management functions can also be utilized to present different hardware or software attributes of the host computing device.
US09355250B2	Method and system for rapidly scanning files The present embodiments provide a method and system for rapidly scanning a file, wherein the method includes obtaining a data packet, the data packet comprising secure file characteristic information for determining whether a file in a system is a secure file, and scanning file characteristic information of files in the system one by one, if the currently scanned file characteristic information matches secure file characteristic information in the data packet identifying a file as a secure file, skipping an anti-virus scanning for the current file, and continuing to scan a next file. By using the data packet, when a new user performs a first scanning, a file with identical characteristic information as that in the data packet can be skipped, which can reduce the time for the first scanning.
US09355249B2	Securing thermal management parameters in firmware from cyber attack Methods and systems may provide for identifying a thermal management setting in a computing system, and comparing the thermal management setting to valid configuration information. In addition, the thermal management setting may be modified if it does not comply with the valid configuration information, wherein the modification can cause the thermal management setting to comply with the valid configuration information. Additionally, a threat risk notification can be initiated in order to notify users of the non-compliance.
US09355248B1	Container and image scanning for a platform-as-a-service system Implementations provide for container and image scanning for a Platform-as-a-Service (PaaS) system. A method of the disclosure includes initiating, by a processing device executing a node of a multi-tenant Platform-as-a-Service (PaaS) system, a scan process at the node to scan containers executing on the node, the containers executing functionality of multiple applications that are owned by multiple owners. The method further includes, for each container of the containers, scanning, by the processing device in accordance with the scan process, a top layer of application image instance used to launch the container in the node without scanning remaining layers of the application image instance, and terminating, by the processing device, the scan process for the container when the scanning generates a clean result.
US09355245B2	Systems and methods for reporter-based filtering of electronic communications and messages Methods and apparatuses for filtering electronic communications in a communication system. The method includes receiving a message report from a user in response to an electronic message received by the user, and identifying a confidence value associated with the user from whom the message report is received. The method also includes adding, if the confidence value exceeds a predetermined confidence value threshold, the confidence value to a signature value associated with the electronic message, and determining if the signature value exceeds a signature value threshold. The method further includes filtering the electronic message if the signature value exceeds the signature value threshold.
US09355241B2	Method for providing a dynamic code via a telephone A user provides an identifier to a computer server operating an online service by means of a network terminal connected to the computer server by a digital network. The user also provides a dynamic code that is to be used with the online service. The dynamic code is made up of a subset of digits that make up the number of a calling line, selected by a code server from among a set of available lines, so as to call the telephone of the user. The number for the dynamic code is transmitted to the online service by the code server. The dynamic code is extracted from the number for the calling line on the basis of an extraction rule indicated by the online service on the network terminal of the user.
US09355239B2	Image-based unlock functionality on a computing device Utilizing an image on a computing device to serve as a template for locking/unlocking the computing device. The image includes a plurality of portions that are defined and thereafter identified and presented to a user via a touch screen. A user selects portions/zones that are defined within the image in a specified sequence and this sequence is stored as a lock/unlock code for unlocking the computing device. In an embodiment, in addition to the specified sequence of selections, a movement or sequence of movements may be also be stored as part of the lock/unlock code.
US09355233B1	Password reset using hash functions Systems and methods disclosed herein may be utilized for resetting passwords to restore access to all or part of a computer system. A user receives a notification that a current password associated is about to expire or has already expired. The notification may comprise a link that, when activated, executes a first hash function on at least one seed of a user profile, for example a time stamp associated with the creation of the current password, to generate a key. The key is sent to the user, the user is prompted to enter the key into, for example, a dialog box. When the entered key is received, a second hash function is executed on the same seed and the result is compared to the entered key. If there is a match, the user is granted access to a part of the system in order to reset their password.
US09355229B2	Method for protecting an application program and related computer program product A Method for protecting an application program executable on a computer against reverse engineering, said application is created to run with at least one selected dynamic link library (DLL) on said computer, comprises the steps of: adding a specific library loader to the executable application program, said loader either contains or has access to said dynamic link library; setting modified references to said dynamic link library such that upon loading said application program and said loader into the main memory of said computer, said dynamic link library is initialized by said library loader instead of the operating system; The library loader and the pseudo-statically linked library could be embedded into the application program, thereby using unused space within the application. The protected application presents itself as a monolithic application without the vulnerable interface to a DLL.
US09355226B2	Digital rights management system implemented on a scanner In a digital rights management system where a scanner is connected to a rights management server, the process of applying digital rights protection is performed by the scanner, rather than the server, so that scanning and document protection can be done even when the server is not available. Upon scanning a document, the operator selects a rights management policy to be applied to the digital document. The scanner generates a document ID, embeds the document ID as metadata in the document, encrypts the document, and stores the document ID, policy ID of the selected policy, and encryption key as an entry in a local document-policy association table on the scanner. The scanner uploads the above information of the digital document to the server, which stores the information in a document-policy association table on server and uses it to perform document access control.
US09355223B2	Providing a managed browser Methods, systems, computer-readable media, and apparatuses for providing a managed browser are presented. In various embodiments, a computing device may load a managed browser. The managed browser may, for instance, be configured to provide a managed mode in which one or more policies are applied to the managed browser, and an unmanaged mode in which such policies might not be applied and/or in which the browser might not be managed by at least one device manager agent running on the computing device. Based on device state information and/or one or more policies, the managed browser may switch between the managed mode and the unmanaged mode, and the managed browser may provide various functionalities, which may include selectively providing access to enterprise resources, based on such state information and/or the one or more policies.
US09355220B2	Medication dispensing cabinet systems and methods A medication dispensing cabinet provides controlled access to medications and supplies stored in it. The cabinet may include at least one lockable storage compartment, and a controller that controls access to the at least one lockable storage compartment. The cabinet may include multiple printers integrated into the cabinet. The cabinet may include a camera operably coupled to the controller. The cabinet may include a set of cabinet electronics, and a power distribution and communications circuit board. The cabinet may include a radio frequency identification (RFID) reader, wherein the controller conditions access to the at least one lockable storage compartment on receipt of information from the RFID reader. Data may be stored in the controller according to an implementation of RAID technology. The controller may include multiple electronic communications network interfaces, and may include an out of band network communication channel. A dispensing cabinet may facilitate printing of labels for medications.
US09355217B2	Interactive medical diagnosing with portable consumer devices Medical tests and examinations are performed with consumer computing devices. The medical tests and examinations are selected and customized in accordance with conditions present in the testing environment, as well as physical characteristics of a user taking the test. The tests can include visual acuity tests, colorblindness tests and other medical tests, such as hearing tests.
US09355214B2	False clinical alarm rate reduction A clinical facility communication network connects a notification system to a plurality of patient monitors and to a plurality of clinician communication devices. Each of the patient monitors operate to detect physiological characteristics associated with a patient and to send event messages to the notification system. The notification system operates to receive the event messages and to determine which of the event messages include information of sufficient clinical significance to warrant generating and sending an alarm to a clinician. The event messages that are determine not to include clinically significant information are ignored.
US09355210B2	Method for deriving equivalent circuit model of capacitor A method for deriving an equivalent circuit model of a capacitor which makes it possible to derive, with high accuracy and with ease, an equivalent circuit model having characteristics in accordance with a direct current voltage applied to a capacitor. Characteristic values of predetermined resistive elements and capacitive elements forming an equivalent circuit model of a capacitor change in response to a DC bias voltage being applied to the capacitor, and the change is attributable to the material of a dielectric forming the capacitor. However, by multiplying the characteristic values of the resistive elements and the capacitive elements held while the DC bias voltage is not applied by a dimensionless coefficient in accordance with an application rule, the characteristic values of the resistive elements and the capacitive elements are corrected to values in accordance with the voltage of the DC bias voltage applied to the capacitor.
US09355204B2	Method of decomposing design layout for double patterning process A method of decomposing a design layout for a double patterning process is provided. The method includes changing, by a computing system, a design layout of a first polygon type to a design layout of a curved polygon type; coloring the design layout of the curved polygon type; generating stitching shapes for preventing acute corners in stitching areas of the colored design layout of the curved polygon type; separating the design layout including the stitching shapes for preventing the acute corners into separated design layouts of curved polygon type according to colors; and changing the separated design layouts of the curved polygon type to design layouts of a second polygon type.
US09355197B2	Real-time depth of field effects within design software Design software can be configured to allow a user in real-time to adjust a depth of field of a perspective of the user within a design space. In one implementation, for example, the design software can receive one or more inputs from a user regarding a layout of one or more objects in a design space. The design software can also render a three-dimensional model of the layout of the design space for display on a computerized display. The software can then receive from the user one or more input selections regarding a desired depth of field of the perspective of the user relative to one of the one or more objects rendered within the three-dimensional model. In addition, the design software can calculate revised rendering instructions that blur at least a portion of the design space. Furthermore, the design software can display, in real-time, the three-dimensional model with the desired depth of field to the user.
US09355191B1	Identification of query completions which change users' original search intent Technology described herein identifies and demotes query completions which divert users from their original search intent. The identified query completions may represent informational requests that are amusing diversions for some users, but which are not relevant to the actual information of interest for many users. For example, the identified query completions may represent information requests that some users may find humorous or entertaining, but which are not relevant to actual information of interest for many other users. The identification of these query completions may allow alternative query completions to be provided that can more likely assist users in finding the information they actually seek.
US09355184B2	Community-based parental controls According to a general aspect, a method includes maintaining rating groups, each rating group providing a rating for content compiled based on information received from a user evaluating the content. The method also includes receiving, from a first user, a selection of a first rating group, from among the rating groups, to be applied to a set of users associated with the first user. The method also includes receiving, from a user, a request for a piece of content from the content. The method also includes determining that the user from which the request was received belongs to the set of users associated with the first user. The method also includes, based upon the determination that the user belonged to the set of users associated with the first user, accessing information associated with the first rating group and determining whether the first rating group includes a rating for the requested piece of content. The method also includes determining whether or not to provide information to the requesting user conditioned on the indication or absence of a rating for the requested piece of content within the first rating group.
US09355181B2	Search result augmenting One or more techniques and/or systems are provided for augmenting search results with a user defined suggestion and/or for providing a user defined suggestion. For example, a venue entity may be associated with search results and/or user information (e.g., a set of search results may correspond to the Eiffel Tower). User defined data associated with the venue entity may be evaluated to generate a user defined suggestion associated with the venue entity. For example, user generated content about the Eiffel Tower, such as tips, advice, opinions, and/or other information specified by social network users, may be evaluated to determine a user defined suggestion “get tower tickets early, they sell out fast”. The user defined suggestion may be provided to a user (e.g., visiting the venue entity) and/or used to augment the set of search results. In this way, practical information, derived from opinions shared by other users, may be provided.
US09355180B2	Name-based customization of executables from web The customized execution of an executable accessed from a web server. Upon receiving a request for the executable, the web server determines a customization to be applied to the executable. For instance, arguments may be parsed from the Uniform Resource Locator (URL) of the request. The web server then sends a copy of the executable to the client, and provides customization argument(s) in the name of the executable. Thus, the name of the executable may differ, depending on the customization to be applied, although the executable binary itself may be the same. The client receives the executable copy, and interprets its name to determine the customization to be applied. For instance, the client may extract the argument(s) from the name of the executable, and provide those argument(s) to the executable when executed.
US09355179B2	Visual-cue refinement of user query results Methods and computer-storage media having computer-executable instructions embodied thereon that facilitate refining query results using visual cues are provided. Query results are determined in response to an indication of a user query. One or more groups of query results are generated from the query results based on categories of query results that share similar features. Visual cues are associated with each of the query result groups. Visual cues, in association with query result groups, are presented to a user. Query results associated with a selected visual cue may be presented to a user. A refined user query may be generated based on a selected visual cue.
US09355178B2	Methods of and systems for searching by incorporating user-entered information A system for and a method of using user-entered information to return more meaningful information in response to Internet search queries are disclosed. A method in accordance with the present invention comprises managing a database in response to multiple user inputs and displaying search results from the database in response to a search query. The search results include a results list and supplemental data related to the search query. Managing the database includes, among other things, re-ranking elements in the results list, storing information related to relevancies of elements in the results list, blocking a link in the results list, storing links to documents related to the search query, or any combination of these. The supplemental data include descriptions of or indices to one or more concepts related to the search query.
US09355176B2	Methods and apparatus to supplement web crawling with cached data from distributed devices Methods and apparatus to supplement web crawling with cached data from distributed devices are disclosed. An example method includes accessing a first set of websites cached in a panelist device; comparing the first set of websites to a second set of websites to be analyzed by a crawler; and retrieving with the crawler a first website included in the second set of websites but not included in the first set of websites from a server associated with the first website.
US09355174B2	Multi-input playlist selection A computer-implemented process comprises identifying, by a computer server system, a base topic for a personalized media stream for a user of a computer system; identifying, with the computer server system, a plurality of media items associated with the base topic using a plurality of different and independent categories of media categorization data, wherein each of the categories of media categorization data is assigned a weighting; building a collection of candidate media items from the identified plurality of media items; ordering the collection of candidate media items to form a personalized media stream; and providing the ordered collection of candidate media items for playing to the user.
US09355171B2	Clustering of near-duplicate documents Documents likely to be near-duplicates are clustered based on document vectors that represent word-occurrence patterns in a relatively low-dimensional space. Edit distance between documents is defined based on comparing their document vectors. In one process, initial clusters are formed by applying a first edit-distance constraint relative to a root document of each cluster. The initial clusters can be merged subject to a second edit-distance constraint that limits the maximum edit distance between any two documents in the cluster. The second edit-distance constraint can be defined such that whether it is satisfied can be determined by comparing cluster structures rather than individual documents.
US09355170B2	Causal topic miner Causal topic mining can include incorporating non-text time series data with a number of articles based on a time relationship and analyzing the incorporated non-text time series data and the number of articles at a particular time to determine a causal relationship.
US09355165B2	Method and system for performing data manipulations associated with business processes and operations A method and apparatus for accessing, processing and manipulating data in an OLAP database. According to one aspect, the present invention comprises a user interface configured for accessing, processing and manipulating data in an OLAP cube. According to another aspect, the present invention comprises a calculation engine for manipulating and managing data in the OLAP cube.
US09355164B2	Autonomically defining hot storage and heavy workloads In defining database objects for storage in a storage hierarchy, frequencies of accesses of a plurality of database objects over a predetermined time period are observed. A mean and standard deviation for the plurality of database objects are computed based on the observed frequencies of accesses of the plurality of database objects. A z-score for a given database object is determined based on a comparison of the frequency of access for the given database with the mean and standard deviation computed for the plurality of database objects by the computing processor; and a level in the storage hierarchy corresponding to the z-score of the given database object is determined. The given database object may then be stored at the level in the storage hierarchy corresponding to the z-score of the given database object.
US09355159B2	Systems and methods for adaptive data visualization utilizing a quick filter pattern A method for adaptive data visualization includes accessing business intelligence data stored in a database, providing an interactive web browser having a filter pane and a result display pane, the filter pane containing a list of characteristics and/or key figures, receiving a user's selection of a parameter associated with the characteristics or the key figures, adaptively filtering the accessed data the selection, where the first selection triggers the adaptive filter to filter the data, displaying results of the adaptive filtering in the result display pane, receiving a second selection from among the parameters, adaptively filtering the accessed data based on the first selection and the second selection, the second selection triggering the adaptive filter, and modifying the displayed results based on the adaptive filtering results of the first and the second selections. A system to implement adaptive data visualization and a computer readable medium containing executable instructions are also described.
US09355152B2	Non-exclusionary search within in-memory databases Methods for non-exclusionary searching within clustered in-memory databases are disclosed. The non-exclusionary search methods may allow the execution of searches where the results may include records where fields specified in the query are not populated or defined. The disclosed methods include the application of fuzzy matching and scoring algorithms, which enables the system to search, score and compare records with different schemata. This may significantly improve the recall of relevant records.
US09355151B1	Systems and methods for assessing the similarity between two non-standardized data sets A computer-based system and method is described for converting non-standardized resumes and job listings into standardized profiles that can be easily searched, compared and referenced. Attributes are identified within the resumes and job listings, and are evaluated for various features. Each resume or job listing is broken down into its component parts and analyzed based on a logic-based routine to identify and package meaningful content.
US09355150B1	Content database for producing solution documents Systems and methods for a content database storing extracted content. A content manager engine executing on a computer system performs various functions in relation to the content database. The content manager engine may extract content fragments from documents of different document types and store the content fragments to content entries of the content database. The content manager engine may reproduce a selected document using the content database, allow direct modification of content entries, and merge two documents of different types into a single document. The content manager engine may also be configured to produce a solution document using the content database based on one or more received user selections. A solution document may be provided to address issues or queries regarding computer system hardware or software. The solution document may comprise a description of any services, products, and/or technologies related to the issue or query.
US09355147B2	Access plan for a database query A system and method of creating an access plan for a database query is disclosed. The system and method include identifying a first portion of a column of a table of a database. The first portion of the column may be in a select statement of the database query. The system and method include estimating a first statistical value for the column. The estimating may occur by analyzing a second portion of the column. The system and method include generating the access plan to predict a characteristic of a set of results for the database query. In generating the access plan, the first statistical value for the column may be used.
US09355145B2	User defined function classification in analytical data processing systems Systems and apparatuses are provided for integrating user defined functions into an analytical data processing framework. The system includes a plurality of user defined functions (28), each having metadata defining an associated class type. A query compiler (22) identifies a call to a user defined function (28) within a query of an associated data table (26), retrieves the associated class type of the user defined function from the metadata, and provides a query plan according to a plurality of processing instructions derived from the retrieved class type.
US09355144B2	Method and apparatus for recycling information fragments in information spaces An approach is provided for recycling information fragments in information spaces. An information management system detects a plurality of information management processes occurring in an information space. The information management processes retrieve one or more information fragments from the information space. The information management system then determines a sequence of states for each of the plurality of information management processes over a period of time and calculates a state trajectory from each of the sequence of states. The calculated state trajectories are used to predict a finite set of possible future states. The information management system uses the prediction to determine which of the one or more information fragments are recyclable and preserves the recyclable information fragments for responding to a subsequent request directed to the information space.
US09355141B2	System and method for aggregating query results in a fault-tolerant database management system A redundant array of independent nodes are networked together. Each node executes an instance of an application that provides object-based storage. Metadata objects are stored in a set of regions distributed among the nodes across the array. A given region is identified by hashing a metadata object attribute and extracting a given set of bits of a resulting hash value. A method of managing query results comprises: receiving, by a first node of the plurality of independent nodes from a client application, a request for a list of objects with a criterion; issuing by the first node a query to all the nodes based on the received request; processing the query by each node over the regions in the node using the metadata objects stored in the regions; aggregating and filtering by the first node results of the query from all the nodes; and returning by the first node the aggregated and filtered results to the client application.
US09355140B1	Associating an entity with a search query Methods and apparatus for associating an entity with at least one search query. Some implementations are directed to methods and apparatus for identifying multiple queries associated with an entity and identifying one or more of the queries as an entity search query that provides desired search results for the entity. Some implementations are directed to methods and apparatus for identifying a particular entity and, in response to identifying the particular entity, identifying an entity search query corresponding to the particular entity.
US09355136B2	Automating generation of messages in accordance with a standard Arrangements described herein relate to automating generation of maps containing message formats and semantic validation rules. First unstructured data defining message formats for messages that conform to a particular standard and second unstructured data defining semantic validation rules to be applied to validate the messages can be scanned. First structured data corresponding to the first unstructured data defining the message formats and second structured data corresponding to the second unstructured data defining the semantic validation rules can be stored into a database. The first structured data and second structured data are configured to be processed to automatically generate a map comprising message formats and sematic validation rules for use in generating messages that conform to the particular standard and validating the messages.
US09355135B2	Data movement from a database to a distributed file system Provided are techniques for data movement. An activity is created that overrides existing security, that is associated with a user, that defines one or more source tables in a relational database and one or more target tables that are available to the user for the activity, and that provides security credentials of an author of the activity for use by the user, wherein the one or more target tables represent data in one or more target files in a file system. The activity is executed using the security credentials of the author to move data in a source table of the one or more source tables to a target file of the one or more target files, wherein a target table of the one or more target tables is defined over the target file. Access is provided to the user to the moved data using the target table.
US09355131B2	System and method for document version curation with reduced storage requirements A system and method for curation of document versions with significantly reduced storage requirements. In some embodiments, all or substantially all versions of a document are at least initially retained. Based on various criteria, versions of the document are selectively deleted while preserving the versions that are likely to provide the highest value. Advantageously, the teachings of embodiments as described can be used in conjunction with various systems, including document versioning, deduplication, and retention systems.
US09355121B1	Segregating data and metadata in a file system A technique for managing a file system includes dividing the addressable space of a file system into multiple subspaces: a data subspace for user data; an inode subspace for inodes describing the user data; and an MDB (metadata block) subspace for indirect blocks and/or directory structures pertaining to the user data. In response to storage requests to write user files to the file system, the file system stores user data of the files in the data subspace, stores inodes pertaining to the user files in the inode subspace, and stores indirect blocks and/or directories in the MDB subspace.
US09355112B1	Optimizing compression based on data activity A method is used in managing data compression in storage systems. A request to compress particular data stored within a memory space is received. An activity level for the particular data is determined. Compression is enabled for data determined to have an activity level below a predetermined threshold and compression is disabled for data determined to have an activity level above the predetermined threshold.
US09355101B2	Boot in a media player with external memory A media player is presented that scans the media files stored on an external memory card in order to update the internal database of the player. Media manager software on a personal computer sets a dirty bit in the internal memory of the media player whenever the media files on the external memory card are altered. The media player checks the dirty bit on start up or when the memory card is inserted. If the dirty bit is set, the media player scans the media files on the memory card, updates its database, then clears the dirty bit. If the dirty bit is not set, the media player does not scan the memory card. The dirty bit is associated in the internal memory with an identifier for the memory card, allowing the use of multiple memory cards.
US09355100B2	Methods and apparatus for reconciling versions of media context lists in communications networks Methods, systems, devices, apparatus and computer-program products are defined for reconciling different versions of media content lists that concurrently exist in a communication network. The merged media content lists are based on foreseen user expectations, taking into account typical user behavior. The merged media content lists includes the merge of media content acquisition priority lists that are maintained and routinely updated by the associated media content user.
US09355099B2	System and method for detecting explicit multimedia content A method for classifying a multimedia content is provided. The method includes processing one or more multimedia content to obtain a set of extracted features, performing a topic modeling on the set of extracted features to obtain a set of topic models, and a set of topic keywords. Each of the topic models includes one or more explicit content topics associated with the one or more multimedia content. The method further includes identifying an explicit content topic from the topics based on the set of topic keywords, and a set of predetermined words, processing a multimedia content to obtain at least one feature, and metadata associated with the multimedia content, deriving a topic distribution based on the at least one feature and the topic models, and classifying the multimedia content as (i) an explicit multimedia content, or (ii) a non-explicit multimedia content based on the explicit content topic, and the topic distribution.
US09355095B2	Click noise characterization model The techniques discussed herein consider a degree of noise associated with user clicks performed during search sessions. The techniques then generate a model that characterizes click noise so that search engines can more accurately infer document relevance.
US09355091B2	Systems and methods for language classification Systems and methods are provided for classifying text based on language using one or more computer servers and storage devices. In general, the systems and methods can include a language classification module for classifying text of an input data set using the output of a training module. In an exemplary embodiment, a bootstrapping step feeds the output of the language classification module back into the training module to increase the accuracy of the language classification module. By iterating the language classification and training modules with input data having certain features, a user can tailor the language classification module for use with text having those or similar features.
US09355090B2	Identification of candidate characters for text input Methods, systems, devices, and apparatus, including computer program products, for identifying candidates for text entry. One or more inputs entering one or more characters are received. One or more first candidate characters are identified and presented for the inputs using a first dictionary. One or more second candidate characters related to a respective first candidate character are identified and presented.
US09355082B2	Contextual history of computing objects Various features for a computer operating system include mechanisms for operating where a single native application, in the form of a Web browser, exists for an operating system, and all other applications run as Web apps of the browser application. A computer-implemented object tracking method includes instantiating, a first time, an operating system object on a computing device; automatically identifying contextual meta data that defines a state of objects that are open on the computing device, other than the instantiated operating system object, when the operating system object is instantiated; and storing the identifying contextual meta data in correlation with the operating system object, wherein the contextual meta data identifies one or more objects that are active in the operating system when the operating system object is instantiated.
US09355081B2	Transforming HTML forms into mobile native forms Techniques disclosed herein transform HTML forms into forms with graphical user interfaces (UIs) native to mobile devices. A user interface virtualization (UIV) agent divides an HTML form into rows based on row breaks. The UIV agent then identifies name-input pairs in the HTML form by applying a trained naïve Bayes classifier to determine name fields, and mapping the name fields to corresponding input fields. In addition, the UIV agent generates metadata which includes both information describing the rows in the form and the name-input information. Based on the metadata, a native form renderer running in the client device draws the form with native UI elements. In addition, the native form renderer forwards native UI events as HTML events.
US09355080B2	Propagating user feedback on shared posts Propagating user feedback on shared posts is described, including receiving a user indication associated with repost content. The repost content is associated with post content. The post content includes at least one item provided on a website. The repost content includes at least one other item provided on another website or the website, and the at least one other item is associated with the at least one item. The repost content is determined to be associated with the post content. Post feedback data based on the user indication is identified. The post feedback data is associated with the post content, and the post feedback data represents previous user indication. The post feedback data is updated based on the user indication.
US09355075B2	Multi-view graphical user interface for editing a base document with highlighting feature A computationally implemented method includes, but is not limited to: receiving indication of an election of a rules packet, the elected rules packet including one or more rules for selecting one or more selective parts of a base document for selective presentation; and presenting a graphical user interface (GUI) for editing the base document, the GUI including at least a first view for displaying at least a segment of the base document and a second view for displaying at least a segment of the one or more selective parts of the base document selected based on the elected rules packet, the segment of the base document to be displayed through the first view including at least a portion of the one or more selective parts of the base document, and the portion of the one or more selective parts of the base document to be displayed through the first view being highlighted in the first view. In addition to the foregoing, other method aspects are described in the claims, drawings, and text forming a part of the present disclosure.
US09355072B2	Recursive embedding by URL parameterization Methods, systems, and apparatus for performing recursive embedding by URL parameterization are provided. Recursive embedding by URL parameterization may be performed by receiving a display parameter for defining a window display area within a portion of a first document associated with a first application having a first format, and a URL-based identifier specifying a portion of a second document associated with a second application having a second format. The first and second formats are different from each other. A display of the portion of first including the window display area is generated. The specified portion of the second document is displayed within the window display area, and the first and second documents are independently executable with respect to each other.
US09355069B2	Systems and methods for determining the uncertainty in parameters of an energy use model Systems and methods for determining the uncertainty in parameters of a building energy use model are provided. A disclosed method includes receiving an energy use model for a building site. The energy use model includes one or more predictor variables and one or more model parameters. The method further includes calculating a gradient of an output of the energy use model with respect to the model parameters, determining a covariance matrix using the calculated gradient, and using the covariance matrix to identify an uncertainty of the model parameters. The uncertainty of the model parameters may correspond to entries in the covariance matrix.
US09355068B2	Vector multiplication with operand base system conversion and re-conversion A method is described that includes performing the following with an instruction execution pipeline of a semiconductor chip. Multiplying two vectors by: receiving a vector element multiplicand and vector element multiplier expressed in a first base system; converting the vector element multiplicand and vector element multiplier into a second lower base system to form a converted vector element multiplicand and a converted vector element multiplier; multiplying with a first execution unit of the pipeline the converted vector element multiplicand and the converted vector element multiplier to form a multiplication result; accumulating in a register a portion of the multiplication result with a portion of a result of a prior multiplication of operands expressed in the second lower base system; and, converting contents of the register into the first base system.
US09355064B2	Tracking vehicle locations in a parking lot for definitive display on a GUI A computer implemented method for displaying on a map a definitive image of precise locations of multiple mobile objects such as vehicles in a lot. The lot is mapped digitally to display precise locations of sub-areas of different types, such as parking and movement slots and their raw, approximate distances from vehicles are determined from approximate coordinates of vehicles obtained remotely. A data base of vehicle and sub-area types is established and a vehicle placement matrix is determined providing probabilities of respective sub-areas being occupiable by respective vehicles derived from business environment rules based on compatibilities of respective vehicle types with respect sub-area types. Raw, approximate distances of vehicles from sub-areas are divided by the probabilities to provided adjusted distances, sub-areas ranked by least adjusted distances and the respective vehicles placed in their top ranked sub-areas for more accurate display of location on a GUI.
US09355063B2	Parking lot detection using probe data Parking lot (18, 20) locations and geometries are discerned from probe data (22) and integrated with a digital map (12) for use in navigation and other map-related activities. The steps of this invention include: identifying the positions in the probe data (22) where cars are probably parked, detecting the positions of parking lots (18, 20), determining the extension and shape of the detected parking lots (18, 20), and adjusting the parking lots (18, 20) into the road network (14). Optionally, the parking lot (18, 20) can be classified and additional attributes computed. Finally, a topological connection of the parking lot (18, 20) is made to the road network (14) during which entrances (34) and exits (36) are identified.
US09355062B2	Method and system for evaluation of fire suppression systems performance An initial (near-field) spray generated by a sprinkler under study is fully characterized using a laser-supported Shadowgraphy/PTV system. Near-field spray characteristics are established from local measurements, which are mapped in a spherical coordinate system consistent with the kinematics of the spray. A novel data compression scheme is introduced to generate analytical functions describing the sprinkler spray based on the measurements. These analytical functions are useful for initiating the sprinkler spray in computational fluid dynamics (CFD) based spray dispersion and fire suppression modeling. The near-field spray measurements and associated data compression approach are validated by comparing volume density measurements 1 meter below the sprinkler with volume density predictions generated from spray dispersion calculations initiated with the analytical spray functions.
US09355055B1	Network and power connection management The use of asset connectivity verification and switchable asset connectivity activation techniques may reduce or eliminate occurrences of human errors with respect to the improper connection and activation of infrastructure components in a data center. Assert connectivity verification involves the acquisition of identifiers corresponding to infrastructure component interfaces that are coupled to each other, and comparing the identifiers to pairing specifications to verify that the coupling of the infrastructure components comply with pairing specifications. Asset connectivity activation involves determining whether the coupling of a switchable coupler to one or more component interfaces complies with pairing specifications based on the corresponding identifiers of each component, and activating the switchable coupler to enable the flow of data signals and/or power when the coupling of the components meets the pairing specifications.
US09355054B2	Digital calibration-based skew cancellation for long-reach MIPI D-PHY serial links A Mobile Industry Processor Interface (MIPI) physical layer (D-PHY) serial communication link and a method of reducing clock-data skew in a MIPI D-PHY serial communication link include apparatus including a clock transmitting circuit for transmitting a clock signal on a first lane of the MIPI D-PHY serial link, a data transmitting circuit for transmitting a data signal on a second lane of the MIPI D-PHY serial link, a clock receiving circuit for receiving the clock signal on the first lane of the MIPI D-PHY serial link, and a data receiving circuit for receiving the data signal on the second lane of the MIPI D-PHY serial link. The clock transmitting circuit and the data transmitting circuit transmit the clock signal and the data signal in phase during a calibration mode and out of phase during a normal operation mode.
US09355053B2	PCIe SMBus slave address self-selection Embodiments of the invention describe an apparatus, system and method for slave devices to “self-select” their own Inter-Integrated Circuit/System Management Bus (I2C/SMBus) slave addresses upon initialization. Embodiments of the invention describe logic/modules to retrieve a first SMBus slave address included in non-volatile memory for a slave device, wherein said slave device is communicatively coupled to a host system via an SMBus. A first message (e.g., a ping) is transmitted to the first SMBus slave address via the SMBus. If a response to the first message is not received, the first SMBus slave address is selected for the slave device. If a response to the first message is received, the first SMBus slave address is changed by an offset value to determine a second SMBus slave address for transmitting a second message via the SMBus.
US09355051B2	Apparatus, method, and manufacture for using a read preamble to optimize data capture A memory controller is provided. In response to a burst read command that includes a target address, the memory controller provides, to one or more busses, data stored in memory at the target address after dummy clock cycles have occurred. The memory controller also provides a preamble on the bus(ses) during some of the dummy clock cycles. The preamble includes a data training pattern.
US09355044B2	System and method for protecting data stored on a removable data storage device A system for protecting data stored in a removable data storage device includes a personal electronic device, a removable solid state data storage device operatively coupled to the personal electronic device, and a circuit configured to protect data stored in the data storage device in response to detecting impending removal of the data storage device from the personal electronic device.
US09355043B2	Cache replacement method and system A system, computer readable medium and method for managing objects in a cache. The method includes receiving a request for a desired object that is not stored in the cache; determining, based on an admission policy, whether one or more segments of a least popular existing object need to be removed from the cache for admitting one or more segments of the desired object into the cache; removing, when there is no space in the cache for the desired object, the one or more segments of the least popular existing object from the cache based on a replacement policy, wherein the replacement policy includes a caching priority function for determining that the least popular existing object is the least popular object of all objects stored by the cache; and admitting at least one segment of the desired object into the cache.
US09355041B2	Frame buffer access tracking via a sliding window in a unified virtual memory system One embodiment of the present invention is a memory subsystem that includes a sliding window tracker that tracks memory accesses associated with a sliding window of memory page groups. When the sliding window tracker detects an access operation associated with a memory page group within the sliding window, the sliding window tracker sets a reference bit that is associated with the memory page group and is included in a reference vector that represents accesses to the memory page groups within the sliding window. Based on the values of the reference bits, the sliding window tracker causes the selection a memory page in a memory page group that has fallen into disuse from a first memory to a second memory. Because the sliding window tracker tunes the memory pages that are resident in the first memory to reflect memory access patterns, the overall performance of the memory subsystem is improved.
US09355038B2	Cache bank spreading for compression algorithms Aspects include computing devices, systems, and methods for implementing a cache memory access requests for compressed data using cache bank spreading. In an aspect, cache bank spreading may include determining whether the compressed data of the cache memory access fits on a single cache bank. In response to determining that the compressed data fits on a single cache bank, a cache bank spreading value may be calculated to replace/reinstate bank selection bits of the physical address for a cache memory of the cache memory access request that may be cleared during data compression. A cache bank spreading address in the physical space of the cache memory may include the physical address of the cache memory access request plus the reinstated bank selection bits. The cache bank spreading address may be used to read compressed data from or write compressed data to the cache memory device.
US09355034B2	Removal and optimization of coherence acknowledgement responses in an interconnect According to one general aspect, a method of performing a cache transaction may include transmitting a cache request to a target device. The method may include receiving a cache response that is associated with the cache request. The method may further include completing the cache transaction without transmitting an exclusive cache response acknowledgement message to the target device.
US09355032B2	Supporting multiple types of guests by a hypervisor A system configuration is provided that includes multiple partitions that have differing translation mechanisms associated therewith. For instance, one partition has associated therewith a single level translation mechanism for translating guest virtual addresses to host physical addresses, and another partition has a nested level translation mechanism for translating guest virtual addresses to host physical addresses. The different translation mechanisms and partitions are supported by a single hypervisor. Although the hypervisor is a paravirtualized hypervisor, it provides full virtualization for those partitions using nested level translations.
US09355030B2	Parallel garbage collection implemented in hardware Embodiments of the invention provide a method and system for dynamic memory management implemented in hardware. In an embodiment, the method comprises storing objects in a plurality of heaps, and operating a hardware garbage collector to free heap space. The hardware garbage collector traverses the heaps and marks selected objects, uses the marks to identify a plurality of the objects, and frees the identified objects. In an embodiment, the method comprises storing objects in a heap, each of at least some of the objects including a multitude of pointers; and operating a hardware garbage collector to free heap space. The hardware garbage collector traverses the heap, using the pointers of some of the objects to identify others of the objects; processes the objects to mark selected objects; and uses the marks to identify a group of the objects, and frees the identified objects.
US09355019B2	Method for test case reduction based on program behavior slices The present invention provides a method of test cases reduction based on program behavior slices. In the present invention, during a static analysis stage, analyzing a control flow and an information flow of a program according to input program codes, extracting control dependence and data dependence of the program; calculating potential dependence of the program according to the control dependence and the data dependence of the program; on the basis of the control dependence, the data dependence and the potential dependence, constructing combination dependence of the program; during a dynamic execution stage, according to an execution path and the dependence relation, calculating program behavior slices covered by the path and program behavior slices uncovered by the path, and guiding symbolic execution to generate a path capable of covering new program slices according to the uncovered program behavior slices.
US09355017B2	Automated error checking system for a software application and method therefor A test system for providing automatic testing of an application on a plurality of devices, the system including an input/output device for communicating with the plurality of devices, a processor and a memory that stores instructions which cause the processor to install an application on a device, monitor the device as it performs a series of steps, and record the results of the series of steps in a log.
US09355016B2	Automated regression testing for software applications Regression testing of an application may gather performance tests for multiple functions within an application and determine when performance changes from one version of the application to another. The analysis may be further broken down by input sequences that may be processed by various functions. A detailed regression analysis may be presented as a heat map or other visualizations. A regression testing system may be launched during a build process by automatically launching a set of performance tests against an application. In many cases, the application may be executed in a system with a known or consistent performance capabilities. The application may be executed and tested in a new version and at least one prior version on the same hardware and software execution environment, so that results may be normalized from one execution run to another. A regression testing system may be deployed as a paid-for service that may integrate into a source code repository.
US09355008B2	Performance analyzer for self-tuning system controller A performance analyzer for a self-tuning system controller, and a method for performance analysis. A range of values for a control parameter of a system controller for a system is split into a plurality of sub-ranges, need is determined to obtain a data point for a sub-range of the plurality of sub-ranges based on a criteria, wherein said sub-range is adjacent to a sub-range having a best performance value that identifies a best performance for the system, the control parameter is set to a value to generate the data point for the adjacent sub-range; and the control parameter set to a value for system performance, based on a search range determined from a window of data points that includes the generated data point.
US09355007B1	Identifying abnormal hosts using cluster processing A method and apparatus for identifying abnormal clusters are disclosed. In the method and apparatus, host activity data is received and cluster processing is performed on the host activity data of the plurality of hosts to determine the presence of any abnormal clusters of abnormal host activity data. The cluster processing results in a yielded clusters that are then compared with baseline clusters to identify the abnormal clusters.
US09355005B2	Detection apparatus and detection method A detection apparatus includes first and second calculating units and a storing unit. The first calculating unit calculates, when a configuration of a system is changed or the like and a combination of messages occurs, a ratio of the number of occurrences of an event at time points corresponding to a time of occurrence of the combination to the number of occurrences of the combination. The second calculating unit calculates an indicator to determine whether the combination of the messages is used to detect occurrence of the event or to detect a sign of occurrence of the event, based on the ratio and on the number of occurrences of the event. When the indicator indicates that a condition is satisfied, the storing unit stores the combination of the messages as a combination used to detect occurrence of the event or to detect the sign of occurrence of the event.
US09355003B2	Capturing trace information using annotated trace output A computer identifies a first trace output, generated during a first execution of a first program, that is annotated with an indication of a first pattern of logged events and one or more second programs that identify additional logged events. The computer identifies the first pattern of logged events in a second trace output, which is generated during a second execution of the first program. The computer executes the one or more second programs to gather one or more additional logged events that are discoverable during the second execution of the first program, wherein the one or more additional logged events are not included in the first trace output.
US09355001B1	Method and apparatus for selecting an operating frequency of a central processing unit, based on determining a millions of instruction per second (MIPS) value associated with the central processing unit Embodiments of the present invention provide a method that comprises, within a sample window, determining an active time of a central processing unit (CPU) at an operating frequency. If there are any different operating frequencies within the sample window, the method further comprises determining active times of the CPU at the different operating frequencies within the sample window and, based upon the active times for the operating frequencies within the sample window, calculating a millions of instructions per second (MIPS) value for the sample window. The method further comprises performing a comparison of the MIPS value to a threshold value and, based upon the comparison of the MIPS value to the threshold value, setting an operating frequency of the CPU for a next sample window.
US09354995B2	Method for controlling operations of server cluster A server cluster has a plurality of application servers. During failover of a failed node of the application servers, right to use of internet protocol (IP) address of the failed node is transferred to a surviving node of the server cluster according to a failed-link index of the failed node, the total number of surviving nodes of the server cluster, and successful link indexes of the surviving nodes.
US09354993B2	System and method to reduce service disruption in a shared infrastructure node environment A method of reducing downtime in a node environment is disclosed. The method includes identifying an originating system board of a plurality of system boards that requires service where the originating system board includes a node operating on a processor. The method further includes identifying a target system board of the plurality of system boards where the target system board includes a target processor. The method further includes transferring operation of the node to the target processor before the originating system board is serviced, and operating the node on the target processor.
US09354992B2	Interconnect path failover One or more techniques and/or systems are provided for interconnect failover between a primary storage controller and a secondary storage controller. The secondary storage controller may be configured as a backup or failover storage controller for the primary storage controller in the event the primary storage controller fails. Data and/or metadata describing the data (e.g., data and/or metadata stored within a write cache) may be mirrored from the primary storage controller to the secondary storage controller over one or more interconnect paths. Responsive to identifying a failover trigger for a failed interconnect path, the secondary storage controller is instructed to fence (e.g., block) I/O operations from the failed interconnect path. Streams of data and/or metadata that were affected by the failure may be instructed to transmit such data and/or metadata over one or more non-failed interconnect paths to the secondary storage controller during failover of the failed interconnect path.
US09354991B2	Locally generated simple erasure codes An “erasure code” is an encoding of multiple different sets of data. Redundant copies of data are maintained in such erasure codes, thereby utilizing only a fraction of the storage capacity of unencoded copies. Erasure codes are efficiently generated, with a minimum of processing resources utilizing XOR functionality. Additionally, erasure codes are generated from local data, thereby avoiding the consumption of network resources. At least one unencoded copy of a set of data is maintained, while the remaining, redundant copies are encoded into erasure codes. Requests for data are provided from the unencoded copy. Should it fail, a new unencoded copy can be generated by another computing device having access to both an erasure code as well as unencoded copies of the other data that was also pressed into that erasure code. Multiple failures can be survived through recursive application of such a decoding of encoded data.
US09354989B1	Region based admission/eviction control in hybrid aggregates Region based admission and eviction control can be used for managing resources (e.g., caching resources) shared by competing workloads with different SLOs in hybrid aggregates. A “region” or “phase” refers to different incoming loads of a workload (e.g., different working set sizes, different intensities of the workload, etc.). These regions can be identified and then utilized along with other factors (e.g., incoming loads of other workloads, maximum cache allocation size, service level objectives, and others factors/parameters) in managing cache storage resources.
US09354988B2	Allocation strategies for data storage applications A physical storage volume can be partitioned into a plurality of master blocks of an equal master block size. Each master block of the plurality of master blocks can be allocated for storage of a single storage page size of a plurality of predefined storage page sizes provided for storage of data by a data storage application. A received page size can be determined for a storage page designated by the data storage application for storage on the physical storage volume, and the storage page can be stored in a free block of a master block of the plurality of master blocks having the single page size equivalent to the received page size. Related methods, systems, and articles of manufacture are also disclosed.
US09354980B2	Dispersed storage having snapshot clones and methods for use therewith A directory file includes a plurality of entries, wherein an entry of the plurality of entries includes a file or directory name field, and a snapshot list field that includes a snapshot list. A clone snapshot identifier (ID) is determined for a data file. The directory file is updated to produce an updated directory file, wherein the updating includes updating the snapshot list field associated with the data file to include the clone snapshot ID in the snapshot list.
US09354976B2	Locating previous versions of an object in a storage cluster Technology for accessing previous versions of data objects within a storage cluster including multiple storage volumes under a common namespace is disclosed herein. In some embodiments, the network storage cluster having multiple cooperative storage nodes receives a namespace identifier for a previous version of a data object. The namespace identifier includes a namespace path containing a volume junction and a time indicator indicating a point in time when the previous version of the data object existed. The network storage cluster identifies a storage volume within the network storage cluster using the volume junction. The volume junction points to a root directory of a file system of the storage volume. The network storage cluster locates, based on the namespace path, the previous version of the data object within a snapshot copy of the storage volume, wherein the snapshot copy is identified by the time indicator.
US09354975B2	Load balancing on disks in raid based on linear block codes An improved technique involves assigning a different generator matrix to each data stripe of the redundant disk array such that all of the different generator matrices represent the same code. For example, when a k×n generator matrix G represents a linear code C, k being the block length and n the code length, then for any invertible k×k matrix P, the matrix G′=PG is also a generator that represents C. When C is a systematic code, then G consists of a k×k identity matrix representing payload data concatenated with a k×(n−k) parity matrix representing parity data. Certain matrices P represent row operations on G, meaning that the matrix G′ may have the columns of the identity matrix in G to different locations in G′.
US09354970B2	Method and apparatus for encoding erroneous data in an error correction code protected memory A method and device are described for encoding erroneous data in an error correction code (ECC) protected memory. In one embodiment, incoming data including a plurality of data symbols and a data integrity marker is received. At least one extra symbol is used to mark the incoming data as error-free data or erroneous data (i.e., poison) based on the data integrity marker. ECC may be created to protect the data symbols. The ECC may include a plurality of check symbols, a plurality of unused symbols and the at least one extra symbol. In another embodiment, an error marker may be propagated from a single ECC word to all ECC words of data block (e.g., a cache line, a page, and the like) to prevent errors due to corruption of the error marker caused by faulty memory in the erroneous ECC word.
US09354969B2	Memory controller, method of operating the same, and system including the same A method of processing data using a memory controller includes determining at least one cell state to which each of a plurality of multi-level cells can be changed to based on a current cell state of each multi-level cell, where each multi-level cell includes a plurality of data pages; determining one of the data pages as having a stuck bit when a value of the data page has a single mapping value based on mapping values mapped to the at least one cell state and generating stuck bit data regarding the stuck bit; and encoding write data to be stored in the multi-level cells based on the stuck bit data.
US09354968B2	Systems and methods for data quality control and cleansing A method for detecting and cleansing suspect building automation system data is shown and described. The method includes using processing electronics to automatically determine which of a plurality of error detectors and which of a plurality of data cleansers to use with building automation system data. The method further includes using processing electronics to automatically detect errors in the data and cleanse the data using a subset of the error detectors and a subset of the cleansers.
US09354966B2	Creating environmental snapshots of storage device failure events A storage device failure in a computer storage system can be analyzed by the storage system by examining relevant information about the storage device and its environment. Information about the storage device is collected in real-time and stored; this is an on-going process such that some information is continuously available. The information can include information relating to the storage device, such as input/output related information, and information relating to a storage shelf where the storage device is located, such as a status of adjacent storage devices on the shelf. All of the relevant information is analyzed to determine a reason for the storage device failure. Optionally, additional information may be collected and analyzed by the storage system to help determine the reason for the storage device failure. The analysis and supporting information can be stored in a log and/or presented to a storage system administrator to view.
US09354953B2	System integrator and system integration method with reliability optimized integrated circuit chip selection Disclosed is a computer system for system integration, wherein chip selection for a specific system is performance and reliability optimized and, thereby cost optimized. In the system, a memory stores a chip-level performance specification and a chip-level reliability specifications, each defined for a specific integrated circuit chip that is to be incorporated into a specific system. The memory also stores an inventory that references manufactured instances of the specific integrated circuit chip sorted into bins, which are associated with different performance process windows and which are assigned different reliability levels. A processor uses the inventory to select an instance of the specific integrated circuit chip from one of the bins for actual incorporation into the specific system and does so such that the chip-level performance specification and the chip-level reliability specification are met. Also disclosed are a method and a computer program product that can similarly perform system integration.
US09354950B1	Method and apparatus for accessing a data source from a client using a driver Certain aspects of the present disclosure relate to a technique to access a data source from a client using a driver. A data source name (DSN) is provided to connect to the data source using the driver. The driver is used to interface between the client and an implementation of a driver interface to access the data source based on the DSN.
US09354949B2	Runtime emulating static thread local storage of portable executable software code A computer readable storage medium containing a program which, when executed by a processor, performs an operation of emulating static thread local storage of an executable software code at runtime, is disclosed. The operation includes executing the executable software code within a process memory space. During the execution of the executable software code, an occurrence of an event that is associated with a thread create operation is monitored. When the monitored event occurs, a thread data block duplicate is established within the process memory space and associated with a thread created by the thread create operation. The thread data block duplicate is configured to be accessed by executing a thread local storage callback function.
US09354948B2	Data models containing host language embedded constraints Techniques are described for expressing a constraint in a host language. A constraint can be defined in the host language as an event handler. The event handler can be registered to a built-in event associated with an object of the database that the constraint is intended to validate. When the object triggers the built-in event, the event handler is called to execute the constraint. Exemplary built-in events include onSave (trigger the event when the object is saved), onValidate (trigger the event when an explicit call to validate the object is detected), onInsert (trigger the event when the object is inserted), onUpdate (trigger the event when the object is updated), and onCheckBeforeSave (trigger the event when the object is checked prior to saving).
US09354947B2	Linking a function with dual entry points A method for a static linker to resolve a function call can include identifying, during link time, a first function call of a calling function to a callee function, determining whether the callee function is a local function, determining whether the callee function has a plurality of entry points, and whether an entry point of the plurality of entry points is a local entry point. The method can include resolving, during link time, the first function call to enter the local entry point, which can include replacing a symbol for the function in the first function call with an address of the local entry point during link time. If the callee function cannot be determined to be a local function, the method can include generating stub code and directing the first function call to enter the stub code during link time.
US09354944B2	Mapping processing logic having data-parallel threads across processors A method for executing a plurality of data-parallel threads of a processing logic on a processor core includes grouping the plurality of data-parallel threads into one or more workgroups, associating a first workgroup from the one or more workgroups with an operating system thread on the processor core, and configuring threads from the first workgroup as user-level threads within the operating system thread. In an example, a method enables the execution of GPU-kernels that has been previously configured for a GPU, to execute on a CPU such as a multi-core CPU. The mapping of the numerous data-parallel threads to the CPU is done in such a manner as to reduce the number of costly operating system threads instantiated on the CPU, and to enable efficient debugging.
US09354943B2	Power management for multi-core processing systems According to an aspect, power management of a multi-core processing system includes determining workload characteristics in the multi-core processing system. A power adjustment scenario is identified based on the workload characteristics. A predetermined actuation order for at least two power adjustment actuators is identified based on the power adjustment scenario. Based on the predetermined actuation order, it is determined whether there is an adequate adjustment capacity for a power adjustment action associated with one of the at least two power adjustment actuators. The power adjustment action is initiated based on the predetermined actuation order and determining that the adequate adjustment capacity is available.
US09354939B2	Generating customized build options for cloud deployment matching usage profile against cloud infrastructure options A decision system for providing customized application build options to users of a cloud computing environment. The decision system can receive user usage history data and determine a customized set of application resources based on the usage history data. Information about the customized set of application resources can then be supplied to the user.
US09354935B2	Work processing apparatus for scheduling work, control apparatus for scheduling activation, and work scheduling method in a symmetric multi-processing environment A work scheduling technology in a symmetric multi-processing (SMP) environment is provided. A work scheduling function for a SMP environment is implemented in a work processing apparatus, thereby reducing the scheduling overhead, and enhancing the efficiency in use of CPU resources and improving the CPU performance.
US09354934B2	Partitioned shared processor interrupt-intensive task segregator Interrupt-intensive and interrupt-driven processes are managed among a plurality of virtual processors, wherein each virtual processor is associated with a physical processor, wherein each physical processor may be associated with a plurality of virtual processors, and wherein each virtual processor is tasked to execute one or more of the processes, by determining which of a plurality of the processes executing among a plurality of virtual processors are being or have been driven by at least a minimum count of interrupts over a period of operational time; selecting a subset of the plurality of virtual processors to form a sequestration pool; migrating the interrupt-intensive processes on to the sequestration pool of virtual processors; and commanding by a computer a bias in delivery or routing of the interrupts to the sequestration pool of virtual processors.
US09354933B2	Remote direct memory access adapter state migration in a virtual environment In an embodiment of the present invention, a method includes partitioning a plurality of remote direct memory access context objects among a plurality of virtual functions, establishing a remote direct memory access connection between a first of the plurality of virtual functions, and migrating the remote direct memory access connection from the first of the plurality of virtual functions to a second of the plurality of virtual functions without disconnecting from the remote peer.
US09354932B2	Dynamically allocated thread-local storage Dynamically allocated thread storage in a computing device is disclosed. The dynamically allocated thread storage is configured to work with a process including two or more threads. Each thread includes a statically allocated thread-local slot configured to store a table. Each table is configured to include a table slot corresponding with a dynamically allocated thread-local value. A dynamically allocated thread-local instance corresponds with the table slot.
US09354931B1	Method, server and computer-readable recording medium for managing size of thread pool dynamically A method for managing a size of a thread pool dynamically is disclosed. The method includes the steps of: (a) a processor increasing a maximum thread size if the number of threads included in the thread pool is close to the maximum thread size; and (b) the processor comparing a size of a task queue before the increase of the maximum thread size with that after the increase thereof by referring to information on the size of the task queue, and increasing the maximum thread size again if the size of the task queue after the increase thereof is larger than, or equal to, that before the increase thereof.
US09354929B2	Shut down real time domain when last real time process terminates on a core A host system includes a plurality of cores and is designed such that one real-time process and one core-local timer is run on each of the plurality of cores.
US09354928B1	User facing load balancing via virtual machine synchronization A native environment on a local device and a virtual environment on a server device linked to the native device over a network can concurrently execute. The concurrently executing can share state information to keep activities between both environments substantially time-synched. The native environment can be a user-machine interactive environment of a machine-to-user interactive interface. The native environment can perform stand-alone operation without appreciable end-user experience degradation. A process in the native environment requiring an excessive quantity of processing cycles can be detected. The native environment can not perform the processing using resources of the native environment. The virtual environment can perform the process and synchronize the result to the native environment, thereby permitting the native environment to continue to function as if the process was performed by the native environment.
US09354926B2	Processor management via thread status Various systems, processes, and products may be used to manage a processor. In particular implementations, managing a processor may include the ability to determine whether a thread is pausing for a short period of time and place a wait event for the thread in a queue based on a short thread pause occurring. Managing a processor may also include the ability to activate a delay thread that determines whether a wait time associated with the pause has expired and remove the wait event from the queue based on the wait time having expired.
US09354925B2	Transaction abort processing A transaction executing within a computing environment ends prior to completion; i.e., execution is aborted. Pursuant to aborting execution, a hardware transactional execution CPU mode is exited, and one or more of the following is performed: restoring selected registers; committing nontransactional stores on abort; branching to a transaction abort program status word specified location; setting a condition code and/or abort code; and/or preserving diagnostic information.
US09354922B2	Metadata-driven workflows and integration with genomic data processing systems and techniques Systems, methods and computer program products configured to provide and perform metadata-based workflow management are disclosed. The inventive subject matter includes a computer readable storage medium having computer readable program instructions embodied therewith. The computer readable program instructions are configured to: initiate a workflow configured to process data; associate the data with metadata; and drive at least a portion of the workflow based on at least some of the metadata. The metadata include anchoring metadata; common metadata; and custom metadata. Inventive subject matter also encompasses a method for managing genomic data processing workflows using metadata includes: initiating a workflow; receiving a request to manage the workflow using metadata comprising: anchoring metadata, common metadata, and custom metadata, associating the metadata with the data; and driving at least a portion of the workflow based on the metadata. The workflow involves genomic analyzes.
US09354916B2	Detection of guest disk cache A virtual machine disk page detector running on a computing device detects guest disk cache usage. The detector detects a request from a virtual operating system to read an object into a virtual memory page from a virtual disk, maintains a record of a page identifier and a corresponding virtual disk address in a guest cache data structure, and modifies a protection identifier of the virtual memory page to indicate that the virtual memory page is protected.
US09354915B2	Method and apparatus of redundant path validation before provisioning Exemplary embodiments of the invention provide a technique to validate physical cabling and logical path before provisioning volume. In accordance with an aspect, a computer comprises a memory storing software and a processor executing the software. The software is operable to: identify first server port and second server port forming redundant ports of a server and first storage port and second storage port forming redundant ports of a storage system; and check whether a redundant relationship is formed by at least one of (i) a physical connection between the first server port and the first storage port and a physical connection between the second server port and the second storage port, or (ii) a logical connection between the first server port and the first storage port and a logical connection between the second server port and the second storage port.
US09354908B2	Instantly restoring virtual machines by providing read/write access to virtual disk before the virtual disk is completely restored A computer-implemented method for instantly restoring virtual machines in high input/output load environments may include (1) identifying a hypervisor that is configurable to maintain simultaneous connections to multiple datastores of a network-attached-storage system, (2) receiving a request to activate a new virtual machine on the hypervisor, (3) determining a usage of at least one connection from the hypervisor to at least one datastore of the network-attached-storage system, and (4) selecting, based on the usage of the connection, a designated connection from the hypervisor to a designated datastore of the network-attached storage system for use by the new virtual machine to store data on the network-attached-storage system. Various other methods, systems, and computer-readable media are also disclosed.
US09354903B2	Control method and electronic device A control method and an electronic device are disclosed in the application. The control method is applied to an electronic device including a CPU. The method includes: obtaining a current state of the electronic device; judging whether the current state is a first or a second state; generating a first control instruction in the case that the current state is the first state, or generating a second control instruction in the case that the current state is the second state; performing the first control instruction to control the operating frequency of the CPU within the first maximum operating frequency or performing the second control instruction to control the operating frequency of the CPU within the second maximum operating frequency. Enabling to regulate the maximum operating frequency of the CPU adaptively based on the current state of the electronic device.
US09354902B2	Comparing system engram with product engram to determine compatibility of product with system A system engram encoding an existing configuration of a target system is received. The existing configuration includes one or more of hardware and software of the target system. The system engram is originally acquired by a first processing device and is received by a second processing device. The second processing device compares the system engram with a product engram encoding a required configuration of the target system for a product to be compatibly installed in relation to the target system. The required configuration includes one or more of required hardware and required software within the target system for the product to be compatibly installed in relation to the target system. The second processing device can output, as compatibility information of the product with the target system, results of comparison of the system engram with the product engram.

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