最新美国发明专利
Document Document Title
US08023323B2 Non-volatile memory device having monitoring memory cell and related method of driving using variable read voltage
A non-volatile memory device and related method of driving data are disclosed. The non-volatile memory device includes an array of multi level cells and a monitoring memory cell. The method of driving including performing a preliminary read operation with respect to a monitoring memory cell using a first read voltage, determining whether data initially stored in the monitoring memory cell is identical with data read from the monitoring memory cell during the preliminary read operation, and setting a main read voltage to a level different from the level of the first read voltage when the data initially stored in the monitoring memory cell is not identical with the data read from the monitoring memory cell in relation to the first read voltage.
US08023320B2 Resistance-change random access memory device including memory cells connected to discharge elements
A resistance-change random access memory device includes a resistance-change memory cell array having a plurality of resistance-change memory cells, where a plurality of word lines are connected to respective first terminals of the plurality of resistance-change memory cells. A plurality of bit lines are disposed perpendicular to the word lines and connected to respective second terminals of the plurality of resistance-change memory cells. The device also includes a plurality of discharge elements that are capable of connecting or disconnecting respective bit lines from a discharge voltage, where the discharge elements connect the respective bit lines to the discharge voltage before write and read operations.
US08023313B2 Resistance change memory device
A resistance change memory device includes a cell array having multiple layers of mats laminated thereon, each of the mats having word lines and bit lines intersecting each other as well as resistance change type memory cells arranged at intersections thereof, each of the mats further having therein a reference cell and a reference bit line connected to the reference cell, the reference cell set to a state of a certain resistance value; a selection circuit configured to select a word line in each mat of the cell array, and select a bit line intersecting a selected word line and the reference bit line at the same time; and a sense amplifier configured to sense data by comparing respective cell currents of a selected memory cell on the selected bit line and the reference cell on the reference bit line.
US08023311B2 Resistive memory devices including selected reference memory cells operating responsive to read operations
A Resistance based Random Access Memory (ReRAM) can include a sense amplifier circuit that includes a first input coupled to a bit line of a reference cell in a first block of the ReRAM responsive to a read operation to a second block.
US08023310B2 Nonvolatile memory cell including carbon storage element formed on a silicide layer
A nonvolatile memory cell includes a storage element, the storage element comprising a carbon material, a steering element located in series with the storage element, and a metal silicide layer located adjacent to the carbon material. A method of making a device includes forming a metal silicide over a silicon layer, forming a carbon layer over the metal silicide layer, forming a barrier layer over the carbon layer, and patterning the carbon layer, the metal silicide layer, and the silicon layer to form an array of pillars.
US08023309B2 Semiconductor memory device, method for fabricating the same and semiconductor switching device
A first electrode is formed on a stacked-layer film, which is formed of a ferroelectric layer and a semiconductor layer, at the ferroelectric layer and a plurality of second electrodes are formed on the stacked-layer film at the semiconductor layer side. Each of parts of the semiconductor layer located in regions in which the second electrodes are formed functions as a resistance modulation element (memory) using the polarization assist effect of the ferroelectric layer. Information (a low resistance state or a high resistance state) held in a memory is read by detecting a value of a current flowing in each part of the semiconductor layer. Information is written in a memory by inverting a polarization of the ferroelectric layer.
US08023304B2 Memory module, method and memory system having the memory module
The memory module includes a plurality of memory devices, a first connector and a second connector. The first connector is disposed at a first position on the memory module. The first connector is configured to carry low-speed signals for the memory devices. The second connector is disposed at a second position on the memory module, different from the first position. The second connector is configured to carry high-speed signals for at least one of the memory devices. The high-speed signals are a higher speed form of signaling than the low-speed signals. The memory system may include at least one slot electrically connected to a chip set and at least one memory module electrically connected to the slot via the first connector. A transmission line such as a fiber optic cable electrically connects the second connector and the chip set.
US08023303B2 Semiconductor memory device and memory access method
A semiconductor memory device includes: first and second memory mats; first and second local input output lines coupled to the first memory mat via a first amplifier circuit; third and fourth local input output lines different from the first and second local input output lines, third and fourth local input output lines coupled to the second memory mat via a second amplifier circuit; a third amplifier circuit coupled between the first local input output line and a first main input output line; a fourth amplifier circuit coupled between the third local input output line and a second main input output line different from the first main input output line; and a first switch coupled between the second and third local input output lines and connecting the second local input output line to the fourth amplifier circuit when the first memory mat is activated and the second memory mat is not activated.
US08023299B1 Content addressable memory device having spin torque transfer memory cells
A CAM device includes an array of CAM cells each having a spin torque transfer (STT) storage cell to store a data bit. Each STT storage cell includes a first magnetic tunnel junction (MTJ) element coupled between a first input node and an output node of the CAM cell, a second MTJ element coupled between a second input node and the output node of the CAM cell, and a first match transistor coupled between the match line and ground potential and having a gate coupled to the output node. The logic state of the data bit is represented by the relative resistances of the first and second MTJ elements.
US08023293B2 On-die anti-resonance structure for integrated circuit
A structure and method for reducing the effects of chip-package resonance in an integrated circuit assembly is described. A series RLC circuit is employed to reduce the output impedance of the power delivery system at the resonance frequency.
US08023289B2 Offline synchronous rectifier with causal circuit for resonant switching power converter
A synchronous rectifier of a resonant switching power converter is provided to improve efficiency. The synchronous rectifier includes a power transistor and a diode connected to a transformer and an output of the resonant switching power converter for ratifications. A controller generates a drive signal to control the power transistor in response to an on signal and an off signal. A causal circuit is developed to generate the off signal in accordance with the on signal. The on signal is enabled once the diode is forward biased. The on signal is coupled to enable the drive signal for switching on the power transistor. The off signal is coupled to disable the drive signal for switching off the power transistor. The off signal is enabled before the on signal is disabled.
US08023288B2 Inverter for grounded direct current source, more specifically for a photovoltaic generator
An inverter (1) for a grounded direct voltage source, in particular for a photovoltaic generator (2), a battery or a fuel cell, for converting the direct voltage into an alternative voltage with a DC-DC converter (3) and a pulse inverter that is supplied by said DC-DC converter (3), said DC-DC converter (3) being configured to be an oscillating circuit inverter and comprising a series resonant oscillating circuit, said DC-DC converter (3), which is configured to be an oscillating circuit inverter, being configured to be a series-compensated oscillating circuit inverter with a choke (L1) and a series-mounted capacitor array consisting of two or several oscillating circuit capacitors, a rectifier bridge branch including 2 diodes (D3, D4; D5, D6, . . . ), being connected to each of the partial oscillating circuit capacitors, said rectifier bridge branch being connected with its positive or its negative pole to output side intermediate circuit capacitors which are preferably connected in series so that said DC-DC converter (3) delivers at least two bipolar output voltages and is combined with the pulse inverter (4) with a divided voltage intermediate circuit that is supplied from the oscillating circuit inverter.
US08023284B2 Display modules and methods of fixing flexible circuit boards therein
An assembly structure of a membrane and a print circuit board (PCB). The assembly structure comprises a membrane, a print circuit board, a cover and bolts. A curved protrusion formed on the cover makes the golden fingers of the membrane and the PCB overlap completely when the membrane and the PCB are assembled by the bolts. Electrical contact between the membrane and the PCB is thus reliable and stable. The assemble cost is lowered, and an easy assemble method is provided.
US08023282B2 Hybrid structure of multi-layer substrates and manufacture method thereof
A hybrid structure of multi-layer substrates comprises a first multi-layer substrate and a second multi-layer substrate. The first multi-layer substrate stacks up first metal layers, first dielectric layers alternately and has VIAs. A border district of a first metal layer connects with a border district of the corresponding first dielectric layer. The border districts are separated from adjacent first metal layers and adjacent first dielectric layers. The second multi-layer substrate stacks up second metal layers and second dielectric layers alternately. A border district of a second metal layer connects with a border district of the corresponding second dielectric layer. The border districts are separated from adjacent second metal layers and adjacent second dielectric layers. The VIAs are located at the border districts of the first dielectric layers and each VIA has electric conductor therein to connect one first metal layer with one second metal layer.
US08023277B2 Electronic component integrated module
The electronic component integrated module includes a wiring board; an electronic component provided on the wiring board; solder for electrically connecting the electronic component onto the wiring substrate; and an encapsulating resin for encapsulating the electronic component and the solder. The average linear thermal expansion coefficient α of the encapsulating resin, which is calculated by using the glass transition temperature of the encapsulating resin, a linear thermal expansion coefficient α1 obtained at a temperature lower than the glass transition temperature, a linear thermal expansion coefficient α2 obtained at a temperature exceeding the glass transition temperature, room temperature, and a peak temperature of reflow packaging of the electronic component integrated module, is not less than 17×10−6/° C. and not more than 110×10−6/° C.
US08023274B2 System for increasing isolation boundary withstand voltage
Insulating ribs are formed into one or more portions of a housing that encloses circuitry of an electrical device. Components mounted on a board are separated according to whether they are related to a primary side of a power transformer or a secondary side. Primary related components are typically mounted on the primary side of an isolation slot formed into a circuit board and components related to the secondary are mounted on the other side. The insulating ribs are strategically placed to protrude through the slots when circuit board is mounted to the housing portion. Thus, when the housing portion is joined to another housing portion, which also may include insulating ribs strategically placed, the ribs increase the breakdown voltage of the boundary.
US08023273B2 Electric device having a plastic plug part arranged on a circuit support
Disclosed is an electrical device, in particular a control unit for a motor vehicle, comprising a plate-shaped circuit support fixed on a metallic base plate of the housing, on which a plastic plug part s fixed on a side facing away from the metallic base plate, characterized in that fixing means which are pivot-shaped and protrude from the base plate, are provided for the common mounting of the plastic plug part, the circuit support and the metallic base plate of the housing, that said fixing means are guided through corresponding recesses in the circuit support and in the plastic plug part, that a deformation is produced at each inserted end and that each deformation is supported y a supporting part on said plastic plug part.
US08023270B2 Optoelectronic transceiver assembly and release mechanism employed therein
An optoelectronic transceiver module includes a cage, a transceiver module, and a release mechanism. The release mechanism includes a latch and a trigger. The latch pivotally attaches to the transceiver module with a first pivot. The latch includes a latch block projecting from a first end of the latch operable to be received in the cage. The trigger pivotally attaches to a second end of the latch with a second pivot. The trigger includes a cam mechanism around the second pivot. When the transceiver module is received in the cage, the first end of the latch separates from the transceiver module. When the trigger rotates about the second pivot, the cam mechanism drives the second end of the latch apart from the transceiver module, and the first end of the latch moves correspondingly toward the transceiver module and the latch block withdraws from the cage.
US08023267B2 Avionics chassis
An avionics chassis comprises a housing having opposing walls, a pair of spaced card rails with one rail mounted to each of the opposing walls where each rail has a channel to define an effective slot between the rails, a circuit card assembly comprising a PCB and a thermal plane in overlying relationship with the PCB, with the PCB defining a first primary plane, and the thermal plane defining a second primary plane and the spatial relationship between them is such that the planes are located within the slot when the circuit card assembly is mounted to the card rails and the thermal plane is conductively coupled to a rail to form a first conductive path from the thermal plane to one of the walls and the PCB is conductively coupled to a rail to form a second conductive path from the PCB to one of the walls.
US08023266B2 AC photovoltaic module and inverter assembly
An AC photovoltaic module includes a DC photovoltaic module for converting solar energy to DC electrical power, and an inverter for converting DC electrical power to AC electrical power, the inverter being adapted for connection to a frame portion of the module and being sized and configured, and provided with arrangements of electrical components thereof, to dispense heat from the inverter, whereby to prolong operational life and reliability of the inverter.
US08023264B2 Battery cover latch mechanism and portable electronic device using same
A battery cover latch mechanism (10) used in portable electronic device (100) is described including a cover member (113), a housing member (111), a latch member (1137), a pressing member (15), and a releasing member (17). The latch member is used to latch the cover member to the housing member. The releasing member can be elastic deformed such that the pressing member moves and deforms the releasing member to release the cover member from the housing member.
US08023250B2 Substrate for use in wet capacitors
A porous substrate for use in a wide variety of applications, such as wet capacitors, is provided. The substrate is formed by subjecting a metal substrate to a voltage while in solution to initiate anodic formation of an oxide film. Contrary to conventional anodization processes, however, the newly created oxide quickly breaks down to once again expose the metal surface to the electrolytic solution. This may be accomplished in a variety of ways, such as by raising the voltage of the solution above a critical level known as the “breakdown voltage”, employing a corrosive acid in the solution that dissolves the oxide, etc. Regardless of the mechanism employed, the nearly simultaneous process of oxide growth/breakdown results in the formation of a structure having pores arranged at substantially regular intervals. The resulting structure is highly porous and can exhibit excellent adhesion to electrochemically-active materials and stability in aqueous electrolytes.
US08023247B2 Electrostatic chuck with compliant coat
The present invention is directed to an electrostatic chuck (ESC) with a compliant layer formed from TT-Kote® and a method of forming a clamping plate for an ESC. The ESC comprises a compliant layer having a low friction surface for reducing or eliminating particulates generated from thermal expansion. The method comprises forming a clamping member for a substrate comprising a ceramic material and a ceramic surface, and coating the ceramic surface with a compliant layer comprising an organic silicide or TT-Kote®.
US08023246B2 Electrostatic chuck and method of manufacturing the same
In a method of manufacturing an electrostatic chuck, the method includes: a step of providing an electrostatic chucking portion including an electrode to which a voltage is applied and a film-like insulating layer covering the electrode; a step of bonding an elastomer layer onto the electrostatic chucking portion; a step of bonding a metal base onto the elastomer layer such that recess portions formed on a surface of the metal base face the elastomer layer.
US08023244B2 Energy preserving wireless remote control system
A system for switching on an electrical device includes a startup circuit for an associated electrical device. The electrical device has a main power circuit comprising first and second paths and a main switch for selectively connecting the electrical device with an associated power source. The startup circuit uses a pulse of electromagnetic energy transmitted wirelessly from an associated remote control device to form a third path, whereby power is supplied from the associated power source for actuating the main switch.
US08023243B2 Quick-operating valve
The switching valve of a quick-operating slider system is an electrically operated stop valve. In the case of a required rapid shutoff, the coil (19) must be de-energized in a very short period of time in order to allow the switching valve (18) to open. For this purpose, a voltage-dependent resistor (33) is provided between the voltage source (25) and the coil (19), said resistor (33) having a high resistance below a switching voltage (Us), but a negligibly small resistance above the switching voltage. An auxiliary voltage source (35) is connected in parallel to the coil (19), the voltage of said auxiliary voltage source (35) being opposite to that of the voltage source (25). In this manner, the switching valve is rapidly opened both when a corresponding signal is received and in the case of power failure.
US08023242B2 Circuit arrangement with a relay incorporating one field coil as well as switch contacts
The invention is directed to a circuit array with a relay (K1; K12) incorporating a field coil (E) as well as a switch contact (1a, 1b), said switch contact (1a, 1b) being provided as a switch point between a grid, in particular a mains supply (N), and an inverter (WR) fed by a direct voltage source, in particular by a photovoltaic generator (PVG), said relay (K1; K12) being configured to be a bistable relay.
US08023231B2 Composite shield structure of PMR writer for high track density
Improved writability and a substantial reduction in adjacent track erasure are achieved by incorporating a composite shield structure in a PMR writer. There is a trailing shield formed a certain distance above the top surface of a write pole, a leading shield formed a certain distance below the bottom surface of the write pole, and a partial side shield having a side shield section formed on each side of the write pole. The partial side shield thickness is less than that of the write pole. Each partial side shield section has a side that is parallel to the nearest write pole side and a top surface that is offset from the write pole top surface by 0 to 0.15 microns. A plurality of magnetic connections between two or more shield elements is employed to ensure correct magnetic potential. The large write pole has a flare angle of 45 to 75 degrees.
US08023230B2 Magnetoresistive element including a pair of ferromagnetic layers coupled to a pair of shield layers
A magnetoresistive element includes a pair of shield portions, and an MR stack and a bias magnetic field applying layer that are disposed between the pair of shield portions. The shield portions respectively include single magnetic domain portions. The MR stack includes a pair of ferromagnetic layers magnetically coupled to the pair of single magnetic domain portions, and a spacer layer disposed between the pair of ferromagnetic layers. The MR stack has a front end face, a rear end face and two side surfaces. The magnetoresistive element further includes two flux guide layers disposed between the pair of single magnetic domain portions and respectively adjacent to the two side surfaces of the MR stack. Each of the two flux guide layers has a front end face and a rear end face. The bias magnetic field applying layer has a front end face that faces the rear end face of the MR stack and the respective rear end faces of the two flux guide layers.
US08023229B2 Flexible mounting slider with anti-static structure, head gimbal assembly and magnetic disk drive with the same
A flexible mounting slider with anti-static structure includes a slider body, an anti-static structure and a lead layer. The slider body includes an ABS, a slider back surface opposite to the ABS and a trailing edge connected with the ABS and the slider back surface. The trailing edge forms a plurality of slider pads thereon. The anti-static structure is provided on the slider back surface, which includes an insulation plate formed on the slider back surface, an anti-static plate formed on the insulation plate and a grounding element. In the invention, the anti-static plate comprises an insulation layer and an anti-static layer. The grounding element is electrically contacting with the anti-static layer of the anti-static plate and the slider back surface simultaneously. The lead layer is sandwiched between the insulation plate and the insulation layer of the anti-static plate and electrically connected with the slider pads of the slider body.
US08023228B2 Heat assisted magnetic recording head and method of manufacturing the same
A heat assisted magnetic recording (HAMR) head and manufacturing method are provided. The HAMR head is mounted on a slider having an air-bearing surface (ABS) and includes a substrate; a recording unit formed on the substrate and having a stepped end; a waveguide located in a space formed by the stepped end; and a near field light emission (NFE) pole located adjacent to the recording unit and having an end located on a same plane as the ABS. The method includes forming a cladding layer on a substrate; forming a first metal layer on the cladding layer; etching a part of the first metal layer; forming a core layer on the etched region; forming a refraction part in a part of the core layer; forming a second metal layer the first metal layer and the core layer; and forming a recording unit on the second metal layer.
US08023221B1 Position gain calibration in disk drives
A system including a signal generating module and a position control module. The signal generating module generates position error signals based on servo bursts read from a servo region of a track of a disk drive. The servo bursts are read by a head of the disk drive and include first, second, third, and fourth servo bursts. The position control module generates differences between the position error signals and determines a position of the head relative to the track based on (i) a first difference of the differences and (ii) a second difference of the differences. The first difference is based on the first servo burst and the second servo burst. The second difference is based on (i) the third servo burst and (ii) the first servo burst or the second servo burst and is independent of the fourth servo burst.
US08023219B2 Storage device, head position detection method and control circuit
According to one embodiment, a storage device includes an area demodulator and a head position demodulator. The area demodulator demodulates a first demodulation signal and a second demodulation signal having a phase difference of 90° from a read signal by a head of an area demodulation pattern recorded on a medium. The head position demodulator receives the first demodulation signal and the second demodulation signal, and outputs a phase angle indicating a direction of a vector formed in a phase plane by the first demodulation signal and the second demodulation signal as a head position signal.
US08023218B2 Electric field assisted magnetic recording
We describe a system for electric field assisted magnetic recording where a recordable magnetic medium includes a magnetic recording layer of high coercivity and vertical magnetic anisotropy that is adjacent to an electrostrictive layer which can be placed in a state of stress by a electric field or which is already pre-stressed and which pre-stress can be turned into strain by an electric field. When the magnetic medium is acted on simultaneously by a magnetic writing field and an electric field, the stress in the electrostrictive layer is transferred to a magnetostrictive layer which is the magnetic recording layer by itself or is coupled to the magnetic recording layer, whereupon the magnetic recording layer is made more isotropic and more easily written upon. Residual stresses in the electrostrictive layer can then be removed by an additional electric field of opposite sign to the stress-producing field.
US08023217B1 Method and system for read gate timing control for storage controllers
A device includes a data path configured to transfer data from a read channel device to a host. A read gate delay module is configured to receive a first read gate signal, to output a second read gate signal to the read channel device based on the first read gate signal, and selectively delay a transition of the second read gate signal between an asserted state and a non-asserted state based on a data sector size of a data segment and positive and negative edges of a write clock.
US08023216B1 Calibrating servos
Methods, systems, and apparatus, including computer program products are described for calibrating servos, and in some implementations, calibrating spiral servos for use in self-servo-write SSW processes. In one aspect, a method is provide that includes rotating a machine readable medium, and detecting a spiral on the machine readable medium. Detecting a spiral on the machine readable medium includes detecting magnitudes of the spiral and a timing mark, storing a timestamp from a clock signal that corresponds to the timing mark of the spiral, determining a peak of the spiral from the magnitudes, and locking the clock signal to the peak of the spiral using the timestamp.
US08023208B2 Miniature stacked glass lens module
A miniature stacked glass lens module is disclosed. The miniature stacked glass lens module includes at least one stacked optical glass lens element, a lens holder and other optical element. The stacked optical glass lens element is formed by cutting along alignment notches on a glued and stacked optical glass lens array. Then the stacked optical glass lens element and other optical element are mounted into the lens holder to form a miniature stacked glass lens module. Thereby the precise alignment of the optical axis of the lens in the lens module can be achieved. The manufacturing processes of the lens module can be simplified dramatically and the manufacturing cost is reduced significantly.
US08023207B2 Clutching jig
A clutching jig is adapted to disassemble a lens module which includes a lens socket and a lens component mounted to the lens socket. The clutching jig includes a base and at least two inserting slices. The base defines two opposite lateral surfaces and a bottom surface. A slot passes through the opposite lateral surfaces and the bottom surface to divide the base into a first holding portion and a second holding portion. The bottom surface has a receiving recess at a portion thereof. The inserting slices are removably mounted to the opposite lateral surfaces and beyond the bottom surface. Wherein the inserting slices are inserted between the lens component and the lens socket, and the receiving recess receives the lens component with a circumferential dimension thereof lessened to clutch the lens component when the first holding portion and the second holding portion are urged to approach each other.
US08023202B2 Imaging lens
The present invention is an imaging lens of which optical performance does not deteriorate even in a high temperature environment, various aberrations are well corrected, optical length is short, and back focus is sufficiently secured, the imaging lens comprising a first diaphragm S1, a first junction type compound lens, a second diaphragm S2, and a second junction type compound lens, characterized in that the first diaphragm, the first junction type compound lens, the second diaphragm and the second junction type compound lens are arranged in this sequence from an object side to an image side. The first junction type compound lens comprises a first lens L1, a second lens L2 and a third lens L3, arranged in the sequence from the object side to the image side, and the second junction type compound lens comprises a fourth lens L4, a fifth lens L5 and a sixth lens L6, arranged in this sequence from the object side to the image side. The first lens, the third lens, the fourth lens and the sixth lens are formed of a curable resin material. The second lens and the fifth lens are formed of a high softening temperature optical glass material.
US08023201B2 Retractable lens barrel with high shock resistance
A retractable lens barrel that improves shock resistance without obstructing miniaturization. In the retractable lens barrel, pins formed in the lens barrel are engaged with grooves formed in a cam ring, and the lens barrel is caused to move in a direction of an optical axis by rotation of the cam ring. The pins include a cam pin for moving the lens barrel, and a slip-off preventive pin for preventing the cam pin from slipping off the groove. The grooves include a cam groove with which the cam pin is engaged, and a slip-off preventive groove with which the slip-off preventive pin is engaged. In an area close to a retracted position of the lens barrel, the cam groove and the slip-off preventive groove overlap to be shared grooves with which the cam pin and the slip-off preventive pin are engaged.
US08023194B2 Display apparatus
A display apparatus is provided. The display apparatus includes a front side that is exposed the outside. A refractor or set of refractors is positioned so as to minimize the appearance of a shield member to a viewer, thus causing a non-display region of the display apparatus to appear to be smaller than its actual size, thus increasing a size of an image display region of the display apparatus.
US08023192B2 Lens array, lens unit, led head, exposing unit, image forming apparatus, and image reading apparatus
A lens array forms an erect image of an object. The lens array includes at least one row of lens elements and at least one rib. The lens elements are aligned in a first direction perpendicular to optical axes of the lens elements having an incidence surface and an exit surface. The rib is formed on the lens array and extending in a second direction parallel to the first direction and in a third direction parallel to the optical axes further than the incidence surface and the exit surface. A lens unit includes a shielding member and the lens array assembled to the shielding member. The shielding member includes diaphragms formed therein and aligned in a first direction, and a first engagement portion. The lens array includes a second engagement portion for engaging the first engagement portion to correct deformation of the lens array.
US08023191B2 Printable static interferometric images
Methods of fabricating a static interferometric image device and static interferometric image device formed by the same are disclosed. In one embodiment, a method includes providing a substrate. A plurality of liquid layers are formed over the substrate by an inkjet process such that the layers are lateral to one another. The liquid layers contain a solidifiable material or particles. Then, the plurality of liquid layers are solidified to form a plurality of solid layers. In some embodiments, the substrate includes pre-defined cavities, and the liquid layers are formed in the cavities. In other embodiments, the substrate includes a substantially planar, stepped, or continuously transitioning surface, and the liquid layers are formed on the surface. The inkjet process provides optical fillers or spacers for defining interferometric gaps between absorbers and reflectors in the display device, based at least partially on an image that the display device is designed to display.
US08023189B2 Retardation compensation element and manufacturing method of the same
Two types of layers are simultaneously formed on a substrate and another substrate under the same layer forming condition, the heights of which are equal to a half height of an intended retardation compensation layer. Physical properties of the respective two types of layers formed on the substrates are identical to each other, and if deviations are produced in retardation distribution characteristics for azimuth angles of incident light, these deviations are commonly provided in the respective two types of layers. When one substrate is superposed with the other substrate and these superposed substrates are integrated with each other in order to make a single sheet of retardation compensation element, after one of these substrates is rotated by an angle of 90 degrees with respect to the other substrate, these substrates are stuck to each other by an adhesive agent.
US08023187B1 Cabinet projection screen with automatic push-pull structural function
A cabinet projection screen with an automatic push-pull structural function is provided, which includes a cabinet body (1). A screen push-pull base (13) is disposed on the cabinet body (1) through sliding rails (2, 4, 10, and 11). A scrolling mechanism (6) is disposed inside the cabinet body (1), and includes a scrolling shaft (61), a scrolling motor (8), a tape (62), and a telescopic device (7). One end of the tape (62) is fixed on the scrolling shaft (61), and the other end thereof is fixed on the screen push-pull base (13). When the scrolling motor (8) drives the scrolling shaft (61) to rotate, the scrolling shaft (61) winds the tape (62) on the scrolling shaft (61), so as to drive the screen push-pull base (13) to move towards one side of the scrolling shaft (61) through the tape (62), and at the same time the screen push-pull base (13) compresses the telescopic device (7). An elevator screen (12) is disposed on the screen push-pull base (13). The cabinet projection screen has advantages of versatility and occupying no space.
US08023174B2 MEMS array substrate and display device using the same
A micro electro-mechanical system (MEMS) array substrate includes a substrate, a plurality of first signal lines, a plurality of second signal lines, a plurality of MEMS switches and a plurality of pixel electrodes. The first signal lines are disposed on the substrate in parallel with one another as well as the second signal lines. The second signal lines intersect with the first signal lines, such that a plurality of pixel regions is defined on the substrate. Each MEMS switch is located at corresponding one of the intersections between the first signal lines and the second signal lines. Each pixel electrode is configured in corresponding one of the pixel regions and electrically connected with the corresponding MEMS switch Compare to thin film transistor, since the operation performance of the MEMS switches would not affected by carrier mobility and on-off current ratio, display performance of the display device can be easily improved. In addition, a display device using the MEMS array substrate is also provided.
US08023173B2 Biaxial mirror color selecting micro imager
A controllable reflecting device having an array of bi-axial mirrors that are capable of pivoting in at least four directions is described. At least three primary colored light beams are directed at each of the bi-axial mirror in three of the four pivoting directions, one for each of the primary colored light beams and a single colored beam is reflected and directed toward a projection lens. In the fourth pivoting direction, no color beam is directed to the projection lens and black is projected.
US08023168B2 Organic layers for tunable optical devices
A method for manipulating light comprises receiving an incoming beam of light at a tunable optical device, the tunable optical device comprising an organic material having an optical property that can be selectively varied under the influence of an external bias. The method further comprises applying a selected external bias to the tunable optical device to change an optical property of the tunable optical device. The method also comprises controlling an optical property of a beam of light exiting the tunable optical device as a result of the selected external bias.
US08023167B2 Backlight displays
A transmissive backlit display is disclosed. In one aspect, the backlit display comprises a backlight and an array of transmissive interferometric modulators. Each interferometric modulator comprises a fixed and moving dielectric mirror stack. The interferometric modulators cause light within the desired wavelength range to be transmitted while reflecting at least a portion of the remaining light.
US08023164B2 Color adjustment apparatus, display apparatus, printing apparatus, image processing apparatus, color adjustment method, graphical user interface displaying method and program
Disclosed herein is a color adjustment apparatus, including: a color information storage section configured to store color information regarding an arbitrary region designated through a pointer in an editing image region; and a color coordinate explicitly displaying section configured to explicitly display a mark, which specifies color coordinates corresponding to the color information, at a pertaining position on a hue ring or a hue bar chart prepared for color adjustment.
US08023162B2 Hexagonal site line scanning method and system
A scanning technique for imaging sites in an array includes illuminating or irradiating sites in lines of the array, and collecting returned radiation from the sites for imaging. The sites are sequentially scanned by means of confocally directed radiation lines from source optics. The orientation of the radiation lines with respect to the lines of sites in the array is such that the distance between nearest edges of sites in adjacent lines is greater than lines through those edges in a direction parallel to the radiation lines used for scanning. The resulting system experiences less crosstalk and a greater ability to distinguish between neighboring sites in resulting images.
US08023161B2 Systems and methods for providing image data encapsulated in a page description language
A multi-function peripheral imaging device for providing page description language (“PDL”) encapsulated image data is disclosed. The imaging device includes a processor for control of the imaging device and memory in electronic communication with the processor. The imaging device also includes a scanner in electronic communication with the processor and a printer in electronic communication with the processor. The multi-function peripheral imaging device includes a control panel for operation of the imaging device by a user. The control panel is in electronic communication with the processor for receiving user inputs. Executable instructions are included that are configured to implement a method for providing PDL encapsulated image data. An image is scanned using the scanner to produce image data. Document and page formatting inputs are obtained from the control panel. The image data is encapsulated in a page description language at the imaging device using the document and page formatting inputs for document formatting.
US08023158B2 Image processing system and image processing method
An image processing system comprising: an image acquisition unit for acquiring a scanned image; a non-voltage storage medium that stores correction information corresponding to a known object having a three-dimensional shape defined by the standard; when an object of the scanned image is the known object, a correction unit that corrects a shadow area of the scanned image corresponding to a shadow resulting from thickness of the known object, on the basis of the correction information.
US08023156B2 Image output color management system and method
Disclosed is an image color management system and method for controlling an image output device. The method for controlling the image output device comprises generating an image output device profile LUT (look-up-table) characterizing the color profile of the image output device for a plurality of drift states associated with the image output device; generating a set of basis vectors representing the LUT; storing the set of basis vectors in an image output device controller; and generating an image output device active profile associated with a current drift state of the image output device to convert image color data for display or printing by the image output device, wherein the image output device active profile is generated from the set of basis vectors.
US08023153B2 Content-aware halftone image resizing
As provided herein, there are supplied teachings to systems and methods for resizing a halftone image using halftone tile parameters. One approach entails receiving into a digital imaging system, a digital halftone image and a desired resizing factor for the digital halftone image. Subsequently the system will define cells within the digital halftone image and determine from those cells, a number of halftone tile seams to suitable for manipulation. The orientation of these halftone tile seams is dictated by the received desired resizing factor. The energy of the number of halftone tile seams is determined according to an energy metric so as to provide indication of at least one low energy determined halftone tile seam. A resizing of the halftone image is then performing by manipulating at least one low energy halftone tile seam in the halftone image. The resized halftone image may then be printed on a printer.
US08023152B2 Method for frequency-modulation screening using error diffusion based on dual-feedback
The present invention relates to a method for producing halftone dots in the field of image hard copying, more particularly to a method for frequency-modulation screening using error diffusion based on dual-feedback. In the known frequency-modulation and amplitude-modulation screening technology, it is hard to output a halftone image with high quality using an output equipment with a low resolution (600 dpi) and the satisfactory effect of representing the gradations of the original image in detail and holding the smoothness of the original image can not be achieved. By using the dual-feedback technology based on a basic algorithm of the error distribution, the method in the present invention realizes the organic combination of the conventional frequency-modulation and amplitude-modulation screens and achieves the effect of mixed screening. The method in the present invention can effectively solve the problem of losing gradations of dots in an output equipment with low resolution and can reduce the moire caused by the random distribution characteristic so as to output halftone images with high quality and full gradations.
US08023147B2 Image processing method and image processing apparatus
An image processing method and image processing apparatus which can execute vector conversion processing by appropriately dividing a clipart image including gradation into regions are provided. To this end, a color document image including a clipart image having an area of gradation is input, the clipart image is selected, and outline information of the clipart image is extracted. The color document image is separated into an achromatic color area and a chromatic color area, which are respectively divided into a plurality of regions. Of the plurality of regions of each of the achromatic color area and the chromatic color area divided in the dividing of region step, regions which meet a set condition are integrated. After that, the clipart image is converted into vector data using a region group after integrating of region and the outline information.
US08023145B2 Image processing system and image processing method
An image processing system is provided and includes a first receiving unit, a print control unit, a second receiving unit, a read control unit, and a composition unit. The first receiving unit receives an order-sheet request, and the print control unit causes a printer unit to print an area notation indicating a free rendering area on paper in accordance with the order-sheet request. The second receiving unit receives a scan request, and the read control unit causes an scan unit to read the paper on which a subject is recorded in the free rendering area in accordance with the scan request. Also, the composition unit composites an image of the free rendering area read by the scan unit in accordance with the scan request and the other image or images. A method that the system performs is also provided.
US08023143B2 Image-forming system and image-forming program
An image-forming system prevents a print overrun error even if there are bands of divided data having different band heights. An image-forming system has a band divider to divide image data into a plurality of bands each containing divided image date, a loader to load the bands into a band memory, and an output unit to sequentially output the bands from the band memory to a print engine at predetermined timing. The band divider can change the height of at least one of the bands from the height of the remaining bands. The band memory includes VRAMs into which a band of bitmap data whose band height is higher than a threshold is loaded and an auxiliary VRAM (VRAM-special) into which a band of bitmap data whose height has been changed.
US08023140B2 Handheld display device for magnifying printed information
A method of magnifying printed content using a handheld display device having a touch-sensitive screen and a transceiver for sending and receiving digital information. The method comprises the steps of: imaging an area of the substrate containing printed content and generating image data using an optical sensor; determining interaction data using the image data, the interaction data identifying a substrate identity; retrieving, using the interaction data and the page description, display data corresponding to the printed content; displaying, on the touch-sensitive screen, display information based on the display data, the display information including displayed content corresponding to the printed content; and interacting with the displayed content via the touch-sensitive screen. Interacting with the displayed content via the touch-sensitive screen magnifies the displayed content on the screen.
US08023138B2 Method of generating interactive substrate from interaction with another interactive substrate
A method of generating a second interactive substrate in response to a first interactive substrate. The method comprises the steps of: (i) interacting with the first interface surface using an optically imaging pen having a nib; (ii) imaging and decoding a coded data tag; (iii) generating indicating data regarding the identity of the first interactive substrate and a position of the nib relative to the first printed surface; and (iv) sending the indicating data to a computer system, thereby causing a printer to print a second interactive substrate in response to the computer system receiving the indicating data.
US08023136B2 Universal scan to store system and method of using the same
A free-standing universal scanner driving device includes a small, light-weight, portable, slow-speed, low memory processor with no monitor or keyboard, and programmed only to support a scanner; a memory having only enough capacity to hold a scanner driver; a slot for receiving an external storage medium; input and output ports; means for writing data on the external storage medium; a housing case; optionally an external numeric keypad; and one and only one push-button, touch pad, or touch screen for initiating an external optical scanner to scan a document placed in the scanner and then directly write the scanned electronic data into the external storage medium by pushing the button, without requiring any setup input from the user. The push-button, touch pad, or touch screen being integrally formed on the case.
US08023135B2 Interface for building a print container
A method is provided for creating a print container with a series of resident fixed documents. The method opens a user interface (UI). Using the UI, a first plurality of elements stored in memory is selected and a print container is created. The print container preserves a second plurality of elements as separate entities in the print container. For example, a print container may have an element hierarchy of jobs in the print container, fixed documents in a job, and fixed pages in a fixed document may be created. Elements are defined as print containers, fixed documents, application-specific documents, page description language (PDL) documents, extensible markup language (XML) paper specification (XPS) fixed documents, or combinations of the above-mentioned elements. In one aspect, the selected elements are extensible markup language (XML) paper specification (XPS) fixed documents, which are preserved as separate entities in an XPS container.
US08023132B2 Method and system for transferring digitized representations of documents via computer network transfer protocols
A method for a computer system includes receiving a first transmission from a user, wherein the first transmission includes a digitized representation of a first document transmitted using a first transmission format, processing the digitized representation of the first document with an optical character recognition process to determine a first electronic destination, wherein the first electronic destination need not be known by the computer system before receiving the first transmission, reformatting at least a portion of the digitized representation of the first document from the first transmission format into a storage format; determining advertisement data in response to the first transmission, and sending an electronic transmission to the first electronic destination, wherein the electronic transmission includes the advertisement data and the portion of the digitized representation of the first document in the storage format.
US08023128B2 Image processing apparatus and image processing method
An object is to provide a user with various options on a processing method of an original document including a code image. To accomplish the object, the image processing apparatus includes a decoding section for extracting information by decoding the code image contained in the original document image, and a decision section for making a decision according to selection of the user as to whether to output the original document image or the information extracted by the decoding section.
US08023126B2 Image forming apparatus with a chargeable capacitor
An image forming apparatus includes a main power unit that outputs a first DC power and an auxiliary power unit that outputs a second DC power to the components of the image forming apparatus. The auxiliary power unit includes a rechargeable capacitor. A measuring unit measures performance of the capacitor and a determining unit determines performance insufficiency of the capacitor based on the measured performance and the system configuration of the image forming apparatus. The performance is, for example, changes in a capacitance of the capacitor with time. When the determining unit determines performance insufficiency of the capacitor, a control unit adjusts, for example, a use range of the capacitor.
US08023121B2 Method for optically collecting numismatic data and associated algorithms for unique identification of coins
A method to generate an optical signature of a coin is disclosed. A plurality of parameters are generated and recorded related to rotational positions around the circumference of a coin. The data from these parameters are combined to produce a searchable value.
US08023120B2 Ophthalmic surgical microscope having an OCT-system
An ophthalmic surgical microscope (100) has a microscope main objective (101) and a viewing beam path (105) which passes through the microscope main objective (101) for visualizing an object region. The ophthalmic surgical microscope (100) includes an OCT-system (140) for recording images of the object region (108). The OCT-system (140) includes an OCT-scanning beam (142) which is guided via a scan mirror arrangement (146) to the object region (108). An optic element (147) is provided between the scan mirror arrangement (146) and the microscope main objective (101). This optic element (147) bundles the OCT-scanning radiation exiting from the scan mirror arrangement (146) and transfers the same into a beam path which passes through the microscope main objective (101). Alternatively or in addition, the ophthalmic surgical microscope (100) includes an ophthalmoscopic magnifier lens (132) which can be pivoted into and out of the viewing beam path (105) and the OCT-scanning beam (142).
US08023119B2 Method for analyzing mucosa samples with optical coherence tomography
A method for analyzing mucosa structure with optical coherence tomography (OCT) is provided, and includes: (a) scanning a mucosa sample with optical coherence tomography; (b) choosing a lateral range from a two- or three-dimensional OCT image and analyzing all the A-scan intensity profiles in the lateral range; (c) calculating three indicators in each A-scan intensity profile, including the standard deviation for a certain depth range below the sample surface, the exponential decay constant of the spatial-frequency spectrum and the epithelium thickness under the condition that the basement membrane is identifiable; and (d) using the three indicators of each A-scan intensity profile within the lateral range to analyze the mucosa structure.
US08023117B2 Establishing and maintaining focus in segmented-optic telescopes
A multi-aperture interferometric optical system collects light propagating from a source of light and develops overlapping diffraction patterns on an optical detector that produces output signals for processing to automatically focus the optical system and form an image corresponding to the diffraction patterns. A preferred embodiment of the invention is a large aperture orbiting, earth-watching ring interferometric optical system configured such that there is no macro-structure pointing. Four mirror-ring structures direct incoming light to a multi-spectral primary optical detector that acquires light-pattern information to focus the optical system and derive an image.
US08023116B1 Resolving quadrature fringes of interferometer signals in real time
Techniques and devices for digitally resolving quadrature fringe signals from interferometers such as optical interferometers and interferometer-based sensing devices. In one implementation, two quadrature fringe signals from an interferometer which causes two signals in two signal paths to interfere with each other are sampled to obtain digital data samples from the two quadrature fringe signals. The digital data samples are used to perform a linear least square fitting to establish coefficients for an ellipse traced by the two quadrature fringe signals as a phase difference between the two signal paths changes. A pair of digital data samples are respectively obtained from the two quadrature signals at a given moment and are used to compute a corresponding phase difference between the two signal paths of the interferometer from established coefficients of the ellipse. The coefficient for the ellipse can be updated over time. This digital processing allows for real time processing.
US08023115B2 Sensor, sensing system and sensing method
A sensor is an optical resonator constituted by: a first reflecting body that exhibits semi transmissivity/semi reflectivity; a transparent body; and a second reflecting body that exhibits one of reflectivity and semi transmissivity/semi reflectivity, provided in this order from the light incident side. The sensor is configured such that the absorption peak of the measuring light beam by resonance in the optical resonator matches the absorption peak of the measuring light beam by local plasmon resonance generated at the surface and/or within the optical resonator. The sensor has absorption properties such that light of specific wavelengths are absorbed depending the mean complex refractive indices of the first and second reflecting bodies and the thickness of the transparent body. An emitted light beam is output from the first reflecting body. The physical properties of the emitted light beam that change according to the absorption properties are detected.
US08023112B2 Alignment apparatus and fabrication apparatus for planar member and alignment method and fabrication method for planar member
An alignment apparatus for a planar member includes, an image capturing unit which captures an image of a rotationally asymmetrical alignment mark provided on the planar member, a position detection unit which detects a position of the alignment mark from the image, a position adjusting unit which adjusts, based on the detected position of the alignment mark, the position of the planar member relative to a reference position, and an orientation detection unit which detects an orientation of the planar member based on the rotational asymmetry of the alignment mark captured in the image.
US08023102B2 Test method for determining reticle transmission stability
Methods, systems and apparatus for monitoring the state of a reticle by providing a reticle having a device exposure region in an imaging tool, defining one or more image fields across the device exposure region, and transmitting energy through the device exposure region. A detector detects the energy in the image field(s) at one or more testing intervals and a system control generates a transmission profile of average energy transmissions for each image field. Using this transmission profile, the state of the reticle is then determined at each testing interval followed by taking action based on the reticle state. The state of the reticle identifies whether the device exposure region has been deleteriously degraded, and as such, the reticle is no longer suitable for use. This is accomplished by determining if any average energy transmission of any image field across the reticle exceeds an allowable energy transmission threshold.
US08023100B2 Exposure apparatus, supply method and recovery method, exposure method, and device producing method
The present invention provides an exposure apparatus that can prevent the degradation of exposure and measurement accuracies. An exposure apparatus (EX) exposes a substrate (P) by irradiating the substrate (P) with exposure light (EL) through a projection optical system (PL) and a liquid (LQ), and comprises: a liquid supply mechanism (10) that supplies the liquid (LQ) between an optical element (2) at the image plane side tip part of the projection optical system (PL) and a substrate (P) that opposes the optical element (2); a timer (60) that measures the time that has elapsed since the supply of the liquid by the liquid supply mechanism (10) was started; and a control apparatus (CONT) that determines, based on a measurement result of the timer (60), whether a space(SP), which is between the optical element (2) and the substrate (P) and includes at least an optical path of the exposure light (EL), is filled with the liquid (LQ).
US08023098B2 Production method for birefringent film, birefringent film, and laminate
Provided is a production method for a thin birefringent film with a satisfactory alignment property, in which a refractive index is controlled three-dimensionally and optical properties are unlikely to decrease in the case where the birefringent film is placed under high temperature and high humidity. The production method for a birefringent film of the present invention includes: the step (1) of preparing a solution that exhibits a nematic liquid crystal phase, containing at least one kind of polycyclic compound containing a —SO3M group and/or a —COOM group (M represents a counter ion) and a solvent; the step (2) of preparing a base material at least one surface of which is subjected to a hydrophilization treatment; and the step (3) of applying the solution prepared in the step (1) to the surface of the base material prepared in the step (2), the surface being subjected to the hydrophilization treatment, followed by drying, in which a contact angle of water at 23° C. on the surface of the base material prepared in the step (2), the surface being subjected to the hydrophilization treatment is 45° or less.
US08023093B2 Display panel, multi-layer display element, and method of fabricating the same
The present invention is to provide a display panel, a multi-layer display element, and a method of fabricating same, which can readily align alignment positions of individual display panels with each other even though common alignment marks are provided on each of display panels. A display panel includes a pair of substrates faced to each other as a display material layer is sandwiched between the substrates, a plurality of pixels provided in a plane almost in parallel with a substrate surface between the substrates, and a plurality of alignment marks formed in different shapes and linearly arranged on at least one of the pair of the substrates at a predetermined interval for alignment in placing the display panels in layers.
US08023091B2 Liquid crystal display device having spacer comprising liquid phase material and fabricating method thereof
A liquid crystal display device and fabricating method thereof are disclosed by which a cell gap can be uniformly maintained, regardless of temperature variation, across an LCD panel. Opposing substrates are spaced apart with a prescribed gap using spacers and liquid crystals in the gap between the substrates. The spacers are provided on either or both of the substrates. The spacers contain an organic resin within which a liquid phase material or liquid crystals is dispersed. The liquid phase material or liquid crystals may be encapsulated. The thermal expansion coefficient of the material is substantially equal to or greater than that of the liquid crystals in the gap between the substrates. The thermal expansion coefficient of the column spacer is substantially equal to or greater than that of the liquid crystals in the gap between the substrates.
US08023085B2 Liquid crystal display apparatus having alignment control for brightness and response
A liquid crystal display apparatus including a pair of substrates having electrodes and vertical alignment layers. A liquid crystal having a negative anisotropy of dielectric is inserted between the substrates. Each substrate has linearly arranged alignment control structures for controlling the alignment of the liquid crystal. The alignment control structures are formed in the form of projections or slits. Each alignment control structure is formed of a plurality of constituent units. In addition, means for forming a boundary of alignment of liquid crystal (singular point in director field) to control the liquid crystal located on the alignment control structures.
US08023075B2 Liquid crystal display and method for forming alignment film
A liquid crystal display substrate includes a first active area and a second active area on the liquid crystal display substrate, a first black matrix and a second black matrix respectively surrounding the first active area and the second active area, a cutting region encircling the first black matrix and the second black matrix, and at least a guarding wall disposed on the black matrix or on the cutting region.
US08023071B2 Transmissive or reflective liquid crystal display
This invention relates to a liquid crystal display with improved contrast ratio, switching performance, reflectivity at the Dmin state and structural integrity, and methods for its manufacture. The liquid crystal display of the present invention comprises microcups as display cells, wherein the microcups are formed from a microcup composition and filled with a liquid crystal composition.
US08023069B2 Liquid crystal display device
A light guiding plate is manufactured with high precision and in a short period of time in a backlight where light emitting diodes are provided on the side of the light guiding plate, even in the case where the light guiding plate is formed so as to have a spherical surface. In a liquid crystal display device having a backlight for illuminating a liquid crystal panel with light, LED's are provided in a light guiding plate in the backlight as a light emitting element, the light emitting portion of the light guiding plate is formed so as to have a spherical surface by applying heat and pressure to a resin in sheet form, and the light guiding plate is manufactured by fusing a light entering portion formed of a resin through injection molding with the light emitting portion.
US08023065B2 Optical element for lateral light spreading in edge-lit displays and system using same
An illumination light unit has at least one light source that generates illumination light. The unit also includes a reflecting cavity having one or more reflectors and a controlled transmission mirror disposed at an output of the reflecting cavity. The controlled transmission mirror includes an input coupling element, an output coupling element and a first multilayer reflector disposed between the input and output coupling elements. At least some of the illumination light is reflected within the reflecting cavity by the one or more reflectors and is transmitted out of the reflecting cavity through the controlled transmission mirror. The illumination light unit may be used for generating light for space lighting, or for illuminating a display. For example, the unit may be used in a backlight to illuminate a lightguide placed behind a display panel.
US08023063B2 Illumination apparatus for display device, display device using the same, and television receiver apparatus comprising the display device
In a backlight apparatus, laminated optical sheets are housed in a tray such that a wall portion thereof surrounds their circumferences so that the optical sheets receive light from fluorescent lights. Tips of one corner portion A of optical sheets preferably have a shape in which the tips are trimmed by line segments extending between two edges defining the corner portions. At the wall portion of the tray, an opposing surface is formed along the line segments of the corner portions so as to correspond to the shape of the corner portions having tips trimmed off. The opposing surface restrains the line segments.
US08023059B2 Array substrate of liquid crystal display, method of repairing same, and liquid crystal display
An array substrate of a liquid crystal display includes data lines; scanning lines configured to cross with the data lines; a test line provided outside a display region of the array substrate for test of the array substrate; and a repair line provided outside the display region for repair of a defective data line. The test line is configured to be electrically isolated from the repair line when the repair is not carried out and is electrically connected to the repair line and the defective data line when the repair is performed. A method of repairing the array substrate and a liquid crystal display using the array substrate are also provided. According to the invention, the test line can be used as a part of a repair circuit for repair of the data lines, thereby greatly decreasing non-display area.
US08023054B2 Flat panel display and fabricating method thereof
A flat panel display device includes a gate line and a data line crossing each other to define a pixel area, a pixel electrode in the pixel area, and a thin film transistor having a gate electrode connected to the gate line, a source electrode connected to the data line, and a drain electrode connected to the pixel electrode, wherein the gate line has at least two or more separated gate line portions where the gate line crosses the data line.
US08023050B2 Optical device and projector
An optical device includes a vertically aligned liquid crystal cell that holds a liquid crystal material, a compensating element made of a negative uniaxial refractive material having an optical axis tilted with respect to a system optical axis, and having a fixed positional relation with the liquid crystal cell, an adjustment element having a planar shape and a phase difference in a plane perpendicular to the system optical axis, and a rotary adjustment mechanism that rotates the adjustment element in the plane perpendicular to the system optical axis to adjust the phase difference influencing light transmitted through the adjustment element.
US08023041B2 Detection of moving interlaced text for film mode decision
A method for detecting moving interlaced text in a video sequence originating through telecine is disclosed. The method generally includes the steps of (A) checking a motion condition of a current block in a current field in the video sequence for motion both (i) from a previous field in the video sequence to the current field and (ii) from the current field to a next field in the video sequence, (B) checking an artifact condition of the current block for a plurality of symmetric interlaced artifacts in both (i) a forward temporal direction and (ii) a backward temporal direction and (C) asserting a block motion indicator for the current block if all of (i) the motion condition is true and (ii) the artifact condition is true.
US08023036B2 Automatic focusing system focus area control
In a focus demand connected to a lens unit of a television camera, a joystick for designating the direction of movement of an AF area is disposed. A direction change switch for reversing the direction of movement of the AF area with respect to the direction of operation of the joystick is also provided. The focus demand is reversed in vertical and horizontal directions between the case of being mounted to be operated by the right hand and the case of being mounted to be operated by the left hand.
US08023030B2 Image pickup apparatus
An image pickup apparatus includes a display that displays photographing information. When the display is turned off in response to an operation performed by a user, the photographing information is prevented from being changed even if a button or a dial for changing a set value, such as a shutter speed or an aperture value, is operated.
US08023028B2 Solid-state imaging device
A solid-state imaging device and a charge transfer method are provided. The solid-state imaging device includes light receiving portions arranged in a matrix of rows and columns, vertical transfer portions, and a horizontal transfer portion. The vertical transfer portions are formed for each column of the matrix of the light receiving portions, for transferring charges transferred from the light receiving portions in a vertical direction. The horizontal transfer portion transfers the charges transferred from the vertical transfer portions in a horizontal direction. The vertical transfer portions divide the charges transferred to the vertical transfer portions and transfer the divided charges in the vertical direction. The horizontal transfer portion transfers the divided charges in a mixed state in the horizontal direction.
US08023027B2 Solid-state imaging device and imaging apparatus utilizing a dynamic bias current for reduced power consumption
A solid-state imaging device includes: a sensor unit; a vertical scanning unit and a horizontal scanning unit; column amplifier units provided at respective vertical signal lines corresponding to columns in the sensor unit and amplifying signal charges read out to the vertical signal lines; a bias current adjustment unit controlling current flowing in the vertical signal lines by changing bias current of the column amplifier units; a signal processing unit processing signal charges read out to the vertical signal lines and amplified at the column amplifier units into image signals to be outputted; an output unit to which signals outputted from the signal processing unit are supplied; a drive signal generation unit supplying drive signals to the vertical scanning unit, the horizontal scanning unit, the signal processing unit and the output unit; and an input unit supplying plural drive mode signals to the drive signal generation unit.
US08023025B2 Photoelectric conversion apparatus and image pickup system using the same
A photoelectric conversion apparatus includes photoelectric conversion elements configured to convert incident light to electric carriers, amplifier sections configured to read signals based on the electric carriers generated in the photoelectric conversion elements, transfer sections configured to transfer electric carriers in the photoelectric conversion elements to input units of the amplifier sections, and voltage supply sections configured to set potentials of the input units, arranged in a two-dimensional array. The photoelectric conversion apparatus further includes output lines configured to read signals from the amplifier sections and voltage supply lines configured to supply voltages to the voltage supply sections. Out of the output lines and the voltage supply lines, only one output line and one voltage supply line related to a first photoelectric conversion element are disposed between the first photoelectric conversion element and an adjacent second photoelectric conversion element.
US08023020B2 Pixel sensor with voltage compensator
A photodetecting circuit is disclosed. The photodetecting circuit includes a photodetector, a storage node with first and second node terminals, a transfer transistor disposed intermediate the first node terminal of the storage node and the photodetector for electrically connecting the first node terminal and the photodetector upon receiving a transfer signal to a gate of the transfer transistor, a reset transistor disposed intermediate a reset voltage node and the first node terminal of the storage node for electrically connecting the first node terminal to the reset voltage node upon receiving a reset signal to a gate of the reset transistor, and an output circuit for generating an output signal based on a voltage at the first terminal. First the reset signal is applied, followed by the transfer signal. Next, a compensation signal is applied at the second terminal of the storage node. The compensation signal increases the voltage at the first terminal whilst the output circuit generates the output signal. The compensation signal is a logically negated version of the transfer signal.
US08023017B2 Pattern of color filter array
The present invention relates to a pattern of a color filter array. The pattern includes a plurality of pixel arrays, which has four color filters arranged in an array. The color of the neighboring color filters is distinct to each other. Moreover, the pattern of the color filter array has enlarged color filters or extended edges in corners of the pattern. These enlarged color filters or extended edges increase the contact area between the pattern and a substrate that the pattern formed on. Therefore, the adhesion strength between the pattern and the substrate can be augmented to prevent peeling from the substrate. According to the invention, the yield of the product will be raised substantially.
US08023015B2 System, method and medium correcting brightness of an image
A system, method and medium correcting brightness of an image, and more particularly, a system, method and medium correcting brightness of an acquired image to achieve a target brightness. The system includes an initial brightness sensing unit to sense an initial brightness of the image from an initial exposure, and an image correction unit to correct the brightness of the sensed initial image toward a target brightness using predetermined brightness information corresponding to a sensed brightness environment of the image.
US08023012B2 Image capture device correcting defective pixel information
An image capture device provided with a first memory unit, which memorizes position information of non-continuous defective pixels of a solid-state image capture component, and a second memory unit with a higher access rate than the first memory unit, which memorizes position information of continuous defective pixels. When a continuous photography mode or a video photography mode is set, defective pixel correction processing is carried out on image data corresponding to each of defective pixels according to the defective pixel position information stored at the second memory unit. Alternatively, when a still photography mode is set, image data corresponding to all defective pixels is corrected, based on both the defective pixel position information stored at the first memory unit and the defective pixel position information stored at the second memory unit. As a result, it is possible to correct defective pixels with high efficiency in accordance with conditions of photography.
US08023010B2 Defective pixel correction device
First pixel data of a pixel of interest is output from a first shift register, while second and third pixel data of neighboring pixels indicative of the same color are output from second and third shift registers, respectively. Differential data between estimated pixel data calculated from the second and third pixel data and the first pixel data is input to a comparator. A threshold value stored in a register is modulated by the estimated pixel data, and is input to the comparator as modulated threshold data. When the comparator judges that the differential data is greater than the modulated threshold data, a selector outputs the estimated pixel data as corrected pixel data.
US08023007B2 Automatic file transmission system
For automatically transmitting an image file, a system transmits the file automatically through specifically specifying information for file transmission such as an address of a destination. The system includes a memory for storing a data file and an automatic transmission control file for briefly describing information of a file name of the file to be transmitted and a destination address, and a communication unit for transmitting the data file according to the automatic transmission control file. Therefore, the system can transmit the data file automatically only by having a memory storing the data file and automatic transmission control file connected to the communication unit.
US08023006B2 Electronic still camera which acquires photography-site data and image processing apparatus which processes image data photographed by electronic still camera
An electronic still camera includes a position calculating unit. A storage unit stores the self-position data calculated by the position calculating unit, as photography-site data, in association with the image data acquired by photographing an object. If the self-position data cannot be acquired at the time of photographing the object, a control unit sets the self-position data acquired by the position calculating unit at a time different from the time of photographing the object, in the storage unit as the photography-site data.
US08023003B2 Apparatus and method for generating panorama images and apparatus and method for object-tracking using the same
Provided are an apparatus and method for generating panorama images and an apparatus and method for tracking an object using the same. The apparatus for generating panorama images estimates regional motion vectors with respect to respective lower regions set in an image frame, determines a frame motion vector by using the regional motion vectors based on a codebook storing sets of normalized regional motion vectors corresponding to a camera's motion and then accumulates motion mediating variables computed with respect to respective continuous image frames to determine an overlapping region, and matches the overlapping regions to generate a panorama image.
US08023002B2 Imager, imaging circuit, and image processing circuit
The number of channels is changed in accordance with an operation mode in an image pickup apparatus. An image-pickup control unit 240 determines the number of operation channels W in accordance with an operation mode. A sensor unit 210 outputs an image pickup signal corresponding to each pixel in accordance with the number of operation channels W. A data sending unit 220 performs serial conversion on image pickup signals, and transfers them to the image processing unit 300 using a high-speed interface (a signal line 229) such as an LVDS in accordance with the number of operation channels W. A data receiving unit 311 performs parallel conversion on the transferred serial signal for each of the channels in units of M bits. A data reconstruction unit 500 detects a synchronization code embedded in the parallel signals, extracts data windows, and supplies, to a signal line 319, image pickup signals of bit length n which are reconstructed from the data windows. A clock gating circuit 330 supplies a clock CLK3 to a signal line 337 only during a period in which a valid flag (a signal line 316) indicates validity.
US08023001B2 Analog front-end circuit and electronic instrument
An analog front-end circuit includes an analog processing circuit, an A/D converter, a calculation circuit, and a correction amount register in which a correction amount is set. The analog processing circuit includes an offset adjustment circuit that includes an offset adjustment register. The calculation circuit monitors an A/D-converted value output from the A/D converter, detects the change amount of the A/D-converted value when changing an offset adjustment value set in the offset adjustment register by 1 LSB as the correction amount, and sets the detected correction amount in the correction amount register.
US08022996B2 Image stabilizing device of the MEMS type, in particular for image acquisition using a digital-image sensor
A device for stabilizing images acquired by a digital-image sensor includes a motion-sensing device, for detecting quantities correlated to pitch and yaw movements of the digital-image sensor, and a processing unit, connectable to the digital-image sensor for receiving a first image signal and configured for extracting a second image signal from the first image signal on the basis of the quantities detected by the motion-sensing device. The motion-sensing device includes a first accelerometer and a second accelerometer.
US08022992B2 Data processing system, data processing device, image display device, and recording medium that records processing program thereof
When directed to transmit data in a personal computer (1), a document image data generating section (22) generates document image data obtained by imaging a document content based on document data for every page. An index image generating section (23) composites a file name of the document data and icon image data corresponding to application software by which the document data is created, and thereby generates index image data. The folder generating section (26) generates a PC folder based on the document image data, the index image data, and the management data, and generated by a management file generating section (24) transmits the PC folder to a digital camera (51) via a data transmitting section (27).
US08022991B1 Massively-parallel three-axis stabilization of focal plane data
A system and method for three-axis stabilization of focal plane data. The system and method include performing a two-dimensional vertical shear transformation and a two-dimensional horizontal shear transformation. The system and method further incorporate a SIMD computer architecture and an array of addressable processing elements that process the field-of-view for a target image received by a focal plane array of detector elements. Each processing element includes a calculation device that calculates the row and column address of virtual pixels for a virtual field-of-view. The system and method further include a plurality of memory modules configured to store data in a plurality of addressable storage locations by column and row, and each memory module is identified with a different processing element. A dedicated memory routing network for the processing elements and memory modules permits the exchange of information between processing elements and memory modules associated with each processing element.
US08022984B2 System and method for reducing jitter during an optical navigation operation
A system and method for reducing jitter during an optical navigation operation operates to automatically switch the current resolution based on jitter-resolution correlation data.
US08022982B2 Camera system and method for operating a camera system
A system and method for controlling a camera assembly may include monitoring an image field for blinks by one or more subjects in the image field. The monitoring may be carried out by generating a video signal of the image field, the video signal having a sequence of frames; subtracting a previous frame of the video signal from a current frame of the video signal to generate a difference frame; and identifying image data in the difference frame that is representative of a blink. Each blink may be tracked and associated with a subject from the one or more subjects. Statistical data regarding blink duration and blink rate for each subject from the one or more subjects may be generated. In response to user input to command the taking of a photograph, a determination if a blink is in progress may be made and a flash of the camera assembly may be fired and image data for the photograph may be captured if no blink is detected at the time of the command. Otherwise, firing of the flash and the capturing of the image data may be delayed by an amount of time that is based on the statistical data to minimize firing the flash and capturing the image data during a blink of the one or more subjects.
US08022978B2 Autotiller control system for aircraft utilizing camera sensing
An automatic control system for directional control of an aircraft moving on the ground utilizing computer vision methods and camera sensing methods (visible, infrared or microwave) to optically recognize and track taxiway navigation features thereby providing pilot television picture steering cues or force inputs to the nosewheel steering system to maintain the aircraft on the centerline.
US08022973B2 Case and time recorder
An inward deformation of one side wall of a main body is corrected, since a shaft serving as a rotatable shaft of a door is in contact with ribs of a side wall. Additionally, an inward deformation of another side wall of the main body is corrected, since ribs of a side wall of door are in contact with side wall.
US08022969B2 Rotatable display with sub-pixel rendering
In a system comprising a processor, an image storage and a display, said display capable of displaying an image, and said image being renderable in a plurality of rotation degrees upon said display upon receipt of a command, a method of rotating an image, said image further comprising at least one member of a group, said group comprising text and images capable of being sub-pixel rendered, comprises the steps of: sub-pixel rendering said at least one member of a group; grouping said sub-pixels into a plurality of sub-pixel groups; rotating said plurality of sub-pixel groups such that each said sub-pixel group is rotated as a pixel on a pixel-to-pixel basis. In another embodiment, the display upon which rotation is performed comprises substantially equal subpixel rendering addressability limits in horizontal, vertical and diagonal directions.
US08022968B2 Image display and storage apparatus, method and medium
An image display and storage device, method, and medium to process an original image and generate a main image so that the original image does not overlap a sub image, and store the original image instead of the main image when the main image and the sub image are displayed. The device includes an image processor to receive an image, and to generate a display image and a storage image using the received image, a display unit to receive the display image from the image processor, and to display the display image, and an image storing unit to receive the storage image from the image processor and to store the image.
US08022965B2 System and method for data assisted chroma-keying
The invention illustrates a system and method of displaying a base image and an overlay image comprising: capturing a base image of a real event; receiving an instrumentation data based on the real event; identifying a visual segment within the base image based on the instrumentation data; and rendering an overlay image within the visual segment.
US08022959B1 Loading an internal frame buffer from an external frame buffer
A system including a first chip, a display controller and a copy device. The first chip includes a first memory. The display controller is configured to read a first frame from a second memory external to the first chip. The copy device is configured to copy the first frame from the second memory to the first memory while the display controller reads the first frame from the second memory. Subsequent to the copy device copying the first frame from the second memory to the first memory, the first frame is stored in both the first memory and the second memory.
US08022957B2 Apparatus and method for processing data
A data processing apparatus includes a plurality of processing units each performing a respective one of process parts into which a predetermined process to be performed on data is divided, and a changing unit that changes a connection between the plurality of processing units on the basis of setting parameters that are set to enable a plurality of types of processing procedures.
US08022955B2 Operability verification apparatus, operability verification method, and computer-readable storage medium storing operability verification program
An operability verification apparatus includes a work plane generation section that generates a work plane on a virtual space where a three-dimensional model of an equipment to be verified is disposed; a plane display section where a two-dimensional image on a work plane generated in the work plane generation section of the three-dimensional model is displayed on the display screen; and a mark display update section in which a mark representative of the pointing device is displayed on the display screen, and upon receipt of the notification of direction of movement and migration length of the pointing device, the mark on the display screen is moved in the direction of the movement corresponding to the direction of the movement of the pointing device by only a migration length in which a ratio of a real size of the equipment to a display size of the two-dimensional image on the display screen is considered.
US08022952B2 Generating a visualization to show mining results produced from selected data items and attribute(s) in a selected focus area and other portions of a data set
To visualize and analyze data, selection of at least one focus area in a visualization of a data set is received. Based on characteristics of the selected at least one focus area, using at least one analytic technique to mine relationships between data items and at least one attribute in the selected at least one focus area and data items and at least one attribute in remaining portions of the data set. At least one visual representation is generated to show mining results produced from selected data items and one or more attributes in the selected at least one focus area and the remaining portions of the data set, where the generated visual representation is composed to have an order and layout to represent the mined results.
US08022950B2 Stochastic culling of rays with increased depth of recursion
According to embodiments of the invention, rays may be stochastically culled before they are issued into the three-dimensional scene. Stochastically culling rays may reduce the number of rays which need to be traced by the image processing system. Furthermore, by stochastically culling rays before they are issued into the three-dimensional scene, minor imperfections may be added to the final rendered image, thereby improving the realism of the rendered image. Therefore, stochastic culling of rays may improve the performance of the image processing system by reducing workload imposed on the image processing system and improving the realism of the images rendered by the image processing system. According to another embodiment of the invention, the realism of images rendered by the image processing system may also be improved by stochastically adding secondary rays after ray-primitive intersections have occurred.
US08022948B2 Image capture and buffering in a virtual world using situational measurement averages
A technique is disclosed for detecting photo opportunities within a virtual environment. In response to detecting a photo opportunity, images of the virtual environment may be captured from perspectives not limited to the user's viewport. A variety of physiological and virtual world parameters are measured to determine when to capture an image of a user interacting with the virtual environment. To improve the quality of images, these parameters may be individually weighted by factors specified by the user. Captured images may be stored in a temporary buffer space, possibly replacing older images. The user may view the buffer contents and select ideal images to move to a permanent gallery. The user's image selections can in turn be used to further improve the quality of future images.
US08022947B2 Systems and methods for imaging waveform volumes
Systems and methods for imaging waveform volumes. An image of the waveform volume may be drawn on a display device as a two-dimensional image or a three-dimensional image of a sampling probe and redrawn in real-time at interactive rates using a graphics accelerator or a graphics card. The image of the waveform volume may also include seismic-data traces that are color-filled according to texture coordinates for pixels on the display device that intersect the waveform volume.
US08022945B2 Operational amplifier with constant offset and apparatus comprising such as operational amplifier
Apparatus (80) comprising an input stage (61) with an NMOS transistor doublet having a first differential input for receiving input signals, and a PMOS transistor doublet having a second differential input for receiving input signals. The apparatus (80) further comprises switching means for receiving and selectively directing analog input signals either to the first differential input or to the second differential input. The means are controlled by a switching signal (φ,φ) in a manner to keep the ratio of the transconductance of the NMOS transistor doublet and the transconductance of the PMOS transistor doublet constant.
US08022941B2 Multi-user touch screen
A multi-user touch-responsive viewing screen is described which uses frustrated total internal reflection in a slab of transparent material to illuminate the contact point between the slab and a finger or other object substantially matching the slab's index of refraction. Light, coupled upon touch, can be detected with a video camera, and used to determine both the position and pressure of the touch. Multiple touches can be accommodated and each touch accurately located. Projected images can be applied to the slab and a diffuser to construct an interactive touch screen.
US08022935B2 Capacitance sensing electrode with integrated I/O mechanism
A touch sensing device is disclosed. The touch sensing device includes one or more multifunctional nodes each of which represents a single touch pixel. Each multifunctional node includes a touch sensor with one or more integrated I/O mechanisms. The touch sensor and integrated I/O mechanisms share the same communication lines and I/O pins of a controller during operation of the touch sensing device.
US08022934B2 Handheld electronic device with text disambiguation and selective disabling of frequency learning
A handheld electronic device includes a reduced QWERTY keyboard and is enabled with disambiguation software. The device provides output in the form of a default output and a number of variants. The output is based largely upon the frequency, i.e., the likelihood that a user is likely to have intended a particular output, but various features of the device provide additional variants that are not based solely on frequency and rather are provided by various logic structures resident on the device. The device provides a learning function that allows the disambiguation function to adapt to provide a customized experience for the user. The learning function is disabled, however, when the relevant words are found to be in a special category for which frequency learning, i.e., frequency revision, is not employed.
US08022929B2 Pointing device for electronic equipment
In a pointing device for electronic equipment, the equipment includes a casing and a receiving space defined by the casing, and the pointing device includes a sensor unit, a column, and a joystick. The sensor unit is disposed in the receiving space. The column is disposed on the sensor unit, and is swingable relative to the sensor unit. The sensor unit is used to detect swinging state of the column. The joystick is mounted on the column, and is movable relative to the column between first and second positions. The joystick projects from an outer surface of the casing when at the first position, and is accommodated in the receiving space when at the second position. Thus, the joystick can be accommodated in the receiving space to avoid inadvertent actuation so as to enhance the convenience of carrying the electronic equipment.
US08022928B2 Free-space pointing and handwriting
A position detection method using one or more one-dimensional image sensors for detecting a light source (22) in free space is adapted for use as a portable free-space data input device (20) for controlling of a cursor (42) on the display (44) of a computer. A user of the portable free-space data input device (20) should move the portable free-space data input device (20) in free space to control the movement of the cursor on the display. This portable free-space data input device (20) can also be used as a free-space handwriting device. It is possible to adapt this pointing device in a design of a user-friendly remote control for a multimedia home entertainment system.
US08022925B2 Method for configuring 3D input device, method for reconfiguring 3D input device, method for recognizing wearing of the 3D input device, and the apparatus thereof
Provided are a method for configuring a three-dimensional (3D) input device, a method for reconfiguring the 3D input device, a method for recognizing wearing of the 3D input device, and an apparatus for the same. The method of configuring a three-dimensional (3D) input device, which performs information input operations using a finger device that is worn by a user and senses the user's finger movement, includes recognizing whether the user is wearing the finger device and recognizing the finger positions of the device, and adaptively configuring the 3D input device based on the recognition results. Thus, it is possible to implement a user-friendly 3D input device by automatically or manually configuring the 3D input device.
US08022924B2 Field sequential liquid crystal display and driving method thereof
A field sequential driving method includes the following steps. First, a liquid crystal display (LCD) including a display unit and a backlight unit is provided. The display unit includes several pixel units. Next, a white light source of the backlight unit is enabled during a first sub-frame period of a frame period of the LCD. Then, red and blue sub-pixel data are provided to drive a first sub-pixel and a second sub-pixel in the pixel unit during the first sub-frame period. Next, a green light source of the backlight unit is enabled during a second sub-frame period of the frame period. Thereafter, green sub-pixel data is provided to drive a third sub-pixel of the pixel unit during the second sub-frame period.
US08022922B2 Liquid crystal display and method of driving the same
A liquid crystal display (LCD) and a method of driving the same are provided. The LCD includes a liquid crystal panel partitioned into a plurality of panel regions, each panel region being independently driven and having data lines and gate lines; a backlight unit that is partitioned into a plurality of backlight regions corresponding to the plurality of panel regions and which irradiates light to the plurality of panel regions; and a driver unit driving the plurality of panel regions.
US08022917B2 LCD panel driving method and device with charge sharing
An LCD panel driving method and device with charge sharing is disclosed. The LCD panel includes a plurality of switches, a plurality of data lines, a signal driving circuit for generating a plurality of image signals, a charge sharing common voltage driving circuit and a common capacitor having one end connected to the charge sharing common voltage driving circuit through a common voltage node. The method turns the switches on to thereby form the charge sharing common voltage driving circuit and the signal driving circuit as a short circuit, such that charges stored in the common capacitor flow into the data lines to drive the common voltage node to enter in an inverse phase state in order to sequentially turn the switches on and then off to accordingly sample the respective data lines.
US08022916B2 Liquid crystal display driving device that reduces crosstalk
A liquid crystal display driving device that reduces horizontal crosstalk and a liquid crystal display employing the driving device are presented. The driving device includes a common voltage generator that generates first and second common voltages, and the common voltage generator includes a first capacitor provided between a first terminal for outputting the first common voltage and a second terminal for outputting the second common voltage. Since the capacitor is provided between two output terminals of the two common voltages, it reduces the distortion components of the common voltages, thereby reducing horizontal crosstalk. The invention reduces the number of parts in the driving device conferring the added benefit of reduced manufacturing cost.
US08022914B2 Display device and method for driving a display device with reduced power consumption
The invention concern a display device comprising a liquid crystal material between a first substrate provided with row electrodes (7) and a second substrate provided with column electrodes (6), in which overlapping parts of the row and column electrodes define pixels (8), driving means (5) for driving the column electrodes (6) in conformity with an image to be displayed, and driving means (4) for driving the row electrodes (7), wherein the row electrodes (7) select at least one row during a row selection time and column voltages (Gj(t)) are supplied to the column electrodes (6), wherein the column voltage waveform depends on the grey scale to be displayed by the driven pixel in a certain column and depends on a used selection signal (Fi) for the selected row, wherein a column voltage (Gj(t)) is switchable between at least two different column voltage levels during a row selection time. To provide a display device having low power consumption and in particular to minimize the number of transitions of the column driving signal the column voltage waveform for a following row selection time is mirrored on a mirror axis, if the column voltage at the end of the current row selection time is the same as the column voltage at the end of the following row selection time.
US08022912B2 Liquid crystal display device
In a liquid crystal display device performing multi-picture element driving, gate OFF timing of a switching element connected between each sub picture element and a signal line is matched with phase timing when all the subsidiary capacity wires are at the same potential. This prevents the occurrence of uneven luminance appearing in a lateral streak.
US08022905B2 Display device, driving method of the same and electronic apparatus using the same
A display device includes a pixel array section and a driving section. The pixel array section includes scanning lines arranged in rows, signal lines arranged in columns, and pixels arranged in a matrix. Each of the pixels includes at least a sampling transistor, a drive transistor, a holding capacitance, and a light-emitting device. The sampling transistor has its control terminal connected to the scanning line and its pair of current terminals connected between the signal line and the control terminal of the drive transistor. The drive transistor has one of its pair of current terminals connected to the light-emitting device and the other of its pair of current terminals connected to a power source. The holding capacitance is connected between the control and current terminals of the drive transistor.
US08022903B2 Organic EL device and organic EL display apparatus
In the present invention, there is provided an organic electro luminescence device including: an organic electro luminescence light emitting element; and a driving circuit for driving the organic electro luminescence light emitting element, wherein the driving circuit includes (A) an element driving transistor, (B) a video-signal write transistor, and (C) a capacitor having a pair of particular and other electrodes, with regard to the element driving transistor, (A-1) a source/drain area provided on a particular side of the element driving transistor to serve as a particular source/drain area of the element driving transistor is connected to a current supply section, and (A-2) a source/drain area provided on the other side of the element driving transistor to serve as another source/drain area of the element driving transistor is connected to the anode electrode of the organic electro luminescence light emitting element and the particular electrode of the capacitor, forming a second node.
US08022902B2 Organic light emitting display device and driving method thereof
An organic light emitting display device includes: a display area including a plurality of pixels coupled to scan, light emission control, and data lines; a scan driver electrically coupled to the display area through the scan lines and the light emission control lines; a data driver electrically coupled to the display area through the data lines; an optical sensor for generating an optical sensor signal corresponding to a brightness of an ambient light; a first luminance control unit for outputting a first luminance control signal for controlling a gamma-corrected gray level voltage of a data signal in accordance with the optical sensor signal, and a second luminance control unit for outputting a second luminance control signal for controlling a width of a light emission control signal in accordance with data of one frame of an image. The first luminance control unit turns the second luminance control unit on and off.
US08022899B2 EL display apparatus and drive method of EL display apparatus
A precharge voltage Vp is applied in period A. The precharge voltage Vp is generated by applying a constant current Iw to a pixel driving transistor of a display panel and using gate terminal voltage of the driving transistor which passes the constant current Iw. The gate terminal potential is held in memory. When displaying images on a display panel, the gate terminal potential is read out of memory, and used as the precharge voltage Vp after arithmetic processing. By the application of the precharge voltage Vp, a source signal line is charged and discharged quickly so that an almost target tone current will flow through the driving transistor. Furthermore, a more accurate program current is written into the pixel during period B.
US08022897B2 Method for driving plasma display panel
Disclosed is a method for driving a plasma display panel in which a plurality of first electrodes and second electrodes are arranged parallel to each other, a plurality of third electrodes are arranged to cross the first and second electrodes, and discharge cells defined with areas in which the electrodes cross mutually are arranged in the form of a matrix.According to the driving method, a reset period is a period during which the distribution of wall charges in the plurality of discharge cells is uniformed. An addressing period is a period during which wall charges are produced in the discharge cells according to display data. A sustain discharge period is a period during which sustain discharge is induced in the discharge cells in which wall charges are produced during the addressing period. The driving method in accordance with the present invention comprises a step of applying a first pulse in which an applied voltage varies with time so as to induce first discharge in the lines defined by the first and second electrodes, and a step of applying a second pulse in which an applied voltage varies with time so as to induce second discharge as erase discharge in the lines defined by the first and second electrodes. These steps are carried out during the reset period.
US08022896B2 ESD protection for MEMS display panels
A MEMS (Microelectromechanical system) device is described. The device includes an array of MEMS elements with addressing lines and MEMS switches configured to selectively connect the addressing lines to a ground or other potential in the event of an over-voltage, such as during an ESD event. The arrangement is particularly advantageous for protecting the array, because the MEMS switches can be formed using substantially the same processing steps which are used to form the array.
US08022893B2 Aspect-ratio independent, multimedia capture and presentation systems and methods thereof
A multimedia capture and presentation system includes a plurality of imaging systems and one or more detection systems. The plurality of imaging systems capture image areas of a scene from at least partially different locations. The one or more detection systems determine a relative position of each of the plurality of imaging systems with respect to the different locations of the scene from where the image areas are captured. The relative position of each of the plurality of imaging systems and the captured image areas are used to generate a multimedia presentation of the scene. The control system adjusts the output of the captured image areas from the plurality of projection systems to conform to a display environment. The one or more detection systems determine another relative position of each of the plurality of imaging systems with respect to the display environment on which the image areas are displayed. The plurality of imaging systems output the captured image areas for the multimedia presentation system. The control system adjusts the output from one or more of the plurality of imaging systems to generate the multimedia presentation based on the determined relative position of each of the plurality of imaging systems with respect to the different locations of the scene from where the image areas are captured and the determined relative position of each of the plurality of imaging systems with respect to the display environment on which the image areas are displayed.
US08022884B2 Circularly or linearly polarized antenna
The invention relates to an antenna that produces a radiation pattern that is axisymmetric about a geometrical axis (X) and exhibits a radiation maximum in a plane perpendicular to the direction of said X axis that includes a feed wire extending along said axis (X) from a first end situated level with a conducting surface forming an earth plane of the antenna to a second end that feeds a set of N radiating strands, N being an integer, characterized in that it also includes at least one earth return rod for the strands, said rod linking one of the radiating strands of the set to the earth plane.
US08022882B2 Antenna device for wireless wide area network (WWAN) and wireless local area network (WLAN)
An antenna device includes a grounding element, a radiating element, and first and second feeding elements. The radiating element includes a first segment that extends from the grounding element and that has an end distal from the grounding element, and second and third segments that extend from the end of the first segment in opposite directions. Each of the first and second feeding elements includes first and second segments. The first segment of each of the first and second feeding elements is disposed proximate to a respective one of the second and third segments of the radiating element. The second segment of each of the first and second feeding elements is disposed proximate to the grounding element.
US08022881B2 Multiband antenna
A multiband antenna comprises a ground plane, a substrate, and a radiating metal element, wherein a side of the substrate is substantially adjacent to a side of the ground plane; the radiating metal element is on a surface of the substrate. The radiating metal element comprises a radiating portion having a slit, a shorting portion having a first end electrically connected to the radiating portion and a second end electrically connected to the ground plane, and a feeding portion; the feeding portion comprises an antenna feeding point for electrically connecting to a signal source, wherein a first spacing is formed between the feeding portion and the radiating portion, and a second spacing is formed between the feeding portion and the shorting portion.
US08022878B2 RFID tag and manufacturing method thereof
An RFID tag having a tag antenna and an LSI chip, comprising: a power-supply pattern on which the LSI chip is mounted; a patch antenna that functions as the tag antenna; and a high-frequency connection section that makes a high-frequency connection between the power-supply pattern and the patch antenna. The high-frequency connection section is formed, for example, by forming a slot in the patch antenna, layering one end of a small dipole antenna that functions as the power-supply pattern over the slot so that it crosses over the slot, and supplying power from the small dipole antenna to the patch antenna.
US08022873B2 Methods and system for determining angles of sight between two devices
A method of determining angles of sight between a receiver device having at least two reception antennas and at least one transmitter device having at least one transmission antenna for the transmission of radioelectric signals including at least two wavelengths. The determining method is based on angular phase measurements of the radioelectric signals, which are measured modulo 2π and are therefore ambiguous since they are known to within an integer number of times 2π. The ambiguity in the phase measurements is resolved in the case of an application of the determining method to a receiver device dimensioned by applying a method of design of a system for determining angles of sight. A receiver device implements the determining method, and a system for determining angles of sight includes the receiver device and at least one transmitter device.
US08022871B2 Positioning device, electronic instrument, and storage medium storing program
A slice set for a specific period of time is acquired from a storage area of a memory which is a ring buffer while changing the read position, and the signal strength total value of each slice set is calculated. The signal strengths of the slices included in the maximum strength slice set and the signal strengths of the slices preceding or subsequent to the maximum strength slice set are calculated, and the final signal read position is determined based on a read offset of the maximum strength slice. A GPS satellite signal is acquired and tracked based on the slice read from the determined signal read position, and a specific positioning process is performed.
US08022870B2 Self monitoring GPS on mobile device
A method, a mobile device arid a computer program product for acquiring GPS on a mobile device possessing GPS capability are disclosed. The method comprises the step of setting a current value of the period of the power-up phase of the GPS dependent upon adaptive predictions of when the GPS should be powered on to meet specifications on positioning accuracy and GPS acquisition time.
US08022867B2 Satellite-positioning-system tracking device and method for determining a position of the same
A global navigation satellite system-tracking (“GNSS-tracking”) device and method for determining one or more positions of the GNSS-tracking device utilizing a user-plane service is disclosed. The GNSS-tracking device may comprise: charging and tracking modules adapted to be disengagably coupled together, wherein the tracking module comprises (i) tracking circuitry for determining at least one position of the tracking module using the user-plane service in a satellite positioning system, and (ii) a chargeable source for supplying power to the tracking circuitry when disengaged from the charging module, and wherein the charging module is operable to charge the chargeable source when the charging module is coupled to the tracking module.
US08022864B2 Detection of transient signals in doppler spectra
Signal processing is used to detect transient signals in the presence of noise. Two embodiments are disclosed. In both embodiments, the time series from a remote sensor is broken into a number of short time series. The power spectrum of each short time series are then calculated along with the mean noise level. The moments of each peak in every power spectrum are calculated and the peak with the largest power selected from each power spectrum. A histogram of the moments from these selected peaks is generated and normalized to become a measured PDF. In addition, a pre-determined PDF is derived, in the same method as above, from theoretically calculated noise, numerically simulated noise, or measured noise. Comparison between the measured and pre-determined PDF's establish the detection of a transient signal. The first embodiment compares the area between the measured and pre-determined PDF's against a threshold to determine detection. In a second embodiment, the differences between the measured and pre-determined PDF's are weighted and summed to form a score. This score is compared to a threshold to determine detection.
US08022861B2 Dual-band antenna array and RF front-end for mm-wave imager and radar
The radar includes a PCB having a top surface and a bottom surface, and a processor mounted on the bottom surface of the PCB. The radar includes a second liquid crystal polymer layer formed on the top surface of the printed circuit board, a second microstrip array printed on the second liquid crystal polymer layer, the second microstrip array having a patch, a first liquid crystal polymer layer formed on the second liquid crystal polymer layer, a first microstrip array printed on the first liquid crystal polymer layer, the first microstrip array having a perforated patch, an antenna positioned underneath the patch and connected to the second microstrip array, and a transmit/receive module connected to a bottom surface of the second liquid crystal polymer layer and configured to transmit a first frequency signal to the first microstrip array and a second frequency signal to the second microstrip array.
US08022857B2 Radar reflector
A submarine warfare radar training system 10 includes an underwater vehicle 15 towing a float device 40 and a radar reflective target 45. The radar reflective target 45 is configured as a hollow tube-shaped element 50 having circular open leading and trailing open circular end to allow water to flow through the target as it is towed. The target 45 includes a positive buoyancy material layer 60 and is horizontally oriented during towing. The float device 40 is configured to support the radar reflective target 45 open leading end above the water surface 30 as the float device 40 and radar reflective target 45 are towed along the water surface to deliver air into the hollow cross-section. The radar reflective target 45 has an adjustable RCS which can be increased or decreased by lengthening or shortening the radar reflective target.
US08022856B2 Successive approximation type A/D converter, method of controlling successive approximation type A/D converter, solid-state imaging device, and imaging apparatus
A successive approximation type A/D converter includes: a reference signal generating section generating a reference signal; a comparator comparing an analog signal input thereto with the reference signal and converting the analog signal into a digital signal; and a control section controlling the reference signal to perform oversampling by executing an A/D conversion process on the analog signal at the comparator plural times such that the analog signal is A/D-converted into a digital value of N bits at the first A/D conversion process and such that the second and subsequent A/D conversion processes are performed starting with a lower bit of the (N−n)-th or lower order with upper n bits of the N-bit digital value obtained at the first A/D conversion process fixed.
US08022855B2 Analog/digital converter
An A/D converter includes a plurality of comparators that performs sampling of a plurality of reference voltages and analog input signals during a sampling time, and compares each of the plurality of reference voltages with each of the plurality of analog signals during a comparison time. The A/D converter detects bubbles in thermometer codes obtained from output signals of the plurality of comparators and adjusts a ratio of the sampling time and the comparison time of the plurality of comparators so as to reduce the bubbles.
US08022850B2 Multiple-bit, digital-to-analog converters and conversion methods
Embodiments include DACs and methods for digital-to-analog conversion. A DAC includes an encoder and a plurality of DAC elements. The encoder maps each of a plurality of bits of a digital input value to one of the DAC elements, and produces a sign indication indicating whether a magnitude of the digital input value is above or below a threshold. Each DAC element produces a DAC element analog output signal that indicates whether a received sign indication and a received bit corresponds to a first state, a second state or a third state (e.g., a zero, positive or negative state). In an embodiment, the DAC uses positive historic mapping information when the magnitude of the digital input value is above the threshold, and negative historic mapping information when the magnitude of the digital input value is below the threshold. DAC elements may be configurable into a Return-to-Zero or a Non-Return-to-Zero mode.
US08022849B2 Phase to digital converter in all digital phase locked loop
A phase to digital converter, all digital phase locked loop, and apparatus having an all digital phase locked loop are described herein. The phase to digital converter includes a phase to frequency converter driving a time to digital converter. The time to digital converter determines a magnitude and sign of the phase differences output by the phase to frequency converter. The time to digital converter utilizes tapped delay lines and looped feedback counters to enable measurement of small timing differences typical of a loop tracking process and large timing differences typical of an loop acquisition process. The tapped delay lines permit the measurement of fractions of a reference period and enable lower power operation of the phase to digital converter by reducing requirements on the speed of the reference clock.
US08022847B2 Signal processing device
A signal processing device, even when a steep difference in DC level is included in a signal read from a disc such as a DVD-RAM format, cuts off the DC level and pulls the read signal into an appropriate A/D input level. A steep difference in DC level between a data section and a CAPA section is absorbed by a first offset unit, and an asymmetry which occurs due to variations in the disc manufacturing stage is corrected by a second offset unit. Further, a control signal for operating the two offset units exclusively is generated by a controller, thereby controlling both offset units.
US08022845B2 Vehicle monitoring and identification system
A vehicle monitoring and traffic enforcement system in which a wireless communication device is associated with motor vehicles. The device will transmit vehicle identification data which is relayed to a database which maintains current information concerning insurance law compliance, motor vehicle registration and licensing compliance, traffic citations and other information. If a violation or compliance failure is noted, this is transmitted to a law enforcement agency and a nearby law enforcement vehicle. A law enforcement officer may be required to pursue the vehicle depending on the violation and traffic conditions. The system uses GPS and GIS technology to provide law enforcement with a real time display which will not only show the vehicle being tracked but also a map of the area showing roads, traffic conditions and even the location of other law enforcement or emergency vehicles so that officials may make a safe and fast response to situations. In another embodiment, the device may be a device such as an RFID tag which can be scanned and interrogated by a law enforcement official and which may be used for traffic and also parking control.
US08022832B2 Methods and systems for certifying provenance of alcoholic beverages
A system for certifying provenance of an alcoholic beverage includes a radio-frequency identification tag and a server. The radio-frequency identification tag, associated with a bottle containing an alcoholic beverage, periodically measures a plurality of values of an environmental condition of the bottle. The radio-frequency identification tag stores the plurality of measured values. The server receives the plurality of measured values for analysis. The server provides, via a user interface, a description of a provenance of the alcoholic beverage, the description generated responsive to an analysis of the plurality of measured values.
US08022831B1 Interactive fatigue management system and method
Systems and methods of detecting fatigue and drowsy conditions of vehicle drivers without initially using any disruptive visual and sound alarms, and instead immediately interacting with the driver as to their condition and providing information on rest stops through onboard GPS (global positioning satellite) systems, as well as alerting acquaintances and friends of the driver through telephones such as a cellular phone. The systems and methods can interact with the driver through touch type screens, and/or audible feedback to alert the driver of their condition and to temporarily take the driver off the roads.
US08022830B1 Lifeguard alarm system for a swimming pool
A lifeguard alarm system for a swimming pool has a sensing device, at least one electromagnetic wave receiver and a host, the sensing device capable of attaching onto a user; wherein when the sensing device detects the more than two conditions, an microprocessor in the sensing device sends a signal to the at least one electromagnetic wave receiver disposed around the swimming pool and wirelessly connected to the host, and the host sends out an alarm. Furthermore, includes a fail-safe mechanism; therefore, when the first detecting mechanism of the sensing device detects that the user is not in the corresponding predetermined dangerous state, to prevent malfunctioning of the first detecting mechanism from creating problems.
US08022824B2 Anti-intrusion system for protecting electronic components
The subject of the invention is an anti-intrusion system for protecting electronic components (3) including a substrate (2) on which the electronic components are placed. A conducting enclosure (1) encapsulates the electronic components on the surface of the substrate (2). The system also includes a warning device. The system includes a transmitting antenna on the surface of the substrate (2), and a capacitive electromechanical microswitch. The microswitch is linked to the warning device by a signal line, so as to be able to activate it.
US08022820B2 User configured display system for motor vehicle
The present invention is directed toward a data acquisition and display system for vehicles that connects to the vehicle's on-board computer(s) via a data link connector (DLC). The system includes a display module suitable for permanent or temporary attachment within the interior of a vehicle. The display module preferably includes a full color monitor that also functions as a touch screen for inputting commands to the computer within the display module. The computer includes a suitable processor, operating system, software and tangible data storage media to allow multiple user configurable graphics. The display module collects information from the vehicle via multiple busses and senders through the data link connector and displays the information on the screen of the display module in a user configured graphics format. The software is constructed and arranged to allow user configuration of the displayed graphics by clicking or touching the graphics image.
US08022819B2 Electronic control apparatus and method for controlling alarm systems of cellular structure
Electronic control apparatus (20) and method for controlling cellular alarm systems (10/11), wherein, by means of sensors (201) of the control apparatus (20), physical measurement parameters (202) of occurring measurement events (203) are triggered and are filtered on the basis of predefined threshold values (204). The alarm systems (10/11) are selected and activated electronically if at least one of the threshold values (204) is exceeded. For the purpose of activation, dedicated activation signals (101) are generated by means of the control apparatus (20) and transmitted to the alarm systems (10/11). By means of a counter module (21) of the control apparatus (20), the generated activation signals (101) are cumulated, as a counter signal (211), within a predefined time window (205) upon each activation. After expiry of the time window (205), the cumulated counter signal (211) is weighted dynamically on the basis of geographical location parameters (2021) and physical measurement parameters (2022) of the measurement parameters (211) by means of a topographical grid (31), and stored in a grid-based topographical lookup table (25). The activation signals (101) transmitted to the alarm systems (10/11) are generated in a grid-cell-wise graduated manner on the basis of the dynamic lookup table elements (251) the alarm systems (10/11) activated accordingly.
US08022818B2 Warning apparatus for a motor vehicle
Warning apparatus (2) for a motor vehicle (1) having an indicator system (6) for indicating a change of lane comprising at least one signal display (7) arranged in the field of view of the driver and having a sensor system for detecting obstacles in the blind spot (4), wherein the sensor system generates a warning signal in the event of detection of an obstacle, wherein the signal display (7) of the indicator system (6) is connected to the sensor system such that the warning signal is reproduced in visual form via the signal display (7).
US08022816B2 System and method for field management using radio frequency tags
A system and methods are provided for field administration of a project, such as construction, maintenance, safety inspections or other projects involving the tracking of issues and one or more levels of review or approval in the closure of the issues. One or more radio frequency tags, each having an identifier, can be affixed to a physical component of a project. A storage device can store an issue list, wherein the issue list has one or more work items corresponding to the physical component of the project on which the radio frequency tag is affixed. User interfaces may be provided to allow interaction by stationary or mobile users with the issue list. The issue list on the storage device may provide better organization and/or a more efficient work flow, particularly during a close-out phase, or other phase of a project, involving the tracking of issues.
US08022814B2 Systems and methods for slot classification
Systems and methods for inventory round slot classification are described. The method includes transmitting, to zero or more RFID tags, a message during a slot of an inventory round and receiving a response from at least some of the zero or more RFID tags. The method also includes analyzing a received response for the presence of the pilot tone and classifying a respective slot in response to the analysis.
US08022809B2 Inventory taking system
A system which is able to take inventory of products stored in high rise racks and immediately provide the inventory information to an information system for immediate processing and which makes use of remote electronic identification means for each product, box, etc. and each row of a correspondent rack, thus allowing the system to read great amounts of information at once.
US08022808B2 Vehicle power door control with passive entry
A vehicle equipped with a passive key entry system may employ a method of controlling a vehicle power sliding door(s) or other door(s), to accomplish locking, unlocking, opening and closing of such doors. A switch on a door handle may be activated by a physical touch or touches of a user, after which, the method may proceed with inquiring and confirming if all vehicle doors are closed; inquiring and confirming if all vehicle doors are locked; inquiring and confirming if a valid passive entry key is exterior to and within range of the vehicle; unlocking a power sliding door with a lock motor; and opening the power sliding door with a door motor. Before actually performing a door opening, closing or locking, a passive entry key system on the vehicle may verify the presence of a passive entry key fob.
US08022806B2 Fluid pressure sensor package
A fluid pressure sensor package can be easily assembled to have different types of probe tubes depending upon different application environments. The sensor package includes a sealed casing accommodating a sensor chip for sensing a pressure of a fluid introduced into the casing. A probe tube extends from the casing for introducing the fluid into contact with the sensor chip. The casing has a top opening, and has a side wall formed on its interior surface with a stepped shoulder for bearing a flange at the lower end of the probe tube. The flange is sealingly bonded to the sidewall of the casing by a sealer. Since the probe tube is prepared as a separate member from the casing, the casing can be a common base for various probe tubes having fluid channels of different lengths or diameters.
US08022800B2 Field coil assembly for electromagnetic clutch
A field coil assembly for an electromagnetic clutch, which includes an electromagnetic coil body formed by winding an electromagnetic coil; a bobbin for supporting the electromagnetic coil body; a field core for receiving the bobbin and the electromagnetic coil body; a holder mounted to the electromagnetic coil body; and a thermal fuse installed to the holder to be connected to the electromagnetic coil body, wherein the holder having the thermal fuse installed thereto is provided with an elastic member for elastically supporting the thermal fuse upwards. Thus, the height of the thermal fuse installed to the holder can be adjusted.
US08022797B2 Superconducting coil apparatus and inductor-type synchronous machine
This superconducting coil apparatus includes: a cylindrical coil container which has an inner circumferential surface and an outer circumferential surface; a superconducting coil which is stored in the coil container to be cooled so that a superconducting member is wound on the inner circumferential surface; and a columnar magnetic body which is fitted to the inner circumferential surface of the coil container.
US08022795B2 Variable impedance adapter for tuning system performance
A variable impedance adapter that has a value of characteristic impedance that is responsive to changes in the configuration of the adapter. In one embodiment, the variable impedance adapter includes an elongated section and a telescoping section that surround a center conductor that transmits an electrical signal across the adapter. A pair of tuning elements is disposed on a portion of the center conductor, one or more of the elements being shaped and configured to move along the center conductor amongst a plurality of positions in response to relative movement between the elongated section and the telescoping section. The first position and the second position correspond to different values of characteristic impedance of the variable impedance adapter.
US08022789B2 Tuning control arrangement
A tuning arrangement for a resonant circuit, the tuning arrangement having an output reactance dependent upon a plurality of input applied signals one of which is an input tuning signal, and including: an array of tuning circuits connected in a network whose output reactance is used to control the resonance frequency of the resonant circuit, each tuning circuit having a control input and having a reactance which varies in dependence upon the value of a control signal applied to the control input; elements for generating a plurality of different control signals for application to the control inputs of the tuning circuits; and each such control signal varying substantially linearly with the input tuning signal throughout a predetermined range specific to that control signal, so that the frequency response of the resonant circuit to the input tuning signal is substantially linear throughout a desired range of the input tuning signal.
US08022788B2 Filter with crosses
The invention relates to a process for the production of a microwave waveguide having a step of determining the zone or zones of the waveguide where an electric field concentration occurs. A step of produces at least one enlargement of the waveguide in the zone or zones thus determined. The invention also relates to a microwave filter in which the stubs are provided with such enlargement. The invention has application in microwave filters.
US08022787B2 Duplexer, module including a duplexer and communication apparatus
A duplexer includes a common terminal, receiving filters, a transmitting filter, and a hybrid having four terminals (terminals 1 to 4). A first terminal (terminal 1), which is one of the four terminals of the hybrid is connected to the common terminal, the receiving filters are connected to a second terminal and a third terminal to which a signal is transmitted if it is input from the first terminal, and a transmitting filter is connected to a fourth terminal (terminal 4) of the hybrid. Thus, it is possible to improve the isolation of the duplexer, while avoiding an increase in the number of parts as well as greater complexity.
US08022784B2 Planar transmission line-to-waveguide transition apparatus having an embedded bent stub
A wireless communication module includes a plurality of monolithic millimeter-wave integrated circuits (MMICs) for signal processing attached to the top surface of a multi-layer low temperature co-fired ceramic substrate; a planar transmission line formed on the top surface of the multi-layer substrate for communications between the MMICs; a metal base attached to the bottom surface of the multi-layer substrate and having an opening to which an antenna is attached; a plurality of vias for connecting the metal base and the planar transmission line within the multi-layer substrate to establish a uniform potential on a ground plane of the multi-layer substrate; an embedded waveguide formed in the opening surrounded with the vias within the multi-layer substrate; and a planar transmission line-to-waveguide transition apparatus for the transition of waves between the planar transmission line and the embedded waveguide.
US08022782B2 Two-point phase modulator and method of calibrating conversion gain of the same
A two-point phase modulator and a method of calibrating conversion gain of the same are provided. The two-point phase modulator locks an output frequency signal by charging and pumping charge in a phase-locked loop (PLL) circuit at the beginning of operation, opens a loop of the PLL circuit for a period of time, and applies a step signal, thus calibrating conversion gain of a modulation signal that controls the output frequency signal. Thus, the conversion gain may be accurately calibrated by the calibration operation at one time.
US08022781B2 Redundancy system for a telecommunication system and related methods
A redundancy system for a co-channel telecommunication system and related methods. Implementations of the redundancy system may include at least a first modulator and a second modulator having a symbol mapper coupled to a parallel bit signal. The symbol mapper may be configured to route each of a plurality of parallel bits received through the parallel bit signal to a plurality of significant bit signals. In a first implementation, a plurality of significant bit signal multiplexers may be used to switch the plurality of parallel bit signals to allow the first and second modulators to operate in either a redundant or operating mode. In a second implementation, a premapped symbol (PMSI) encoder and a PMSI decoder may be used to transmit the plurality of significant bit signals across an interface bus as a real dual-data rate (DDR) signal and an imaginary DDR signal.
US08022779B2 Integrated circuit oscillators having microelectromechanical resonators therein with parasitic impedance cancellation
An integrated circuit oscillator includes a microelectromechanical (MEM) resonator having input and output terminals. An oscillation sustaining circuit is provided. The oscillation sustaining circuit is electrically coupled between the input and output terminals of the microelectromechanical resonator. The oscillation sustaining circuit includes a sustaining amplifier and a negative impedance circuit electrically coupled to the sustaining amplifier. The negative impedance circuit is configured to increase a tuning range of the oscillator by at least partially cancelling a parasitic shunt capacitance associated with the microelectromechanical resonator.
US08022776B2 Origami cascaded topology for analog and mixed-signal applications
The present disclosure relates to coupled circuits and methods of coupling circuits having a power supply wherein a plurality of transistors are inductively coupled directly to the power supply for providing a single DC supply voltage directly to each of the plurality of transistors, and wherein a plurality of transformers have primary and secondary windings, the primary and secondary windings providing, at least in part, inductive loads for inductively coupling the plurality of transistors to the power supply, the plurality of transformers also providing an AC signal path for coupling neighboring ones of the plurality of transistors together.
US08022775B2 Systems and methods for maintaining a drive signal to a resonant circuit at a resonant frequency
Systems and methods for maintaining a drive signal to a resonant circuit at a resonant frequency are provided. A system for maintaining a drive signal to a resonant circuit at a resonant frequency can include: an oscillator configured to provide an output to a phase comparator and a drive circuit, the drive circuit configured to provide a drive signal to a resonant circuit; a phase detector configured to receive a filtered version of the drive signal from the resonant circuit and provide a phase-indicating signal to the phase comparator; and the phase comparator, wherein the phase comparator is configured to provide a signal based on the phase difference between the oscillator output and the phase-indicating signal, wherein the signal from the phase comparator is used to control the frequency of the oscillator such that the phase difference converges to a fixed value.
US08022774B2 Phase-locked loop circuit, recording-and-reproducing apparatus, and electronic apparatus
A phase-locked loop circuit includes a phase detection unit which detects phase information of an input signal, a loop filter unit including a series circuit of a resistor and a capacitor, first and second pulse-current output units which supply pulse currents corresponding to the phase information output to one and the other of the resistor and the capacitor, and an oscillating unit capable of varying an oscillation frequency in accordance with a component obtained by combining a voltage generated at both ends of the one of the resistor and the capacitor on the basis of the pulse current supplied from the output terminal of the first pulse-current output unit and a voltage generated at both ends of the other one of the resistor and the capacitor on the basis of the pulse current supplied from the output terminal of the second pulse-current output unit.
US08022773B2 Clock signal generation device, and wireless base station
A wireless base station (11) includes a wireless communication unit (17) and a clock signal generation unit (20). The clock signal generation unit (20) includes a voltage-controlled oscillation unit (21) that outputs a clock signal of an oscillating frequency according to an inputted control voltage, a time information generation unit (22) that generates time information based on the clock signal, a time information comparison unit (23) that compares the time information with reference time information; and a control voltage instruction unit (24) that instructs a control voltage according to the comparison result to the voltage-controlled oscillation unit (21). Accordingly, the oscillating frequency of the clock signal can be kept easily and highly precisely.
US08022770B1 System and method for preventing power amplifier supply voltage saturation
A system for preventing power amplifier supply voltage saturation includes a multiple stage voltage regulator configured to provide a regulated voltage, a power amplifier configured to receive the regulated voltage, and a saturation protection circuit configured to apply a current into a first stage of the multiple stage voltage regulator when the regulated voltage reaches a reference voltage, the applied current causing a subsequent stage of the multiple stage voltage regulator to prevent the regulated voltage from exceeding the reference voltage.
US08022761B2 Error driven RF power amplifier control with increased efficiency
A power amplifier controller for adjusting a supply voltage to a power amplifier. The power amplifier controller adjusts the supply voltage so that distortion in an RF output signal corresponds to a predetermined limit. An amplitude error signal is generated by the power amplifier controller which represents a difference between an RF output signal and an attenuated RF output signal. The AC components of the amplitude error signal are processed to generate a deviation signal that represents the distortion in the RF output signal. The supply voltage to the power amplifier is increased when the deviation signal exceeds a distortion level control signal, and decreased when the deviation signal drops below the distortion level control signal.
US08022759B2 Dynamic range improvements of load modulated amplifiers
The present invention relates to methods and devices to control and operate the functionality of a power amplifier system (100) capable of operating in at least three differential amplification modes. The drive signal's amplitude envelope controls an integrated switch network (104; 105, 106) that routes both the signal envelope and signal phase to different modulation blocks (111, 112: 109, 110: 115). Depending on the envelope strength, the operational mode of the amplifier system is possible to alter to best serve the signal statistics to provide the highest overall power efficiency.
US08022758B2 Impedance matching circuit and method thereof
A circuit comprises an amplifier circuit and a trimming circuit. The amplifier circuit includes an operational amplifier. The operational amplifier has a first input configured to receive input signals, and the operational amplifier also has a second input and an amplifier output. One of the first input or the second input is a negative input. The trimming circuit is coupled to the amplifier output. The trimming circuit includes a termination resistor coupled in parallel with at least one trimming resistor. The termination resistor is coupled to a first switch in series, and the trimming resistor is coupled to a second switch in series. The amplifier output is connected back to the negative input through the first switch.
US08022756B2 Output circuits with class D amplifier
Output circuits using pulse width modulation (PWM) and/or pulse density modulation (PDM) are described. In one aspect, a PWM output circuit includes a PWM modulator that operates based on a square wave signal instead of a sawtooth or triangular wave signal. In another aspect, a PDM output circuit includes a PDM modulator that uses variable reference voltages to reduce variations in switching frequency. In yet another aspect, a dual-mode output circuit supports both PWM and PDM and includes a pulse modulator and a class D amplifier. The pulse modulator performs PWM on an input signal if a PWM mode is selected and performs PDM on the input signal if a PDM mode is selected. The class D amplifier receives a driver signal from the pulse modulator and generates an output signal.
US08022755B2 Amplifier with automatic gain profile control and calibration
Embodiments of the present invention provide systems and methods for automatic amplifier gain profile control, including a method for automatically configuring a variable gain profile amplifier according to received input and a variable gain profile amplification system. Further, embodiments of the present invention provide systems and methods for increased gain profile accuracy, including methods and systems to reduce the effects of temperature and/or process variations on the gain profile of an amplifier.
US08022754B2 Demodulation circuit
A demodulation circuit, including: an input terminal (IN) inputting a current amplitude modulated signal; a first transistor (101) connected to the input terminal; a capacitance (105) connected to a control terminal of the first transistor; a diode (102) connected between the input terminal and the control terminal of the first transistor; and a first current source (104) applying a current of the input terminal, is provided.
US08022753B2 Semiconductor integrated circuit with intermittent power supply operation of circuit blocks
A semiconductor integrated circuit that carries out intermittent operation, includes a processor block; an logical operation block other than a processor; a first switch part configured to supply a normal operation voltage to the logical operation block other than a processor; a second switch part configured to supply the normal operation voltage to the processor block; a third switch part configured to supply a data holding voltage lower than the normal operation voltage to the processor block; and a fourth switch part configured to be turned on, when the second switch means is turned off and the third switch means is turned on, and supply the data holding voltage to the processor block.
US08022752B2 Voltage reference circuit for low supply voltages
A voltage reference circuit and method for generating a reference voltage using the circuit uses a comparison of the voltages on first and second nodes of a diode resistor network to produce a comparison signal, which is then used to increase the voltage on an output of a charge pump to generate the reference voltage.
US08022748B2 Power source circuits for driving liquid crystal displays
This invention is suitable for use in the field of integrated circuits. It provides a type of power source circuit. Said power source circuit includes: a charge pump circuit used to operate the charge pump to produce driving voltages; a first control circuit, used in the closed-loop control of said charge pump circuit to produce a positive high voltage; a bias-ratio circuit, used with the positive high voltage and the zero-potential voltage produced by the first control circuit to produce a positive sub-high voltage and a lowest positive high voltage; and a second control circuit, used in accordance with the positive sub-high voltage and the lowest positive high voltage produced by said bias-ratio circuit in the closed-loop control of said charge pump circuit to produce a negative high voltage. Using this invention, the system contains no voltage higher than the liquid crystal's driving voltages, and also does not contain any lower negative voltage than the liquid crystal's highest negative driving voltage, thereby reducing the circuit's electrical consumption.
US08022745B1 High voltage switch using multiple cascode circuits
The present invention is a high voltage semiconductor switch that is formed from a chain of series coupled cascode circuits. In one embodiment, the switch may be a single-throw configuration coupled between an output and a direct current (DC) reference. In an alternate embodiment, the switch may be a double-throw configuration such that the output is switched between either a first DC reference or a second DC reference, such as ground. Each cascode circuit may have clamp circuits to prevent over voltage during switching transitions. The series coupled cascode circuits may be formed using discrete components or on a silicon-on-insulator (SOI) wafer, which may have a Silicon Dioxide insulator layer or a Sapphire insulator layer.
US08022744B2 Signal generator
Embodiments include a signal generator circuit for generating a time-varying signal, comprising capacitive element; FET to supply to or from the capacitive element a current matched to the FET drain current; a bias voltage generator to provide a bias voltage to the FET gate, wherein: the capacitances per unit area of the capacitive element and the FET gate are matched; the bias voltage is substantially equal to a sum of a first voltage substantially proportional to a reference voltage and a second voltage substantially proportional to temperature; the FET source-gate voltage substantially equal to the sum of the bias voltage and the gate threshold voltage, the bias voltage and a further voltage approximately equal to the gate threshold voltage summed to determine the FET source-gate voltage, the circuit to control a time period of the time-varying signal dependent on the current supply.
US08022743B2 Pulse width modulation circuit and liquid jet printing apparatus
A pulse width modulation circuit includes: a reference signal generator which generates a plurality of mutually differing reference signals; a comparator which compares the reference signals and an input signal with respect to magnitude, and outputs results of the comparison as a plurality of comparison signals with mutually differing phases; and a synthesizer which, using a logical operation, outputs the plurality of comparison signals output from the comparator as a pulse width modulated signal configured of one or more binary signals.
US08022742B2 Circuit for reducing duty distortion in a semiconductor memory device
A circuit for outputting an amplified clock signal is disclosed. The circuit includes a first input terminal for inputting a first clock signal, a second input terminal for inputting a second clock signal, a first amplifier circuit for amplifying the first clock signal and outputting a first amplified clock signal at a first output terminal, and a second amplifier circuit for amplifying the second clock signal and outputting a second amplified clock signal at a second output terminal. The circuit additionally includes a level maintenance circuit connected to the first output terminal and the second output terminal. The circuit further includes an output circuit connected to the first output terminal and the second output terminal and configured to output a further amplified clock signal based on the first amplified clock signal and the second amplified clock signal. The level maintenance circuit is configured to reduce duty distortion in the further amplified clock signal.
US08022740B2 Fast-response phase-locked loop charge-pump driven by low voltage input
Phase-locked loop charge pump driven by low voltage input. In one aspect, a phase-locked loop circuit includes a phase frequency detector operating at a low voltage and providing low-voltage sourcing control signals and low-voltage sinking control signals at the low voltage. A charge pump operates at a high voltage and includes a sourcing control circuit coupled to the low-voltage sourcing control signals and selectively causing the charge pump to source the sourcing current to an output of the charge pump based on the low-voltage sourcing control signals. The charge pump also includes a sinking control circuit that receives the low-voltage sinking control signals and selectively causes the charge pump to sink the sinking current from the output of the charge pump based on the low-voltage sinking control signals.
US08022739B2 Charge pump circuit
A charge pump circuit and a method of compensating current mismatch in a charge pump circuit. The charge pump circuit comprises a core charge pump circuit; a replica charge pump circuit for sensing a current mismatch in the core charge pump circuit and for converting the sensed current mismatch into a voltage signal V_ctrl; wherein V-ctrl is utilized for compensating the current mismatch in the core charge pump circuit.
US08022734B1 Low current power detection circuit providing window comparator functionality
A power detection system is disclosed that includes a detector circuit and a comparator circuit. The detector circuit includes a first transistor, a second transistor that is not identical to the first transistor, and a third transistor that is substantially identical to the first transistor. Each of the transistors is commonly coupled to a current source and is coupled to a differential input voltage. The comparator circuit is for providing an output that is representative of whether the input voltage is above or below a threshold voltage responsive to a difference between the first transistor and the second transistor.
US08022731B2 Advanced repeater with duty cycle adjustment
An advanced repeater with duty cycle adjustment. In accordance with a first embodiment of the present invention, an advanced repeater includes an output stage for driving an output signal line responsive to an input signal and a plurality of active devices for selectably adjusting a duty cycle of the signal. The advanced repeater may further include circuitry for producing a delayed version of the signal.
US08022730B2 Driving circuit with slew-rate enhancement circuit
A driving auxiliary circuit receiving an input voltage to control an output voltage of an operational amplifier via a first switch and a second switch is provided. A pull-low circuit turns on the first switch, including a first input terminal coupled to a high voltage source providing a high voltage and a first output terminal for controlling the voltage level of the output voltage. The output voltage is charged to be equal to the input voltage when the input voltage exceeds the output voltage. A pull-high circuit turns on the second switch, including a second input terminal coupled to the high voltage source providing the high voltage and a second output terminal for controlling the voltage level of the output voltage. The output voltage is discharged to be equal to the input voltage when the output voltage exceeds the input voltage.
US08022729B2 Signal driver circuit having adjustable output voltage for a high logic level output signal
A signal driver circuit having an adjustable output voltage for a high-logic level output signal. The signal driver circuit includes a signal driver configured to output a first logic level signal having a first voltage and output a second logic level signal having a second voltage according to an input signal. A voltage controlled voltage supply coupled to the signal driver provides the first voltage for the first logic level signal. The magnitude of the first voltage provided by the voltage controlled voltage supply is based on a bias voltage. A bias voltage generator can be coupled to the voltage controlled voltage supply to provide the bias voltage.
US08022728B2 Common-mode voltage controller
A common-mode voltage controller for adjusting common-mode voltages between a first buffer and a second buffer at a subsequent stage or a preceding stage of the first buffer in a signal transmission circuit, comprising: a first reference voltage generation unit for generating a common-mode voltage corresponding to the first buffer; a second reference voltage generation unit for generating a common-mode voltage corresponding to the second buffer at the subsequent stage or the preceding stage; and a control signal generation unit for generating a control signal for controlling a common-mode voltage of the first buffer according to a difference voltage between an output of the first reference voltage generation unit and an output of the second reference voltage generation unit, and giving the control signal to the first buffer and first reference voltage generation unit.
US08022727B2 Electronic clamps for integrated circuits and methods of use
An electronic clamp is provided for an integrated circuit having a first voltage island (1) to which an output signal (clamp out) of the clamp is applied and a second voltage island (2) operative to produce an input signal (clamp in) to the clamp, where power to the second voltage island can be switched off to save power. The clamp comprises a latch (22) which stores or retains the clamp value (0 or 1) of the input signal (clamp in) during a reset period and clamps the output signal (clamp out) to the stored or retained value in response to a clamp enable signal, (clamp in) in order to protect the first voltage island from a non-stabilised input signal.
US08022725B2 Convertible logic circuits comprising carbon nanotube transistors having ambipolar charateristics
A convertible logic circuit includes a plurality of carbon nanotube transistors. Each carbon nanotube transistors are configurable as p-type or an n-type transistors according to a voltage of a power source voltage. Each carbon nanotube transistor includes a source electrode, a drain electrode, a channel formed of a carbon nanotube between the source electrode and the drain electrode, a gate insulating layer formed on the carbon nanotubes, and a gate electrode formed on the gate insulating layer.
US08022724B1 Method and integrated circuit for secure reconfiguration of programmable logic
Approaches for secure configuration of a programmable logic integrated circuit (IC). In one approach, a method includes programming configuration memory of the programmable logic IC with a first configuration bitstream. At least a portion of a second configuration bitstream is encrypted using values stored in a portion of the configuration memory as a key. The second configuration bitstream is input to the programmable logic IC, and the encrypted portion of the second configuration bitstream is decrypted using the values stored in the portion of the configuration memory. The configuration memory is then programmed with each decrypted portion of the second bitstream.
US08022722B1 Quantum logic gates utilizing resonator mediated coupling
Systems and methods are provided for performing a quantum gate operation. A first classical control parameter, configured to tune an associated frequency of a first qubit, is adjusted from a first value to a second value. The first value is selected such that the first qubit is tuned far from a characteristic frequency of an associated resonator, and the second value is selected such that the first qubit is tuned near to the characteristic frequency of the resonator. A second classical control parameter, configured to tune an associated frequency of a second qubit, is adjusted from a third value to a fourth value. The third value is selected such that the second qubit is tuned far from the characteristic frequency of the resonator. The first classical control parameter is returned to the first value. The second classical control parameter is returned to the third value.
US08022721B2 Conveyor-based memory-module tester with elevators distributing moving test motherboards among parallel conveyors for testing
A conveyor-stack test system has motherboards that test memory modules. The motherboards are not stationary but are placed inside movable trays that move along conveyors. A loader-unloader removes tested memory modules from test sockets on the motherboards and inserts untested memory modules into the motherboards using a robotic arm. A conveyor carries the motherboards from the loader-unloader to an elevator. The elevator raises or lowers the motherboards to different levels in a conveyor stack with multiple levels of conveyors each with many test stations. The motherboards move along conveyors in the conveyor stack until reaching test stations. A retractable connector from the test station extends to make contact with a motherboard connector to power up the motherboard, which then tests the memory modules. Test results are communicated from the test station to a host controller, which instructs the loader-unloader to sort the tested memory modules once the motherboard returns.
US08022719B2 Carrier tray for use with prober
A carrier tray for use with a prober is arranged to allow the prober to measure or test not only semiconductor wafers but also semiconductor packages and accurately position each of different-shaped semiconductor packages. A carrier tray includes a lowermost tray and an uppermost tray interposing therebetween an intermediate tray. The lowermost and uppermost trays and are each of a circular shape having a diameter D1. A diameter D3 of the intermediate tray is smaller than the diameter D1. The intermediate tray is centrally formed with a screw hole portion in which a locking spacer screw is screwed. A semiconductor package is to be placed in a package holding pocket. With the locking spacer screw, the intermediate is slidable in an X and Y directions, so that the X and Y coordinates of the semiconductor package are determined uniquely relative to the carrier tray.
US08022718B2 Method for inspecting electrostatic chucks with Kelvin probe analysis
A method of inspecting an electrostatic chuck (ESC) is provided. The ESC has a dielectric support surface for a semiconductor wafer. The dielectric support surface is scanned with a Kelvin probe to obtain a surface potential map. The surface potential map is compared with a reference Kelvin probe surface potential map to determine if the ESC passes inspection.
US08022716B2 Dielectric breakdown lifetime enhancement using alternating current (AC) capacitance
A time-to-breakdown for a dielectric layer in a semiconductor device is determined based upon a sudden change in capacitance. An alternating voltage, greater in magnitude than an operating voltage of the device, is applied to the semiconductor device, capacitance is measured across the dielectric layer during the application of the voltage until a sudden change in capacitance occurs, thereby indicating a breakdown in the dielectric layer, and the breakdown time is scaled to the operating voltage.
US08022713B2 Method for measuring antenna characteristics out operational frequency range of chamber
There is provided to a method for measuring antenna characteristics operating in an out-of-operational frequency range of a chamber, in the chamber having a predetermined operational frequency range, including the steps of: a) measuring reflected wave characteristics of the out-of-operational frequency range generated within the chamber; b) measuring the characteristics of a measurement target antenna operating in the out-of-operational frequency range of the chamber; and c) measuring final characteristics of the measurement target antenna by compensating the characteristic data of the measurement target antenna measured in the step b) for reflected wave data measured in the step a).
US08022712B2 Testing adapter
The invention relates to a testing adapter suitable for testing a wireless telecommunication device. The testing adapter comprises a first contact member and a second contact member, the first contact member and the second contact member having at least one degree of freedom relative to each other and arranged to provide an attachable and detachable mechanical coupling with a surface of a component recess of the wireless telecommunication device on the basis of the at least one degree of freedom.
US08022711B2 Wire fault locating in distributed power systems
An electrical fault locating system for distributing power from an input to a plurality of output channels provides fault detection and locating for each of the plurality of output channels. Each of the plurality of output channels is monitored by a fault detection circuit to detect the presence of an electrical fault. In response to a detected fault condition, the fault detection circuit isolates the output channel from the input and generates an output identifying the output channel on which the fault was detected. A fault locating device injects a high-frequency (HF) signal onto the input of the electrical system, the HF signal is distributed to each of the plurality of output channels, and the monitored reflection of the HF signal is monitored by the fault locating device to calculate a distance to the detected fault. The distance calculated by the fault locating device is combined with the channel identification provided by the fault detection circuit to generate a specific location associated with the detected fault.
US08022710B2 Methods for common mode voltage-based AC fault detection, verification and/or identification
Methods for AC fault (ACF) detection are provided. In addition, methods for AC fault (ACF) detection and verification are provided. In addition, methods for identification of a module which is the cause of an AC fault (ACF) are provided. In one implementation, one or more of these methods can be combined to provide a fast, simple, low cost and reliable ACF detection, verification and/or identification.
US08022707B2 Methods and apparatus for determining a presence of a non-conductive coating on electrodes in downhole fluid resistivity measurement devices
Methods and apparatus for determining a presence of a non-conductive coating on electrodes in fluid resistivity measurement devices are described. An example method of determining a presence of a non-conductive coating on electrodes of a fluid resistivity measurement device involves obtaining a first electrical potential value associated with a substantially uncoated condition of first and second electrodes of a fluid resistivity measurement device. The example method also involves measuring a second electrical potential value at a location between the first and second electrodes, comparing the first and second electrical potential values, and determining the presence of a non-conductive coating on at least one of the first and second electrodes based on the comparison.
US08022706B2 Silent and thin RF body coil
An imaging subject (16) is disposed in an examination region (12) for examination. A cover (18) is disposed around the examination region (12). Magnetic field gradient coils (30) impose selected magnetic field gradients on a main magnetic field (B0) within the examination region (12). A radio frequency (RF) coil (36) generates radio frequency excitation pulses in the examination region (12), the radio frequency coil (36) including a plurality of coil elements (381, 382, 383) disposed on the cover (18) distally from the examination region (12). A radio frequency (RF) screen (40) associated with the coil elements (381, 382, 383) shields the coil elements (381, 382, 383) and is disposed about the gradient coils (30) such that the coil elements (381, 382, 383) are mechanically decoupled from the RF screen (40) and substantially acoustically isolated from the RF screen (40) and gradient coils (30).
US08022704B2 Method for producing a magnetic resonance image of an object having a short T2 relaxation time
A method for producing a magnetic resonance image using an ultra-short echo time. The method includes applying a pulse sequence to an object, detecting a spirally encoded and phase encoded magnetic resonance signal associated with the object, and reconstructing the magnetic resonance image based on the spirally encoded and phase encoded magnetic resonance signal. The pulse sequence includes a slab-selective radiofrequency pulse, a slab-selective gradient pulse, a plurality of variable duration slice encoding gradient pulses, a plurality of first spiral encoding gradient pulses, and a plurality of second spiral encoding gradient pulses. The detection of the spirally encoded and phase encoded magnetic resonance signal occurs concurrently with the application of one of the plurality of first spiral encoding gradient pulses and with the application of one of the plurality of second spiral encoding gradient pulses.
US08022701B2 Method and apparatus for simultaneously acquiring multiple slices/slabs in magnetic resonance system
Provided is a method for simultaneously acquiring magnetic resonance slices/slabs of a subject. The method comprises steps as follows. First, apply one or more than one RF pulse, which carries at least two frequency components, and a slice/slab selection magnetic field gradient so that at least two slices/slabs of the subject respectively corresponding to the at least two frequency components are excited simultaneously. Second, apply a spatial encoding magnetic field gradient. Third, apply a slice/slab separation magnetic field gradient so as to separate the at least two slices/slabs. The method according to the present invention can be used to acquire data for simultaneously reconstructing multiple slices/slabs. The method is compatible with existing MRI systems.
US08022691B2 Microminiature gauging displacement sensor
A device for providing displacement information includes a housing holding a displacement sensor. The displacement sensor includes a coil and a captive core. An electrical measurement of the coil provides information about displacement of the core. The coil has an axis extending in a first direction, wherein the housing has a minimum outside dimension that is less than 3.00 mm when measured perpendicular to that first direction. The housing has an inner surface having a housing inside dimension. The housing is for holding a displacement sensor and a guidance mechanism. The displacement sensor includes a coil and a captive core having a core outside dimension. The guidance mechanism includes a first part and a second part for guiding the core. The first part includes a bearing connected to the housing. The bearing has an axial hole having a hole dimension about equal to the core outside dimension. The core slidably extends through this axial hole. The second part has a second part outside dimension about equal to the housing inside dimension. The guidance mechanism is for resisting lateral movement and lateral rotation of the core while allowing axial movement of the core into and out of the coil.
US08022685B2 Temperature dependent voltage source compensation
A circuit and a method for regulating a voltage supply where the method includes the steps of concurrently measuring temperature, IR drop and frequency response within the circuit, adjusting voltage supplied to the circuit in response to the measured temperature, IR drop and frequency response, and determining a correction value based on the variance of the measured frequency response from an expected frequency response and providing a correction for subsequent predetermined frequency response values. The frequency response measurement is dependent upon the constant bandgap voltage source which may very according to temperature. Upon a determination that corrections may be required for the bandgap voltage source to compensate for temperature variations, the measurement process which uses the bandgap voltage source can be altered to compensate for the temperature variations.
US08022684B2 External regulator reference voltage generator circuit
Disclosed is an external regulator reference voltage generator circuit that precisely controls the supply voltage applied to core logic to optimize the operational characteristics of the core logic 120 without using excessive power. An adaptive voltage and scaling optimization circuit 124 is used to detect the operating parameters of the core logic 120 and generate a voltage control signal to control a reference voltage regulator. The reference voltage regulator generates a regulator reference voltage in response to the voltage control signal that controls an external regulator which, in turn, generates the supply voltage.
US08022681B2 Hybrid low dropout voltage regulator circuit
A voltage regulator circuit includes a digital control block, an amplifier and a transistor. The digital control block receives a first reference voltage and a feedback voltage, converts the received voltages from analog to digital signals, performs an integration operation on the converted signals, and converts the result of the integration operation to an analog signal. The amplifier is responsive to the output of the digital control block and to a regulated output voltage of the regulator circuit. The transistor has a first terminal responsive to the output of the amplifier, a second terminal that receives the input voltage being regulated, and a third terminal that supplies the regulated output voltage. The transistor may be an NMOS or a bipolar NPN transistor. The feedback voltage may be generated by dividing the regulated output voltage. The digital control block optionally generates a biasing signal to bias the amplifier.
US08022679B2 Systems and methods for fast switch turn on approximating ideal diode function
A switching circuit approximating the fast switching characteristics and small forward voltage drop of an ideal diode is provided. The switching circuit may include a voltage multiplier circuit, a reservoir capacitor and a pull up switch configured to be coupled to the control terminal of a semiconductor switch.
US08022678B2 Power supply device
A power supply device includes first and second power factor correctors, and first and second resonant circuits. The first and second power factor correctors are for receiving an alternating current (AC) input voltage, and are driven by first and second driving signals for rectifying the AC input voltage to generate first and second driving voltages, respectively. The first and second resonant circuits are coupled to the first and second power factor correctors for receiving the first and second driving voltages, respectively, and have output sides that are coupled in parallel for outputting an output voltage. The first power factor corrector and the first resonant circuit in combination is parallel-connected to the second power factor corrector and the second resonant circuit in combination.
US08022677B2 Electrical device and operating method
An electrical device having a generator, e.g., for use in the vehicle electrical system of a motor vehicle, includes a controller for controlling the generator voltage. In the device, an area is provided in which a voltage control is carried out, and other areas are provided in which a torque control is carried out.
US08022675B2 Detection of the supply state of a load supplied by a variable voltage
A method and a circuit for detecting the state of supply of a load by a variable voltage, including measuring the difference between values representative of the variable supply voltage and of a voltage across the load.
US08022672B2 Charger control circuit and charger control method
The present invention discloses a charger control circuit and a charger control method for controlling a charger having a transformer, the transformer including a primary winding and a secondary winding. The charger control circuit comprises: a power switch coupled to the primary winding; a switch control circuit controlling the operation of the power switch; and a detection circuit which generates a signal according to a voltage at a node between the power switch and the primary winding, and supplies the signal to the switch control circuit.
US08022668B2 Charger
A charger includes a shell assembly defining a receiving space therein, a locating body fixed in the shell assembly and defining a locating cavity and a plurality of locating fillisters communicating with the locating cavity, and a plug pivotally received in the receiving space and having a base portion and at least two conductive blades fixed partially in the base portion. The base portion protrudes oppositely to form a pair of pivoting shafts pivoted in the shell assembly. A free end of one of the pivoting shafts defines a locating pillar pivoted in the locating cavity of the locating body. A side surface of the locating pillar protrudes outward to form a plurality of locating ribs buckled into the corresponding locating fillisters of the locating body when the conductive blades of the plug are completely rotated into and out of the receiving space.
US08022665B2 Bidirectional power converting device
A bidirectional power converting device coupled between first and second power storage units includes: a coupling circuit including a first winding coupled to the first power storage unit, and a second winding coupled in series to the first winding; first and second switches coupled to the first winding; a capacitor coupled between the first and second switches; a third switch coupled between the second winding and the capacitor; and a fourth switch between the second winding and the second power storage unit. The first, second, third and fourth switches are operable so that an input voltage supplied by one of the first and second power storage units is converted into an output voltage that is to be supplied to the other one of the first and second power storage units.
US08022664B2 Battery charger
A battery charger includes a housing, an electrical connector, magnets, and sensors. The electrical connector with a magnet attached thereon is received in the housing. The electrical connector is connected to the rear wall of the housing via an elastic member. The electrical connector is capable of extending out of the housing and through an opening in the housing. Another magnet is secured at a front end of the housing. When an attractive force is induced between the magnets, the electrical connector is extended towards and through the opening in the housing. The sensors are configured for detecting that a robot is in position to be charged and for turning on the attractive force between the magnets.
US08022658B2 Motor control system including electrical insulation deterioration detecting system
A motor control system of the present invention includes an accurate electrical insulation deterioration detecting system. A voltage divider circuit is arranged between a negative DC output portion and a ground, through a normally open switch circuit. A detecting operation control section closes the normally open switch while a circuit breaker is opened, and places at least one of transistors electrically connected to a positive DC output portion into a conductive state, from among six transistors included in three arm circuits. A voltage across the first resistor is inputted as a divided voltage into a voltage comparator of a voltage comparison section. The voltage comparison section compares a divided voltage outputted from the voltage divider circuit and a reference voltage using the voltage comparator and outputs an alarm signal if the divided voltage exceeds the reference voltage.
US08022654B2 Soft start for electric motor of a power tool
A power tool has an electric motor with field windings. Each field winding includes two coils. When the motor is first energized, the two coils of each field winding are connected in series, reducing in-rush current. Upon expiration of a soft start period, the two coils of each field winding are connected in parallel. In another aspect, the field windings that are connected in series with a separate start winding when the motor is first energized. Upon expiration of the soft start period, the start winding is bypassed. In another aspect, the field windings are connected in series with a start impedance when the motor is first energized and a time delay relay having a set of delay contacts coupled across the start impedance energized. Upon expiration of the soft start period, the time delay contacts close, bypassing the start impedance. In an aspect, the motor is a universal motor.
US08022652B2 Method for controlling a mechanically communicated electric motor
A method for controlling a mechanically commutated electric motor, wherein the rotational angle of the output of said motor is determined by means of detection of the change in back electromotive force, when the electric motor commutates, and wherein the power supply to the electric motor is halted after a predetermined number of detected commutations.
US08022647B1 Gas water heater actuator
A system and method for enabling automated activation of a temperature control shaft of a gas valve includes an electric motor having a motor shaft and integral coupler, wired to a relay control circuit and controlled by a standard electric timer device.
US08022644B2 Gas discharge lamp ignition
Ignition of a gas discharge lamp 10, which has a gas containing main space and two inner electrodes, of a lighting unit 4 of a lighting system is achieved by the use of a high frequency resonance circuit. The resonance circuit is connected to the inner electrodes and to a supply device 2, which supplies an alternating supply voltage. An outer electrode 22 is arranged near one the inner electrodes and to a node of the resonance circuit. Upon supplying the supply voltage a high voltage alternating burst will be generated at the outer electrode. This will result into a discharge of the gas in the main space. In turn, this will induce a discharge of the remaining gas. Then the frequency of the supply voltage will increase and a small reactive current only will remain to flow through the resonance circuit.
US08022641B2 Recessed LED down light
In an embodiment of the present invention, a light emitting diode (LED) recessed down light fixture comprises a housing, a reflector assembly mounted to the housing, and an LED circuit board attached to the housing over the reflector assembly. The LED circuit board includes a plurality of resistors electrically connected to the LED circuit board, a bridge rectifier, and a plurality of at least 80 miniature LEDs electrically connected to the LED circuit board and configured to provide light. The plurality of miniature LEDs are separated into a plurality of LED clusters. Each cluster is electrically connected to at least one resistor. Further, the plurality of miniature LEDs are arranged in a configuration such that a voltage differential across any two proximate LEDs is less than 36 volts. The down light fixture further comprises a lens cover attached to the top end of the reflector assembly.
US08022639B2 Dimming fluorescent ballast system with shutdown control circuit
A ballast system for, and a method of, controlling illumination of a lamp, include a dimmer switch having an actuator settable at different settings corresponding to different output voltages across the dimmer switch, a dimming electronic ballast operatively connected to an electrical power source and to the dimmer switch for dimming the lamp upon setting of the actuator, and a shutdown circuit, preferably provided in the ballast, for measuring the output voltages across the dimmer switch, and for automatically powering the ballast off and, in turn, for turning the lamp off when one of the voltages measured by the shutdown circuit does not exceed a reference voltage that corresponds to one of the settings of the actuator.
US08022637B2 Method for detection of non-zero-voltage switching operation of a ballast of fluorescent lamps, and ballast
A method detects a non-zero-voltage switching operation of a lamp ballast, the lamp ballast including a half-bridge circuit with a first and a second semiconductor switching element, a resonant circuit connected to the half-bridge circuit, and a snubber capacitance connected in parallel with one of the semiconductor switching elements. The method includes obtaining a voltage measurement signal representative of a voltage at an output of the half-bridge circuit. The method also includes providing a comparison signal representative of a comparison of the voltage measurement signal with a reference value. The method further includes evaluating the comparison signal in each case before the first semiconductor element is switched on and in each case before the second semiconductor element is switched on, and detecting one of a first and second non-zero-switching operations based on these evaluations.
US08022636B2 Control of delivery of current through one or more discharge lamps
Control of delivery of current through one or more discharge lamps. Methods include alternately switching on and off switching elements that control a fluorescent lamp, in response to receiving input, until the brightness of the lamp decreases to a threshold. Further, methods include providing control signals at complementary duty cycles to further decrease the brightness and alternating the duty cycles of the signals applied to the filaments of the fluorescent lamp.
US08022635B2 CCFL controller with multi-function terminal
A cold cathode fluorescent lamp controller exhibiting a multi-function terminal and operative alternately in a strike mode and a run mode, the controller comprising: a phase locked loop arranged for synchronization of an oscillator, associated with the controller, with an external signal, the phase locked loop comprising a capacitor coupled to the multi-function terminal; and a soft start circuit arranged to limit drive current immediately after reset of the controller responsive to a signal at the multi-function terminal. In one embodiment the controller further comprises an error detection circuit arranged to output an error signal on the multi-function terminal. In one embodiment the controller further comprises a frequency sweeping circuit operative to sweep the frequency of a drive signal during the strike mode of the controller, the frequency of the drive signal being swept by the frequency sweeping circuit responsive to a signal at the multi-function terminal.
US08022633B2 Display device using electron source elements and method of driving same
In the case where the number of pixels is increased in a display device making use of electron source elements, a period, in which one pixel is caused to continue to emit light, shortened, and so there is caused a need of applying a high voltage between upper and lower electrodes of an electron source element in a short period. Therefore, there is caused a problem that a drive circuit is made severe in operating condition and so the display device is degraded in reliability. Two TFTs are arranged on each of pixels. Also, a time gradation system is used, in which one frame period is divided into a plurality of sub-frame periods, a light emitting or non-emitting state of each of the pixels is selected in the respective sub-frame periods, and gradation is represented by adding up periods, in which the light emitting state is selected in the respective sub-frame periods. Thus it is possible to provide a display device having a high reliability and a method of driving the same.
US08022630B2 High intensity discharge lamp with corrosion-resistant electrical connector
An arc discharge lamp (10) has an envelope (12) including a base (14) containing lead-ins (16, 18). An arc tube (20) is positioned within the envelope (12) and has electrodes (22, 24) sealed therein. The electrodes have connection ends (26, 28) extending outside of the arc tube (20). A flexible primary electrical connector (30) is fixed between one of the lead-ins (16) and one of the connection ends (26) of one of the electrodes (22), the flexible primary electrical connector (30) having an area “A” subject to intergranular corrosion in the presence of oxygen and arc tube operating temperatures. A rigid secondary, intergranular-corrosion-resistant electrical connector (32) is electrically connected between the lead-in (16) and the one of the connection ends (26) of the one of the electrodes (22), the rigid secondary electrical connector (32) by-passing the area “A” that is subject to intergranular corrosion.
US08022629B2 Plasma display panel and method for manufacturing the same
A plasma display panel having a dielectric with a stepped structure and a method for manufacturing the same are disclosed. The plasma display panel includes a first panel comprising a plurality of electrode pairs each including a scan electrode and a sustain electrode, and a dielectric layer formed over the electrode pairs, a second panel comprising a plurality of address electrodes arranged to cross the plurality of electrode pairs, and barrier ribs formed on the second substrate, to define discharge cells. The dielectric layer includes recesses respectively arranged between two electrodes arranged in each discharge cell and between two electrodes arranged adjacent to each other at opposite sides of each barrier rib.
US08022627B2 Electrodeless high pressure discharge lamp
An electrodeless high pressure discharge lamp is described. The lamp includes a resonating body configured to provide microwave energy and a discharge vessel, the discharge vessel containing a fill that forms a light-emitting plasma when receiving the microwave energy. The lamp further includes an outer bulb surrounding the discharge vessel. The lamp further includes a support structure within the outer bulb, the support structure comprising a plurality of wires forming a cage, wherein each end of each of the plurality of wires are directed to either end of the discharge vessel. The lamp further includes a first wire structure configured to hold the discharge vessel in place within the cage and surrounding each end of the discharge vessel.
US08022625B2 Electro-luminescence device for improved display quality by suppressing irregularity of the gap and method of manufacturing electro-luminescence device
There is provided an electro-luminescence device in which a display base substrate including a display body layer having a switching element disposed in the shape of a matrix and a light emitting element having a light emitting state controlled by the switching element and a sealing layer having a gas barrier layer that is formed on the display body layer and has at least a function for blocking water vapor and a protection substrate made of a translucent material and having a surface on which at least two types of gap control layers made of different materials are stacked are bonded such that a gap control layer, disposed on the uppermost layer, of the gap control layers and the gas barrier layer are brought into contact with each other, wherein the gap control layer disposed on the uppermost layer has a Young's modulus lower than the gas barrier layer.
US08022624B2 Moisture protection for OLED display
An OLED display, comprising: a substrate; an OLED having two spaced-apart electrodes and organic layers disposed therebetween and the OLED being disposed over the substrate; first desiccant material disposed over at least a portion of one of the electrodes; a compliant protection layer having a Young's Modulus <4 GPa disposed over at least a portion of the first desiccant material; and an encapsulation container fixed to the substrate and disposed over the compliant protection layer.
US08022622B2 Organic light-emitting display device including a photo diode
An organic light emitting display device including: a substrate having a pixel region and a non-pixel region; a first buffer layer and a second buffer layer formed over the substrate; a thin film transistor formed over the second buffer layer; an organic light emitting device formed in the pixel region and electrically connected with the thin film transistor; and a photo diode formed in the non-pixel region, for receiving external light of red wavelength at a certain absorption rate, and for controlling brightness of the organic light emitting device. Here, the first buffer layer can be formed to be from 2900 Å to 3100 Å in thickness, the second buffer layer can be formed to be from 200 Å to 400 Å in thickness, and the photo diode can include: an N-type doping region, a channel region being from 3 to 10 μm in width, and a P-type doping region.
US08022620B2 Display device for improving chromatic purity
A display device includes a substrate, light-emitting elements formed on the substrate, a reflective layer disposed between the substrate and the light-emitting elements and reflecting the light emitted from the light-emitting elements. The light-emitting elements each include a transparent layer that contact the reflective layer, a light-emitting layer disposed on the upper surface of the transparent layer, and an electrode layer with transparency disposed on a side of the light-emitting layer. The distance between the reflective layer and the electrode layer in each of the light-emitting elements is set such that a light component of a specific color in the light emitted from the corresponding light-emitting layer is enhanced by interference and emitted from the electrode layer. The light-emitting elements include light-emitting elements in which blue and red light components in the light emitted from the light-emitting layers are simultaneously enhanced and emitted from the electrode layers.
US08022615B2 Light generating layer for a reflective display
A self emission device (644) that emits light (526). The self emission device can include at least one light emission layer (104) encompassing an area, and generating light over such area in a distributed fashion. The self emission device also can include a first electrode (113) interfacing with a first side (116) of the light emission layer and a second electrode (114) interfacing with a second side (117) of the light emission layer. The first electrode and the second electrode can provide energy used by the light emission layer to illuminate. The self emission device can be a component of a display (100) comprising a reflective display panel (102).
US08022614B2 Display panel and method for manufacturing the same
A display panel includes pixels with a light emissive layer and an electrode layer deposited on the light emissive layer. A first pixel is determined by a first barrier structure and a second pixel, adjacent to the first pixel, is determined by a second barrier structure. The first and second barrier structures are separated by an electrically conductive structure in electrical contact with the electrode layer. Accordingly, space is available between the barrier structures for electrical shunting of the electrode layer.
US08022612B2 White-light LED having two or more commonly controlled portions with improved angular color performance
A light-emitting diode device, includes a substrate; and a light-emitting element having two or more commonly-controlled portions, the light-emitting element having two electrodes and a common unpatterned white-light-emitting layer formed between the two electrodes, at least one portion having an optical spacer, each portion having a different optical structure, the optical structure in one portion being tuned to emit substantially white light and that one portion having a transparent electrode, and the optical structure in a different portion being tuned to emit colored light.
US08022611B2 Light emitter substrate and image displaying apparatus using light emitter substrate
There is provided a light emitter substrate which can suppress halation by forming a rib between adjacent light-emitting members of respectively different light emitting colors, and at the same time can withdraw a potential difference when a discharge occurs between adjacent metal backs, thereby achieving a desired discharging current suppressing capability. For that purpose, the plural parallel ribs protruding from a substrate are formed, a phosphor is provided between the adjacent ribs, plural divided metal backs are disposed respectively on the phosphors in the direction along the ribs, the metal back is connected to a feeding resistor on the rib by means of a connection conductor, and the feeding resistor is covered by a high-resistance cover member.
US08022607B2 Plasma lamp with small power coupling surface
In an example embodiment, an electrodeless plasma lamp is, provided which comprises a dielectric body having an effective dielectric constant greater than two. The dielectric body may have a surface with a first region coated with an electrically conductive material and a second region that is not coated with the electrically conductive material. A bulb is located proximate to the second region of the dielectric body and having an outer surface area and the second region may have an uncoated surface area that is less than about sixty percent (60%) of the outer surface area of the bulb. A power source is coupled to the dielectric body to provide radio frequency power to the dielectric body at a frequency that resonates at a fundamental mode in the dielectric body. The bulb contains a fill that forms a plasma when the radio frequency power is provided from the dielectric body through the second region.
US08022602B2 Piezoelectric resonant power generator
A method for generating power in a wellbore includes moving an actuator; inducing an oscillating stress on a piezoelectric component with the actuator; and generating a voltage with the piezoelectric component in response to the induced stress on the piezoelectric component.
US08022601B2 Piezoelectric-coated carbon nanotube generators
A generator includes a first conductive layer, a plurality of elongated piezoelectric nanostructures and a conductive electrode. The piezoelectric nanostructures extend upwardly from the first conductive layer and include a carbon nanotube core and a piezoelectric sheath enveloping at least a portion of the carbon nanotube core. Each piezoelectric nanostructure includes a first end disposed adjacent to the first conductive layer and an opposite second end. The conductive electrode is disposed adjacent to the second end of each of the piezoelectric nanostructures. The conductive electrode is configured so that a Schottky barrier is formed between the second end of at least one of the piezoelectric nanostructures and the conductive electrode when a force is applied to the generator that causes the conductive electrode to touch the piezoelectric nanostructures and to induce stress in the piezoelectric nanostructures.
US08022599B2 Actuator
An actuator includes: a substrate; a fixed electrode provided on a major surface of the substrate; a first dielectric film provided on the fixed electrode, and made of crystalline material; a movable beam opposed to the major surface, and held above the substrate with a gap thereto; a movable electrode; and a second dielectric film. The movable electrode is provided on a surface of the movable beam facing the fixed electrode, and has an alternate voltage applied between the fixed electrode and the movable electrode. The second dielectric film is provided on a surface of the movable beam facing the fixed electrode, and is made of crystalline material.
US08022596B2 Guided electromechanical motor
An electromechanical actuator arrangement (50) comprises an electromechanical motor (10) and a rail arrangement (35). The rail arrangement (35) has a rail (30) relative which the electromechanical motor drives in a main displacement direction (3). The electromechanical motor has electromechanically active actuators attached to a motor block (20) and are arranged to provide an actuating action against the rail. The rail arrangement has further at least one guide member (31) provided parallel to the main displacement direction. The guide members have a guiding surface (36) facing the motor block. The motor block in turn has guidance surfaces (37) facing the guiding surface of the guide members. The guiding surface or the guidance surface has a tangent line parallel to the main displacement direction. The other one of the guiding surface and the guidance surface has a tangent surface in a second plane parallel to the first plane
US08022595B2 Asymmetric composite acoustic wave sensor
A composite acoustic wave device provides improved protection from environmental factors while maintaining high electrical characteristics and dynamic range is provided. The device comprises a rigid protector plate having high quality acoustical characteristics and a thickness which is a multiple of half wavelength of the resonant frequency. A piezoelectric plate is coupled to the protector plate, is supported therefrom, and forms an energy interface therewith. The piezoelectric and protector plates are dimensioned such that a wave of resonant frequency traveling between the excitation face and the loaded/sensing face, forms a substantially continuous-phase wave, at substantially peak amplitude, at the energy interface. By doing so the device decouples the electrical thickness of the wave device from the mechanical thickness thereof.
US08022593B2 Electrical machine
An axial flux electrical machine is provided. The machine includes a plurality of rotors, each sandwiched between a respective pair of stator parts. The plurality of rotors, together with their respective stators, are axially-stacked to form a multistage machine. Heat exchangers are provided adjacent each stator to provide cooling. Each rotor disc is a composite rotor disc in which permanent magnets are embedded. The magnets are embedded in apertures through each disc so that surfaces of the magnets are flush with surfaces of the respective rotor disc.
US08022592B2 Coil fixing member and rotary electric machine
Each coil fixing member is placed between a stator coil and at least one end surface of a stator core in an electric rotary machine in order to suppress a displacement between the stator core and the stator coil. The coil fixing member consists of a spacer and a bolt. The bolt and a corresponding screw hole formed on an end surface of the stator core are used to fix the stator core in the electric rotary machine. The spacer consists of a main body part and a bolt fixing part. The bolt fixing part has a bolt hole. The main body part has a tapered shape. The main body part is placed between the end surface of the stator core and connection parts of windings of the stator coil, and fixed to the stator core by the bolt through the bolt hole of the bolt fixing part.
US08022584B2 Stator of a dynamoelectric machine equipped with temperature detection
A stator for a dynamoelectric machine includes a stator body having slots and a winding system positioned in the slots of the stator body and having coils terminating in winding heads on end faces of the stator body, wherein each slot receives different coil sides of neighboring coils. Arranged between the coil sides in at least one of the slots is a temperature sensor to ascertain a temperature in the stator, in particular between the coil sides of the winding system in the slots of the stator.
US08022579B2 Brownout solution for electromechanical automatic transfer switch
A circuit for dynamically increasing the drop-out voltage of an electromechanical automatic transfer switch (ATS) into a brownout voltage range is provided. The automatic transfer switch includes a first input, a first coil connected to the first input, and a first, normally-open auxiliary contact in magnetic communication with the first coil. The circuit includes a first resistor adapted to connect to the first, normally-open auxiliary contact, and a first transformer having a primary winding connected to the first resistor, and a secondary winding adapted to connect to the first coil. An operating voltage across the first coil is reduced a proportional amount by a secondary voltage across the secondary winding when the first, normally-open auxiliary contact is closed.
US08022578B2 Electric power supply cut-off circuit and liquid droplet discharge apparatus
An electric power supply cut-off circuit comprises an IC which outputs a normal operation signal when the IC is operated normally, a switch which makes connection or disconnection between the IC and a power source, and a switching control circuit which continuously outputs a connection instruction signal during a period in which the normal operation signal is inputted from the IC, wherein the switch connects the IC and the power source when the connection instruction signal is inputted, and the switch cuts off the connection between the IC and the power source when the connection instruction signal is not inputted. Accordingly, it is possible to reliably avoid any excessive increase in the temperature of the IC and the ignition of the IC.
US08022576B2 Wireless non-radiative energy transfer
The electromagnetic energy transfer device includes a first resonator structure receiving energy from an external power supply. The first resonator structure has a first Q-factor. A second resonator structure is positioned distal from the first resonator structure, and supplies useful working power to an external load. The second resonator structure has a second Q-factor. The distance between the two resonators can be larger than the characteristic size of each resonator. Non-radiative energy transfer between the first resonator structure and the second resonator structure is mediated through coupling of their resonant-field evanescent tails.
US08022574B2 Maximum voltage source selector
A maximum voltage source selector adapted for use in a semiconductor device operative in a disable state or an enable state is disclosed. The maximum voltage source selector includes an output unit having an output node providing a maximum voltage selected from a first input voltage and a second input voltage. First and second gate transistors are commonly coupled to the output node and are respectively configured to select and provide the greater of the first and second input voltages to the output node in response to first and second selection signals without regard to whether the semiconductor device is in the disable state or the enable state. A selection unit generates the first and second selection signals in response to the first and second input voltages.
US08022573B2 Shipping container active lock release failsafe
A lock mechanism to lock at least one door of a container in a closed position includes a housing enclosing at least a portion of the lock mechanism, and a lock circuit at least partially enclosed within the housing. The lock circuit includes a main power supply, a backup power supply, a plurality of subsystems, and a lock controller coupled to the main power supply and the backup power supply. The lock controller is configured to receive commands related to operation of the lock mechanism, determine a battery level remaining in the main power supply, determine if the remaining battery level is below a threshold level, and cause the lock circuit to enter a lower power mode upon determining that the remaining battery level is below the threshold level. When in the lower power mode, at least a portion of the subsystems of the lock circuit are not powered, the lock controller receives power from the main power supply, and the lock controller monitors an interface to detect a command to unlock the lock mechanism.
US08022572B2 Genset system with energy storage for transient response
A power generating system having a variable speed genset is provided. The variable speed genset includes an engine and a variable speed generator. The variable speed generator is mechanically coupled to the engine and is configured to generate electrical power. The power generating system further includes an energy storage device, which is charged or discharged during transient load conditions of a power grid. The power generating system includes a controller to generate a speed control signal to select a speed for the genset. The speed control signal is selected based upon stored energy in the energy storage device and power generating system conditions, power grid conditions or combinations thereof.
US08022571B2 Power management circuitry and solar cells
This is directed to methods, systems, and apparatuses for implementing circuitry that can be used to control multiple solar cells to generate power for a portable electronic device. For example, in response to determining that one or more of the solar cells is generating a reduce voltage output (e.g., due to a partial obstruction of one or more of the solar cells), the connections among the solar cells can be configured to generate a constant preset voltage, as long as a subset of the solar cells is operating. The voltage generated by the solar cells can then be boosted to a value suitable for powering the portable electronic device and/or any of its individual components. As another example, the connections among the solar cells can be configured to generate a startup voltage to directly power the portable electronic device and/or any of its components.
US08022570B2 Systems and methods for lighting control in flight deck devices
Systems and methods for illuminating flight deck devices are disclosed. In one embodiment, a flight deck panel illumination system includes at least one illuminated panel having at least one illumination source, and a power supply coupled to the at least one illumination source and to an electrical energy source that is configured to selectively provide a suitable power conversion mode in response to an applied signal. A processor is coupled to the power supply to generate the applied signal.
US08022567B2 Underwater ducted turbine
An apparatus is disclosed for a turbine for generating electrical power from water or air flow comprising at least one rotor disk having a plurality of hydrofoil blades, guide vanes, a cylindrical housing, and a generator means. A rim generator comprising a magnet race rotor rim and fixed stator coils in the housing is used. The apparatus is fitted with a screen to stop the ingress of debris and marine life, and a skirt augmenter device to reduce the Betz effect. The apparatus is preferably for sub-sea deployment and driven by tidal currents, but may be powered by river current or wave driven air or by wind. The apparatus may be deployed on at least one telescoping pole, tethered to the sea-bed and kept buoyant by buoyant concrete in the housing, or inserted in a dam, under a barge or in a tidal power array.
US08022566B2 Methods and systems for operating a wind turbine
A method for controlling operation of a floating wind turbine is described. The floating wind turbine includes a wind turbine generator coupled to a support tower. The method includes measuring a tower inclination, determining an operating parameter control value based on at least the measured tower inclination, and adjusting wind turbine operation based at least partially on the operating parameter control value.
US08022564B2 Speed reducer for use in yaw drive apparatus for wind power generation apparatus, and yaw drive method and apparatus for wind power generation apparatus using the speed reducer
A yaw drive method of a wind power generation apparatus, in which a second gear engaged with a first gear attached to one of tower or a wind power generation unit supported to the upper end of the tower so as to be capable of yawing and supported to a tower or to the upper end of the tower is rotated by a drive motor attached to the other of the tower or the wind power generation unit for yawing the wind power generation unit. A drive energy, which is supplied to the drive motor for a predetermined time from when the supply of the drive energy to the drive motor begins to start, is made to be smaller than the drive energy supplied to the drive motor in a common yawing.
US08022563B2 Wave energy converter
A wave energy generator includes a float for floating on the surface of a body of water. An electrical energy generator that is capable of generating usable electrical energy from the kinetic energy of waves is mounted to or otherwise engaged with the float. The electrical energy generator includes a housing, a coil of electrically conductive material, a reciprocally movable electromagnetically active mass, and springs for connecting the mass to the housing. The electrical energy generator may optionally include spring adjustment means engaged with the housing, means for constraining non-linear motion of the electromagnetically active mass, and/or means of mitigating motion retardation of the electromagnetically active mass within the housing.
US08022557B2 Near chip scale semiconductor packages
Flip chip ball grid array semiconductor devices and methods for fabricating the same. In one example, a near chip scale method of semiconductor die packaging may comprise adhering the die to a substrate in a flip chip configuration, coating the die with a first polymer layer, selectively removing the first polymer layer to provide at least one opening to expose a portion of the die, and depositing a first metal layer over the first polymer layer, the first metal layer at least partially filling the at least one opening to provide an electrical contact to the die, and including a portion that substantially surrounds the die in a plane of an upper surface of the first metal layer to provide an electromagnetic shield around the die.
US08022548B2 Method for fabricating conducting plates for a high-Q MIM capacitor
A method of forming one or more capacitors on or in a substrate and a capacitor structure resulting therefrom is disclosed. The method includes forming a trench in the substrate, lining the trench with a first copper-barrier layer, and substantially filling the trench with a first copper layer. The first copper layer is substantially chemically isolated from the substrate by the first copper-barrier layer. A second copper-barrier layer is formed over the first copper layer and a first dielectric layer is formed over the second copper-barrier layer. The dielectric layer is substantially chemically isolated from the first copper layer by the second copper-barrier layer. A third copper-barrier layer is formed over the dielectric layer and a second copper layer is formed over the third copper-barrier layer. The second copper layer is formed in a non-damascene process.
US08022545B2 Top layers of metal for high performance IC's
A method of closely interconnecting integrated circuits contained within a semiconductor wafer to electrical circuits surrounding the semiconductor wafer. Electrical interconnects are held to a minimum in length by making efficient use of polyimide or polymer as an inter-metal dielectric thus enabling the integration of very small integrated circuits within a larger circuit environment at a minimum cost in electrical circuit performance.
US08022538B2 Base package system for integrated circuit package stacking and method of manufacture thereof
A method of manufacture of a base package system includes: forming a substrate strip assembly including: providing a substrate strip having ball lands, mounting an integrated circuit on the substrate strip, and molding a finger structure, having a knuckle region, on the integrated circuit; and singulating a substrate from the substrate strip assembly.
US08022537B2 Semiconductor device
The present invention provides a semiconductor device comprising a semiconductor substrate, and transistors formed on the semiconductor substrate, wherein control electrode terminals constituting external electrode terminals of the transistors, and first electrode terminals which transmit output signals, are provided on a main surface of the semiconductor substrate, wherein the control electrode terminals are provided at least one, and a plurality of the first electrode terminals are arranged on one side and a plurality of the first electrode terminals are arranged on the other side with the control electrode terminals being interposed therebetween, wherein a portion including the control electrode terminals and a plurality of the first electrode terminals located on one side of the control electrode terminals constitute a first transistor portion, and wherein a portion including the control electrode terminals and a plurality of the first electrode terminals located on the other side of the control electrode terminals constitute a second transistor portion. The semiconductor device is quadrangular.
US08022536B2 Semiconductor substrate for build-up packages
The present invention provides techniques to fabricate build-up single or multichip modules. In one embodiment, this is accomplished by dispensing die-attach material in one or more pre-etched cavities on a substrate. A semiconductor die is then placed over each pre-etched cavity including the die-attach material by urging a slight downward pressure on the substrate such that an active surface of each placed semiconductor die is disposed across from the substrate and is further substantially coplanar with the substrate. The semiconductor die is then secured to the substrate by curing the die-attach material. A miniature circuit board, including one or more alternating layer of dielectric material and metallization structures, is then formed over the substrate and the active surface of each semiconductor die to electrically interconnect the semiconductor dies.
US08022533B2 Circuit apparatus provided with asperities on substrate surface
Circuit elements including a plurality of semiconductor devices and passive elements embedded in an insulating resin film are formed on a metal substrate having a surface roughness Ra of 0.3 to 10 μm. This produces an anchoring effect occurs between the substrate and the insulating film, thereby improving the adhesiveness between the substrate and the insulating resin film.
US08022530B2 Package substrate having electrically connecting structure
A package substrate having an electrically connecting structure are provided. The package substrate include: a package substrate substance with at least a surface having a plurality of electrically connecting pads formed thereon, allowing an insulating protective layer to be formed on the surface of the package substrate substance and the electrically connecting pads and formed with a plurality of openings corresponding in position to the electrically connecting pads so as to expose a portion of the electrically connecting pads, respectively; and a metal layer provided on an exposed portion of the electrically connecting pads, walls of the openings of the insulating protective layer, and a circular portion of the insulating protective layer encircling each of the openings thereof, and provided with a slope corresponding in position to a bottom rim of each of the openings. Accordingly, solder bleeding and short circuits are prevented.
US08022526B2 Distributed computing
On a typical motherboard the processor and memory are separated by a printed circuit data bus that traverses the motherboard. Throughput, or data transfer rate, on the data bus is much lower than the rate at which a modern processor can operate. The difference between the data bus throughput and the processor speed significantly limits the effective processing speed of the computer when the processor is required to process large amounts of data stored in the memory. The processor is forced to wait for data to be transferred to or from the memory, leaving the processor under-utilized. The delays are compounded in a distributed computing system including a number of computers operating in parallel. The present disclosure describes systems, method and apparatus that tend to alleviate delays so that memory access bottlenecks are not compounded within distributed computing systems.
US08022525B2 Semiconductor device and method of manufacturing semiconductor device
A semiconductor device has a plurality of wafers which are laminated to each other, wherein: each wafer includes an lamination surface to which another wafer is laminated and a substrate having an element formed thereon; the lamination surface is provided with an electric signal connecting portion that electrically connects to said another wafer so as to form a semiconductor circuit; at least one of the electrical signal connecting portions facing each other is a protruding connection portion that protrudes from a region which exposes the substrate on the lamination surface; and a reinforcing protruding portion that is insulated from the semiconductor circuit, and is formed of the same material as the substrate to protrude from the lamination surface with a height equal to the length of a gap between the lamination surfaces of wafers facing each other is provided in an area where the protruding connection portion is not disposed on the lamination surface formed with the protruding connection portion.
US08022523B2 Multi-chip stack package
A multi-chip stack package comprising a first wiring substrate, a first chip, a second wiring substrate, and a second chip is provided. The first wiring substrate is with a front side and a rear side. The first chip is disposed on the front side of the first wiring substrate and electrically connected to the first wiring substrate and the first chip has a first active surface. The second wiring substrate is disposed on the first active surface of the first chip and electrically connected to the first wiring substrate. The second chip is disposed on the second wiring substrate and electrically connected to the second wiring layer. The second active surface of the second chip faces the first active surface of the first chip.
US08022521B1 Package failure prognostic structure and method
In accordance with one embodiment, a failure prognostic package includes a substrate having a first surface and an opposite second surface. An electronic component trace is coupled to the first surface. An electronic component is electrically coupled to the electronic component trace. A prognostic trace is coupled to the first surface of the substrate and is electrically isolated from the electronic component. A failure zone of the failure prognostic package includes a plurality of sides and a plurality of corners, wherein the prognostic trace is weaker at the failure zone than the electronic component trace. Failure of the prognostic trace does not cause failure of the failure prognostic package. However, failure of the prognostic trace provides advanced notice of failure of the failure prognostic package.
US08022520B2 System for hermetically sealing packages for optics
A system for hermetically sealing devices. The system includes a substrate, which includes a plurality of individual chips. Each of the chips includes a plurality of devices and each of the chips are arranged in a spatial manner as a first array. The system also includes a transparent member of a predetermined thickness, which includes a plurality of recessed regions arranged in a spatial manner as a second array and each of the recessed regions are bordered by a standoff region. The substrate and the transparent member are aligned in a manner to couple each of the plurality of recessed regions to a respective one of said plurality of chips. Each of the chips within one of the respective recessed regions is hermetically sealed by contacting the standoff region of the transparent member to the plurality of first street regions and second street regions using at least a bonding process to isolate each of the chips within one of the recessed regions.
US08022519B2 System-in-a-package based flash memory card
A system-in-a-package based flash memory card including an integrated circuit package occupying a small overall area within the card and cut to conform to the shape of a lid for the card. An integrated circuit may be cut from a panel into a shape that fits within and conforms to the shape of lids for a finished memory card, such as for example an SD Card. The integrated circuit package may be a system-in-a-package, a multi-chip module, or other arrangement where a complete electronic system is formed in a single package.
US08022517B2 Semiconductor chip package
A semiconductor chip package includes a lead frame, an insulation member, a chip, bonding wires and a sealing member. The lead frame includes a plurality of first leads and a plurality of second leads. The second leads have a chip adhesion region. The insulation member fills a space between the second leads in the chip adhesion region. The chip is provided on at least one surface of the insulation member. The chip has single-side bonding pads. The bonding wires electrically connect the leads and the bonding pads. The sealing member covers the lead frame, the insulation member, the chip and the bonding wires. Since the space between the second leads is filled with the insulation member, voids may be prevented from occurring.
US08022515B2 Semiconductor device
A semiconductor device includes a lead frame having an element support and a lead portion. The lead frame has an area from the element support to inner leads of the lead portion, which is formed flat. First and second semiconductor elements are stacked in order on a lower surface of the lead frame. Electrode pads of the first semiconductor element are connected to the inner leads via first metal wires. Ends of the first metal wires, which are connected to the first semiconductor element, are embedded in the second adhesive layer of the second semiconductor element.
US08022507B2 Varactor diodes
An improved varactor diode is obtained by providing a substrate having a first surface and in which are formed a first N region having a first peak dopant concentration located at a first depth beneath the surface, and a first P region having a second peak dopant concentration greater than the first peak dopant concentration located at a second depth beneath the surface less than the first depth, and a second P region having a third peak dopant concentration greater than the second peak dopant concentration and located at a third depth at or beneath the surface less than the second depth, so that the first P region provides a retrograde doping profile whose impurity concentration increases with distance from the inward edge of the second P region up to the second peak dopant concentration.
US08022506B2 SOI device with more immunity from substrate voltage
A semiconductor on insulator device has an insulator layer, an active layer (40) on the insulator layer, a lateral arrangement of collector (10), emitter (30) and base (20) on the active layer, and a high Base-dose region (70) extending under the emitter towards the insulator to suppress vertical current flowing under the emitter. This region (70) reduces the dependence of current-gain and other properties on the substrate (Handle-wafer) voltage. This region can be formed of the same doping type as the base, but having a stronger doping. It can be formed by masked alignment in the same step as an n type layer used as the body for a P-type DMOS transistor.
US08022504B2 Semiconductor device having capacitor with upper electrode whose circumference is made long and its manufacture method
A capacitor is formed over a semiconductor substrate. The capacitor includes a lower electrode, a capacitor dielectric film and an upper electrode in this order recited, and has an area S equal to or larger than 1000 μm2 and L/S equal to or larger than 0.4 μm−1, where S is an area of a capacitor region in which the lower and upper electrodes face each other across the dielectric film, and L is a total length of a circumference line of the capacitor region.
US08022500B2 Semiconductor device having a high aspect ratio isolation trench
A semiconductor device having high aspect ratio isolation trenches and a method for manufacturing the same is presented. The semiconductor device includes a semiconductor substrate, a first insulation layer, and a second insulation layer. The semiconductor substrate has a second trench that is wider than a first trench. The first insulation layer is partially formed within the wider second trench in which the first insulation layer when formed clogs the opening of the narrower first trench. A cleaning of the first insulation layer unclogs the opening of the narrower first trench in which a second insulation layer can then be formed within both the first and second trenches.
US08022499B2 Semiconductor memory device including cell isolation structure using inactive transistors
Disclosed herein is a semiconductor memory device including floating body cells. The semiconductor memory device includes memory cell active regions formed on a Silicon-On Isolator (SOI) semiconductor substrate, a plurality of floating body cell transistors formed in the memory cell active regions, and “inactive transistors” for providing cell isolation that are formed between the plurality of floating body cell transistors. Here, the inactive transistors for providing cell isolation are controlled so that they always are in an OFF state while the semiconductor memory device is operating.
US08022492B2 Semiconductor device for performing photoelectric conversion
A semiconductor device for performing photoelectric conversion has a semiconductor substrate of a first conductivity type and a well region of a second conductivity type different from the first conductivity type and formed in a predetermined region of the semiconductor substrate. A pair of trenches are formed directly adjacent to respective opposite sides of the well region and have widths greater than those of respective depletion layers generated on the respective opposite sides so as to remove junction interfaces on the respective opposite sides. A depth of each trench from a surface of the semiconductor substrate is greater than that of a depletion layer generated on a bottom side of the well region. An insulating layer is buried in each of the trenches.
US08022489B2 Air tunnel floating gate memory cell
An air tunnel floating gate memory cell includes an air tunnel defined over a substrate. A first polysilicon layer (floating gate) is defined over the air tunnel. An oxide layer is disposed over the first polysilicon layer such that the oxide layer caps the first polysilicon layer and defines the sidewalls of the air tunnel. A second polysilicon layer, functioning as a word line, is defined over the oxide layer. A method for making an air tunnel floating gate memory cell is also disclosed. A sacrificial layer is formed over a substrate. A first polysilicon layer is formed over the sacrificial layer. An oxide layer is deposited over the first polysilicon layer such that the oxide layer caps the first polysilicon layer and defines the sidewalls of the sacrificial layer. A hot phosphoric acid (H3PO4) dip is used to etch away the sacrificial layer to form an air tunnel.
US08022488B2 High-performance FETs with embedded stressors
A high-performance semiconductor structure and a method of fabricating such a structure are provided. The semiconductor structure includes at least one gate stack, e.g., FET, located on an upper surface of a semiconductor substrate. The structure further includes a first epitaxy semiconductor material that induces a strain upon a channel of the at least one gate stack. The first epitaxy semiconductor material is located at a footprint of the at least one gate stack substantially within a pair of recessed regions in the substrate which are present on opposite sides of the at least one gate stack. A diffused extension region is located within an upper surface of said first epitaxy semiconductor material in each of the recessed regions. The structure further includes a second epitaxy semiconductor material located on an upper surface of the diffused extension region. The second epitaxy semiconductor material has a higher dopant concentration than the first epitaxy semiconductor material.
US08022487B2 Increasing body dopant uniformity in multi-gate transistor devices
Techniques and structures for increasing body dopant uniformity in multi-gate transistor devices are generally described. In one example, an electronic device includes a semiconductor substrate, a multi-gate fin coupled with the semiconductor substrate, the multi-gate fin comprising a source region, a drain region, and a gate region wherein the gate region is disposed between the source region and the drain region, the gate region being body-doped after a sacrificial gate structure is removed from the multi-gate fin and before a subsequent gate structure is formed, a dielectric material coupled with the source region and the drain region of the multi-gate fin, and the subsequent gate structure coupled to the gate region of the multi-gate fin.
US08022484B2 Semiconductor memory device
In a semiconductor memory device which includes a shared sense amplifier portion, a pair of memory cell portions disposed on opposite sides of the shared sense amplifier portion, a pair of transfer gates between the pair of memory cell portions and the shared sense amplifier portion, and bit lines constituting a plurality of bit line pairs and connecting the pair of memory cell portions to each other through the pair of transfer gates and the shared sense amplifier portion, the bit lines in a bit line pair of the plurality of bit line pairs are twisted at a substantial center between the pair of transfer gates on the opposite sides.
US08022482B2 Device configuration of asymmetrical DMOSFET with schottky barrier source
A trenched semiconductor power device includes a trenched gate insulated by a gate insulation layer and surrounded by a source region encompassed in a body region above a drain region disposed on a bottom surface of a semiconductor substrate. The source region surrounding the trenched gate includes a metal of low barrier height to function as a Schottky source. The metal of low barrier height further may include a PtSi or ErSi layer. In a preferred embodiment, the metal of low barrier height further includes an ErSi layer. The metal of low barrier height further may be a metal silicide layer having the low barrier height. A top oxide layer is disposed under a silicon nitride spacer on top of the trenched gate for insulating the trenched gate from the source region. A source contact disposed in a trench opened into the body region for contacting a body-contact dopant region and covering with a conductive metal layer such as a Ti/TiN layer. In a preferred embodiment, the semiconductor power device constitutes an asymmetrical double diffusion metal oxide semiconductor field effect transistor (DMOSFET) device.
US08022480B2 Semiconductor device and method for manufacturing the same
Disclosed are a semiconductor device and a method for manufacturing the same. The semiconductor device includes at least two of first and second conductive-type high-voltage transistors and first and second conductive-type low-voltage transistors. The first conductive-type high-voltage transistor include a first conductive-type well in a semiconductor substrate, a device isolation film in the first conductive-type well, a gate pattern on the first conductive-type well, second conductive-type drift regions in the semiconductor substrate at opposite sides of the gate pattern, second conductive-type source and drain regions in the second conductive-type drift region, a pick-up region to receive a bias voltage, and a first latch-up inhibiting region under the pick-up region. Accordingly, it is possible to reduce and prevent latchup without using a double guard ring and to eliminate an additional process to form first and second latch-up inhibiting regions.
US08022477B2 Semiconductor apparatus having lateral type MIS transistor
A semiconductor apparatus comprises: a semiconductor substrate; and a lateral type MIS transistor disposed on a surface part of the semiconductor substrate. The lateral type MIS transistor includes: a line coupled with a gate of the lateral type MIS transistor; a polycrystalline silicon resistor that is provided in the line, and that has a conductivity type opposite to a drain of the lateral type MIS transistor; and an insulating layer through which a drain voltage of the lateral type MIS transistor is applied to the polycrystalline silicon resistor.
US08022468B1 Ultraviolet radiation blocking interlayer dielectric
A memory device may include a substrate, a first dielectric layer formed over the substrate and a charge storage element formed over the first dielectric layer. The memory device may also include a second dielectric layer formed over the charge storage element and a control gate formed over the second dielectric layer. The memory device may further include an interlayer dielectric formed over the control gate and the substrate, where the interlayer dielectric includes a material that is substantially opaque to ultraviolet radiation.
US08022466B2 Non-volatile memory cells having a polysilicon-containing, multi-layer insulating structure, memory arrays including the same and methods of operating the same
Memory cells including a semiconductor layer having at least two source/drain regions disposed below a surface of the semiconductor layer and separated by a channel region; a lower insulating layer disposed above the channel region; a charge storage layer disposed above the lower insulating layer; an upper insulating multi-layer structure disposed above the charge storage layer, wherein the upper insulating multi-layer structure comprises a polysilicon material layer interposed between a first dielectric layer and a second dielectric layer; and a gate disposed above the upper insulating multi-layer structure are described along with arrays thereof and methods of operation.
US08022463B2 Semiconductor device and method of manufacturing the same
This semiconductor device comprises a semiconductor substrate, a gate insulating film formed thereon, and a gate electrode formed through the gate insulating film on the semiconductor substrate. The first silicon nitride film is formed on the upper surface of the gate electrode, and a protection insulating film is formed on the side thereof. The second silicon nitride film is formed on the side of the protection insulating film. The third silicon nitride film is formed on the upper surface of the protection insulating film, and the bottom thereof is formed on a higher position than the bottom of the first silicon nitride film.
US08022458B2 Capacitors integrated with metal gate formation
A semiconductor structure including a capacitor having increased capacitance and improved electrical performance is provided. The semiconductor structure includes a substrate; and a capacitor over the substrate. The capacitor includes a first layer including a first capacitor electrode and a second capacitor electrode, wherein the first capacitor electrode is formed of a metal-containing material and is free from polysilicon. The semiconductor structure further includes a MOS device including a gate dielectric over the substrate; and a metal-containing gate electrode on the gate dielectric, wherein the metal-containing gate electrode is formed of a same material, and has a same thickness, as the first capacitor electrode.
US08022453B2 Image sensor and manufacturing method for same
An image sensor including a first region where a pad is to be formed, and a second region where a light-receiving element is to be formed. A pad is formed over a substrate of the first region. A passivation layer is formed over the substrate of the first and second regions to expose a portion of the pad. A color filter is formed over the passivation layer of the second region. A microlens is formed over the color filter. A bump is formed over the pad. A protective layer is formed between the bump and the pad to expose the portion of the pad.
US08022450B2 Image sensor and method for manufacturing the same
Disclosed are an image sensor and a method for manufacturing the same. The image sensor includes a first pixel having a first photodiode and a first readout circuit and a second pixel having a second photodiode and a second readout circuit. The second pixel is aligned at one side of the first pixel, and a light receiving area of the first photodiode is different from a light receiving area of the second photodiode.
US08022448B1 Apparatus and methods for evaporation including test wafer holder
Apparatus and methods for evaporating metal onto semiconductor wafers are disclosed. One such apparatus can include an evaporation chamber that includes a wafer holder, such as a dome, and a test wafer holder that is separate and spaced apart from the wafer holder. In certain implementations, the test wafer can be coupled to a cross beam supporting at least one shaper. A metal can be evaporated onto production wafers positioned in the wafer holder while metal is evaporated on a test wafer positioned in a test wafer holder. In some instances, the production wafers can be GaAs wafers. The test wafer can be used to make a quality assessment about the production wafers.
US08022447B2 Metal-oxide-semiconductor device including an energy filter
A MOS device includes first and second source/drains spaced apart relative to one another. A channel is formed in the device between the first and second source/drains. A gate is formed in the device between the first and second source/drains and proximate the channel, the gate being electrically isolated from the first and second source/drains and the channel. The gate is configured to control a conduction of the channel as a function of a potential applied to the gate. The MOS device further includes an energy filter formed between the first source/drain and the channel. The energy filter includes an impurity band operative to control an injection of carriers from the first source/drain into the channel.
US08022445B2 Method of manufacturing a semiconductor device
A method of manufacturing a semiconductor device, including the steps of preparing a silicon substrate which has a main surface whose plane direction is a surface (100); forming an n channel MISFET (Metal Insulator Semiconductor Field Effect Transistor) which has a gate electrode, a source region, a drain region and a channel whose channel length direction is parallel to a crystal orientation <100> of the silicon substrate; and forming NiSi over the gate electrode and NiSi2 over the source region and the drain region at the same steps.
US08022444B2 Biosensor and method of manufacturing the same
Provided are a biosensor with a silicon nanowire and a method of manufacturing the same, and more particularly, a biosensor with a silicon nanowire including a defect region formed by irradiation of an electron beam, and a method of manufacturing the same. The biosensor includes: a silicon substrate; a source region disposed on the silicon substrate; a drain region disposed on the silicon substrate; and a silicon nanowire disposed on the source region and the drain region, and having a defect region formed by irradiation of an electron beam. Therefore, by irradiating a certain region of a high-concentration doped silicon nanowire with an electron beam to lower electron mobility in the certain region, it is possible to maintain a low contact resistance between the silicon nanowire and a metal electrode and to lower operation current of a biomaterial detection part, thereby improving sensitivity of the biosensor.
US08022443B1 Memory and interconnect design in fine pitch
An integrated circuit includes a plurality of signal lines. A first signal line layer includes a plurality of first signal lines. A second signal line layer includes a plurality of second signal lines arranged on top of and insulated from the first signal line layer. A third signal line layer includes a plurality of third signal lines arranged on top of and insulated from the second signal line layer. A contact extends through the second signal line layer and connects at least one of the plurality of third signal lines to at least one of the first signal lines. At least one of the second signal lines further extends in a second direction to bend around the contact such that a predetermined distance separates the plurality of second signal lines from the contact.
US08022442B2 Semiconductor device having STI with nitride liner and UV light shielding film
A semiconductor device has: a silicon substrate; trench formed downward from the surface of the silicon substrate, the trench defining active regions on the surface of the silicon substrate; a first liner layer of a silicon nitride film covering an inner wall of the trench; a second liner layer of a silicon nitride layer formed on the first liner layer; an element isolation region of an insulator formed on the second liner layer; a p-channel MOS transistor formed in and on one of the active regions; a contact etch stopper layer of a silicon nitride layer not having a ultraviolet shielding ability, formed above the silicon substrate, and covering the p-channel MOS transistor; and a light shielding film of a silicon nitride layer having the ultraviolet shielding ability and formed above the contact etch stopper layer.
US08022441B2 Semiconductor device and associated layouts having transistors formed from six linear conductive segments with gate electrode-to-gate electrode connection through single interconnect level and common node connection through different interconnect level
A semiconductor device is disclosed as having a substrate portion that includes a plurality of diffusion regions that include at least one p-type diffusion region and at least one n-type diffusion region. A gate electrode level region is formed above the substrate portion to include a number of conductive features defined to extend in only a first parallel direction. Each of the conductive features within the gate electrode level region is fabricated from a respective originating rectangular-shaped layout feature. Some of the conductive features within the gate electrode level region extend over the p-type diffusion regions to form respective PMOS transistor devices. Also, some of the conductive features within the gate electrode level region extend over the n-type diffusion regions to form respective NMOS transistor devices. A number of the PMOS transistor devices is equal to a number of the NMOS transistor devices in the gate electrode level region.
US08022438B2 Chamfered freestanding nitride semiconductor wafer and method of chamfering nitride semiconductor wafer
Technology of making freestanding gallium nitride (GaN) wafers has been matured at length. Gallium nitride is rigid but fragile. Chamfering of a periphery of a GaN wafer is difficult. At present edges are chamfered by a rotary whetstone of gross granules with weak pressure. Minimum roughness of the chamfered edges is still about Ra 10 μm to Ra 6 μm. The large edge roughness causes scratches, cracks, splits or breaks in transferring process or wafer process. A wafer of the present invention is bevelled by fixing the wafer to a chuck of a rotor, bringing an edge of the wafer into contact with an elastic whetting material having a soft matrix and granules implanted on the soft matrix, rotating the wafer and feeding the whetting material. Favorably, several times of chamfering edges by changing the whetting materials of smaller granules are given to the wafer. The chamfering can realize small roughness of Ra 10 nm and Ra 5 μm at edges of wafers.
US08022434B2 Light-emitting diode
Disclosed is an improved light-emitting diode, which can be a PLCC or SMD type light-emitting diode. The light-emitting diode includes a package body, at least one pair of conductive terminals, and an optic lens. The package body has an end surface, a circumferential surface extending from the end surface, and a receptacle for accommodating a light-emitting chip. The pair of conductive terminals is fixed to the package body. The optic lens covers the end surface of the package body and is even expanded to cover the circumferential surface of the package body. In this way, effects of improved bonding strength, improved optic advantages, being easy to adjust to a desired angle with the optic lens, and alleviation of troubles caused by overflow of adhesive can be realized.
US08022432B2 Light-emitting device comprising conductive nanorods as transparent electrodes
Disclosed herein is an electrical light-emitting device including a transparent conductive nanorod type electrode, in which transparent conductive nanorods grown perpendicular to a light-emitting layer are used as the electrode. Hence, light is not absorbed by the electrode, and tunneling easily occurs due to nanocontact of the nanorods, thus increasing current injection efficiency, and also, total internal reflections decrease. Thereby, the light-emitting device according to this invention has light-emitting properties and luminous efficiency superior to conventional light-emitting devices, including metal electrodes or thin film type transparent electrodes.
US08022429B2 Light emitting device
A light emitting device includes a light emitting element (LEE) on a mounting board, a metal reflector surrounding the side surfaces of the LEE on the mounting board, a conductor electrically connecting the LEE with the mounting board, and a sealing resin fitted within the reflector to cover and seal the LEE and the conductor. The mounting board includes a metal baseboard, and an insulating board laminated on the base board with a window hole larger than the outer periphery of the LEE. A mount for the LEE is on the base board within the window hole with a clearance defined from window hole side surfaces. The conductor straddles the clearance, and electrically connects the wiring pattern on the insulating board with the LEE and mount. Part of the clearance associated with the area that projects from the conductor to the mounting board is narrower than the remainder.
US08022426B2 Color mixing light emitting diode device
An exemplary color mixing light emitting diode (LED) device includes a substrate, LED dies, an encapsulating body, and a light mixing structure. The substrate has a main surface. The LED dies are arranged adjacent the main surface of the substrate. The light mixing structure is arranged adjacent an outer portion of the main surface of the substrate, around the LED dies. The encapsulating body encapsulates the LED dies and the light mixing structure. The light mixing structure is made of light transmissive material, and the light mixing structure has light scattering particles doped therein.
US08022425B2 Semiconductor device
An exemplary semiconductor device is provided. The semiconductor device includes a semiconductor stacked layer and a conductive structure. The conductive structure is located on the semiconductor stacked layer. The conductive structure includes a bottom portion and a top portion on opposite sides thereof. The bottom portion is in contact with the semiconductor stacked layer. A ratio of a top width of the top portion to a bottom width of the bottom portion is less than 0.7. The conductive structure can be a conductive dot structure or a conductive line structure.
US08022422B2 Display apparatus with color pixels
A display apparatus includes pixel electrodes disposed on a first base substrate, a second base substrate which faces the first base substrate, color pixels disposed on the second base substrate, the color pixels correspond to the pixel electrodes in a one-to-one correspondence, each color pixel partially covers the corresponding pixel electrode, a common electrode disposed on the second base substrate to cover the pixel electrodes and an electrophoretic layer including a plurality of electrophoretic particles, the electrophoretic layer being interposed between the pixel electrodes and the common electrode.
US08022421B2 Light emitting module having LED pixels and method of forming the same
A method for forming a pixel of an LED light source is provided. The method includes following steps: forming a first layer on a substrate; forming a second layer and a first light-emitting active layer on the first layer; exposing a portion of an upper surface of the first layer; forming a third layer on the substrate; forming a fourth layer and a second light-emitting active layer on the third layer; exposing a portion of an upper surface of the third layer; and forming a first electrode on the exposed upper surface of the first layer, a second electrode on a portion of an upper surface of the second layer, a third electrode on the exposed upper surface of the third layer, and a fourth electrode a portion of an upper surface of the fourth layer. The first light-emitting active layer and the second light-emitting active layer emit different colors of light.
US08022420B2 Semiconductor light emitting device, illumination module, illumination apparatus, method for manufacturing semiconductor light emitting device, and method for manufacturing semiconductor light emitting element
A semiconductor light emitting device (10) is provided with a base substrate (12) and three LED chips (14A, 14B, and 14C) disposed on the base substrate (12). Each LED chip (14A, 14B, and 14C) includes a semiconductor multilayer structure (20) and has a rhombus shape with interior angles of approximately 60° and approximately 120° in plan view. Each semiconductor multilayer structure (20) has an HCP single crystal structure and includes a light emission layer (24). The LED chips (14A, 14B, and 14C) are arranged on the base substrate (12) so as to face one another at a vertex forming the larger interior angle in plan view. With this arrangement, the LED chips (14A, 14B, and 14C) as a whole form a substantially regular hexagonal shape.
US08022409B2 Semiconductor device with omega gate and method for fabricating a semiconductor device
A substrate has an active region divided into storage node contact junction regions, channel regions and a bit line contact junction region. Device isolation layers are formed in the substrate isolating the active region from a neighboring active region Recess patterns are formed each in a trench structure and extending from a storage node contact junction region to a channel region Line type gate patterns, each filling a predetermined portion of the trench of the individual recess pattern, is formed in a direction crossing a major axis of the active region in an upper portion of the individual channel region.
US08022408B2 Crystalline nanowire substrate, method of manufacturing the same, and method of manufacturing thin film transistor using the same
Example embodiments relate to a crystalline nanowire substrate having a structure in which a crystalline nanowire film having a relatively fine line-width may be formed on a substrate, a method of manufacturing the same, and a method of manufacturing a thin film transistor using the same. The method of manufacturing the crystalline nanowire substrate may include preparing a substrate, forming an insulating film on the substrate, forming a silicon film on the insulating film, patterning the insulating film and the silicon film into a strip shape, reducing the line-width of the insulating film by undercut etching at least one lateral side of the insulating film, and forming a self-aligned silicon nanowire film on an upper surface of the insulating film by melting and crystallizing the silicon film.
US08022404B2 Luminescent device and process of manufacturing the same
In the case where a material containing an alkaline-earth metal in a cathode, is used, there is a fear of the diffusion of an impurity ion (such as alkaline-earth metal ion) from the EL element to the TFT being generated and causing the variation of characteristics of the TFT. Therefore, as the insulating film provided between TFT and EL element, a film containing a material for not only blocking the diffusion of an impurity ion such as an alkaline-earth metal ion but also aggressively absorbing an impurity ion such as an alkaline-earth metal ion is used.
US08022402B2 Active device array substrate
An active device array substrate including a substrate, a pixel array, and peripheral circuit is provided. The substrate has a display region and a peripheral region. The pixel array is disposed on the display region of the substrate, wherein the pixel array includes signal lines and pixels, each of the pixels is electrically connected to the signal lines respectively and extends from the display region to the peripheral region. The peripheral circuit is disposed on the peripheral region and includes a testing circuit electrically connected to the signal lines. Additionally, the testing circuit includes shorting bars and connecting conductors, wherein each of the signal lines is electrically connected to one of the shorting bars through one of the connecting connectors respectively, and at least two of the signal lines connected to the same shorting bar are electrically connected to each other through one of the connecting conductors.
US08022399B2 Organic light-emitting device
The organic light-emitting device of the present invention includes: a substrate; a plurality of organic light-emitting elements formed on the substrate; and an element isolation layer formed between the plurality of organic light-emitting elements, each of the elements having: on the substrate in mentioned order, a first electrode patterned for each of the organic light-emitting elements, an organic compound layer patterned for each of the organic light-emitting elements, and a second electrode; the element isolation layer formed across a space between the plurality of first electrodes to cover the ends of the first electrodes, and having an opening at a portion corresponding to the organic light-emitting elements, and at least a portion of the element isolation layer in contact with the organic compound layer is formed of an inorganic material.
US08022397B2 Transistor
An electrolyte-gated field effect transistor is disclosed, the transistor comprising an electrolyte including a polymeric ionic liquid analogue. In a preferred embodiment, the transistor further comprises a source electrode, a drain electrode disposed so as to be separated from the source electrode, forming a gap between the source and drain electrodes, a semiconductor layer bridging the gap between the source and drain electrodes and thus forming a transistor channel, and a gate electrode positioned so as to be separated from the source electrode, the drain electrode and the semiconductor layer. In this embodiment, the electrolyte is disposed so as to contact at least a part of both the gate electrode and the semiconductor layer.
US08022394B2 Molecular quantum interference apparatus and applications of same
A molecular quantum interference device for use in molecular electronics. In one embodiment, the device includes a molecular quantum interference unit having a first terminal group and a second terminal group between which quantum interference affects electrical conduction, a molecular spacer having a first terminal group and a second terminal group and coupled to the molecular quantum interference unit through a chemical bonding between the first terminal group of the molecular spacer and the second terminal group of the molecular quantum interference unit, a first electrode electrically coupled to the molecular quantum interference unit and configured to supply charge carriers to or receive charge carriers from the molecular quantum interference unit, and a second electrode electrically coupled to the molecular spacer and configured to receive charge carriers from or supply charge carriers to the molecular spacer.
US08022392B2 Semiconductor layer structure with superlattice
The semiconductor layer structure includes an active layer and a superlattice composed of stacked layers of III-V compound semiconductors of a first and at least one second type. Adjacent layers of different types in the superlattice differ in composition with respect to at least one element. The layers have predefined layer thicknesses, such that the layer thicknesses of layers of the first type and of the layers of the second type increase from layer to layer with increasing distance from an active layer. An increasing layer thickness within the layers of the first and the second type is suitable for adapting the electrical, optical and epitaxial properties of the superlattice to given requirements in the best possible manner.
US08022385B2 Memory devices with buried lines
A memory device wherein a diode is serially connected to a programmable resistor and is in electrical communication with a buried digit line. An electrically conductive plug is electrically interposed between the digit line and a strapping layer, thereby creating a double metal scheme wherein the strapping layer is a second metal layer overlying metal wordlines. In a method of a first embodiment the strapping material is electrically connected to the digit line through a planar landing pad overlying the conductive plug. An insulative material is sloped to the planar landing pad in order to provide a surface conducive to the formation of the strapping material.
US08022382B2 Phase change memory devices with reduced programming current
A phase change memory device and a method of forming the same are provided. The phase change memory device includes a conducting electrode in a dielectric layer, a bottom electrode over the conducting electrode, a phase change layer over the bottom electrode, and a top electrode over the phase change layer. The phase change memory device may further include a heat sink layer between the phase change layer and the top electrode. The resistivities of the bottom electrode and the top electrode are preferably greater than the resistivity of the phase change material in the crystalline state.
US08022380B2 Laser irradiation method in which a distance between an irradiation object and an optical system is controlled by an autofocusing mechanism and method for manufacturing semiconductor device using the same
The present invention is to provide a laser irradiation method for performing homogeneous laser irradiation to the irradiation object even when the thickness of the irradiation object is not even. In the case of irradiating the irradiation object having uneven thickness, the laser irradiation is performed while keeping the distance between the irradiation object and the lens for condensing the laser beam on the surface of the irradiation object constant by using an autofocusing mechanism. In particular, when the irradiation object is irradiated with the laser beam by moving the irradiation object relative to the laser beam in the first direction and the second direction of the beam spot formed on the irradiation surface, the distance between the irradiation object and the lens is controlled by the autofocusing mechanism before the irradiation object is moved in the first and second directions.
US08022379B2 Beam position sensor for optical switch modules
A beam direction sensor for determining the direction of each beam in an array of light beams. The invention basically consists of a screen positioned to intersect the array of beams and a video camera to record the position of the images of the intersections. The screen can be any of a wide variety of screens that produce an image of the beams when illuminated with the beam. These include frosted glass and various diffusers. A preferred screen is a holographic diffusers.
US08022376B2 Method for manufacturing semiconductor device or photomask
A method for manufacturing a semiconductor device or a photomask by exposing a pattern while scanning a plurality of deflection regions determined depending on a deflection width of an exposure device on an exposure target with electron beams, enables a computer to execute a step of extracting a first pattern that exists near the boundary of the deflection region and in a first deflection region, a step of searching a second pattern that is adjacent to the first pattern and in a second deflection region different from the first deflection region, and a step of performing data processing of exposure data in accordance with a width of the first pattern so as to minimize the change in distance between the extracted first pattern and the searched second pattern due to positional deviation of the deflection region.
US08022368B2 Hybrid method for randoms variance reduction
A method for reducing randoms variance in a Positron Emission Tomograph (PET) or Positron Emission Tomograph combined with another Medical Imaging device is disclosed. An average of an element of the randoms event (delayeds) sinogram may be estimated by dividing fan sums in delayeds sinogram by singles rates taken from headers of the delayeds sinogram.
US08022366B2 Non-invasive qualitative measurement of chemistry of blood and bodily fluids
Mid-IR spectrometer with no moving parts, which is small and compact, low power consuming, and can monitor blood sugar (glucose) and other blood and bodily fluid analytes on a continuing basis. It has many applications in the health, forensic, environmental and other areas.
US08022364B2 Electron spin detector, and spin polarized scanning electron microscope and spin-resolved x-ray photoelectron spectroscope using the electron spin detector
An electron spin detector includes plural magnetoresistive sensors and a deceleration lens of an electron beam, and each magnetoresistive sensor is inclined so that the electron beam spread by the deceleration lens can be input perpendicularly to the magnetoresistive sensor.
US08022361B2 Monolithic multinozzle emitters for nanoelectrospray mass spectrometry
Novel and significantly simplified procedures for fabrication of fully integrated nanoelectrospray emitters have been described. For nanofabricated monolithic multinozzle emitters (NM2 emitters), a bottom up approach using silicon nanowires on a silicon sliver is used. For microfabricated monolithic multinozzle emitters (M3 emitters), a top down approach using MEMS techniques on silicon wafers is used. The emitters have performance comparable to that of commercially-available silica capillary emitters for nanoelectrospray mass spectrometry.
US08022348B2 Projection type display apparatus having a controlling unit for controlling a rotation rate of the fan of a cooling unit with reference to information regarding lighting state of light sources
A projection type display apparatus includes a plurality of light sources 7a-7d, a display device unit 5, a light-combining unit 3 that combines output light from the plural light sources, a condensing unit 4 that propagates output light from the light-combining unit to the display device unit, and a projecting unit 6 that projects an image by the use of output light from the display device unit. In the projection type display apparatus, cooling units having fans 21a-21d are disposed respectively on the plural light sources, and a controlling unit 31 is provided to control the cooling units. Information regarding the lighting state of the plural light sources is inputted into the controlling unit, and the controlling unit controls a rotation rate of the fans of the cooling units with reference to the information. Concerning a case of temperature management of a plurality of light sources used, an accurate and reliable control is performed; problems such as whitening of the light sources, degradation of life property, blacking, brightness degradation and the like are suppressed, thereby high quality and high reliability are obtained.
US08022347B2 Optical scanning device, image forming apparatus, and optical scanning method having a plurality of light intensity control devices with a switching unit
A surface-emitting laser array includes a plurality of surface-emitting laser devices arranged in an array. An optical system includes a plurality of optical devices to guide a light beam composed of lights emitted from the surface-emitting laser array to a target surface to be scanned. A light-intensity-control-device switching unit places one of light-intensity control devices having different light transmittances at a predetermined position in an optical path of the light beam.
US08022346B2 Automatic fault detection and laser shut-down method for a laser-generated windshield display
The laser of a laser-generated windshield display is controlled to initially deflect the laser beam in the direction of a reflective target disposed outside a display region of the windshield, and a sensor disposed in a reflection path of the target is sampled to detect the presence of a feedback signal that occurs when the laser beam impinges on the sensor. If the feedback signal is detected, the laser beam is deflected onto the display region to generate a driver display; but if the feedback signal is not detected, the laser is automatically turned-off. Once the laser is turned off for lack of a feedback signal, the control is repeated following a specified delay interval so that the driver display will automatically resume the when the condition that prevented generation of the feedback signal is cured.
US08022344B2 Optical wavefront control pattern generating apparatus and optical wavefront control pattern generating method
An optical wavefront control pattern generating apparatus (1) relating to the present invention includes: a target image detector unit (60) configured to detect spatial information of the object (B) as a target image; a reconstructed image detector unit (40) configured to detect the reconstructed image displayed on the reconstructed image display unit (30); and an optimizer unit (50) configured to evaluate, on the basis of the target image detected by the target image detector unit (40), the reconstructed image detected by the reconstructed image detector unit (40), and to apply a modification process to the optical wavefront control pattern in a way that a result of the evaluation satisfies a predetermined condition, so as to generate the optimum optical wavefront control pattern.
US08022343B2 Aiming system with integrated deviation meter
According to the invention, the system comprises an infrared detector (7) for alternately generating images (5′) of sources of light (5) in the near infrared emitted by a missile flying towards a target and thermal images of the observed scene, said thermal images being visible on the display means (11).
US08022341B2 High-speed cooking oven with optimized cooking efficiency
An improved oven is aimed at optimizing heat transfer and delivering an optimal cooking efficiency in comparison to conventional high-speed cooking ovens. The oven includes tubes that generate plume arrays of a heated gas and introduce them into a cooking chamber of the oven. The tubes may be removably located at the bottom of the cooking chamber of the oven. The tubes are dimensioned for hot air impingement to tighten impingement plume arrays, subject to the space constraints of the oven's cooking chamber. With the optimized cooking efficiency provided by the present invention, high-speed cooking technology may now be extended to ovens operating on a power supply based on a voltage less than 220 volts, preferably between 110 and 125 volts, with more productive results, so that the high-speed cooking technology may find wider applicability and a broader customer base.
US08022340B2 Attaching unit and knob for a heating unit of a cigar lighter
The invention relates to a unit for fixing a base body provided with a housing of a cigar lighter heating element, in particular for motor vehicles. The inventive fixing unit is used for fixing a button actuating said heating element. Said fixing unit comprises a fixing element fixable to the housing of the base body of the heating element and an adapter for fixing the button, wherein said adapter is adjustably inserted into the fixing element and is guided in such a way that it is axially displaceable with respect thereto. The fixing unit makes it possible to mount the button only at a last operation for assembling said heating element, thereby enabling the button, which is embodied in the form of a decorative element, not to be exposed to mechanical stresses produced during an assembling process and to prevent the button damage by assembling operations.
US08022338B2 Heating element for a filter press
The invention relates to a heating element for a filter press, that can be supplied with a fluid heating medium and comprises at least one heating plate consisting of a heat-conducting material and extending essentially over a plane. Said heating plate is fixed to a base body of the heating element, exclusively in a continuous partial region, the surface of the continuous partial region being smaller than the remaining surface of the heating plate. The invention also relates to a heating element for a filter press, comprising two heating plates which are interconnected by means of spacers, outside the lateral expansion of the base body. The entire base body can be freely displaced between the heating plates, in relation thereto, at least in such a way that a thermal expansion of the heating plates and a different thermal expansion of the base body can take place.
US08022335B2 Rapid warm-up and cool-down pressure roll assembly and a fusing apparatus including same
A rapid warm-up and cool-down pressure roll assembly is provided and includes (a) a rotatable pressure roll including a cylindrical sleeve having an outer surface, and an inner surface defining a hollow interior to the rotatable pressure roll; (b) a thermoelectric assembly sheet positioned within the hollow interior and having a first substrate facing the inner surface of the cylindrical sleeve, a second substrate, an electric current flow path therethrough, and electric current input and output terminals associated with the electric current flow path; and (c) an electric current input switching device connected to the electric current input and output terminals for enabling selective reversing of a direction of electric current flow through the electric current flow path, thereby reversing which of the first substrate and the second substrate of the thermoelectric assembly sheet is hot and which is cold, and therefore selectively enabling a rapid warm-up or rapid cool-down of the cylindrical sleeve of the pressure roll.
US08022327B2 Switch, circuitry, and method of assembly for electrosurgical pencil
Formation of an assemblage of electrically conductive components for a new electrosurgical pencil is disclosed, and assembly of those components in a method for automating the manufacture and combination of current carrying metal circuitry and operable switching components in “electrosurgical pencils” which supply current to an active terminal, for application of high frequency or high power electrical current to a surgical site, and control of such current through coaction of the elements of the switch. In manufacture, the design of the switch components allows start-to-finish automated assembly of the switch, in an industry which knows only partially automated assembly, and partial assembly by hand, to create an improved tool for surgical cutting, coagulation, and cauterizing.
US08022321B2 Hydraulic pressure switch with porous disc as snubbing element
A hydraulic pressure switch apparatus includes a porous disc directly installed at a media entry port for dampening and filtration purposes. The porous disc includes a number of pores that are connected together and to the surface of the porous disc for allowing media to flow into a base fitting. The media exerts pressure on a piston associated with the base fitting, which in turn is capable of being absorbed by a compression spring. The compression spring transfers a required motion to a plunger associated with a micro switch in order to provide on/off switching capabilities. Electrical indications can then be transferred to a vehicle control unit utilizing a termination connector, based on particular user requirements. The porous disc can be utilized to dampen the pressure spikes and surges, which significantly prolong the life of the pressure switch apparatus in harsh applications.
US08022318B2 Arrangement for removable control elements
An arrangement is provided for the overall handling of removable controls for an electrical device including the installation and removal of controls from a base or other housing portion of the overall device, e.g. an overhead switch utilized in electrical power distribution/transmission. The arrangement includes facilities for selectively securing or releasing the controls with respect to cooperating housing portions of the device. An operating member is provided with provisions for cooperating with the controls for securing and releasing the control with respect to the operating member. In a preferred arrangement, the controls have separate control functions.
US08022309B2 Flexible printed circuit board
An exemplary FPCB includes a signal layer having a differential pair consisting of two transmission lines arranged therein, a ground layer, and a dielectric layer lying between the signal layer and the ground layer. Two sheets made of conductive materials are respectively arranged at opposite sides of the differential pair, and both connected to ground. The sheets are apart from and parallel to the transmission lines. The ground layer has a void defined therein, and the void is located under the two transmission lines.
US08022307B2 Fabric circuits and method of manufacturing fabric circuits
A flexible, fabric-based circuit comprises a non-conductive flexible layer of fabric and a conductive flexible layer of fabric adjacent thereto. A non-conductive thread, an adhesive, and/or other means may be used for attaching the conductive layer to the non-conductive layer. In some embodiments, the layers are attached by a computer-driven embroidery machine at pre-determined portions or locations in accordance with a pre-determined attachment layout before automated cutting. In some other embodiments, an automated milling machine or a computer-driven laser using a pre-designed circuit trace as a template cuts the conductive layer so as to separate an undesired portion of the conductive layer from a desired portion of the conductive layer. Additional layers of conductive fabric may be attached in some embodiments to form a multi-layer construct.
US08022301B2 Collet-type splice and dead end for use with an aluminum conductor composite core reinforced cable
This invention relates to collet-type splices and collet-type dead ends and methods for splicing together two electricity transmission cables or terminating one electricity transmission cable, the cables comprising a composite core surrounded by a conductor. The collet-type fittings use a collet inside a collet housing to hold the composite cores without penetrating or otherwise weakening the core itself. The composite cores can be stripped of the aluminum conductor to provide a bond between the collet and the composite core. The collet seats within the collet housing thereby holding the composite core with frictional forces. The design of the collet enables the composite core to stretch longitudinally through the collet to strengthen the frictional hold.
US08022299B2 Rotatory emergency stop cover with plug-in unit
A kind of rotatory emergency stop cover with plug-in unit includes lock cover 11 having shutter 9 that contains raised block b and return spring inside, lock base 15 having groove a, stop button 4 having torsional spring; lock cover has cam 8 and torsional spring, stop button 4 has retainer 3 and plug-in unit that is passing through stop button 4 to go into cam 8 for the connection of stop button 4 to cam 8. Shape and size of unit 1 are adjusted to woke in with that of cam 8 for only use in plug-in unit 1. Plug-in unit is operable to actuate and separate synchronously stop button 4 from cam 8 to ensure that stop button 11 won't open if plug-in unit is not inserted after locking. Support plate 13 has additional hole b, with rectangular hole c being on lock cover 7; it is convenient for user to secure with a lock without removal of unit when lock cover 11 is operated. Stop button 4 has retainer 3, retainer is used to cover hole g to prevent foreign objects from falling into after removal of plug-in unit 1.
US08022298B2 Weatherproof outlet and gasket assembly
A weatherproof outlet includes a base plate for coupling to an electrical box and a hinged cover. The base plate has at least one opening for accessing an electrical wiring device such as an electrical receptacle mounted in the electrical box. The top surface of the base plate includes an inner rim and an outer rim having a dimension to shed water away from the access opening and the wiring device. A weatherproof gasket is attached to the top surface of the base plate within the confines of the inner wall and overlying the access opening. The gasket includes a plurality of slits for receiving the prongs of a plug and to form a waterproof seal around the prongs when inserted into the slots of an electrical receptacle.
US08022297B1 Apparatus for installation of electrical floor boxes
An electrical floor box assembly for installation in a floor structure includes an electrical floor box having a plurality of sidewalls and at least one clamp device attached to a sidewall so that the floor box may be mounted to a raised floor structure or leveled atop a support surface using the clamp device. The clamp device includes a clamp body, a threaded rod mounted for rotation along a longitudinal axis within the clamp body, and a clamp arm threadingly engaging the threaded rod so that it is movable along the rod in association with rotation thereof and can be moved into engagement with the undersurface of the floor structure to secure the floor box in place. The clamp device may further include a leveling subassembly for installation of the electrical floor box onto a support surface prior to construction of the floor around the leveled floor box.
US08022296B2 Coaxial cable connector insulator and method of use thereof
A coaxial cable connector having an insulator is provided, the connector insulator including a body having a circumferential surface and a central longitudinal axis, the body having a first axial end and a second axial end and having a first reentrant cavity extending from the first end toward the second end, wherein at least a portion of a wall surface of the first reentrant cavity is oblique to a central axis of the body. A corresponding method of insulating a coaxial cable connector is disclosed.
US08022283B1 Anthropometric scaffold for keyboard-control pedal
A scaffold for ergonomic positioning and reliable support of foot-control pedals of musical instruments is disclosed. The scaffold includes a three-walled channel for engaging the distal portion of the base of typical known keyboard control pedals. The scaffold is securely positioned for optimal foot access on the floor by means of a fixation socket which is engages an adjacent floor tube of a typical stand. The foot-pedal channel is adapted to engage the typical pedal base by friction and interference clamping to support its active elements at an ergonomic height and angular orientation during an energetic live performance with the keyboard player sitting and standing during different portions.
US08022279B2 Liposomal formulations of anthracycline agents and cytidine analogs
Compositions which comprise an anthracycline agent, and a cytidine analog are encapsulated in liposomal carriers. The preferred anthracycline agent is selected from the group of daunorubicin, doxorubicin, and idarubicin, while the preferred cytidine analog is selected from the group of cytarabine, gemcitabine, or 5-azacytidine. The combination of the anthracycline agent and cytidine analog encapsulated in said liposomal carriers are useful in achieving a drug retention and a sustained drug release for each therapeutic agent.
US08022276B2 Soybean variety D5886524
The invention relates to the soybean variety designated D5886524. Provided by the invention are the seeds, plants and derivatives of the soybean variety D5886524. Also provided by the invention are tissue cultures of the soybean variety D5886524 and the plants regenerated therefrom. Still further provided by the invention are methods for producing soybean plants by crossing the soybean variety D5886524 with itself or another soybean variety and plants produced by such methods.
US08022270B2 Expression of biologically active polypeptides in duckweed
Methods, nucleic acid sequences, and transformed duckweed plant or duckweed nodule cultures for the expression and the secretion of biologically active polypeptides from genetically engineered duckweed are provided. Expression of recombinant polypeptides in duckweed is improved by modifying the nucleotide sequence of the expression cassette encoding the polypeptide for improved expression in duckweed. Recovery of biologically active polypeptides from duckweed is improved by linking the biologically active polypeptide to a signal peptide that directs the secretion of the polypeptide into the culture medium.
US08022268B2 Transgenic animal model for alzheimer's disease
Provided is a novel APP (amyloid precursor protein) transgenic non-human animal modeling in vivo the pathophysiological effects and effects on cognitive behavior of early intraneuronal and extracellular brain parenchymal amyloid-β (Aβ) deposition and cerebral amyloid angiopathy associated with brain microhemorrhages and reduced vasoreactivity and blood flow. Furthermore, methods of screening for therapeutic or diagnostic agents useful in the treatment or diagnosis of Alzheimer's disease, in particular for improving blood flow to the brain are provided as well as the corresponding therapeutic methods.
US08022267B2 Hydroentangled nonwoven fabric, method of making it and absorbent article containing the fabric
A nonwoven fabric comprising at least 50% by weight microfibers having a fineness of 1.0 dtex or less and a length of at least 30 mm and having been combined by hydroentangling. The fabric is apertured by said hydroentangling, and has been carded before hydroentangling. The fabric may be used as a topsheet material on an absorbent article.
US08022265B2 Reduced weight decontamination formulation utilizing a solid peracid compound for neutralization of chemical and biological warfare agents
A reduced weight decontamination formulation that utilizes a solid peracid compound (sodium borate peracetate) and a cationic surfactant (dodecyltrimethylammonium chloride) that can be packaged with all water removed. This reduces the packaged weight of the decontamination formulation by ˜80% (as compared to the “all-liquid” DF-200 formulation) and significantly lowers the logistics burden on the warfighter. Water (freshwater or saltwater) is added to the new decontamination formulation at the time of use from a local source.
US08022262B1 UZM-35 zeolitic composition method of preparation and processes
A new family of crystalline aluminosilicate zeolitic compositions, UZM-35 compositions, has been synthesized. These zeolitic compositions are represented by the empirical formula. Mmn+Rr+Al(1-x)ExSiyOz where M represents a combination of potassium and sodium exchangeable cations, R is a singly charged organoammonium cation such as the dimethyldipropylammonium cation and E is a framework element such as gallium. These compositions comprise a MSE zeolite, a MFI zeolite and an ERI zeolite. The compositions are similar to MCM-68 but are characterized by unique x-ray diffraction patterns and have catalytic properties for carrying out various hydrocarbon conversion processes.
US08022261B2 Catalyst composition, the method of manufacturing, and the process of use thereof in aromatics alkylation
A catalyst composition comprises a crystalline MCM-22 family molecular sieve and a binder, wherein the catalyst composition is characterized by an extra-molecular sieve porosity greater than or equal to 0.122 ml/g for pores having a pore diameter ranging from about 2 nm to about 8 nm, wherein the porosity is measured by N2 porosimetry. The catalyst composition may be used for the process of alkylation or transalkylation of an alkylatable aromatic compound with an alkylating agent. The molecular sieve may have a Constraint Index of less than 12, e.g., less than 2. Examples of molecular sieve useful for this disclosure are a MCM-22 family molecular sieve, zeolite Y, and zeolite Beta.
US08022252B2 Spatially-defined macrocyclic compounds useful for drug discovery
Novel spatially-defined macrocyclic compounds containing specific conformational control elements are disclosed. Libraries of these macrocycles are then used to select one or more macrocycle species that exhibit a specific interaction with a particular biological target. In particular, compounds according to the invention are disclosed as agonists or antagonists of a mammalian motilin receptor and a mammalian ghrelin receptor.
US08022248B2 Substituted acids for the treatment of respiratory diseases
The invention relates to substituted acids of formula (I), where T, W, X, Y, Z, R1 and R2 as defined in the claims, as useful pharmaceutical compounds for treating asthma and rhinitis, pharmaceutical compositions containing them, and a processes for their preparation.
US08022247B2 Process for production of 2,3,4-trifluoro-5-(iodo or bromo)-benzoic acid
The invention provides a process for production of 2,3,4-trifluoro-5-(iodo or bromo)benzoic acid, the process comprising a halogenation step in which direct iodination or bromination of 2,3,4-trifluorobenzoic acid is performed with an iodinating agent or brominating agent in a reaction solvent in the presence of an oxidizing agent. According to the invention, there is provided a process for convenient production of 2,3,4-trifluoro-5-(iodo or bromo)benzoic acid in high yield and high purity in a highly regioselective manner.
US08022244B2 Method for producing benzoic acid esters
A process for preparing benzoic esters whose alkoxy groups have from 7 to 13 carbon atoms by reacting benzoic acid with at least one alcohol having from 7 to 13 carbon atoms, the water of reaction formed being removed during the esterification reaction by distillation, and the alcohol not converted in the esterification reaction being removed after the esterification reaction, in which the reaction takes place in the presence of a tin(II) compound as catalyst and, without treatment with a base, the catalyst and/or its derivatives is/are separated off by filtering or by centrifuging from the reaction mixture which remains after the unconverted alcohol has been separated off.
US08022240B2 Processes for purifying diaryl carbonates
Processes comprising: transesterifying a dialkyl carbonate and an aromatic hydroxyl compound in the presence of a transesterification catalyst to provide a diaryl carbonate product comprising the transesterification catalyst as an impurity; subjecting the diaryl carbonate product to distillation in a first distillation column having an upper part and a lower part, wherein the upper part comprises a rectifying section and the lower part comprises a stripping section; and withdrawing a first sidestream from the first distillation column, wherein the first sidestream comprises a purified diaryl carbonate.
US08022238B2 Phosphate surfactants
A compound of Formula 1 Rf-A-OP(O)(O−M+)(OROH)  Formula 1 wherein Rf is a C2 to C6 linear or branched perfluoroalkyl optionally interrupted by one, two or three ether oxygen atoms; A is (CH2CF2)m(CH2)n—, (CH2)oSO2N(CH3)(CH2)p—, O(CF2)q(CH2)r—, or OCHFCF2OE-; m is 0 to 4; n, o, p, and r are each independently 2 to 20; q is 2; E is a C2 to C20 linear or branched alkyl group optionally interrupted by oxygen, sulfur, or nitrogen atoms; a cyclic alkyl group, or a C6 to C10 aryl group; M is H or a Group I metal or an ammonium cation (NHxR2y)+ wherein R2 is a C1 to C4 alkyl, x is 0 to 4, y is 0 to 4 and x+y is 4; and R is a C2 to C60 linear or branched alkyl group optionally interrupted by hetero atoms selected from the group consisting of an oxygen, sulfur, or nitrogen atom; a cyclic alkyl; or a C6 to C10 aryl; provided that when R is greater than 8 carbons, the ratio of hetero atoms to carbon atoms is at least 1:2.
US08022236B2 Fatty acid alkyl ester production from oleaginous seeds
A process is described for producing fatty acid alkyl esters for both diesel fuel and non-fuel uses. The feed material includes whole oleaginous seeds slurried in a liquid triglyceride oil containing at least two weight percent free fatty acid, wherein oil from inside the seeds is first extracted with concurrent esterification of free fatty acids from all sources in an acidic environment. Following sufficient free fatty acid reaction, the intermediate product is subjected to base-catalyzed concurrent extraction and transesterification. Decanting of the byproduct glycerin is followed by water washing. Subsequently, the fatty acid ester product is concurrently purified and fractionated into a biodiesel fuel stream and a non-fuel fraction, each of which undergoes post treatment as needed. The process is optionally integrated with glycerin purification and/or methanol recovery.
US08022231B2 Process for preparing monochloroethylene carbonate and subsequent conversion to vinylene carbonate
Processes for preparing monochloroethylene carbonate include reacting ethylene carbonate with chlorine gas in a liquid phase under irradiation of UV light and introducing a separate feed of an inert gas into the liquid phase. Monochloroethylene carbonate may be subsequently converted to vinylene carbonate.
US08022230B2 Dimeric IAP inhibitors
Molecular mimics of Smac are capable of modulating apoptosis through their interaction with cellular IAPs (inhibitor of apoptosis proteins). The mimetics are based on a monomer or dimer of the N-terminal tetrapeptide of IAP-binding proteins, such as Smac/DIABLO, Hid, Grim and Reaper, which interact with a specific surface groove of IAP. Also disclosed are methods of using these peptidomimetics for therapeutic purposes. In various embodiments of the invention the Smac mimetics of the invention are combined with chemotherapeutic agents, including, but not limited to topoisomerase inhibitors, kinase inhibitors, NSAIDs, taxanes and platinum containing compounds use broader language.
US08022226B2 Nonsedating α-2 agonists
The present invention provides an α-2A/α-1A selective agonist that includes a compound represented by Structure 1 or a pharmaceutically acceptable salt, ester, amide, sterioisomer or racemic mixture thereof. The present invention further provides a pharmaceutical composition that contains a pharmaceutical carrier and a therapeutically effective amount of an α-2A/α-1A selective agonist that includes a compound represented by Structure 1 or a pharmaceutically acceptable salt, ester, amide, sterioisomer or racemic mixture thereof.
US08022222B2 Glucokinase activators
Provided are compounds of formula I wherein R2, L, Z, Y, G and R1 are as defined herein, that are useful in the treatment and/or prevention of diseases or disorders mediated by deficient levels of glucokinase activity or which can be treated by activating glucokinase including, but not limited to, diabetes mellitus, impaired glucose tolerance, IFG (impaired fasting glucose) and IFG (impaired fasting glycemia), as well as other diseases and disorders such as those discussed herein.
US08022221B2 Aurora kinase modulators and method of use
The present invention relates to chemical compounds having a general formula I wherein A1, A2, C1, C2, D, L1, L2, Z and R3, R4, R6, R7 and R8 are defined herein, which are capable of modulating Aurora kinase protein activity, thereby influencing various disease states and conditions related to the activities of Aurora kinase proteins. For example, the compounds are capable of influencing the process of cell cycle and cell proliferation to treat cancer and cancer-related diseases. The invention also includes pharmaceutical compositions, processes of preparing compounds of the invention, synthetic intermediates and methods of treatment of conditions related to the activity of Aurora kinase.
US08022218B2 4-phenyl-5-oxo-1,4,5,6,7,8-hexahydroquinoline derivatives for the treatment of infertility
The present invention relates to 4-phenyl-5-oxo-1,4)5,6,7,8-hexahydroquinoline derivatives according to Formula I, Formula I or a pharmaceutically acceptable salt thereof, wherein R1 is (1-6C)alkyl, (2-6C)alkenyl or (2-6C)aDcynyl; R2, R3 are independently halogen, (1-4C)allcyl, (2-4C)alkenyl, (2-4C)-alkynyl, (1-4C)aBcoxy, (3-4C)alkenyloxy or (3-4C)alkynyloxy; R4 is phenyl or (2-5C)-heteroaryl, both substituted with R7 and optionally substituted on the (hetero)aromatic ring with one or more substituents selected from hydroxy, amino, halogen, nitro, trifluoromethyl, cyano, (1-4C)alkyl, (1-4C)alkoxy, (1-4C)alkylthio and (di)(1-4C)-alkylamino. The invention also relates to pharmaceutical compositions comprising said derivatives, as well as to the use of these 4-phenyl-5-oxo-1,4,5,6,7,8-hexahydro-quinoline derivatives in therapy, more specifically for the treatment of infertility.
US08022216B2 Maleate salts of (E)-N-{4-[3-chloro-4-(2-pyridinylmethoxy)anilino]-3-cyano-7-ethoxy-6-quinolinyl}-4-(dimethylamino)-2-butenamide and crystalline forms thereof
The present invention relates to maleate salt forms of (E)-N-{4-[3-chloro-4-(2-pyridinylmethoxy)anilino]-3-cyano-7-ethoxy-6-quinolinyl}-4-(dimethylamino)-2-butenamide, methods of preparing crystalline maleate salt forms, the associated compounds, and pharmaceutical compositions containing the same. The maleate salts are useful in treating cancers, particularly those affected by kinases of the epidermal growth factor receptor family.
US08022214B2 Organic semiconductor materials and precursors thereof
The present teachings provide novel organic semiconductor compounds and their soluble precursors, methods for preparing these compounds and precursors, as well as compositions, materials, articles, structures, and devices that incorporate such compounds.
US08022212B2 Light-emitting element and iridium complex
A light-emitting element having excellent light-emitting properties and with which it is possible to emit blue light at a high luminance for a long period of time, and an iridium complex for realizing the same. The light-emitting element has an external quantum efficiency of at least 5% and a light emission maximum wavelength λ max of no more than 500 nm. Further, there is provided a light-emitting element including a light-emitting layer or a plurality of organic compound layers having the light-emitting layer, with at least one of the compound layers including at least one kind of a compound having a partial structure represented by the general formula K-0. In the general formula K-0, R1 to R7 each independently represents a hydrogen atom or a substituent, provided that if R2 is a fluorine atom, R3 is not a hydrogen atom.
US08022210B2 Soluble amide and ester pyrazinoylguanidine sodium channel blockers
The present invention relates to pyrazinoylguanidine compounds represented by formula (I): where X, Y and R1-R4 are as defined herein. The compounds of the present invention are useful as sodium channel blockers.
US08022208B2 Benzene derivative or salt thereof
Problem: To provide compounds which have an anticoagulation effect based on their ability to inhibit the activated blood coagulation factor X and are useful as coagulation inhibitors or agents for prevention or treatment for diseases caused by thrombi or emboli.Means for Solution: Benzene derivatives or their salts having a characteristic chemical structure with a phenol ring and a benzene ring bonding to each other via an amide bond, in which the phenol ring further bonds to a benzene ring or a heteroaryl ring via an amide bond. They have an excellent effect of inhibiting the activated blood coagulation factor X, and especially have an excellent oral activity.
US08022205B2 Pyrimidine derivatives as PI3K inhibitor and use thereof
A drug is provided that is useful as a preventive or therapeutic for cancer as a result of having superior PI3K inhibitory effects as well as superior stability in the body and water-solubility.A compound, or pharmaceutically acceptable salt thereof, represented by formula (I): [wherein, X represents a single bond, etc.; Y represents a single bond, etc. (provided that X and Y are not simultaneously single bonds); Z represents a hydrogen atom, etc.; m represents an integer of 1 or 2; and R1 represents a cyclic substituent].
US08022199B2 SiRNA targeting myeloid differentiation primary response gene (88) (MYD88)
Efficient sequence specific gene silencing is possible through the use of siRNA technology. By selecting particular siRNAs by rational design, one can maximize the generation of an effective gene silencing reagent, as well as methods for silencing genes. Methods, compositions, and kits generated through rational design of siRNAs are disclosed including those directed to nucleotide sequences for MYD88.
US08022197B2 Nucleic acid and gene derived from novel HCV strain and replicon-replicating cell using said gene
The present invention relates to a gene derived from a novel fulminant hepatitis C virus strain, an HCV replicon RNA with a high replication efficiency obtained using the gene, and an HCV replicon-replicating cell transfected with the replicon RNA. When the HCV replicon RNA and the HCV replicon-replicating cell of the present invention are used, HCV proteins can be continuously produced in a large amount.
US08022194B2 2′-nitrobenzyl-modified ribonucleotides
This disclosure provides novel reversibly terminated ribonucleotides which can be used as a reagent for DNA sequencing reactions. Methods of sequencing nucleic acids using the disclosed nucleotides are also provided.
US08022187B2 FVIII-independent FIX-mutant proteins for hemophilia A treatment
The present invention relates to recombinant blood coagulation factor IX (rFIX) mutants having factor VIII (FVIII) independent factor X (FX) activation potential. Five full length FIX proteins with combinations of mutations of amino acids important for functional activity of FIX and FIX wild type were cloned and expressed in HEK 293 cells. The proteins were tested by an activated partial thromboplastin time (aPTT) assay in FVIII-depleted plasma as well as in FVIII-inhibited patient plasma. In FVIII-depleted plasma functional activity of the FIX mutants was calculated as increased FVIII equivalent activity. The mutant proteins had increased FVIII equivalent activity. In FVIII-inhibited patient plasma the FEIBA equivalent activity was calculated for analysis of FVIII independent FX activation potential. The proteins had also increased FEIBA equivalent activity. Furthermore, the pre-activated FIX proteins had an increased activity in FIX-depleted plasma containing FVIII inhibitors. Therefore these FIX mutants are alternatives as bypassing agents for treatment of FVIII inhibitor patients.
US08022186B2 Modified human plasma polypeptide or Fc scaffolds and their uses
Modified human plasma polypeptides or Fc and uses thereof are provided.
US08022184B2 IFBM's to promote the specific attachment of target analytes to the surface of orthopedic implants
The present invention provides an improved coating for surfaces of medical implants. The coating comprises at least one interfacial biomaterial (IFBM) which is comprised of at least one binding module that binds to the surface of an implant or implant-related material (“implant module”) and at least one binding module that selectively binds to a target analyte or that is designed to have a desired effect (“analyte module”). The modules are connected by a linker. In some embodiments, the IFBM coating acts to promote the recognition and attachment of target analytes to surface of the device. The IFBM coating improves the performance of implanted medical devices, for example, by promoting osteointegration of the implant.
US08022181B2 Composition and method for the release of protected peptides from a resin
The present invention provides a composition and a method for cleaving a peptide from a solid support resin. Hydrochloric acid in an organic water miscible solvent is used to cleave the peptide-resin attachment. Optionally, trifluoroethanol or hexafluoroisopropanol may be added to the cleavage composition to improve results. When using the present cleavage composition, an evaporation or other step to remove carboxylic byproducts is not necessary following the cleavage reaction. After the resin is filtered out of the cleavage mixture, the peptide may be immediately precipitated with water.
US08022180B2 Method for preventing and treating Alzheimer's disease
The invention relates to the use of a compound comprising the following amino acid sequence X1X2X3X4X5X6X7, wherein X1 is an amino acid, except of C, X2 is an amino acid, except of C, X3 is an amino acid, except of C, X4 is an amino acid, except of C, X5 is an amino acid, except of C, X6 is not present or any amino acid, X7 is not present or any amino acid, and wherein X1X2X3X4X5X6 is not DAEFRH, said compound having a binding capacity to an antibody being specific for the natural N-terminal Aβ42 sequence DAEFRH, and 5-mers thereof having a binding capacity to said antibody being specific for the natural N-terminal Aβ42 sequence DAEFRH, for the preparation of a vaccine for Alzheimer's disease.
US08022175B1 Production of anti-peptide monoclonal antibodies to distinguish Exotic New Castle diseases viruses from vaccine strains of Newcastle disease virus
Anti-peptide monoclonal antibodies (MAb's) specific for Exotic Newcastle Disease (END) are used for rapid diagnostic identification between poultry infected with vaccine strains of NDV (LaSota/B1) and END virus (ENDV). Exotic Newcastle Disease is a contagious and fatal viral disease of birds and poultry. The present invention provides for diagnostic detection of ENDV in commercial poultry.
US08022172B2 Luminescence resonance energy transfer (LRET) assays for clostridial toxin activity
Clostridial toxin substrates comprising a lanthanide donor complex, an acceptor, and a Clostridial toxin recognition sequence including a cleavage site; methods for determining the activity of a Clostridial toxin from a test sample using such Clostridial toxin substrates; cell compositions comprising such Clostridial toxin substrates and a Clostridial toxin receptor; and methods for determining the activity of a Clostridial toxin from a test sample using such cell compositions.
US08022171B2 Process for making a monofilament-like product
The invention relates to a process for making a monofilament-like product from a precursor containing a multitude of continuous polyolefin filaments, comprising exposing the precursor to a temperature within the melting point range of the polyolefin for a time sufficient to at least partly fuse adjacent fibers and simultaneously stretching the precursor at a draw ratio of at least 2.8. With the process according to the invention a monofilament-like product can be made that shows improved tensile properties; making it very suitable for application as e.g. fishing line.
US08022169B2 Aliphatic copolyesters and method of preparing the same
A method of preparing an aliphatic copolyester by mixing a first compound defined by the equation: and a catalyst, and adding a second compound defined by and a lactide, wherein the second compound and the lactide have a total weight less than the first compound, wherein a is 10-230, b, d and e have a ratio of 10-35:10-35:80-30, c is 1-4, and f is 1-10. The method further adds the second compound and the lactide, wherein the second compound and the lactide have a total weight less than the first compound, the second compound and the lactide in the prior mixing step. The method further adds the second compound and the lactide, wherein the second compound and the lactide have a total weight less than the first compound, the second compound and the lactide in of the prior mixing steps.
US08022168B2 Spheroidal polyester polymer particles
Spheroidal polyester polymer particles, as well as preforms and stretch blow molded bottles made from the spheroidal particles, are provided which have: A) an It.V. of at least 0.72 dL/g, and either B) at least two melting peaks (on a DSC first heating scan), wherein one of said at least two melting peaks is a low peak melting point having a peak temperature within a range of 140° C. to 220° C. and having a melting endotherm area of at least the absolute value of 1 J/g, or C) a low degree of crystallinity within a range of at least 20% and a maximum degree of crystallinity Tcmax defined by the equation: Tcmax=50%−CA−OH where CA is the total mole % of all carboxylic acid residues other than terephthalic acid residues, based on 100 mole % of carboxylic acid residues in the polyester polymer, and OH is the total mole % of hydroxyl functional compound residues other than ethylene glycol residues, based on 100 mole % of the hydroxyl functional compounds residues; or both B) and C); and optionally but preferably D) 10 ppm or less of residual acetaldehyde.
US08022166B2 Polycarbonate compositions
Polycarbonate compositions are disclosed. The compositions comprise a polycarbonate polymer (A) having repeating units derived from 2-phenyl-3,3-bis(4-hydroxyphenyl)phthalimidine (PPPBP); a polycarbonate polymer (B) which is different from polymer (A); and an impact modifier (C) which is different from polymer (A) and polymer (B). The resulting composition has an improved combination of properties, particularly heat resistance, low temperature impact performance, and viscosity. Also disclosed are articles formed from such compositions.
US08022164B1 Two-component solvent-free polyurethane adhesives
A two-component solvent-free polyurethane laminating adhesive for flexible packaging, including a First Component and a Second Component is provided. The First Component, which acts as a resin, includes a first vegetable oil based Polyol A in an amount from 20 to 40 weight percent, a second vegetable oil based Polyol B in an amount from 0.5 to 5 weight percent, and a Polyisocyanate C in an amount from 60 to 74 weight percent. The Second Component, which acts as a hardener, includes a first vegetable oil based Polyol A in an amount from 87 to 99 weight percent, and a Polyol E in an amount from 0.5 to 5 weight percent. The first vegetable oil based Polyol A is preferably a hydroxylated castor oil, and the second vegetable oil based Polyol B is preferably hydroxylated linseed oil.
US08022160B2 Process for making a monofilament-like product
The invention relates to a process for making a monofilament-like product from a precursor containing at least one strand of fibers made from ultra-high molar mass polyethylene, comprising a) exposing the precursor to a temperature within the melting point range of the polyethylene for a time sufficient to at least partly fuse adjacent fibers and b) simultaneously stretching the precursor, wherein the precursor is mechanically compressed during fusing. The monofilament-like product thus made has a smoother surface appearance, and improved abrasion resistance, for example a reduced tendency to pilling during use as fishing line, than known similar products; making it very suitable for use as fishing line and the like. The invention further relates to a monofilament-like product obtainable by said process, and to semi-finished and end-use products comprising said monofilament-like product.
US08022156B2 Greaseproof paper
A greaseproof paper is provided for use in food processing and/or packaging of foods in which paper has been rendered oleophobic by treatment with a fluorine-containing polymer. The fluorine-containing polymer may be prepared by polymerizing a fluorine-containing monomer in the presence of a mercapto group-containing organopolysiloxane. The fluorine-containing polymer may be applied to paper by coating onto pre-formed paper, or by applying the polymer as a size during a papermaking process.
US08022152B2 Copolymers of vinyl- and allylsilanes
Ethylene and allyl- or vinylsilanes are efficiently copolymerized by certain late transition metal complexes containing selected bidentate or tridentate ligands. The resulting novel polymers may be crosslinked by moisture when vinylsilane contains groups bound to silicon which are hydrolyzable. The polymers are useful for wire coating, crosslinked foams, pipes, and other uses.
US08022151B2 Adamantane derivative, method for producing the same, resin composition containing the adamantane derivative and use thereof
Provided are: an adamantane derivative represented by the following general formula (I) giving a cured product excellent in optical characteristics such as transparency and light resistance, durabilities such as heat resistance, and electrical characteristics such as dielectric constant; a method of producing the adamantane derivative; a resin composition containing the adamantane derivative and an epoxy resin curing agent; and a sealing agent for an optical semiconductor using the resin composition: where: Y represents a group selected from a hydrocarbon group, a hydroxyl group, a carboxyl group, and an ═O group formed by two Y's being combined together; Z represents a cyclic ether group; n represents an integer of 0 or more; and p represents an integer of 2 to 4 and q represents an integer of 0 to 14, while satisfying 2≦p+q≦16.
US08022149B2 Organic polymer containing reactive silicon group
The present invention provides a solution to a problem that a composition including a reactive silicon group-containing polyether undergoes red coloration. More specifically, in a reactive silicon group-containing organic polymer which contains Co, the problem concerned is solved by limiting the Co content to 0.5 ppm or less. As the reactive silicon group-containing organic polymer, for example, a reactive silicon group-containing polyether (A) or a mixture of the reactive silicon group-containing polyether (A) and a vinyl polymer (B) may be cited. The reactive silicon group-containing polyether (A) is obtained, for example, by reacting a polyether or a derivative thereof which contains Co in a content of 0.5 ppm or less with a silane compound which has a group capable of reacting with the polyether or the derivative thereof and has a hydrolyzable group.
US08022147B2 Zwitterionic block copolymers and methods
Zwitterionic block copolymers having oppositely charged or chargeable terminal groups, and methods of making and using the same, are disclosed. The zwitterionic block copolymers can undergo microphase separation.
US08022145B2 Dicing and die attach adhesive
Provided is a single layer adhesive that provides the appropriate balance of adhesion and clean release required for a wafer dicing function and also provides the necessary bond required in a subsequent die attach step. The adhesive composition comprises an acrylate ester polymer having a functional group, a multi-functional thermosetting resin, wherein the acrylate ester polymer and the thermosetting resin are capable of reacting with each other, a multi-functional acrylate ester, an acrylate ester polymerization catalyst or curing agent, a thermally-latent catalyst suitable for curing the multi-functional thermosetting resin, and an acrylic acid salt.
US08022142B2 Thermoplastic olefin compositions
An in-reactor polymer blend including (a) a propylene-containing first polymer; and (b) propylene-containing second polymer having a different crystallinity from the first polymer. The polymer blend has a melting temperature, Tm, of at least 135° C., a melt flow rate of at least 70 dg/min, a tensile strength of at least 8 MPa, an elongation at break of at least 300%.
US08022140B2 Epoxy resin, styrene-maleic anhydride copolymer and crosslinking agent
A composition useful as an impregnant for the making of laminates for printed wiring boards including an epoxy resin, a first cross-linking agent of a strene-maleic anhydride copolymer and a second co-cross-linking agent.
US08022132B2 Rubber composition for studless tire and studless tire
The present invention provides a rubber composition for a studless tire, which can achieve sufficient abrasion resistance, performance on ice and snow, and wet grip performance in a balanced manner, and a studless tire having a tread produced from the above composition. The rubber composition for a studless tire contains a rubber component including natural rubber and butadiene rubber; aromatic oil; silica; and carbon black, wherein the total amount of the natural rubber and the butadiene rubber is 30% by mass or more based on 100% by mass of the rubber component, the amount of the aromatic oil is 12-85 parts by mass and the amount of the silica is 12-85 parts by mass, per 100 parts by mass of the rubber component, and the proportion of the silica is 45% by mass or more based on 100% by mass of the total of the silica and the carbon black.
US08022129B2 Conjugated diolefin copolymer rubber, method for producing the same, rubber composition and tire
A conjugated diolefin copolymer rubber is produced by copolymerization of a conjugated diolefin and an aromatic vinyl compound and has a primary amino group and an alkoxysilyl group bonded to the copolymer chain. The conjugated diolefin copolymer rubber contains the aromatic vinyl compound in an amount of 5 to 60 wt %. The aromatic vinyl compound is densely distributed in one terminal of the copolymer chain, and is scarcely distributed in the other terminal. The conjugated diolefin copolymer rubber has a temperature difference (ΔTg) of 25° C. or more. The conjugated diolefin copolymer rubber has low hysteresis loss properties as well as improved abrasion resistance, rupture characteristics, and road grip characteristics without impairing wet skid characteristics. A method for producing the conjugated diolefin copolymer rubber is also disclosed.
US08022127B2 Plastisols containing glycerol esters as plasticizers
Plastisols and organosols are provided that include plasticizers that include mono-, di- and triesters of glycerol. The plasticizers are good solvators for polyvinyl chloride and impart low plastisol and organosol viscosities.
US08022125B2 Pressure-sensitive adhesive sheet
A pressure-sensitive adhesive sheet contains at least a pressure-sensitive adhesive layer containing an acrylic pressure-sensitive adhesive containing an acrylic polymer composition containing an acrylic polymer as a main component and a tackifier containing a tackifying resin as a main component, wherein reflection rate and attached amount in the fogging test in accordance with German Industrial Standard DIN 75201 are 70% or more and 2.0 mg or less, respectively. In the acrylic pressure-sensitive adhesive which forms the pressure-sensitive adhesive layer, a ratio of components having a molecular weight of 300 or less is preferably 4.2% by weight or less based on the total amount of solid matter of the acrylic pressure-sensitive adhesive. Furthermore, in the tackifying resin in the tackifier, a ratio of components having a molecular weight of 300 or less is suitably 4.2% by weight or less based on the total amount of solid matter of the tackifying resin.
US08022121B2 Rubber composition for studless tire and studless tire
The present invention provides a rubber composition for a studless tire and a high-performance studless tire produced therefrom, which achieve good braking force and handling stability on ice and snow. The rubber composition for a studless tire includes: a rubber component; a zinc salt of a C4-C12 aliphatic carboxylic acid, or a C4-C12 aliphatic carboxylic acid and zinc oxide; and an oil or a plasticizer. The rubber component contains 40% by mass or more of butadiene rubber per 100% by mass of the rubber component.
US08022120B2 Comb polymers and their use as additives for preparations of mineral binders
The present invention relates to novel comb polymers which bear poly-C2-C4-alkylene ether side chains A and functional groups B which at a pH of >12 are present in the form of anionic groups on a carbon backbone and also the salts of such comb polymers. The invention also relates to the use of these comb polymers as additives in preparations comprising a mineral binder. The polyalkylene ether side chains A have the following formula: *—U—(C(O))k—X-(Alk-O)n—Y—Z  A.
US08022116B2 Lightweight rigid structural compositions with integral radiation shielding including lead-free structural compositions
Lightweight and rigid, leaded or lead-free integral radiation shielding structural compositions comprising two or more radiation attenuating elements or compounds thereof, selected for having compatible radiation attenuating characteristics, dispersed in a thermoplastic or thermoset resin. The radiation shielding structural compositions of the present invention can be used to functionally and structurally replace lead-lined structures in medical and industrial x-ray systems. The radiation shielding structural compositions of the present invention can also be formulated to minimize the density of the resulting structure.
US08022113B2 Composition containing aziridino groups and use thereof
The invention relates to a composition comprising a prepolymer as component (A), wherein the prepolymer comprises aziridino groups and is characterized by an equivalent weight EW1, a crosslinker as component (B), wherein the crosslinker has a structure being different from the structure of the prepolymer and comprises aziridino groups and is characterized by an equivalent weight EW2, an initiator as component (C) being able to start curing of the composition, optionally filler(s) as component (D) and optionally additive(s) as component (E), wherein equivalent weight is defined as (molecular mass of the molecule)/(number of aziridino groups present in the molecule) and wherein EW1>EW2. The invention also relates to the use of the composition for coating, sealing, moulding, adhering, making impressions, producing a dental material.
US08022112B2 Plasticized mixture and method for stiffening
A plasticized ceramic-forming mixture and a method for stiffening the mixture, the mixture comprising a combination of inorganic powder, one or more plasticizing organic binders, a radiation-curable monomer, a photoinitiator, and water, and the method comprising stiffening the surfaces of extruded shapes of the mixture by applying electromagnetic energy to the surfaces following extrusion.
US08022108B2 Acid treatment of a fischer-tropsch derived hydrocarbon stream
Novel methods of treating a Fischer-Tropsch product stream with an acid are disclosed. Such methods are capable of removing contamination from the Fischer-Tropsch product stream such that plugging of the catalyst beds of a subsequent hydroprocessing step is substantially reduced.
US08022102B2 Unsaturated tetracyclic tetrahydrofuran derivatives
This invention concerns novel substituted unsaturated tetracyclic tetrahydrofuran derivatives with binding affinities towards serotonine receptors, in particular 5-HT2A and 5-HT2C receptors, and towards dopamine receptors, in particular dopamine D2 receptors and with norepinephrine reuptake inhibition properties, pharmaceutical compositions comprising the compounds according to the invention, the use thereof as a medicine, in particular for the prevention and/or treatment of a range of psychiatric and neurological disorders, in particular certain psychotic, cardiovascular and gastrokinetic disorders and processes for their production.The compounds according to the invention can be represented by general Formula (I) and comprises also the pharmaceutically acceptable acid or base addition salts thereof, the stereochemically isomeric forms thereof, the N-oxide form thereof and prodrugs thereof, wherein all substitutents are defined as in Claim 1.
US08022101B2 Method of treating a knee meniscus with a cross-linking reagent to increase resistance to tearing or rupturing
A method of treatment of native, non-denatured tissue to increase resistance to tearing, fissuring, rupturing, and/or delamination, comprising the step of: contacting at least a portion of the tissue with an effective amount of a reagent that increases crosslinks in the tissue.
US08022097B2 Adamantane-dipyrromethane derivatives, method of preparation and applications in anion sensing
Aamantane dipyrromethane derivatives are obtained by reacting adamantane carbonyl derivatives with pyrrole or pyrrole derivative, in the presence of acid. Adamantane-dipyrromethanes are used to bind anions of the group consisting of: F—, Cl—, Br—, acetate, HSO4-NO3-, and H2PO4-, and particularly F—.
US08022094B2 Carvedilol phosphate
The invention encompasses novel amorphous and crystalline forms of carvedilol phosphate, carvedilol hydrogen phosphate, and carvedilol dihydrogen phosphate as well as methods of making the novel amorphous and crystalline forms. Also disclosed are pharmaceutical compositions comprising the novel amorphous and crystalline forms and uses thereof.
US08022092B2 (2,5-dioxoimidazolidin-1-yl)-N-hydroxy-acetamides as metalloproteinase inhibitors
The invention provides compounds of the formula (I) wherein the variables are as defined in the specification. The compounds of the invention are inhibitors of metalloproteinase MMP-12 and are among other things useful for the treatment of obstructive airway diseases, such as chronic obstructive pulmonary disease (COPD).
US08022091B2 Triazole derivative
An object of the present invention is to provide a compound having an action of inhibiting binding between S1P and its receptor, Edg-1 (S1P1), and is useful as a pharmaceutical compound. A compound or a pharmaceutically acceptable salt thereof, which compound is represented by the formula below (where A represents an oxygen atom, a sulfur atom, a group represented by Formula —SO—, a group represented by Formula —SO2—, or the like, R1 represents a hydrogen atom, an alkyl group having 1-6 carbon atoms, or the like, R1A represents a hydrogen atom or the like, R2 represents an alkyl group having 1-6 carbon atoms, a cycloalkyl group having 3-6 carbon atoms, or the like, R3 represents an aryl group, R4 represents a hydrogen atom or an alkyl group having 1-6 carbon atoms and optionally substituted with a carboxyl group, and R5 represents an alkyl group having 1-10 carbon atoms, a cycloalkyl group having 3-8 carbon atoms, an aryl group which is optionally substituted, or the like).
US08022075B2 Diagnostic and remedy for disease caused by amyloid aggregation and/or deposition
To provide a diagnostic drug which binds specifically to an amyloid aggregate and/or an amyloid deposit, to thereby realize imaging and quantification of a disease caused by amyloid aggregation and/or deposition.The invention provides a compound represented by formula (1): (wherein X1 represents an optionally substituted bicyclic heterocyclic group; X2 represents a hydrogen atom, a halogen atom, or a chelate-forming group; ring A represents a benzene ring or a pyridine ring; and ring B represents an optionally substituted 5-membered aromatic heterocyclic group which is bonded to the benzene ring or the pyridine ring via a carbon atom of ring B), a salt thereof, a solvate of any of these, or a transition metal coordination compound of any of these, and a diagnostic, preventive, or therapeutic drug containing the same.
US08022069B2 Substituted piperidines as renin inhibitors
The present invention relates to compounds of the general formula (I) and the salts thereof, preferably the pharmaceutically acceptable salts thereof; in which R has the meaning explained in the description, a process for their preparation and the use of these compounds as medicines, especially as renin inhibitors.
US08022066B2 2-(2-hydroxyphenyl) benzothiadiazines useful for treating obesity and diabetes
The present invention relates to novel compounds that act as chemical uncouplers. Compounds of the invention are useful, inter alia, in the treatment, including prevention, of obesity, diabetes and a number of diseases or conditions associated therewith.
US08022060B2 Spirocyclic heterocyclic derivatives and methods of their use
Spirocyclic heterocyclic derivatives, pharmaceutical compositions containing these compounds, and methods for their pharmaceutical use are disclosed. In certain embodiments, the spirocyclic heterocyclic derivatives are ligands of the δ opioid receptor and may be useful, inter alia, for treating and/or preventing pain, anxiety, gastrointestinal disorders, and other δ opioid receptor-mediated conditions.
US08022059B2 Indazole acrylic acid amide compound
A compound of the formula: wherein ring X is benzene or pyridine; R1 is substituted alkyl; R2 is optionally substituted aryl or optionally substituted heterocyclic group; R3 is hydrogen or alkyl; R4 is hydrogen, halogen or alkyl; R5 is hydrogen or alkyl; R6 and R7 are the same or different and each hydrogen or halogen, or a pharmaceutically acceptable salt thereof, which is useful as IKur blocker effective for preventing or treating cardiac arrhythmia such as atrial fibrillation.
US08022056B2 Compositions and methods for the treatment of cancer
The present invention relates to the use of specific compounds related to the indolocarbazole K252a, for the preparation of pharmaceutical compositions for the treatment of various forms of cancer.
US08022055B2 Betulinic acid derivatives
The invention relates to novel betulinic acid derivatives of formula (I), wherein R is C(═CH2)CH3 or CH(CH3)2; R2 together with the adjacent carbonyl group forms a carboxylic acid, carboxylic acid ester or amide or substituted amide; R3 or R4 are hydrogen or aryl with the proviso that both are not independently hydrogen or alkyl or R3 and R4 are combined together to form an aryl ring optionally substituted with a group X, wherein X is selected from halogen, alkyl, cyano, nitro, alkoxy, amino or substituted amine; Y is N or O; and R1 is zero when Y is O, and R1 is hydrogen, alkyl or aryl alkyl when Y is N, useful for inhibition of tumor cancer cells.
US08022053B2 Oral solid dosage forms containing a low dose of estradiol
The present invention relates to oral solid dosage forms containing a very low dose of estradiol. The dosage forms are formulated in a manner so as to avoid degradation of the estradiol and to minimise the content of polyvinylpyrrolidone, while still achieving similar fast dissolution of the estradiol. The dosage forms are useful in preventing or treating a physical condition in a woman caused by insufficient endogenous levels of estradiol.
US08022052B2 Inhibition of PPAR gamma expression by specific osteogenic oxysterols
This invention relates to methods for using agents to inhibit peroxisome proliferator activated receptor expression.
US08022042B2 Composition and methods for the treatment of cancer
The present invention discloses anti-cancer compositions, and associated methods, including an anti-cancer composition comprising: a cellular energy inhibitor having the structure according to formula I wherein X is selected from the group consisting of: a nitro, an imidazole, a halide, sulfonate, a carboxylate, an alkoxide, and amine oxide; and R is selected from the group consisting of: OR′, N(R″)2, C(O)R′″, C1-C6 alkyl, C6-C12 aryl, C1-C6 heteroalkyl, a C6-C12 heteroaryl, H, and an alkali metal; where R′ represents H, alkali metal, C1-C6 alkyl, C6-C12 aryl or C(O)R′″, R″ represents H, C1-C6 alkyl, or C6-C12 aryl, and R′″ represents H, C1-C20 alkyl or C6-C12 aryl. The anti-cancer composition can additionally comprise at least one sugar, which stabilizes the cellular energy inhibitor by substantially preventing the inhibitor from hydrolyzing. Also, the anti-cancer composition can comprise a glycolysis inhibitor. Further, the anti-cancer composition can comprise a biological buffer that is present in an amount sufficient to at least partially deacidify the cellular energy inhibitor and neutralize metabolic by-products of the cellular energy inhibitor.
US08022041B2 Prodrug of an ICE inhibitor
This invention describes an ICE inhibitor prodrug (I) having good bioavailability. Compound I is useful for treating IL-1 mediated diseases such as rheumatoid arthritis, inflammatory bowel disease, Crohn's disease, ulcerative colitis, inflammatory peritonitis, septic shock, pancreatitis, traumatic brain injury, organ transplant rejection, osteoarthritis, asthma, psoriasis, Alzheimer's disease, myocardial infarction, congestive heart failure, Huntington's disease, atherosclerosis, atopic dermatitis, leukemias and related disorders, myelodysplastic syndrome, uveitis or multiple myeloma.
US08022039B2 Immunogenic HER-2 variants
The present invention provides for a novel method for purification of EGFR family proteins obtained from cultures of insect cells. The process comprises subsequent steps of a) diafiltration and exchange of culture medium with buffer, b) immobilized metal affinity chromatography (IMAC), C) size exclusion chromatography (SEC), and d) anion exchange chromatography (AIE). The method also provides for an immunogenic variant of HER-2 protein which for which the purification process has been especially adapted, as well as means for the preparation of the variant.
US08022036B2 Use of thymosin alpha 1 for the treatment of immunological diseases
It is described the use of thymosin alpha 1 for preparing a medicament useful for the prevention or treatment of graft-versus-host disease or graft rejection reactions in organ transplantation, in a mammal subject, in which the cells, tissues or organs for transplant is selected from the group comprising: stem cells, hematopoietic stem cells, bone marrow, heart, liver, kidney, lung, pancreas, small intestine, cornea or skin.
US08022035B2 Y4 selective receptor agonists for therapeutic interventions
Y4 receptor agonist peptide selected from the group consisting of: [Ala30]PP2-36, [Thr30]PP2-36, [Asn30]PP2-36, [Gln30]PP2-36, [Glu10]PP2-36, [Glu10,Leu17,Thr30]PP2-36, [Nle17,Nle30]PP2-36, [Glu10,Nle17,Nle30]PP2-36, their PP1-36 equivalents, and analogues and derivatives thereof as described in the specification, are selective agonists of the Y4 receptor relative to the Y1 and Y2 receptors, and are useful in the treatment, for example, of obesity and overweight, and conditions in which these are considered contributory factors, and in the treatment of diarrhoea and intestinal hypersecretion.
US08022031B2 Liquid composition of factor VII polypeptides
A liquid aqueous composition comprising (i) a factor VII polypeptide, (ii) an agent suitable for keeping pH in the range of from about 4.0 to about 8.0; (iii) an agent selected from the list of: a calcium salt, a magnesium salt, or a mixture thereof; wherein the concentration of (iii) is at least 15 mM.
US08022029B2 Fabric softening compositions comprising polymeric materials
Fabric softening compositions comprising polymeric materials capable of retaining volatile perfume ingredients are disclosed, as well as methods of softening fabrics.
US08022028B2 Light duty liquid cleaning compositions and methods of manufacture and use thereof comprising organic acids
The invention encompasses liquid cleaning compositions, for example, dish washing liquids, and methods of their manufacture and use, which possess enhanced cleaning ability. The cleaning compositions of the invention include acidic light duty liquid cleaning compositions with low toxicity and antibacterial efficacy on surfaces, for example, hard surfaces.
US08022023B2 Lubricating oil additive and lubricating oil composition containing same
A molybdated succinimide complex is disclosed which is prepared by a process comprising (a) reacting a succinimide of a polyamine of formula I: wherein R is a hydrocarbon radical having a number average molecular weight of about 500 to about 5,000, a and b are independently 2 or 3, and x is 0 to 10, with an ethylenically unsaturated carboxylic acid or anhydride thereof, in a charge mole ratio of the ethylenically unsaturated carboxylic acid or anhydride thereof to the succinimide of formula I of about 0.9:1 to about 1.05:1; and (b) reacting the succinimide product of step (a) with an acidic molybdenum compound. Also disclosed is a lubricating oil composition containing at least (a) a major amount of a base oil of lubricating viscosity and (b) a minor amount of the molybdated succinimide complex.
US08022019B2 Method of making proppant used in gas or oil extraction
Method and system for making a spherical proppant having a selected grade from a naturally occurring mined mineral having a hardness of over 6.0 Mohs. The method and system involves preprocessing the mineral mechanically into a semi-dry feedstock comprising a mass of particles with initial sphericity values generally less than 0.60; subjecting the semi-dry feedstock to an aggressive abrasive attrition operation for a process time; and, controlling the process time to a value wherein the particles of the feedstock are converted to final processed particles having a sphericity greater than 0.60 by increasing the sphericity of the feedstock particles by at least 0.10. In addition, the processed particles are screened to obtain a proppant having a selected grade.
US08022009B2 Process for synthesizing LixFeMZO4/ carbon and LixMZO4/ carbon composite materials
The present invention provides a cost effective process of generating LixMyZO4/carbon composite material. Further, this novel method of preparation can be modified by adding a dopant and the calcinations can be carried out using microwave heating to reduce the synthesis time and cost. The LixMyZO4/carbon composite material can be used as a cathode for a secondary electrochemical cell. Selection of one or more metals in the cathode material can be used change the voltage, the capacity, and the energy density of the electrochemical cell.
US08022008B2 Hydrogenation catalyst with improved textural properties
A method is provided for making a catalyst support, and includes the steps of providing an aqueous suspension of refractory inorganic oxide and refractory inorganic carbide; forming the suspension into droplets; exposing the droplets to a gelling agent whereby the droplets are at least partially solidified so as to provide substantially sphere-shaped portions of refractory inorganic oxide and refractory inorganic carbide; and drying and calcining the sphere-shaped portions so as to provide substantially spherical particles of catalyst support containing refractory inorganic oxide and refractory inorganic carbide. Catalytically active metal phases and hydrogenation processes using the catalyst are also described.
US08022004B2 Multi-coated electrode and method of making
Various embodiments provide an electrode comprising a conductive substrate, a first layer of a mixture comprising iridium oxide in a crystalline phase and tantalum oxide in an amorphous phase on a portion of an outer surface of the conductive substrate, and a second layer of the mixture comprising iridium oxide in an amorphous phase and tantalum oxide in an amorphous phase on an outer surface of the first layer.
US08022000B2 Display device and production method thereof
A bonding glass containing V2O5: 25 to 50 wt %, TeO2: 20 to 40 wt % and BaO: 5 to 30 wt %, and not containing lead.
US08021997B2 Multicomponent spunbonded nonwoven, method for its manufacture, and use of the multicomponent spunbonded nonwovens
A multicomponent spunbonded nonwoven is provided which is composed of at least two polymers which form interfaces toward one another, which are produced by at least one spinning machine having uniform spinning nozzle apertures, and which are hydrodynamically drawn, lapped in a sheet-like manner, and bonded, the multicomponent spunbonded nonwoven being composed of different filaments which contain at least two polymers, or it being composed of a mixture of multicomponent filaments and monocomponent filaments which each contain only one of the polymers, the multicomponent filament being composed of at least two elementary filaments and the titer of the individual filaments varying by the number of elementary filaments contained in the filaments.
US08021996B2 Nonwoven web and filter media containing partially split multicomponent fibers
The present invention provides a nonwoven web prepared from multicomponent fibers which are partially split. The partially split multicomponent fibers have at least one component of the multicomponent fiber separated from the remaining components of the multicomponent fiber along a first section of the longitudinal length of the multicomponent fibers. Along a second section of the longitudinal length of the multicomponent fibers the components of the multicomponent fibers remain together as a unitary fiber structure. In addition, part of the second section of the multicomponent fibers is bonded to part of a second section of an adjacent multicomponent fiber.
US08021995B2 Mixed fiber and stretch nonwoven fabric comprising said mixed fiber and method for manufacture thereof
A fiber mixture according to the invention comprises fibers A comprising a polymer A containing a thermoplastic polyurethane elastomer and fibers B comprising a thermoplastic polymer B other than the thermoplastic polyurethane elastomer, said thermoplastic polyurethane elastomer having a starting temperature for solidifying of 65° C. or above as measured by a differential scanning calorimeter (DSC) and containing 3.00×106 or less polar-solvent-insoluble particles per g counted on a particle size distribution analyzer, which is based on an electrical sensing zone method, equipped with an aperture tube having an orifice of 100 μm in diameter. An elastic nonwoven fabric comprises the fiber mixture.
US08021991B2 Technique to radiation-harden trench refill oxides
Oxide films are deposited under conditions generating a silicon-rich oxide in which silicon nanoclusters form either during deposition or during subsequent annealing. Such deposition conditions include those producing films with optical indices (n) greater than 1.46. The method of the present invention reduces the TID radiation-induced shifts for the oxides.
US08021990B2 Gate structure and method
A MOSFET structure including silicate gate dielectrics with nitridation treatments of the gate dielectric prior to gate material deposition.
US08021989B2 Method for high topography patterning
One inventive aspect is related to a method for isolating structures of a semiconductor material, comprising providing a pattern of the semiconductor material comprising at least one elevated line, defining device regions in the pattern, the device regions each comprising at least said at least one elevated line, and modifying the conductive properties of the semiconductor material outside said device regions, such that the device regions are electrically isolated.
US08021988B2 Method of forming semiconductor device and semiconductor device
The present invention provides a semiconductor device having an improved silicon oxide film as a gate insulation film of a Metal Insulator Semiconductor structure and a method of making the same.
US08021987B2 Method of modifying insulating film
An insulting film is modified by subjecting the insulting film to a modification treatment comprising a combination of a plasma treatment and a thermal annealing treatment. There is provided a method of enhancing the characteristic of an insulating film by improving deterioration in the characteristic of the insulating film due to carbon, a suboxide, a dangling bond or the like contained in the insulating film.
US08021986B2 Method for producing a transistor with metallic source and drain
A method for producing a transistor with metallic source and drain including the steps of: a) producing a gate stack, b) producing two portions of a material capable of being selectively etched relative to a second dielectric material and arranged at the locations of the source and of the drain of the transistor, c) producing a second dielectric material-based layer covering the stack and the two portions of material, d) producing two holes in the second dielectric material-based layer forming accesses to the two portions of material, e) etching of said two portions of material, f) depositing a metallic material in the two formed cavities, and also including, between steps a) and b), a step of deposition of a barrier layer on the stack, against the lateral sides of the stack and against the face of the first dielectric material-based layer.
US08021985B2 Method to form semiconductor laser diode
The process of the present invention to form a mask made of inorganic material containing silicon reduces the plasma damage induced in the semiconductor layers due to the plasma-ashing. The semiconductor material is heat-treated at a high temperature after the growth thereof to form an oxide layer positively in the surface of the semiconductor material before it is covered by the silicon inorganic film. This inorganic film is dry-etched by an etchant containing fluorine to get a mask for forming a mesa and for growing burying layer selectively.
US08021983B2 Method of forming pattern of inorganic material film comprising thermally induced cracking
A method of forming a pattern of an inorganic material film, which method is more versatile, easy, and practical. The method includes the steps of: (a) forming a sacrifice layer having a pattern on a substrate by employing a material having a different thermal expansion coefficient from that of an inorganic material of the inorganic material film; (b) forming an inorganic material layer on the substrate, on which the sacrifice layer has been formed, at a predetermined deposition temperature by employing the inorganic material; (c) lowering a temperature of at least the inorganic material layer to produce cracks in the inorganic material layer formed on the sacrifice layer; and (d) removing the sacrifice layer and the inorganic material layer formed thereon.
US08021981B2 Redistribution layers for microfeature workpieces, and associated systems and methods
Redistribution layers for microfeature workpieces, and associated systems and methods are disclosed. One method for processing a microfeature workpiece system includes positioning a preformed redistribution layer as a unit proximate to and spaced apart from a microfeature workpiece having an operable microfeature device. The method can further include attaching the redistribution layer to the microfeature workpiece and electrically coupling the redistribution layer to the operable microfeature device.
US08021979B2 Method of manufacturing semiconductor device
To provide a technology capable of improving reliability and manufacturing yield of a semiconductor device by reducing variations of electrical characteristics in connection hole portions. After a semiconductor wafer is placed over a wafer stage provided in a chamber for dry cleaning treatment of a deposition system, dry cleaning treatment is performed to a principal surface of the semiconductor wafer by supplying reducing gas, sequentially, heat treatment is performed to the semiconductor wafer at a first temperature of 100 to 150° C. by a showerhead which is maintained at 180° C. Next, after the semiconductor wafer is vacuum transferred from the chamber to a chamber for heat treatment, heat treatment is performed to the semiconductor wafer at a second temperature of 150 to 400° C. in the chamber, thereby removing a product remaining over the principal surface of the semiconductor wafer.
US08021978B2 Methods of fabricating flash memory devices having shared sub active regions
Flash memory devices include a pair of elongated, closely spaced-apart main active regions in a substrate. A sub active region is also provided in the substrate, extending between the pair of elongated, closely spaced-apart main active regions. A bit line contact plug is provided on, and electrically contacting, the sub active region and being at least as wide as the sub active region. An elongated bit line is provided on, and electrically contacting, the bit line contact plug remote from the sub active region.
US08021977B2 Methods of forming contact structures and semiconductor devices fabricated using contact structures
Provided are methods of forming contact structures and semiconductor devices fabricated using the contact structures. The formation of a contact structure can include forming a first molding pattern on a substrate, forming an insulating layer to cover at least a sidewall of the first molding pattern, forming a second molding pattern to cover a sidewall of the insulating layer and spaced apart from the first molding pattern, removing a portion of the insulating layer between the first and second molding patterns to form a hole, and forming an insulating pattern between the first and second molding patterns, and forming a contact pattern in the hole.
US08021976B2 Method of wire bonding over active area of a semiconductor circuit
A method and structure are provided to enable wire bond connections over active and/or passive devices and/or low-k dielectrics, formed on an Integrated Circuit die. A semiconductor substrate having active and/or passive devices is provided, with interconnect metallization formed over the active and/or passive devices. A passivation layer formed over the interconnect metallization is provided, wherein openings are formed in the passivation layer to an upper metal layer of the interconnect metallization. Compliant metal bond pads are formed over the passivation layer, wherein the compliant metal bond pads are connected through the openings to the upper metal layer, and wherein the compliant metal bond pads are formed substantially over the active and/or passive devices. The compliant metal bond pads may be formed of a composite metal structure.
US08021974B2 Structure and method for back end of the line integration
An improved semiconductor structure consists of interconnects in an upper interconnect level connected to interconnects in a lower interconnect level through use of a conductive protrusion located at the bottom of a via opening in an upper interconnect level, the conductive protrusion extends upward from bottom of the via opening and into the via opening. The improved interconnect structure with the conductive protrusion between the upper and lower interconnects enhances overall interconnect reliability.
US08021970B2 Method of annealing a dielectric layer
A method includes forming a first dielectric layer over a substrate; forming nanoclusters over the first dielectric layer; forming a second dielectric layer over the nanoclusters; annealing the second dielectric layer using nitrous oxide; and after the annealing the second dielectric layer, forming a gate electrode over the second dielectric layer.
US08021968B2 Susceptor and method for manufacturing silicon epitaxial wafer
Provided is a susceptor 13 for manufacturing an epitaxial wafer, comprising a mesh-like groove 13b on a mount face on which a silicon substrate W is to be mounted, wherein a coating H of silicon carbide is formed on the mount face, and the coating has a surface roughness of 1 μm or more in centerline average roughness Ra and a maximum height of a protrusion 13p generated in forming the coating H of 5 μm or less. Thus, defects such as warping and slip as well as adhesion of the silicon substrate to the susceptor are prevented.
US08021963B2 Wafer treating method
A wafer treating method includes the steps of irradiating a wafer, provided with devices on the face side, from the back side with a laser beam capable of being transmitted through the wafer, while converging the laser beam to a predetermined depth, so as to form a denatured layer between the face side and the back side of the wafer, and separating the wafer into a back-side wafer on the back side relative to the denatured layer and a face-side wafer on the face side relative to the denatured layer. The denatured layer remaining in the face-side wafer is removed, and the face-side wafer is finished to a predetermined thickness, whereby the devices constituting the face-side wafer are finished into products, and the back-side wafer is recycled.
US08021960B2 Method for manufacturing semiconductor device
A chip provided with a layer for separation of a surface region and a hydrophilic surface is manufactured. One or both of a hydrophilic region and a hydrophobic region are formed on a substrate surface where the chip is placed. Liquid is dropped onto the hydrophilic region on the substrate surface, and the chip is placed thereon. The substrate and the chip are heated while being pressure-bonded so that the chip is fixed on the substrate surface, and then the surface region of the chip is separated. By providing a liquid layer in a position where the chip is placed, the chip can be placed on the substrate with high accuracy and thus productivity can be increased.
US08021959B2 Method for the ultrasonic planarization of a substrate, from one surface of which a buried weakened layer has been uncovered by fracture
A method for forming a plurality of thin films from a microtechnological donar substrate with a view to recycling of the donor substrate, the method including exposing a face of the donor substrate by fracturing the donor substrate along a layer weakened by implantation and placing the exposed face in a bath and applying ultrasound with a frequency of between 10 kHz and 80 kHz under conditions suitable for causing cavitation along the exposed face. In the case of a silicon donor substrate, the bath is exposed to an ultrasound power per unit volume of greater than 5 W/I, at a power of greater than 10 W with a duration of greater than 1 minute, and at a temperature between 1° C. and 100° C.
US08021958B2 Method for manufacturing SOI substrate and method for manufacturing semiconductor device
A method for manufacturing an SOI substrate in which crystal defects of a single crystal semiconductor layer are reduced is provided. An oxide film containing halogen is formed on each of surfaces of a single crystal semiconductor substrate and of a semiconductor substrate provided with a single crystal semiconductor layer separated from the single crystal semiconductor substrate, whereby impurities that exist on the surfaces of and inside the substrates are decreased. In addition, the single crystal semiconductor layer provided over the semiconductor substrate is irradiated with a laser beam, whereby crystallinity of the single crystal semiconductor layer is improved and planarity is improved.
US08021957B2 Process of forming an electronic device including insulating layers having different strains
An electronic device can include a field isolation region and a first insulating layer having a first strain and having a portion, which from a top view, lies entirely within the field isolation region. The electronic device can also include a second insulating layer having a second strain different from the first strain and including an opening. From a top view, the portion of the first insulating layer can lie within the opening in the second insulating layer. In one embodiment, the field isolation region can include a dummy structure and the portion of the first insulating layer can overlie the dummy structure. A process of forming the electronic device can include forming an island portion of an insulating layer wherein from a top view, the island portion lies entirely within the field isolation region.
US08021956B2 Ultrathin SOI CMOS devices employing differential STI liners
An oxynitride pad layer and a masking layer are formed on an ultrathin semiconductor-on-insulator substrate containing a top semiconductor layer comprising silicon. A first portion of a shallow trench is patterned in a top semiconductor layer by lithographic masking of an NFET region and an etch, in which exposed portions of the buried insulator layer is recessed and the top semiconductor layer is undercut. A thick thermal silicon oxide liner is formed on the exposed sidewalls and bottom peripheral surfaces of a PFET active area to apply a high laterally compressive stress. A second portion of the shallow trench is formed by lithographic masking of a PFET region including the PFET active area. A thin thermal silicon oxide or no thermal silicon oxide is formed on exposed sidewalls of the NFET active area, which is subjected to a low lateral compressive stress or no lateral compressive stress.
US08021954B2 Integrated circuit system with hierarchical capacitor and method of manufacture thereof
A method of manufacture of an integrated circuit system includes: providing a substrate including front-end-of-line circuitry; forming a first group of metal layers including a first finger and a second finger over the substrate utilizing a first design rule, the first group of metal layers being formed without a finger via; forming a second group of metal layers including a first finger, a second finger, and a finger via over the first group of metal layers utilizing a second design rule that is larger than the first design rule; and interconnecting the first group of metal layers with the second group of metal layers to form a capacitor.
US08021953B2 Method for making PMC type memory cells
A microelectronic device includes: at least one cell or element including at least one first electrode, at least one second electrode, and at least one stack of thin layers between the first electrode and the second electrode. The stack includes at least one doped chalcogenide layer capable of forming a solid electrolyte, the doped chalcogenide layer being provided on and in contact with the first electrode; at least one interface layer provided on and in contact with the doped chalcogenide layer, the interface layer being based on a material different from the chalcogenide, the material being carbon or carbon comprising a metallic additive or a semiconducting additive; and at least one metallic ion donor layer provided on and in contact with the interface layer, the metallic ion donor layer being an ion source for the solid electrolyte.
US08021952B2 Integrated transistor, particularly for voltages and method for the production thereof
Integrated transistor and method for the production is disclosed. An explanation is given of, inter alia, a transistor having an electrically insulating isolating trench extending from a main area in the direction of a connection region remote from the main area. Moreover, the transistor contains an auxiliary trench extending from the main area as far as the connection region remote from the main area. The transistor requires a small chip area and has outstanding electrical properties.
US08021949B2 Method and structure for forming finFETs with multiple doping regions on a same chip
A method for fabrication of features for an integrated circuit includes patterning a first semiconductor structure on a surface of a semiconductor device, and epitaxially growing semiconductor material on opposite sides of the first semiconductor structure to form fins. A first angled ion implantation is applied to one side of the first semiconductor structure to dope a respective fin on the one side. The first semiconductor structure is selectively removed to expose the fins. Fin field effect transistors are formed using the fins.
US08021945B2 Bottle-shaped trench capacitor with enhanced capacitance
In accordance with an aspect of the invention, a method is provided for fabricating a semiconductor chip including a trench capacitor. In such method, a monocrystalline semiconductor region can be etched in a vertical direction through an opening in a dielectric layer to form a trench exposing a rough surface of monocrystalline semiconductor material. The trench has an initial lateral dimension in a first direction transverse to the vertical direction. The semiconductor material exposed at the surface of the trench then is etched in a crystallographic orientation-dependent manner to expose a multiplicity of crystal facets of the semiconductor material at the trench surface. A dopant-containing liner may then be deposited to line the surface of the trench and a temperature of the substrate then be elevated to drive a dopant from the dopant-containing liner into the semiconductor region adjacent to the surface. During such step, typically a portion of the semiconductor material exposed at the wall is oxidized. At least some of the oxidized portion is removed to expose a wall of an enlarged trench, along which wall a dielectric layer and conductive material are formed in order to form a trench capacitor.
US08021939B2 High-k dielectric and metal gate stack with minimal overlap with isolation region and related methods
A high-k dielectric and metal gate stack with minimal overlap with an adjacent oxide isolation region and related methods are disclosed. One embodiment of the gate stack includes a high dielectric constant (high-k) dielectric layer, a tuning layer and a metal layer positioned over an active region defined by an oxide isolation region in a substrate, wherein an outer edge of the high-k dielectric layer, the tuning layer and the metal layer overlaps the oxide isolation region by less than approximately 200 nanometers. The gate stack and related methods eliminate the regrowth effect in short channel devices by restricting the amount of overlap area between the gate stack and adjacent oxide isolation regions.
US08021938B2 Semiconductor device and method for fabricating the same
A semiconductor device includes: a first gate insulating film on a first region of a semiconductor substrate; a first gate electrode on the first gate insulating film; a second gate insulating film on a second region of the semiconductor substrate; and a second gate electrode on the second gate insulating film. The first gate insulating film includes a first insulating film composed of a first material containing a first metal, and the second gate insulating film includes a second insulating film composed of the first material and a second material containing a second metal.
US08021937B2 Array substrate including thin film transistor and method of fabricating the same
A method of fabricating an array substrate includes: forming a gate line and a gate electrode connected to the gate line; forming a gate insulating layer on the gate line and the gate insulting layer; sequentially forming an intrinsic amorphous silicon pattern and an impurity-doped amorphous silicon pattern on the gate insulating layer over the gate electrode; forming a data line on the gate insulating layer and source and drain electrodes on the impurity-doped amorphous silicon pattern, the data line crossing the gate line to define a pixel region, and the source and drain electrodes spaced apart from each other; removing a portion of the impurity-doped amorphous silicon pattern exposed through the source and drain electrodes to define an ohmic contact layer; irradiating a first laser beam onto the intrinsic amorphous silicon pattern through the source and drain electrode to form an active layer including a first portion of polycrystalline silicon and a second portion of amorphous silicon at both sides of the first portion; forming a passivation layer on the data line, the source electrode and the drain electrode, the passivation layer having a drain contact hole exposing the drain electrode; and forming a pixel electrode on the passivation layer in the pixel region, the pixel electrode connected to the drain electrode through the drain contact hole.
US08021935B2 Thin film device fabrication process using 3D template
A fabrication process for a device such as a backplane for a flat panel display includes depositing thin film layers on a substrate, forming a 3D template overlying the thin film layers, and etching the 3D template and the thin film layers to form gate lines and transistors from the thin film layers. An insulating or passivation layer can then be deposited on the gate lines and the transistors, so that column or data lines can be formed on the insulating layer.
US08021933B2 Integrated circuit including structures arranged at different densities and method of forming the same
A method of forming an integrated circuit includes forming first structures in a first portion of the integrated circuit and forming second structures, which are arranged more densely than the first structures, in a second portion. The first and second structures are defined by lithography processes using photomasks. At least one of the photomasks includes both openings in a first region for supporting the definition of the first structures and openings in a second region for supporting the definition of the second structures.
US08021932B2 Semiconductor device, and manufacturing method therefor
To provide a semiconductor device with improved reliability. The semiconductor device includes a wiring board, a microcomputer chip flip-chip bonded over the wiring board via gold bumps, a first memory chip laminated over the microcomputer chip, wires for coupling the first memory chip to the wiring board, an underfill material with which a flip-chip coupling portion of the microcomputer chip is filled, and a sealing member for sealing the microcomputer chip and the first memory chip with resin. Further, the corner of a second opening portion of a solder resist film of the wiring board corresponding to the corner of the chip on the air vent side in charging the underfill material is made close to the microcomputer chip, which can improve the wettability and spread of the underfill material at the second opening portion, thus reducing the exposure of leads to the second opening portion, thereby improving the reliability of the semiconductor device.
US08021930B2 Semiconductor device and method of forming dam material around periphery of die to reduce warpage
A semiconductor device has a temporary carrier with a designated area for a first semiconductor die. A dam material is deposited on the carrier around the designated area for a first semiconductor die. The first semiconductor die is mounted to the designated area on the carrier. An encapsulant is deposited over the first semiconductor die and carrier. The dam material is selected to have a CTE that is equal to or less than the CTE of the encapsulant. The carrier is removed to expose the encapsulant and first semiconductor die. A first interconnect structure is formed over the encapsulant. An EMI shielding layer can be formed over the first semiconductor die. A second interconnect structure is formed over a back surface of the first semiconductor die. A conductive pillar is formed between the first and second interconnect structures. A second semiconductor die is mounted to the second interconnect structure.
US08021927B2 Die down ball grid array packages and method for making same
A method of forming a ball grid array (BGA) package is provided. The method includes coupling an integrated circuit (IC) die to a heat spreader in an opening of a substrate, the opening of the substrate extending through the substrate, such that a portion of the heat spreader is accessible through the opening and coupling a first surface of a second substrate to the IC die via a bump interconnect. The second surface of the second substrate has an array of contact pads capable of coupling to a board.
US08021923B2 Semiconductor package having through-hole vias on saw streets formed with partial saw
A method of forming through-hole vias in a semiconductor wafer involves forming a semiconductor wafer having a plurality of die with contact pads disposed on a surface of each die. The semiconductor wafer has a saw street between each die. A trench is formed in the saw street without using support material to support the semiconductor wafer. The trench extends only partially through the semiconductor wafer. The portion of the saw street below the trench along a backside of the semiconductor wafer has sufficient thickness to maintain structural support for the semiconductor wafer without support material during formation of conductive vias between the die, and electrically connection of the conductive vias to the contact pads. The portion of the saw street below the trench along the backside of the semiconductor wafer is removed. The semiconductor wafer is singulated along the saw street to separate the die.
US08021920B2 Method for producing a metal-ceramic substrate for electric circuits on modules
The invention relates to a metal-ceramic substrate for electric circuits or modules, the substrate including a ceramic layer which is provided with at least one metallic layer of a first type applied to a surface of the ceramic layer in a plane manner. An insulating layer made up of a glass-containing material is applied to at least one partial region of a surface of the metallic layer of the first type, the surface opposing the ceramic layer, and a metallic layer of a second type is applied to the insulating layer, the insulating layer and the metallic layer of a second type respectively being thinner then the ceramic layer and the metallic layer of the first type.
US08021919B2 Method of manufacturing a semiconductor device
A method of manufacturing a semiconductor device or a substrate is described. The method includes providing a chip attached to a carrier or providing a substrate. A foil is held over the chip and the carrier or the substrate. A laser beam is directed onto the foil, and substance at the foil is ablated and deposited on the chip and the carrier or on the substrate.
US08021918B2 Integrated circuit chips with fine-line metal and over-passivation metal
An integrated circuit chip includes a silicon substrate, a first circuit in or over said silicon substrate, a second circuit device in or over said silicon substrate, a dielectric structure over said silicon substrate, a first interconnecting structure in said dielectric structure, a first pad connected to said first node of said voltage regulator through said first interconnecting structure, a second interconnecting structure in said dielectric structure, a second pad connected to said first node of said internal circuit through said second interconnecting structure, a passivation layer over said dielectric structure, wherein multiple opening in said passivation layer exposes said first and second pads, and a third interconnecting structure over said passivation layer and over said first and second pads.
US08021916B2 Method for manufacturing semiconductor device
To provide a method for manufacturing a thin film transistor in which contact resistance between an oxide semiconductor layer and source and drain electrode layers is small, the surfaces of the source and drain electrode layers are subjected to sputtering treatment with plasma and an oxide semiconductor layer containing In, Ga, and Zn is formed successively over the source and drain electrode layers without exposure of the source and drain electrode layers to air.
US08021906B2 Hermetic sealing and electrical contacting of a microelectromechanical structure, and microsystem (MEMS) produced therewith
Disclosed are methods and microsystems for vertically through-plating (6) cover plates (5) for microsystem components (2, 2a) by means of a conductive solder glass (8). Said methods and microsystems make it possible to simplify through-plating, reduce the failure rate, and increase reliability.
US08021903B2 Method for fabricating micro-lens and micro-lens integrated optoelectronic devices using selective etch of compound semiconductor
Provided are a method of fabricating a microlens using selective etching of a compound semi-conductor and a method of fabricating a photoelectric device having the microlens. The formation of the microlens includes patterning a compound semiconductor layer and removing a lateral surface of the compound semiconductor layer to form a roughly hemispheric lens. The lateral surface of the compound semiconductor layer is removed by a digital alloy method. In particular, the lateral surface of the compound semiconductor layer is removed by a wet etching process.
US08021900B2 Planar waveguide with patterned cladding and method for producing same
Methods for the production of integrated optical waveguides which have a patterned upper cladding with a defined opening to allow at least one side or at least one end of a light transmissive element to be air clad The at least one side or at least one end is, for preference, a lens structure unitary with the waveguide or a bend.
US08021898B2 Method and apparatus for controlled thermal processing
A materials processing system comprises a thermal processing chamber including a heating source, a first noncontacting thermal measurement device positioned to measure temperature on a first area of the material being processed, and, a second noncontacting thermal measurement device positioned to measure temperature on a second area of the material being processed, the first device being relatively more sensitive to changes in surface emissivity than the second device. By comparing the outputs of the two devices, emissivity changes can be detected and used as a proxy for some physical change in the workpiece and thereby determine when the desired process has been completed. The system may be used to develop a process recipe, or it may be part of a system for real-time process control based on emissivity changes. Applicable processes include heating, annealing, dopant activation, silicide formation, carburization, nitridation, sintering, oxidation, vapor deposition, metallization, and plating.
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