专利汇可以提供Fault simulation system for determining the testability of a non-linear integrated circuit by an electrical signal test pattern专利检索,专利查询,专利分析的服务。并且A system involving the use of fault simulation for determining whether a proposed non-linear integrated circuit is testable by a proposed incremental bilevel electrical signal test pattern. The system, which is particularly advantageous in determining the testability of integrated circuits having sequential logic, involves the conversion of the bilevel electrical test pattern into a corresponding three-level test pattern, and the application of said three-level pattern to a three-level ''''good'''' circuit simulation of the integrated circuit and to a number of three-level ''''bad'''' circuit simulations of said circuit, each of said ''''bad'''' circuit simulations being representative of a different stuck fault condition which is to be determined by the test pattern. The resulting output of the ''''good'''' circuit simulation is compared to each of the resulting outputs of the ''''bad'''' circuit simulations, and there is determined both the proportion of the total ''''bad'''' circuits whose definitive outputs fail to compare at least once with the corresponding definitive outputs from the ''''good'''' circuit simulation, and the proportion of total ''''bad'''' circuit simulation manifesting an output at an indeterminate level when the ''''good'''' circuit simulation is at a definitive level.,下面是Fault simulation system for determining the testability of a non-linear integrated circuit by an electrical signal test pattern专利的具体信息内容。
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